Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel defining layer including a first portion overlapping the display area and a second portion overlapping the non-display area; a bank structure on the pixel defining layer; a remaining pattern including a first portion overlapping the display area and a second portion overlapping the non-display area; a power line on the non-display area of the substrate; a dam structure disposed on the power line; and a power connection electrode on the power line and the dam structure, a portion of the power connection electrode being covered by the second portion of the remaining pattern and the second portion of the pixel defining layer, a side surface of the power connection electrode facing the dam structure being in contact with the second portion of the remaining pattern, and may be fully covered by a second portion of the remaining pattern and a second portion of the pixel defining layer.

Description

Technical Field

[0001] The present invention relates to a display device and a manufacturing method thereof. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigators, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, an organic light emitting display device, etc. In such a flat panel display device, the light emitting display device includes a light emitting element capable of making each pixel of the display panel emit light by itself, so that an image can be displayed even without a backlight unit that supplies light to the display panel.

[0003] Recently, with the development of various electronic devices, the demand for high-resolution display devices is increasing. For a high-resolution display device, due to the need for high pixel integration, the interval between light emitting elements overlapping with each light emitting area may be reduced. Therefore, the high-resolution display device can be formed by a patterning process of forming a single pixel without using a process of a fine metal mask. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display device including a bank structure disposed in a display area and a non-display area, and to solve the corrosion defect of a power connection electrode connected to a connection electrode at a portion overlapping with the non-display area.

[0005] The technical problems of the present invention are not limited to the above-mentioned technical problems, and those skilled in the technical field to which the present invention pertains can clearly understand other technical problems not mentioned through the following description.

[0006] A display device according to an embodiment for solving the above technical problem includes: a substrate including a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; an anode electrode located on the light-emitting area of the substrate; a pixel defining layer including a first portion overlapping with the display area and a second portion overlapping with the non-display area, and the first portion is located on the non-light-emitting area of the substrate and defines a first opening; a bank structure located on the pixel defining layer and defining a second opening; a remaining pattern including a first portion overlapping with the display area and a second portion overlapping with the non-display area, and the first portion is disposed between the anode electrode and the first portion of the pixel defining layer in a direction perpendicular to the substrate within the second opening; a light-emitting layer located on the anode electrode and in contact with the bank structure; a cathode electrode located on the light-emitting layer and in contact with the bank structure; a power line located on the non-display area of the substrate; a dam structure disposed on the power line; and a power connection electrode located on the power line and the dam structure, spaced apart from the anode electrode, a part of the power connection electrode is covered by the second portion of the remaining pattern and the second portion of the pixel defining layer, a side surface of the power connection electrode facing the dam structure is in contact with the second portion of the remaining pattern, and may be completely covered by the second portion of the remaining pattern and the second portion of the pixel defining layer.

[0007] In some embodiments, the bank structure may include: a first bank layer in contact with the cathode electrode; and a second bank layer including a protruding end protruding toward the light-emitting area from a side surface of the first bank layer facing the first opening.

[0008] In some embodiments, the second portion of the remaining pattern overlapping with the non-display area includes a first side surface overlapping with the power line in a direction perpendicular to the substrate, and the first side surface may be in contact with the first bank layer and completely covered by the first bank layer.

[0009] In some embodiments, the first portion of the remaining pattern overlapping with the display area and the second portion of the remaining pattern overlapping with the non-display area may be spaced apart.

[0010] In some embodiments, the first portion of the remaining pattern overlapping with the display area may overlap with the protruding end of the second bank layer in a direction perpendicular to the substrate.

[0011] In some embodiments, in a portion overlapping with the non-display area, the second portion of the pixel defining layer may be disposed between the first bank layer and the second portion of the remaining pattern in a direction perpendicular to the substrate.

[0012] In some embodiments, the second portion of the pixel defining layer overlapping with the non-display area may include a first side surface overlapping with the power line in a direction perpendicular to the substrate, and the first side surface may be in contact with the first bank layer and completely covered by the first bank layer.

[0013] In some embodiments, the first portion of the pixel defining layer overlapping with the display area and the second portion of the pixel defining layer overlapping with the non-display area may be separated from each other.

[0014] In some embodiments, the second portion of the remaining pattern and the second portion of the pixel defining layer overlapping with the non-display area may completely cover the dam structure.

[0015] In some embodiments, a side surface of the power connection electrode facing the dam structure may be completely covered by the bank structure, and the bank structure may completely cover the dam structure.

[0016] In some embodiments, the power connection electrode may include a first surface facing the bank structure, and the first surface may include a first portion in contact with the second portion of the remaining pattern and a second portion in contact with the first bank layer.

[0017] In some embodiments, the first surface may be completely covered by the second portion of the remaining pattern and the first bank layer.

[0018] In some embodiments, the first portion of the first surface may overlap with the second portion of the pixel defining layer and the bank structure in a direction perpendicular to the substrate, and the second portion of the first surface may not overlap with the second portion of the pixel defining layer and the second portion of the remaining pattern in a direction perpendicular to the substrate.

[0019] In some embodiments, a voltage applied to the power line may be applied to the cathode electrode through the power connection electrode and the first bank layer.

[0020] In some embodiments, the display device may further include: an organic pattern disposed on a protruding end of the second bank layer, including the same material as the light-emitting layer and separated from the light-emitting layer; and an electrode pattern disposed on the organic pattern, including the same material as the cathode electrode and separated from the cathode electrode.

[0021] In some embodiments, a thin film encapsulation layer is included on the cathode electrode, the electrode pattern, and the bank structure, and the thin film encapsulation layer is arranged to overlap with the display area and the non-display area, and the thin film encapsulation layer may include at least one organic material layer and at least one inorganic material layer.

[0022] A display device according to an embodiment for solving the above technical problem includes: a substrate including a display area and a non-display area surrounding the display area, the display area including a light-emitting area and a non-light-emitting area; a pixel defining layer including a first portion overlapping with the display area and a second portion overlapping with the non-display area, and the first portion is located on the non-light-emitting area of the substrate and defines a first opening; a bank structure located on the pixel defining layer and defining a second opening; a power line located on the non-display area of the substrate and surrounding the display area; a dam structure arranged on the power line and surrounding the display area; and a power connection electrode covering the power line and the dam structure, wherein, in a direction perpendicular to the substrate, a remaining pattern and the second portion of the pixel defining layer are arranged between the bank structure and the power connection electrode, and the bank structure located in the non-light-emitting area and the bank structure located in the non-display area may be integrated in a plane.

[0023] In some embodiments, the bank structure may completely cover the power connection electrode and the dam structure in a plane.

[0024] In some embodiments, the second opening may completely surround the first opening in a plane, and the bank structure may completely surround the second opening in a plane.

[0025] A manufacturing method of a display device according to an embodiment for solving the above technical problems includes the following steps: After forming a substrate including a display area and a non-display area surrounding the display area, and forming a power supply line on the non-display area of the substrate, a dam structure and a power connection electrode connected to the power supply line are formed on the power supply line, and a sacrificial layer is formed to entirely cover the power connection electrode and the dam structure; A photoresist is formed around the dam structure, and a part of the sacrificial layer is removed by performing a first etching process so that a part of the power connection electrode is re-exposed, and then a pixel defining material layer is entirely formed on the sacrificial layer and the power connection electrode; A photoresist is formed around the dam structure, and a part of the pixel defining material layer is removed by performing a second etching process so that a part of the power connection electrode is re-exposed, and a bank structure is entirely formed on the pixel defining material layer and the power connection electrode; A mask is formed at a portion overlapping with the dam structure and the power connection electrode, and a part of the exposed bank structure, the pixel defining material layer, and the sacrificial layer are removed by performing a third etching process, thereby forming a pixel defining layer and a remaining pattern covering a part of the power connection electrode and the dam structure, a side surface of the power connection electrode facing the dam structure is in contact with the remaining pattern, and the power connection electrode can be completely covered by the remaining pattern and the bank structure.

[0026] Specific matters of other embodiments are included in the detailed description and the drawings.

[0027] A display device according to an embodiment includes a power connection electrode connected to a connection electrode in a portion overlapping with a non-display area, and includes a pixel defining layer, a remaining pattern, and a bank structure that completely cover the power connection electrode, thereby being able to solve the corrosion defect of the power connection electrode caused in the manufacturing process of the display device.

[0028] The effects according to the embodiments are not limited by the content of the above examples, and more diverse effects are included in this specification. Description of the Drawings

[0029] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0030] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0031] Figure 3 is showing Figure 2 a schematic side sectional view of the display device.

[0032] Figure 4 is showingFigure 3 Schematic plan view of the display layer.

[0033] Figure 5 It shows the arrangement of Figure 4 light-emitting regions in the display area.

[0034] Figure 6 It is a cross-sectional view taken along Figure 5 X1-X1' in

[0035] Figure 7 It is an enlarged Figure 6 cross-sectional view of the first light-emitting region.

[0036] Figure 8 It is an enlarged Figure 4 plan view of part A.

[0037] Figure 9 It is a cross-sectional view taken along Figure 8 X3-X3' in

[0038] Figure 10 It is an enlarged Figure 9 cross-sectional view of the overlapping part of the power connection electrodes.

[0039] Figure 11 It shows Figure 8 the overlapping structure of the bank structure.

[0040] Figures 12 to 18 It illustrates Figure 9 a cross-sectional view of the manufacturing process of a display device according to an embodiment overlapping with the non-display area.

[0041] Explanation of reference numerals Detailed description of the invention

[0042] Referring to the embodiments described in detail later with reference to the accompanying Figure 1 drawings, the advantages and features of the present invention and the methods for achieving them can be clarified. However, the present invention can be implemented in various different forms and is not limited to the embodiments disclosed below. The purpose of providing these embodiments is only to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the present invention. The present invention is only defined by the scope of the claims.

[0043] When referring to an element or layer being “on” another element or layer, it includes all cases where it is immediately above the other element or layer and cases where there are other layers or other elements interposed therebetween. Similarly, when referring to an element or layer being “below,” “left,” or “right” of another element or layer, it includes cases where it is disposed directly adjacent to the other element or layer or cases where there are other layers or other materials interposed therebetween. Throughout the specification, the same reference numerals refer to the same components.

[0044] Although terms such as “first” and “second” are used to describe various components, these components are clearly not limited by these terms. These terms are only used to distinguish one component from other components. Thus, the first component mentioned below can clearly also be the second component within the technical concept of the present invention.

[0045] Hereinafter, embodiments will be described with reference to the drawings.

[0046] Figure 1 is a schematic perspective view of an electronic device 1 according to an embodiment.

[0047] Reference Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 can refer to all electronic devices that provide a display screen. For example, a television, a notebook computer, a monitor, an advertisement board, an Internet of Things device, a mobile phone, a smart phone, a tablet computer (PC: Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an e-book, a portable multimedia player (PMP: Portable Multimedia Player), a navigator, a game machine, a digital camera, a video camera, etc., which provide a display screen, can be included in the electronic device 1.

[0048] In Figure 1The first direction (X-axis direction), the second direction (Y-axis direction), and the third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) can be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) can be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) can be perpendicular to each other. It can be understood that the first direction (X-axis direction) represents the horizontal direction in the drawing, the second direction (Y-axis direction) represents the vertical direction in the drawing, and the third direction (Z-axis direction) represents the upper direction and the lower direction in the drawing, that is, the thickness direction. In the following description, unless otherwise mentioned, "direction" can refer to all directions towards both sides extending along the direction. In addition, when it is necessary to distinguish between two "directions" extending to both sides, one side is called "one side of the direction" and the other side is called "the other side of the direction" for separate distinction. Taking Figure 1 as a reference, the direction towards which the arrow pointing to the direction faces is called "one side", and the opposite direction is called "the other side".

[0049] Hereinafter, for the sake of convenience in description, when representing the surface of the electronic device 1 or each component constituting the electronic device 1, the display image direction, that is, the surface facing the third direction (Z-axis direction) side is called the "upper surface", and the opposite surface of the said surface is called the "other surface". However, it is not limited thereto, the "upper surface" and the "other surface" of the said component can be respectively called the "front surface" and the "rear surface", or can also be called the "first surface" and the "second surface". And when explaining the relative positions of the components of the electronic device 1, the side of the third direction (Z-axis direction) can be called "upper part", and the other side of the third direction (Z-axis direction) can be called "lower part".

[0050] The shape of the electronic device 1 can be deformed in various ways. For example, the electronic device 1 can have a shape such as a rectangle with a long horizontal length, a rectangle with a long vertical length, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc.

[0051] The electronic device 1 can include a display area DA and a non-display area NDA. The display area DA is an area capable of displaying a screen, and the non-display area NDA is an area that does not display a screen. The display area DA can also be called the effective area, and the non-display area NDA can also be called the non-effective area. The display area DA can generally occupy the center of the electronic device 1.

[0052] Figure 2 is a perspective view showing a display device 10 included in the electronic device 1 according to an embodiment.

[0053] Reference Figure 2, an electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide a screen displayed in the electronic device 1. As an example of the display device 10, an inorganic light-emitting diode display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, a field emission display device, etc. may be cited. Hereinafter, a case where an organic light-emitting diode display device is schematically shown as an example of the display device is shown, but it is not limited thereto, and as long as the same technical concept can be applied, it may also be applied to other display devices.

[0054] The display device 10 may have a planar form similar to that of the electronic device 1. For example, the display device 10 may have a form similar to a rectangle including a short side in the first direction (X-axis direction) and a long side in the second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be smoothly formed in a manner having a curvature, but it is not limited thereto, and may also be formed as right angles. The planar form of the display device 10 is not limited to a quadrilateral, and may be formed similar to other polygons, circles, or ellipses.

[0055] The display device 10 may include a display panel 100, a display driving unit 200, a circuit board 300, and a touch driving unit 400.

[0056] The display panel 100 may include a main area MA and a sub area SBA. The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA disposed around the display area DA.

[0057] The display area DA may emit light from a plurality of light-emitting areas or a plurality of openings described later. The non-display area NDA may be an outer area of the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100.

[0058] The sub area SBA may be an area extending from one side of the main area MA. The sub area SBA may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub area SBA bends, the sub area SBA may overlap the main area MA in the thickness direction (as an example, the third direction (Z-axis direction)). The sub area SBA may include display pads ( Figure 4 "PD" in) connected to the display driving unit 200 and the circuit board 300. In another embodiment, the sub area SBA may be omitted, and the display driving unit 200 and the display pads may be located in the non-display area NDA.

[0059] The display driving unit 200 can output signals and voltages for driving the display panel 100. The display driving unit 200 can supply data voltages to the data lines ( Figure 4 “DL”). In addition, the display driving unit 200 can supply power voltages to the power lines ( Figure 4 “VL1”, “VL2”), and can supply gate control signals to the gate driving unit ( Figure 5 “210”). The display driving unit 200 can be formed as an integrated circuit (IC: Integrated Circuit) and mounted on the display panel 100 in a chip on glass (COG: Chip on Glass) manner, a chip on plastic (COP: Chip on Plastic) manner, or an ultrasonic bonding manner. For example, the display driving unit 200 can be disposed in the sub-region SBA, and can overlap with the main region MA in the thickness direction by the bending of the sub-region SBA. As another example, the display driving unit 200 can be mounted on the circuit board 300.

[0060] The circuit board 300 can be attached to the display pads of the display panel 100 using an anisotropic conductive film (ACF: Anisotropic Conductive Film). The circuit board 300 can be electrically connected to the display pads. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0061] The touch driving unit 400 can be mounted on the circuit board 300. The touch driving unit 400 can be connected to the touch sensor layer ( Figure 3 “180”) of the display panel 100.

[0062] Figure 3 is Figure 2 a schematic cross-sectional view of the display device 10.

[0063] Reference Figure 3 , the display panel 100 can include a display layer DPL, a touch sensor layer 180, and a color filter layer 190. The display layer DPL can include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170.

[0064] The substrate 110 may be a base substrate or a base component. The substrate 110 may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate 110 may include a glass material or a metal material.

[0065] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include a plurality of thin film transistors constituting pixels ( Figure 4 "PX").

[0066] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may be disposed to overlap with the display area DA. The display element layer 150 may include a plurality of light emitting elements ( Figure 6 "ED"). As an example, the display element of one embodiment may include at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode, but is not limited thereto.

[0067] The thin film encapsulation layer 170 may be located on the display element layer 150. The thin film encapsulation layer 170 may be disposed to overlap with the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150, and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0068] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may be disposed to overlap with the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0069] The color filter layer 190 may be disposed on the touch sensor layer 180. The color filter layer 190 may be disposed to overlap with the display area DA and the non-display area NDA. The color filter layer 190 may reduce the reflected light caused by external light by absorbing a part of the light flowing in from the outside of the display device 10. Therefore, the color filter layer 190 may prevent color distortion caused by external light reflection.

[0070] Since the color filter layer 190 is directly disposed on the touch sensor layer 180, the display device 10 may not require a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small. In addition, according to an embodiment, the color filter layer 190 may also be omitted.

[0071] As Figure 3 shown, a part of the display layer DPL overlapping with the sub-region SBA may be bent. When a part of the display layer DPL is bent, the display driving unit 200, the circuit board 300, and the touch driving unit 400 may overlap with the main region MA in the third direction (Z-axis direction).

[0072] Figure 4 is a schematic plan view showing Figure 3 the display layer.

[0073] Referring to Figure 4 , the display layer DPL included in an embodiment may overlap with the display area DA of the main region MA and include a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of second power supply lines VL2.

[0074] Each of the plurality of pixels PX may be defined as the smallest unit that emits light. Each of the plurality of pixels PX may constitute a first light emitting region EA1, a second light emitting region EA2, and a third light emitting region EA3 described later.

[0075] The plurality of gate lines GL may supply gate signals received from the gate driving unit 210 to the plurality of pixels PX. The plurality of gate lines GL may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction) intersecting the first direction (X-axis direction).

[0076] The plurality of data lines DL may supply data voltages received from the display driving unit 200 to the plurality of pixels PX. The plurality of data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0077] A plurality of second power supply lines VL2 can supply the power supply voltage received from the display driving unit 200 to a plurality of pixels PX. Here, the power supply voltage can be at least one of a driving voltage, an initialization voltage, and a reference voltage. The plurality of second power supply lines VL2 can extend in the second direction (Y-axis direction) and can be spaced apart from each other in the first direction (X-axis direction).

[0078] The display layer DPL included in one embodiment may overlap with the non-display area NDA of the main area MA and include a first power supply line VL1, a gate driving unit 210, a plurality of fan-out lines FOL, and a gate control line GCL.

[0079] The gate driving unit 210 can generate a plurality of gate signals based on the gate control signal and can supply the plurality of gate signals to the plurality of gate lines GL in a set order.

[0080] The first power supply line VL1 can surround the display area DA and be disposed in the non-display area NDA. The first power supply line VL1 can supply the power supply voltage received from the display driving unit 200 to a plurality of pixels PX. In addition, the first power supply line VL1 can also be electrically connected to various wirings located in the display area DA.

[0081] The plurality of fan-out lines FOL can extend from the display driving unit 200 to the display area DA. The fan-out lines FOL can supply the data voltage received from the display driving unit 200 to the plurality of data lines DL.

[0082] The gate control line GCL can extend from the display driving unit 200 to the gate driving unit 210. The gate control line GCL can supply the gate control signal received from the display driving unit 200 to the gate driving unit 210. In the drawings, a case where the gate driving unit 210 is only disposed in the non-display area NDA arranged on the left side of the display area DA is schematically shown, but it is not limited thereto. In another embodiment, the display device 10 may include a plurality of gate driving units 210 respectively disposed on the left and right sides of the display area DA.

[0083] The display layer DPL included in one embodiment may overlap with the sub-area SBA and include a display driving unit 200 and a plurality of display pads PD.

[0084] The display driving unit 200 can output signals and voltages for driving a plurality of pixels PX to the plurality of fan-out lines FOL. The display driving unit 200 can supply the data voltage to the data lines DL through the plurality of fan-out lines FOL. Thus, the data voltage can be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX can be controlled. In addition, the display driving unit 200 can supply the gate control signal to the gate driving unit 210 through the gate control line GCL.

[0085] A plurality of display pads PD can be connected to a graphics system via a circuit board 300. The plurality of display pads PD can be connected to the circuit board 300 to receive digital video data and can supply the digital video data to the display driving unit 200.

[0086] Figure 5 It is a plan view showing the arrangement of the light-emitting areas EA in the display area DA.

[0087] Reference Figure 5 , the display area DA of one embodiment may include a plurality of first light-emitting areas EA1 to third light-emitting areas EA3 and a non-light-emitting area NLA. The non-light-emitting area NLA may be arranged to surround the plurality of first light-emitting areas EA1 to third light-emitting areas EA3.

[0088] The non-light-emitting area NLA can block each light emitted from the plurality of first light-emitting areas EA1 to third light-emitting areas EA3. Thus, the non-light-emitting area NLA can assist so that each light emitted from the plurality of first light-emitting areas EA1 to third light-emitting areas EA3 does not mix colors. A pixel defining layer ( Figure 6 "151") and a bank structure ( Figure 6 "160") described later can be arranged in the non-light-emitting area NLA.

[0089] The light-emitting area EA may include a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3 that emit lights of different colors from each other. The first light-emitting area EA1 to the third light-emitting area EA3 may emit red light, green light, and blue light, respectively, and the color of the light emitted in each of the first light-emitting area EA1 to the third light-emitting area EA3 may be different according to the type of the light-emitting element ED described later. As an example, the first light-emitting area EA1 may emit red light of a first color, the second light-emitting area EA2 may emit green light of a second color, and the third light-emitting area EA3 may emit blue light of a third color, but it is not limited thereto. In the drawings, a case where the size and shape of each of the first light-emitting area EA1 to the third light-emitting area EA3 are the same is shown, but it is not limited thereto. The size and shape of each of the first light-emitting area EA1 to the third light-emitting area EA3 can be freely adjusted according to the required characteristics.

[0090] The plurality of first light-emitting areas EA1 to third light-emitting areas EA3 can be defined by a first opening OP1 and a second opening OP2. As an example, the first opening OP1 can be defined by a pixel defining layer ( Figure 6 "151") described later, and the second opening OP2 can be defined by a bank structure ( Figure 6It is defined by "160". On a plane, the second opening OP2 can completely surround the first opening OP1. On a plane, the second opening OP2 can be completely surrounded by the non-light-emitting area NLA.

[0091] In some embodiments, at least one first light-emitting area EA1, at least one second light-emitting area EA2, and at least one third light-emitting area EA3 arranged adjacent to each other can form a pixel group PXG. The pixel group PXG can be the smallest unit that emits white light. However, the type and / or quantity of each of the first light-emitting area EA1 to the third light-emitting area EA3 constituting the pixel group PXG can be variously changed according to the embodiments.

[0092] Figure 6 is a cross-sectional view taken along Figure 5 X1-X1' in Figure 6 shows a schematic cross-section of the display layer DPL overlapping with the display area DA. That is, Figure 6 shows a cross-section of the substrate 110, the thin-film transistor layer 130, the display element layer 150, and the thin-film encapsulation layer 170 of the display device 10 in one embodiment. The substrate 110 has been described, and repeated descriptions are omitted.

[0093] Referring to Figure 6 , the thin-film transistor layer 130 can be arranged on the substrate 110. The thin-film transistor layer 130 can include a first buffer layer 111, a first thin-film transistor TFT1, a gate insulating layer 113, a first interlayer insulating layer 121, a capacitor electrode CPE, a second interlayer insulating layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0094] The first buffer layer 111 can be arranged on the substrate 110. The first buffer layer 111 can include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer 111 can include a plurality of inorganic films stacked alternately.

[0095] The first thin-film transistor TFT1 can be arranged on the first buffer layer 111 and can form a pixel circuit connected to each of the plurality of pixels. As an example, the first thin-film transistor TFT1 can be a driving transistor or a switching transistor of the pixel circuit. The first thin-film transistor TFT1 can include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0096] The active layer ACT may be disposed on the first buffer layer 111. The active layer ACT may overlap with the gate electrode GE in the third direction (Z-axis direction), and may be insulated from the gate electrode GE by the gate insulating layer 113. A part of the active layer ACT may form the source electrode SE and the drain electrode DE by conducting the material of the active layer ACT.

[0097] The gate electrode GE may be disposed on the gate insulating layer 113. The gate electrode GE may overlap with the active layer ACT by placing the gate insulating layer 113 between the gate electrode GE and the active layer ACT.

[0098] The gate insulating layer 113 may be disposed on the active layer ACT. The gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111, and may insulate the active layer ACT from the gate electrode GE. The gate insulating layer 113 may include a contact hole through which the first connection electrode CNE1 passes.

[0099] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer insulating layer 123.

[0100] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 121. The capacitor electrode CPE may overlap with the gate electrode GE in the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0101] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer 123 may be connected to the contact hole of the first interlayer insulating layer 121 and the contact hole of the gate insulating layer 113.

[0102] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the first thin film transistor TFT1 and the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into the contact holes formed in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113 to contact the drain electrode DE of the first thin film transistor TFT1.

[0103] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the underlying structure. The first via layer 125 may include a contact hole through which the second connection electrode CNE2 passes.

[0104] The second connection electrode CNE2 may be disposed on the first via layer 125. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the anode electrode AE.

[0105] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include a contact hole through which the anode electrode AE penetrates.

[0106] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a light emitting element ED, a pixel defining layer 151, a remaining pattern 153, and a bank structure 160.

[0107] The light emitting element ED may include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE. The light emitting element ED may include a first light emitting element ED1 disposed in a first light emitting region EA1, a second light emitting element ED2 disposed in a second light emitting region EA2, and a third light emitting element ED3 disposed in a third light emitting region EA3.

[0108] The first light emitting element ED1 to the third light emitting element ED3 may emit lights of different colors from each other according to the materials of the first light emitting layer EL1 to the third light emitting layer EL3. For example, the first light emitting element ED1 may emit red light of a first color, the second light emitting element ED2 may emit green light of a second color, and the third light emitting element ED3 may emit blue light of a third color.

[0109] The anode electrode AE may be disposed on the second via layer 127. The anode electrode AE may be electrically connected to the drain electrode DE of the first thin film transistor TFT1 through the first connection electrode CNE1 and the second connection electrode CNE2.

[0110] The anode electrode AE may include a first anode electrode AE1 disposed in the first light emitting region EA1, a second anode electrode AE2 disposed in the second light emitting region EA2, and a third anode electrode AE3 disposed in the third light emitting region EA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be spaced apart from each other on the second via layer 127.

[0111] In an exemplary embodiment, the anode electrode AE may have a layer stack structure formed by stacking a layer of a material with a high work function, such as indium-tin-oxide (ITO: Indium-Tin-Oxide), indium-zinc-oxide (IZO: Indium-Zinc-Oxide), zinc oxide (ZnO: Zinc Oxide), indium oxide (Indium Oxide; In 2 O 3 ), and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), or a mixture thereof. As an example, the anode electrode AE may have a multilayer structure such as ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, but is not limited thereto.

[0112] A pixel defining layer 151 may be disposed on the second via layer 127 and the anode electrode AE. As described above, the pixel defining layer 151 may define a first opening OP1 for forming a light emitting region EA. The pixel defining layer 151 may be disposed on the entire surface of the second via layer 127 and may expose a part of the upper surface of the anode electrode AE. For example, the pixel defining layer 151 may expose the anode electrode AE at a portion overlapping with the first opening OP1, and the light emitting layer EL may be directly disposed on the anode electrode AE at a portion overlapping with the first opening OP1.

[0113] The pixel defining layer 151 may include an inorganic insulating material. As an example, the pixel defining layer 151 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0114] A bank structure 160 may be disposed on the pixel defining layer 151. The bank structure 160 may define a second opening OP2 for forming a light emitting region EA, and the light emitting element ED of the display device 10 may be disposed to overlap with the second opening OP2. The bank structure 160 may include a first bank layer 161 and a second bank layer 163, and the first bank layer 161 and the second bank layer 163 include different metal materials and structures and perform different functions. The bank structure 160 will be described later.

[0115] The light-emitting layer EL can be disposed on the anode electrode AE. The light-emitting layer EL can be an organic light-emitting layer formed using an organic material and can be formed on the anode electrode AE by a deposition process. For the light-emitting layer EL, if the first thin-film transistor TFT1 applies a predetermined voltage to the anode electrode AE and the cathode electrode CE receives a common voltage or a cathode voltage, holes and electrons move to the light-emitting layer EL through the hole transport layer and the electron transport layer respectively, and the holes and electrons can combine with each other in the light-emitting layer EL to emit light.

[0116] The light-emitting layer EL can include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 disposed in the first light-emitting region EA1 to the third light-emitting region EA3 respectively. As an example, the first light-emitting layer EL1 can be a light-emitting layer that emits red light of a first color, the second light-emitting layer EL2 can be a light-emitting layer that emits green light of a second color, and the third light-emitting layer EL3 can be a light-emitting layer that emits blue light of a third color, but is not limited thereto.

[0117] In some embodiments, the anode electrode AE and the pixel defining layer 151 can be arranged to be separated in the third direction (Z-axis direction). The light-emitting layer EL and the remaining pattern 153 can be arranged in the portion where the anode electrode AE is separated from the pixel defining layer 151. The remaining pattern 153 can be the residue of a temporary protective layer that is temporarily formed on the anode electrode AE during the manufacturing process of the display device 10 and then removed.

[0118] The cathode electrode CE can include a transparent conductive material so that the light generated in the light-emitting layer EL can be emitted. The cathode electrode CE can receive a common voltage or a low-potential voltage. If the anode electrode AE receives a voltage corresponding to the data voltage and the cathode electrode CE receives a low-potential voltage, a potential difference is formed between the anode electrode AE and the cathode electrode CE, so that the light-emitting layer EL can emit light.

[0119] In an exemplary embodiment, the cathode electrode CE can include materials with a small work function such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or their compounds or mixtures (such as a mixture of Ag and Mg, etc.), and materials having a multilayer structure such as LiF / Ga (a stacked structure of LiF and Ga), LiF / Al (a stacked structure of LiF and Al). The cathode electrode CE can also include a transparent metal oxide layer disposed on the material layer with a small work function.

[0120] The cathode electrode CE may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3 disposed in a first light-emitting region EA1 to a third light-emitting region EA3, respectively. The first cathode electrode CE1 may be disposed on the first light-emitting layer EL1 in the first light-emitting region EA1, the second cathode electrode CE2 may be disposed on the second light-emitting layer EL2 in the second light-emitting region EA2, and the third cathode electrode CE3 may be disposed on the third light-emitting layer EL3 in the third light-emitting region EA3.

[0121] The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be disposed at intervals. The spaced-apart cathode electrodes CE may be electrically connected through the first bank layer 161 of the bank structure 160 without being directly connected.

[0122] On the bank structure 160, a plurality of first organic patterns ELP1 to third organic patterns ELP3 and first electrode patterns CEP1 to third electrode patterns CEP3 may be disposed in a manner surrounding the periphery of the first opening OP1.

[0123] The plurality of first organic patterns ELP1 to third organic patterns ELP3 may be located on the second bank layer 163. The first organic patterns ELP1 to third organic patterns ELP3 may each include the same material as the first light-emitting layer EL1 to the third light-emitting layer EL3. The first organic pattern ELP1 may include the same material as the first light-emitting layer EL1, the second organic pattern ELP2 may include the same material as the second light-emitting layer EL2, and the third organic pattern ELP3 may include the same material as the third light-emitting layer EL3. The first organic patterns ELP1 to third organic patterns ELP3 may be traces formed by being disconnected because the bank structure 160 includes a protruding end TIP and cannot be connected to the first light-emitting layer EL1 to the third light-emitting layer EL3.

[0124] The plurality of first electrode patterns CEP1 to third electrode patterns CEP3 may be disposed on the first organic patterns ELP1 to third organic patterns ELP3. The arrangement relationship between the first electrode patterns CEP1 to third electrode patterns CEP3 and the first organic patterns ELP1 to third organic patterns ELP3 may be the same as the arrangement relationship between the first light-emitting layer EL1 to the third light-emitting layer EL3 and the first cathode electrode CE1 to the third cathode electrode CE3. The first electrode patterns CEP1 to third electrode patterns CEP3 may include the same material as the first cathode electrode CE1 to the third cathode electrode CE3. The first electrode patterns CEP1 to third electrode patterns CEP3 may be traces formed by being disconnected because the bank structure 160 includes a protruding end TIP and cannot be connected to the first cathode electrode CE1 to the third cathode electrode CE3.

[0125] The thin film encapsulation layer 170 may be disposed on the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic film to protect the display element layer 150 from foreign substances such as dust.

[0126] In an exemplary embodiment, the thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 stacked in sequence. The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 disposed therebetween may be an organic encapsulation layer.

[0127] The first encapsulation layer 171 may include a first inorganic layer 171-1 to a third inorganic layer 171-3. The first inorganic layer 171-1 to the third inorganic layer 171-3 may be arranged to cover the light emitting element ED and the bank structure 160. Since the first inorganic layer 171-1 to the third inorganic layer 171-3 may be formed by a chemical vapor deposition (CVD) process, the first inorganic layer 171-1 to the third inorganic layer 171-3 may be formed to have a uniform thickness along the contour of the lower structure.

[0128] The first inorganic layer 171-1 to the third inorganic layer 171-3 may be set to overlap with the first light emitting region EA1 to the third light emitting region EA3, respectively. As an example, the first inorganic layer 171-1 may overlap with the first light emitting region EA1 to cover the first cathode electrode CE1 and the first electrode pattern CEP1, the second inorganic layer 171-2 may overlap with the second light emitting region EA2 to cover the second cathode electrode CE2 and the second electrode pattern CEP2, and the third inorganic layer 171-3 may overlap with the third light emitting region EA3 to cover the third cathode electrode CE3 and the third electrode pattern CEP3. The first inorganic layer 171-1 to the third inorganic layer 171-3 may overlap with the non-light emitting region NLA, respectively, to expose the bank structure 160, and are spaced apart from each other.

[0129] Although the first inorganic layer 171-1 to the third inorganic layer 171-3 are shown in the drawings as being formed in the same layer, the first inorganic layer 171-1 to the third inorganic layer 171-3 may be formed by different processes, respectively. Exemplarily, the first inorganic layer 171-1 may be formed after the first cathode electrode CE1 is formed, the second inorganic layer 171-2 may be formed after the second cathode electrode CE2 is formed, and the third inorganic layer 171-3 may be formed after the third cathode electrode CE3 is formed.

[0130] Each of the first encapsulation layers 171 may include more than one type of inorganic insulator. The inorganic insulator may include aluminum oxide (Al 2 O3 ), titanium oxide (Ti 2 O 3 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and silicon oxynitride (Si 2 N 2 O).

[0131] The second encapsulation layer 173 may be located on the first encapsulation layer 171. The second encapsulation layer 173 may planarize the step difference formed by the first encapsulation layer 171.

[0132] The second encapsulation layer 173 may include a polymer-based material. The polymer-based material may include acrylic resins, epoxy resins, polyimide resins, and polyethylene resins. For example, the second encapsulation layer 173 may include an acrylic resin, such as polymethyl methacrylate, polyacrylic acid, etc. The second encapsulation layer 173 may be formed by curing a monomer or coating a polymer.

[0133] The third encapsulation layer 175 may be located on the second encapsulation layer 173. The third encapsulation layer 175 may include the same material as the first encapsulation layer 171. The third encapsulation layer 175 may prevent oxygen or moisture from penetrating into the second encapsulation layer 173.

[0134] Figure 7 is an enlarged Figure 6 cross-sectional view of the first light-emitting region EA1 in

[0135] Referring to Figure 7 , the pixel defining layer 151 may be located on the second via layer 127 and the first anode electrode AE1. The pixel defining layer 151 may be arranged to overlap with the second opening OP2 and be spaced apart from the first anode electrode AE1 in the third direction (Z-axis direction). A remaining pattern 153 may be arranged between the pixel defining layer 151 and the first anode electrode AE1. The remaining pattern 153 may be arranged to be in contact with both sides of the first light-emitting layer EL1 in the first direction (X-axis direction) and may overlap with the protruding end TIP of the bank structure 160 in the third direction (Z-axis direction).

[0136] The bank structure 160 may be located on the pixel defining layer 151. The bank structure 160 may include a first bank layer 161 and a second bank layer 163 that include different metal materials and structures from each other and perform different functions.

[0137] The first bank layer 161 may be arranged to be adjacent to the pixel defining layer 151. The first bank layer 161 may include a metal with high conductivity. As an example, it may include aluminum (Al).

[0138] In some embodiments, the first bank layer 161 may include a side surface 161c facing the first opening OP1. The side surface 161c of the first bank layer 161 may be an inclined surface. In other words, the side surface 161c of the first bank layer 161 may be inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). That is, the side surface 161c of the first bank layer 161 may include a structure that is recessed in the first direction (X-axis direction) compared to the pixel defining layer 151.

[0139] The side surface 161c of the first bank layer 161 in one embodiment may be adjacent to the first light emitting layer EL1 and the first cathode electrode CE1. In the display device 10 of one embodiment, since the bank structure 160 includes a protruding end TIP, a fine metal mask may not be used in the manufacturing process, and the first light emitting layer EL1 and the first cathode electrode CE1 may be formed by a deposition and photolithography process. Therefore, the first light emitting layer EL1 and the first cathode electrode CE1 may be adjacent to the side surface 161c of the first bank layer 161 at a portion overlapping with the second opening OP2.

[0140] The first cathode electrode CE1 in one embodiment may cover the side surface 161c of the first bank layer 161 more than the first light emitting layer EL1. As described above, the first cathode electrode CE1 and the first bank layer 161 may be electrically connected, and the larger the area where the first cathode electrode CE1 is adjacent to the side surface 161c of the first bank layer 161, the lower the resistance of the display device 10.

[0141] In some embodiments, the side surface 161c of the first bank layer 161 may include a first portion 161c1, a second portion 161c2, and a third portion 161c3 according to the adjacent structure. The first portion 161c1 may be a portion adjacent to the first light emitting layer EL1, the second portion 161c2 may be a portion adjacent to the first cathode electrode CE1, and the third portion 161c3 may be a portion adjacent to the first inorganic layer 171-1.

[0142] The second portion 161c2 may be arranged between the first portion 161c1 and the third portion 161c3, and the area Wc2 of the second portion 161c2 may be adjusted according to the manufacturing method of the first cathode electrode CE1. When the area Wc2 of the second portion 161c2 is adjusted, the area Wc3 of the third portion 161c3 may also be adjusted. As an example, when the area Wc2 of the second portion 161c2 increases, the area Wc3 of the third portion 161c3 may decrease.

[0143] The second bank layer 163 of an embodiment may be located on the first bank layer 161. The second bank layer 163 may include a material having an etching rate lower than that of the first bank layer 161. As an example, the second bank layer 163 may include titanium (Ti). The second bank layer 163 may have a protruding end TIP that protrudes toward the first light-emitting region EA1 more than the side surface 161c of the first bank layer 161. In the display device 10 of an embodiment, since the second bank layer 163 includes the protruding end TIP, the first light-emitting element ED1 may be formed without a fine metal mask in the manufacturing process of the display device 10. Repeated descriptions other than this are omitted.

[0144] The first organic pattern ELP1 may be located on the second bank layer 163. The first organic pattern ELP1 may be located in the second opening OP2 at a portion overlapping the protruding end TIP of the second bank layer 163. In addition, the first organic pattern ELP1 may cover the second bank layer 163 in a portion overlapping the non-light-emitting region NLA.

[0145] In the manufacturing process of the display device 10, the first organic pattern ELP1 may first cover the entire surface of the second bank layer 163, and then be formed by etching a part of it through a subsequent etching process. A groove portion TP may be formed on the side surface of the etched first organic pattern ELP1, and the groove portion TP may be covered by the second encapsulation layer 173.

[0146] The first electrode pattern CEP1 may be located on the first organic pattern ELP1. The first electrode pattern CEP1 may be located in the second opening OP2 at a portion overlapping the protruding end TIP of the second bank layer 163. In addition, the first electrode pattern CEP1 may cover the first organic pattern ELP1 in a portion overlapping the non-light-emitting region NLA.

[0147] In the manufacturing process of the display device 10, the first electrode pattern CEP1 may first cover the entire surface of the first organic pattern ELP1, and then be formed by etching a part of it through a subsequent etching process. A groove portion TP may be formed on the side surface of the etched first electrode pattern CEP1, and the groove portion TP may be covered by the second encapsulation layer 173.

[0148] The first inorganic layer 171-1 may cover the first light-emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer 171-1 may be arranged to be in contact with the first cathode electrode CE1 and the side surface 161c of the first bank layer 161 in the second opening OP2, and may cover the protruding end TIP of the second bank layer 163. In addition, the first inorganic layer 171-1 may cover the first electrode pattern CEP1 in a portion overlapping the non-light-emitting region NLA.

[0149] In the manufacturing process of the display device 10, the first inorganic layer 171-1 may first cover the entire surface of the first electrode pattern CEP1 and then be formed by etching a part thereof through a subsequent etching process. A trench portion TP may be formed in a part of the etched first inorganic layer 171-1, and the trench portion TP may be covered by the second encapsulation layer 173.

[0150] The second encapsulation layer 173 may planarize the step difference formed by the first inorganic layer 171-1 in a portion overlapping with the first opening OP1, and may cover the first inorganic layer 171-1 and the second bank layer 163 in portions overlapping with the second opening OP2 and the non-light-emitting region NLA. Repetitive descriptions other than this are omitted.

[0151] Figure 8 is an enlarged Figure 4 plan view of part A. Figure 9 is a cross-sectional view taken along Figure 8 X3-X3' in

[0152] Reference Figure 8 and Figure 9 , a display device 10 according to an embodiment may include a light-emitting element ED overlapping with the light-emitting region EA of the display region DA and a bank structure 160 overlapping with the non-light-emitting region NLA, and may include a gate driving unit 210, a first power line VL1, a plurality of hole patterns OH, a power connection electrode CAE, and a dam structure DM in a portion overlapping with the non-display region NDA. Repetitive descriptions of the structures overlapping with the light-emitting region EA and the non-light-emitting region NLA are omitted.

[0153] The gate driving unit 210 may be disposed in a portion overlapping with the non-display region NDA and may be disposed between the first thin-film transistor TFT1 and the first power line VL1. The gate driving unit 210 may include a second thin-film transistor TFT2 and a plurality of gate driving electrodes 211, 212. The second thin-film transistor TFT2 may be disposed on the first buffer layer 111 and may constitute a driving circuit of the gate driving unit 210. The second thin-film transistor TFT2 may include the same structure and characteristics as the first thin-film transistor TFT1. As an example, the second thin-film transistor TFT2 may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE, and the gate electrode GE may be disposed on the gate insulating layer 113, and the gate electrode GE may overlap with the active layer ACT with the gate insulating layer 113 interposed therebetween.

[0154] A plurality of first gate driving electrodes 211 may be disposed on the second interlayer insulating layer 123. The plurality of first gate driving electrodes 211 may be disposed on the same layer as the first connection electrode CNE1 of the display area DA. The plurality of first gate driving electrodes 211 may function as connection electrodes in the circuit of the gate driving unit 210.

[0155] A plurality of second gate driving electrodes 212 may be disposed on the first via layer 125. The plurality of second gate driving electrodes 212 may be disposed on the same layer as the second connection electrode CNE2 of the display area DA. The plurality of second gate driving electrodes 212 may function as connection electrodes in the circuit of the gate driving unit 210.

[0156] The first power line VL1 may be disposed outside the gate driving unit 210 in a portion overlapping with the non-display area NDA. The first power line VL1 is disposed on the second interlayer insulating layer 123, and a part of the upper surface of the first power line VL1 may be exposed through a hole penetrating the first via layer 125 and the second via layer 127. The exposed upper surface of the first power line VL1 may be in contact with the connection electrode BE.

[0157] A plurality of hole patterns OH may be disposed between the gate driving unit 210 and the first power line VL1, and a part of the plurality of hole patterns OH may overlap with the gate driving unit 210. In the process of manufacturing the display device 10, the plurality of hole patterns OH may form an exhaust path for gas generated in the first via layer 125 and the second via layer 127.

[0158] The connection electrode BE may be disposed in a portion overlapping with the non-display area NDA and may be disposed on the first power line VL1. Although not shown in the drawings, the connection electrode BE may be disposed in a shape similar to that of the first power line VL1 in a plane and extend in a manner surrounding the display area DA. The connection electrode BE may be disposed outside the gate driving unit 210 without overlapping with the gate driving unit 210.

[0159] The connection electrode BE may be disposed on the first via layer 125 and may be in direct contact with the first power line VL1 through a hole penetrating the first via layer 125. The connection electrode BE may be disposed between the first power line VL1 and the power connection electrode CAE and function as a bridge for electrically connecting them to each other.

[0160] The power connection electrode CAE may be disposed in a portion overlapping with the non-display area NDA and may overlap with the gate driving unit 210, the connection electrode BE, and the first power line VL1. As Figure 8 shown, in a plane, the power connection electrode CAE may completely cover the first power line VL1 and the gate driving unit 210.

[0161] The power connection electrode CAE may be disposed on the second via layer 127 and may be disposed on the same layer as the anode electrode AE of the display area DA. The power connection electrode CAE may separate the pixel defining layer 151 from the anode electrode AE in the first direction (X-axis direction).

[0162] The power connection electrode CAE may be in direct contact with the connection electrode BE at a portion overlapping with the hole HOL penetrating the first via layer 125 and the second via layer 127. The power connection electrode CAE may be disposed between the connection electrode BE and the first bank layer 161 and serve as a bridge for electrically connecting them to each other. That is, the power connection electrode CAE may be electrically connected to the first power line VL1. Therefore, the voltage applied through the first power line VL1 may be transmitted to the cathode electrode CE disposed in the light emitting area EA through the connection electrode BE, the power connection electrode CAE, and the first bank layer 161.

[0163] The dam structure DM of an embodiment may include a first dam DM1 and a second dam DM2. In a plane, the first dam DM1 and the second dam DM2 may be disposed in a portion overlapping with the non-display area NDA and may surround the display area DA. In a plane, the first dam DM1 may be disposed close to the display area DA to surround the display area DA, and in a plane, the second dam DM2 may surround the first dam DM1. The first dam DM1 and the second dam DM2 can prevent the overflow of the second encapsulation layer 173.

[0164] In some embodiments, the first dam DM1 may include a first sub-dam SDM1 and a second sub-dam SDM2, and the second dam DM2 may include a first sub-dam SDM1, a second sub-dam SDM2, and a third sub-dam SDM3. The first sub-dam SDM1 may include the same material as the first via layer 125 and be disposed on the same layer as the first via layer 125. The second sub-dam SDM2 may include the same material as the second via layer 127 and be disposed on the same layer as the second via layer 127. The third sub-dam SDM3 is disposed on the second sub-dam SDM2 and may include the same material as the second sub-dam SDM2. The third sub-dam SDM3 may be at the same height as the pixel defining layer 151 disposed in the display area DA. In another embodiment, the third sub-dam SDM3 may also include the same material as the pixel defining layer 151.

[0165] The height of the first dam DM1 of an embodiment may be lower than the height of the second dam DM2, but is not limited thereto. The height of the first dam DM1 may be substantially the same as or higher than the height of the second dam DM2.

[0166] In a portion overlapping with the non-display area NDA, the remaining pattern 153 may be disposed on the dam structure DM and the power connection electrode CAE. In one embodiment, the remaining pattern 153 may be disposed on the power connection electrode CAE in a portion overlapping with the hole HOL that penetrates through the first via layer 125 and the second via layer 127, and may extend therefrom and be disposed on the dam structure DM. A portion of the remaining pattern 153 in one embodiment may be disposed to be in contact with the power connection electrode CAE, and another portion of the remaining pattern 153 may be in contact with the dam structure DM.

[0167] The remaining pattern 153 disposed to overlap with the display area DA and the remaining pattern 153 disposed to overlap with the non-display area NDA are formed integrally in the manufacturing process of the display device 10, and then a portion of the remaining pattern 153 is removed in a subsequent etching process so that the two can be separated from each other. Therefore, the remaining pattern 153 disposed to overlap with the display area DA and the remaining pattern 153 disposed to overlap with the non-display area NDA may include the same material and may be separated from each other.

[0168] In a portion overlapping with the non-display area NDA, the pixel defining layer 151 in one embodiment may be disposed on the remaining pattern 153. The pixel defining layer 151 disposed to overlap with the display area DA and the pixel defining layer 151 disposed to overlap with the non-display area NDA may be separated in the first direction (X-axis direction). The pixel defining layer 151 in one embodiment may completely cover the remaining pattern 153 and the dam structure DM in a portion overlapping with the non-display area NDA.

[0169] The bank structure 160 may be disposed on the power connection electrode CAE and the pixel defining layer 151 in a portion overlapping with the non-display area NDA. The bank structure 160 disposed to overlap with the display area DA and the bank structure 160 disposed to overlap with the non-display area NDA may be integral. However, as Figure 9 shown, in a cross section, the bank structure 160 may separate the light-emitting elements ED therebetween in the first direction (X-axis direction) in a portion overlapping with the display area DA.

[0170] In a portion overlapping with the non-display area NDA, the first bank layer 161 may completely cover the power connection electrode CAE and the pixel defining layer 151, and may be in contact with the power connection electrode CAE and the pixel defining layer 151. In addition, in a portion overlapping with the non-display area NDA, the first bank layer 161 may completely cover the gate driving unit 210, the connection electrode BE, the first power line VL1, the remaining pattern 153, the first dam DM1, and the second dam DM2 in the third direction (Z-axis direction).

[0171] In a portion overlapping with the non-display area NDA, the second dam layer 163 may cover along the contour of the first dam layer 161. In a portion overlapping with the non-display area NDA, the second dam layer 163 may overlap with the gate driving unit 210, the power connection electrode CAE, the connection electrode BE, the first power line VL1, the remaining pattern 153, the pixel defining layer 151, the first dam DM1, and the second dam DM2 in the third direction (Z-axis direction).

[0172] The first encapsulation layer 171 of one embodiment may cover the light-emitting element ED, the organic pattern ELP, and the electrode pattern CEP in a portion overlapping with the display area DA, and extend therefrom to cover along the contour formed by the second dam layer 163 in a portion overlapping with the non-display area NDA. The first encapsulation layer 171 may cover the dam structure DM and may extend to the outermost edge of the display device 10. Repetitive descriptions other than this are omitted.

[0173] The second encapsulation layer 173 of one embodiment may flatten the step difference formed by the first encapsulation layer 171 in a portion overlapping with the display area DA, and extend therefrom to be disposed up to a portion overlapping with a part of the first dam DM1 in a portion overlapping with the non-display area NDA. The second encapsulation layer 173 of one embodiment may be prevented from overflowing to the outer contour of the display device 10 by the step difference of the dam structure 160 formed by overlapping with the second dam DM2.

[0174] The third encapsulation layer 175 of one embodiment may cover along the contour formed by the second encapsulation layer 173 and the first encapsulation layer 171. The third encapsulation layer 175 of one embodiment may cover the dam structure DM and may extend to the outermost edge of the display device 10. Repetitive descriptions other than this are omitted.

[0175] Figure 10 is an enlarged Figure 9 cross-sectional view of a portion overlapping with the power connection electrode CAE in

[0176] Reference Figure 10 , the power connection electrode CAE of one embodiment may include a first side surface c1, a second side surface c2, and an upper surface c3. The first side surface c1 of one embodiment may be disposed toward a portion overlapping with the first dam DM1 or the dam structure DM, and may be in contact with the remaining pattern 153 disposed overlapping with the non-display area NDA. The first side surface c1 of the power connection electrode CAE of one embodiment is completely covered by the remaining pattern 153 and the pixel defining layer 151, thereby solving the corrosion defect caused by the penetration of the etching solution in the manufacturing process of the display device 10.

[0177] The second side surface c2 of an embodiment may face the first side surface c1 and may be in contact with the pixel defining layer 151. The second side surface c2 of an embodiment may be completely covered by the pixel defining layer 151 disposed to overlap with the non-display area NDA.

[0178] The upper surface c3 of an embodiment may be disposed along the direction toward the bank structure 160 and may be in contact with the first bank layer 161 and the remaining pattern 153. The upper surface c3 of an embodiment may be divided into a first part c3a and a second part c3b according to the contacting structure. The first part c3a may be in contact with the remaining pattern 153 and may overlap with the pixel defining layer 151 and the bank structure 160 in the third direction (Z-axis direction). In addition, the second part c3b may be in contact with the first bank layer 161 and may not overlap with the pixel defining layer 151 and the remaining pattern 153 in the third direction (Z-axis direction).

[0179] In some embodiments, the remaining pattern 153 that overlaps with the non-display area NDA of an embodiment may include a side surface 153c in a portion overlapping with the hole HOL. The remaining pattern 153 that overlaps with the non-display area NDA may be formed to cover the entire upper surface c3 of the power connection electrode CAE in the manufacturing process of the display device 10, and then a part thereof may be removed by a subsequent etching process. Thus, it may be formed into Figure 10 the form shown. The side surface 153c included in the remaining pattern 153 may be the result of performing the above-described etching process. The side surface 153c of the remaining pattern 153 may be in contact with the first bank layer 161 and may be completely covered by the first bank layer 161.

[0180] In some embodiments, the pixel defining layer 151 that overlaps with the non-display area NDA of an embodiment may include a side surface 151c in a portion overlapping with the hole HOL. The pixel defining layer 151 that overlaps with the non-display area NDA may be first formed to cover the entire upper surface c3 of the power connection electrode CAE in the manufacturing process of the display device 10, and then a part thereof may be removed by a subsequent etching process. Thus, it may be formed into Figure 10 the form shown. The side surface 151c included in the pixel defining layer 151 may be the result of performing the above-described etching process. The side surface 151c of the pixel defining layer 151 may be in contact with the first bank layer 161 and may be completely covered by the first bank layer 161. The manufacturing process will be described later.

[0181] In one embodiment, the first bank layer 161 overlapping the non-display area NDA may be in contact with the upper surface c3 of the power connection electrode CAE, the side surface 153c of the remaining pattern 153, and the side surface 151c of the pixel defining layer 151, and may completely cover the upper surface c3 of the power connection electrode CAE, the side surface 153c of the remaining pattern 153, and the side surface 151c of the pixel defining layer 151. Since the first bank layer 161 in one embodiment is in contact with and covers the upper surface c3 of the power connection electrode CAE, it is possible to solve the corrosion defect of the power connection electrode CAE caused by the penetration of the etching solution in the manufacturing process of the display device 10. Repeated descriptions other than this are omitted.

[0182] Figure 11 is a plan view showing Figure 8 the overlapping structure of the bank structure 160 in

[0183] Reference Figure 11 , in the portion overlapping the display area DA in the plane, the bank structure 160 is disposed in the non-light-emitting area NLA and may completely surround the light-emitting area EA. In addition, in the portion overlapping the non-display area NDA in the plane, the bank structure 160 may completely cover the gate driving unit 210, the first power line VL1, the first dam DM1, and the second dam DM2.

[0184] The bank structure 160 disposed in the display area DA in the plane and the bank structure 160 disposed in the non-display area NDA may be integrated.

[0185] Figures 12 to 18 is a cross-sectional view illustrating Figure 9 the manufacturing process of the display device 10 according to one embodiment overlapping the non-display area NDA in Figures 12 to 18 . For ease of explanation,

[0186] Reference Figure 12, a sacrificial layer SFL is formed over the entire surface of the second via layer 127, the power connection electrode CAE, and the dam structure DM. The sacrificial layer SFL may be disposed in contact with the power connection electrode CAE and the dam structure DM.

[0187] The sacrificial layer SFL may include an oxide semiconductor. As an example, the sacrificial layer SFL may be formed of at least one of indium-gallium-zinc oxide (IGZO: Indium Gallium Zinc Oxide), zinc-tin oxide (ZTO: Zinc Tin Oxide), indium-tin oxide (IZO: Indium Tin Oxide), etc.

[0188] Then, referring to Figure 13 , a photoresist PR is formed by overlapping with the dam structure DM and the peripheral portion of the dam structure DM, and a first etching process is performed. As an example, the first etching process may be performed using wet etching. In this process, a part of the sacrificial layer SFL overlapping with the photoresist PR may be retained, and a part of the sacrificial layer SFL not overlapping with the photoresist PR may be removed. Thereby, a part of the power connection electrode CAE overlapping with the second via layer 127 and the via hole HOL may be re-exposed.

[0189] Next, referring to Figure 14 and Figure 15 , a pixel defining material layer 151L is formed over the entire surface of the sacrificial layer SFL and the exposed power connection electrode CAE retained in the foregoing process. The pixel defining material layer 151L may be disposed in contact with the sacrificial layer SFL and the power connection electrode CAE.

[0190] Next, a photoresist PR is formed in a portion overlapping with the dam structure DM and the peripheral portion of the dam structure DM, and a second etching process is performed. As an example, the second etching process may be performed using dry etching. When the second etching process is performed as a dry etching process, the pixel defining material layer 151L may be etched isotropically. Through this process, trench portions TP may be formed on the side surface of the sacrificial layer SFL and on the side surface of the pixel defining material layer 151L overlapping with the via hole HOL.

[0191] In this process, a part of the pixel defining material layer 151L overlapping with the photoresist PR may be retained, and a part of the pixel defining material layer 151L not overlapping with the photoresist PR may be removed. Thereby, in a portion overlapping with the non-display area NDA, the sacrificial layer SFL of one embodiment may be covered by the pixel defining material layer 151L. In this process, a part of the power connection electrode CAE overlapping with the second via layer 127 and the via hole HOL may be re-exposed.

[0192] Through the above process, the end of the power connection electrode CAE facing the other side of the first direction (X-axis direction) and the upper surface of the power connection electrode CAE can be in contact with the sacrificial layer SFL, and can be completely covered by the sacrificial layer SFL and the pixel defining material layer 151L. Thus, the display device 10 according to an embodiment can solve the corrosion defect of the power connection electrode CAE, the connection electrode BE, and the first power line VL1 caused by the penetration of the etching solution used in the manufacturing process.

[0193] In addition, through this process, a pixel defining layer 151 can be formed to cover the end of the power connection electrode CAE on one side in the first direction (X-axis direction). Although not shown in Figure 15 , the pixel defining layer 151 covering the end of the power connection electrode CAE on one side in the first direction (X-axis direction) can be integral with the pixel defining layer 151 formed in the Figure 9 light emitting region EA shown.

[0194] In another embodiment, the first etching process and the second etching process can be combined and performed. In this case, the entire pixel defining material layer 151L is formed on the sacrificial layer SFL formed over the entire surface, and then by alternately performing a wet etching process and a dry etching process, a part of the sacrificial layer SFL and a part of the pixel defining material layer 151L can be etched simultaneously.

[0195] Then, referring to Figure 16 , a first bank material layer 161L and a second bank material layer 163L are sequentially stacked on the pixel defining material layer 151L and the power connection electrode CAE. The first bank material layer 161L and the second bank material layer 163L can be disposed over the entire surface of the pixel defining material layer 151L and the power connection electrode CAE. The first bank material layer 161L can be in contact with the trench portion TP formed by the sacrificial layer SFL and the pixel defining material layer 151L, and can completely cover the trench portion TP. In addition, the first bank material layer 161L can be in contact with the upper surface of the power connection electrode CAE exposed by the foregoing process, and can completely cover the upper surface of the power connection electrode CAE. Thus, the display device 10 according to an embodiment can solve the corrosion defect of the power connection electrode CAE, the connection electrode BE, and the first power line VL1 caused by the penetration of the etching solution used in the manufacturing process.

[0196] Next, referring to Figure 17 and Figure 18, after forming a mask MASK in a portion overlapping the power connection electrode CAE and the dam structure DM, a third etching process for etching the exposed portion of the pixel defining material layer 151L, the sacrificial layer SFL, the first dam material layer 161L, and the second dam material layer 163L is performed. As an example, the third etching process may be performed by a dry etching process, but is not limited thereto.

[0197] In this process, in a portion overlapping the non-display area NDA, the pixel defining material layer 151L may be formed in the form of the pixel defining layer 151 as Figure 9 shown, and the sacrificial layer SFL may be formed in the form of the remaining pattern 153. In addition, the first dam material layer 161L may be formed in the form of the first dam layer 161, and the second dam material layer 163L may be formed in the form of the second dam layer 163.

[0198] Next, a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 are sequentially formed on the second dam layer 163, thereby forming a thin film encapsulation layer 170.

[0199] As described above, the display device 10 of an embodiment includes the remaining pattern 153 and the pixel defining layer 151 that cover a part of the power connection electrode CAE in a portion overlapping the non-display area NDA, and includes the dam structure 160 that completely covers the power connection electrode CAE in a portion overlapping the non-display area NDA, thereby solving the corrosion defect of the power connection electrode CAE, the connection electrode BE, and the first power line VL1 caused by the penetration of the etching solution used in the manufacturing process of the display device 10.

[0200] Above, embodiments of the present invention have been described with reference to the drawings, but those of ordinary skill in the art to which the present invention pertains can understand that, without changing the technical concept or essential features of the present invention, it can be implemented in other specific forms. Therefore, it should be understood that the above embodiments are exemplary in all aspects and not restrictive.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area surrounding the display area, wherein the display area comprises a light-emitting area and a non-light-emitting area; an anode electrode, located on the light emitting area of ​​the substrate; a pixel defining layer, comprising a first portion overlapping the display area and a second portion overlapping the non-display area, wherein the first portion is located on the non-luminescent area of ​​the substrate and defines a first opening; A bank structure is located on the pixel defining layer and defines a second opening; a remaining pattern, comprising a first portion overlapping the display area and a second portion overlapping the non-display area, wherein the first portion is arranged between the anode electrode and the first portion of the pixel defining layer in the second opening in a direction perpendicular to the substrate; A light-emitting layer, located on the anode electrode and connected to the bank structure; A cathode electrode, located on the light-emitting layer and connected to the bank structure; A power line, located on the non-display area of ​​the substrate; A dam structure is arranged on the power line; as well as A power connection electrode is located on the power line and the dam structure and is separated from the anode electrode. A portion of the power connection electrode is covered by the second portion of the remaining pattern and the second portion of the pixel defining layer, A side surface of the power connection electrode facing the dam structure is in contact with the second portion of the remaining pattern and is completely covered by the second portion of the remaining pattern and the second portion of the pixel defining layer.

2. The display device according to claim 1, wherein: The embankment structure comprises: A first bank layer connected to the cathode electrode; and The second bank layer includes a protruding end that protrudes toward the light emitting region from a side surface of the first bank layer facing the first opening.

3. The display device according to claim 2, wherein: The second portion of the remaining pattern overlapping the non-display area includes a first side surface overlapping the power line in a direction perpendicular to the substrate, The first side surface is connected to the first bank layer and is completely covered by the first bank layer.

4. The display device according to claim 3, wherein: The first portion of the remaining pattern overlapping the display area is spaced apart from the second portion of the remaining pattern overlapping the non-display area.

5. The display device according to claim 4, wherein: The first portion of the remaining pattern overlapping the display area overlaps a protruding end of the second bank layer in a direction perpendicular to the substrate.

6. The display device according to claim 2, wherein: The second portion of the pixel defining layer is arranged between the first bank layer and the second portion of the remaining pattern in a direction perpendicular to the substrate in a portion overlapping the non-display area.

7. The display device according to claim 6, wherein: The second portion of the pixel defining layer overlapping the non-display area includes a first side surface overlapping the power line in a direction perpendicular to the substrate, The first side surface is connected to the first bank layer and is completely covered by the first bank layer.

8. The display device according to claim 7, wherein: The first portion of the pixel defining layer overlapping the display area is spaced apart from the second portion of the pixel defining layer overlapping the non-display area.

9. The display device according to claim 1, wherein: The second portion of the remaining pattern overlapping the non-display area and the second portion of the pixel defining layer completely cover the dam structure.

10. The display device according to claim 1, wherein: The side of the power connection electrode facing the dam structure is completely covered by the dike structure. The dike structure completely covers the dam structure.

11. The display device according to claim 2, wherein: The power connection electrode includes a first surface facing the bank structure, The first surface includes a first portion connected to the second portion of the remaining pattern and a second portion connected to the first bank layer.

12. The display device according to claim 11, wherein: The first surface is completely covered by the second portion of the remaining pattern and the first bank layer.

13. The display device according to claim 12, wherein: The first portion of the first surface overlaps with the second portion of the pixel defining layer and the bank structure in a direction perpendicular to the substrate. The second portion of the first surface does not overlap with the second portion of the pixel defining layer and the second portion of the remaining pattern in a direction perpendicular to the substrate.

14. The display device according to claim 2, wherein: A voltage applied to the power line is applied to the cathode electrode through the power connection electrode and the first bank layer.

15. The display device according to claim 2, further comprising: an organic pattern, arranged on the protruding end of the second bank layer, including the same material as the light-emitting layer, and spaced apart from the light-emitting layer; as well as The electrode pattern is arranged on the organic pattern, includes the same material as the cathode electrode, and is spaced apart from the cathode electrode.

16. The display device according to claim 15, wherein: A thin film encapsulation layer is included on the cathode electrode, the electrode pattern and the bank structure, The thin film encapsulation layer is arranged to overlap with the display area and the non-display area, The thin film encapsulation layer includes at least one organic material layer and at least one inorganic material layer.

17. A display device comprising: A substrate, comprising a display area and a non-display area surrounding the display area, wherein the display area comprises a light-emitting area and a non-light-emitting area; a pixel defining layer, comprising a first portion overlapping the display area and a second portion overlapping the non-display area, wherein the first portion is located on the non-luminescent area of ​​the substrate and defines a first opening; A bank structure is located on the pixel defining layer and defines a second opening; A power line, located on the non-display area of ​​the substrate and surrounding the display area; A dam structure is arranged on the power line and surrounds the display area; as well as A power connection electrode covers the power line and the dam structure, Wherein, in a direction perpendicular to the substrate, a remaining pattern and the second portion of the pixel defining layer are arranged between the embankment structure and the power connection electrode, The bank structure located in the non-light emitting area and the bank structure located in the non-display area are integrated in a plane.

18. The display device according to claim 17, wherein: In a plane, the dike structure completely covers the power connection electrode and the dam structure.

19. The display device according to claim 18, wherein: On a plane, the second opening completely surrounds the first opening. The embankment structure completely surrounds the second opening in a plan view.

20. A method for manufacturing a display device, comprising the following steps: After forming a substrate including a display area and a non-display area surrounding the display area, and forming a power line on the non-display area of ​​the substrate, forming a dam structure and a power connection electrode connected to the power line on the power line, and forming a sacrificial layer that entirely covers the power connection electrode and the dam structure; forming a photoresist around the dam structure, removing a portion of the sacrificial layer by performing a first etching process so that a portion of the power connection electrode is exposed again, and then forming a pixel definition material layer entirely on the sacrificial layer and the power connection electrode; forming a photoresist around the dam structure, removing a portion of the pixel defining material layer by performing a second etching process so that a portion of the power connection electrode is exposed again, and forming a dam structure entirely on the pixel defining material layer and the power connection electrode; A mask is formed at a portion overlapping the dam structure and the power connection electrode, and a third etching process is performed to remove the exposed portion of the dam structure, the pixel defining material layer, and the sacrificial layer, thereby forming a pixel defining layer covering a portion of the power connection electrode and the dam structure and a remaining pattern. The side of the power connection electrode facing the dam structure is in contact with the remaining pattern. The power connection electrode is completely covered by the remaining pattern and the bank structure.

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