Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a display area, and the display area comprises a plurality of data signal lines, a plurality of initial signal connecting lines, a plurality of first fan-out lines and a plurality of first power lines which are located on a substrate. The plurality of data signal lines, the plurality of initial signal connecting lines, the plurality of first fan-out lines and the plurality of first power lines are arranged along a first direction and extend along a second direction; wherein the at least one initial signal connecting line and the at least one first fan-out line are located between the two adjacent data signal lines, the two adjacent data signal lines are located between the two adjacent first power lines, and the data signal lines, the initial signal connecting lines, the first power lines and the first fan-out lines are located on the same conductive layer. The wiring layout can be optimized, the distance between adjacent wires is increased, and signal crosstalk is avoided.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, bendability, and low cost.

[0003] Currently, there is a problem of signal crosstalk in a local area of the display region of the display substrate. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a display device, which can solve the problem of local signal crosstalk existing in the display region of the existing display substrate.

[0005] On the one hand, embodiments of the present disclosure provide a display substrate, including a display region and a bonding region located on one side of the display region; the display region includes:

[0006] A substrate;

[0007] A plurality of data signal lines located on the substrate, the plurality of data signal lines are arranged at intervals in a first direction and extend in a second direction; the first direction intersects with the second direction and the plane formed by them is parallel to the plane where the substrate is located;

[0008] A plurality of initial signal connection lines located on the substrate, the plurality of initial signal connection lines are arranged at intervals in the first direction and extend in the second direction;

[0009] A plurality of first fan-out lines located on the substrate, the plurality of first fan-out lines are arranged at intervals in the first direction and extend in the second direction, and the first fan-out lines are connected to the data signal lines; and

[0010] A plurality of first power supply lines and a plurality of pixel driving circuits located on the substrate, the plurality of first power supply lines are arranged in the first direction and extend in the second direction, and the first power supply lines are configured to provide high-level signals to the pixel driving circuits;

[0011] Among them, at least one of the initial signal connection lines and at least one of the first fan-out lines are located between two adjacent data signal lines, and the two data signal lines are located between two adjacent first power supply lines, and the data signal lines, the initial signal connection lines, the first fan-out lines, and the first power supply lines are located on the same conductive layer.

[0012] In some exemplary embodiments, the display area further includes at least one of a first initial signal line, a second initial signal line, and a third initial signal line, and the first initial signal line, the second initial signal line, and the third initial signal line all extend along the first direction; the plurality of initial signal connection lines include at least one of a first initial signal connection line, a second initial signal connection line, and a third initial signal connection line;

[0013] The first initial signal line is connected to the first initial signal connection line to form a mesh structure for transmitting a first initial signal; the second initial signal line is connected to the second initial signal connection line to form a mesh structure for transmitting a second initial signal; the third initial signal line is connected to the third initial signal connection line to form a mesh structure for transmitting a third initial signal.

[0014] In some exemplary embodiments, the first initial signal connection line, the second initial signal connection line, the third initial signal connection line, and the second initial signal connection line are alternately arranged in sequence along the first direction.

[0015] In some exemplary embodiments, the first power supply line includes a connected extension portion and a pad portion, and the extension portion extends along the second direction, and the pad portions of at least two adjacent first power supply lines are an integrally connected structure;

[0016] The display area further includes a plurality of light-emitting devices, and the plurality of light-emitting devices are located on a side of the plurality of first power supply lines away from the substrate; the light-emitting device includes an anode, an organic light-emitting layer, and a cathode arranged in a stacked manner, the anode is closer to the substrate than the cathode, and the anode is connected to the pixel driving circuit; among them, the positive projection of at least one anode and at least one of the integrally connected pad portions on the plane of the substrate at least partially overlaps.

[0017] In some exemplary embodiments, the pixel driving circuit includes a compensation transistor, and the compensation transistor is a transistor with a double-gate structure; the display area further includes at least one first shielding electrode, and the positive projection of the active layer between the two gate electrodes of the compensation transistor and the first shielding electrode on the plane of the substrate at least partially overlaps.

[0018] In some exemplary embodiments, the display area further includes a first initial signal line and at least one second shielding electrode; the pixel driving circuit includes a first initialization transistor and a compensation transistor, a first pole of the first initialization transistor is connected to the first initial signal line, and a first pole of the compensation transistor is connected to a second pole of the first initialization transistor; the second shielding electrode at least partially overlaps a positive projection of an active layer between the second pole and a gate electrode of the first initialization transistor in a plane of the substrate, and the second shielding electrode and the first initial signal line are an integrally connected structure.

[0019] In some exemplary embodiments, the display area further includes a first initial signal line and at least one third shielding electrode, the pixel driving circuit includes a first initialization transistor and a data writing transistor, a first pole of the first initialization transistor is connected to the first initial signal line, and a first pole of the data writing transistor is connected to the data signal line; at least a part of a positive projection of the third shielding electrode in the plane of the substrate is located between positive projections of the second pole of the first initialization transistor and the first pole of the data writing transistor in the plane of the substrate, and the third shielding electrode and the first initial signal line are an integrally connected structure.

[0020] In some exemplary embodiments, the display area further includes a first initial signal line, a second initial signal line, and a third initial signal line; the first initial signal line and the third initial signal line are located in the same conductive layer, and the second initial signal line and the first initial signal line are located in different conductive layers; the first initial signal line, the second initial signal line, and the initial signal connection line are located in different conductive layers.

[0021] In some exemplary embodiments, the plurality of initial signal connection lines includes a first initial signal connection line; the display area further includes at least one first connection electrode, and the first connection electrode and the second initial signal line are located in the same conductive layer, and the first connection electrode and the first initial signal line partially overlap in a positive projection in the plane of the substrate;

[0022] The first connection electrode includes a connected first section, a second section, and a third section, both the first section and the third section extend along the second direction, the second section extends along the first direction, and the second section is located between the first section and the third section, the first section is connected to the first initial signal line, and the third section is connected to the first initial signal connection line.

[0023] In some exemplary embodiments, the plurality of initial signal connection lines include a second initial signal connection line; the display area further includes at least one second connection electrode, and the second connection electrode and the second initial signal line are located in the same conductive layer;

[0024] The second connection electrode extends along the second direction and includes a first end and a second end which are oppositely arranged. The first end is connected to the second initial signal line, the second end is located on one side of the second initial signal line in the opposite direction of the second direction, and the second end is connected to the second initial signal connection line.

[0025] In some exemplary embodiments, the plurality of initial signal connection lines include a third initial signal connection line; the display area further includes at least one third connection electrode, and the third connection electrode and the second initial signal line are located in the same conductive layer; at least a part of the orthographic projection of the third connection electrode and the third initial signal line on the plane where the substrate is located overlaps;

[0026] The third connection electrode extends along the first direction and includes a first end, a second end and a middle part located between the first end and the second end. The middle part is connected to the third initial signal line, and the first end is connected to the third initial signal connection line.

[0027] On the other hand, an embodiment of the present disclosure provides a display device, including the display substrate described in any one of the foregoing embodiments.

[0028] Other features and advantages of the present application will be described in the subsequent description, and part of them will become obvious from the description, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. Description of the Drawings

[0029] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the description. They are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0030] Figure 1 It is a schematic structural diagram of a display device;

[0031] Figure 2 It is a schematic plan view of a display substrate;

[0032] Figure 3 It is a schematic cross-sectional view of a display substrate;

[0033] Figure 4 It is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0034] Figure 5 Schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure;

[0035] Figure 6 Schematic diagram of a display substrate after forming a semiconductor layer pattern according to an embodiment of the present disclosure;

[0036] Figure 7A and Figure 7B Schematic diagram of a display substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0037] Figure 8A and Figure 8B Schematic diagram of a display substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0038] Figure 9A and Figure 9B Schematic diagram of a display substrate after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 10A and Figure 10B Schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0040] Figure 11 Schematic diagram of a display substrate after forming an anode conductive layer pattern according to an embodiment of the present disclosure;

[0041] Figure 12 Schematic diagram of a display substrate after forming a pixel definition layer pattern according to an embodiment of the present disclosure. Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0043] In the accompanying drawings, sometimes for clarity, the sizes, thicknesses of layers or regions of one or more constituent elements are exaggerated. Therefore, one manner of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one manner of the present disclosure is not limited to the shapes or values shown in the drawings.

[0044] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure includes two or more quantities.

[0045] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0046] In the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0047] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0048] In the present disclosure, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0049] In the present disclosure, "electrically connected" includes the case where constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0050] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus, a state where the angle is more than -5° and less than 5° can be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus, a state where the angle is more than 85° and less than 95° can be included.

[0051] In the present disclosure, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0052] "About" in the present disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0053] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn) respectively. The scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo) respectively. The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the light-emitting signal line, and the data signal line respectively. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0054] Figure 2It is a schematic plan view of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area located around the display area. As Figure 2 shown, the display area of the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting unit may at least include a light-emitting device. The light-emitting device is respectively connected to the pixel driving circuit of the sub-pixel where it is located. The light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.

[0055] In some exemplary embodiments, at least one pixel unit P may include one first sub-pixel P1, one second sub-pixel P2, and two third sub-pixels P3, and are arranged in the order of the first sub-pixel P1, the third sub-pixel P3, the second sub-pixel P2, and the third sub-pixel P3. The first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal.

[0056] Figure 3 It is a schematic cross-sectional view of a display substrate, showing the structures of three sub-pixels in the display substrate. As Figure 3 shown, on a plane perpendicular to the plane of the display substrate, the display area of the display substrate may include a driving circuit layer 102 provided on a substrate 101, a light-emitting structure layer 103 provided on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 provided on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited herein in the present disclosure.

[0057] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but not limited to, one or more of glass and quartz. The flexible substrate may be, but not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0058] In some exemplary embodiments, the driving circuit layer 102 may include a plurality of circuit units. The circuit units may at least include pixel driving circuits. The pixel driving circuits may include a plurality of transistors and storage capacitors. The light-emitting structure layer 103 may include a plurality of light-emitting units. The light-emitting units may at least include light-emitting devices. The light-emitting devices may include anodes, organic light-emitting layers, and cathodes. The anodes are connected to the pixel driving circuits, the organic light-emitting layers are connected to the anodes, and the cathodes are connected to the organic light-emitting layers. The organic light-emitting layers emit corresponding color light under the drive of the anodes and cathodes.

[0059] In some exemplary embodiments, the encapsulation structure layer 104 may include a stacked first encapsulation layer, second encapsulation layer, and third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external moisture from entering the light-emitting structure layer 103.

[0060] In some exemplary embodiments, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0061] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. As Figure 4 shown, in an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure, etc. As Figure 4 shown, the pixel driving circuit of the exemplary embodiment of the present disclosure may be an 8T1C structure, and may include eight transistors (a first transistor T1 to an eighth transistor T8) and one storage capacitor C. The pixel driving circuit is respectively connected to nine signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light-emitting signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power supply line VDD).

[0062] In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. Among them, the first node N1 is respectively connected to the second pole of the first transistor, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C. The second node N2 is respectively connected to the first pole of the third transistor T3, the second pole of the eighth transistor T8, the second pole of the fifth transistor T5, and the second pole of the fourth transistor T4. The third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6. The fourth node N4 is respectively connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7. The first end (first electrode plate) of the storage capacitor C is connected to the first node N1, and the second end (second electrode plate) of the storage capacitor C is connected to the first pole of the fifth transistor T5.

[0063] In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first pole of the first transistor T1 is connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first pole of the second transistor T2 is connected to the first node N1, and the second pole of the second transistor T2 is connected to the third node N3. The gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C. The first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first pole of the fourth transistor T4 is connected to the data signal line DATA, and the second pole of the fourth transistor T4 is connected to the second node N2. The gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first pole of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is connected to the fourth node N4. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first pole of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second pole of the eighth transistor T8 is connected to the second node N2.

[0064] In some exemplary embodiments, the first transistor T1 may be referred to as a first initialization transistor, the second transistor T2 may be referred to as a compensation transistor, the third transistor T3 may be referred to as a driving transistor, the fourth transistor T4 may be referred to as a data writing transistor, the fifth transistor T5 may be referred to as a first light-emitting transistor, the sixth transistor T6 may be referred to as a second light-emitting transistor, the seventh transistor T7 may be referred to as a second initialization transistor, and the eighth transistor T8 may be referred to as a third initialization transistor.

[0065] In some exemplary embodiments, the light-emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, the second electrode of the light-emitting device EL is connected to the second power supply line VSS, the signal of the second power supply line VSS is a continuously provided low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal.

[0066] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0067] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 may adopt low-temperature poly-silicon thin-film transistors, or may adopt oxide thin-film transistors, or may adopt low-temperature poly-silicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature poly-silicon thin-film transistor adopts low-temperature poly-silicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor adopts an oxide semiconductor (Oxide). The low-temperature poly-silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature poly-silicon thin-film transistor and the oxide thin-film transistor on a display substrate, that is, an LTPS+Oxide (abbreviated as LTPO) display substrate, can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0068] Figure 5 This is a schematic partial planar structure diagram of a display substrate according to an embodiment of the present disclosure. The display substrate may include a display area, a bonding area on one side of the display area, and a border area on other sides of the display area. As Figure 5As shown, the display substrate may adopt a structure with fan-out lines located in the panel (Fanout in Panel, abbreviated as FIP). A plurality of data fan-out lines may be provided in the display area. One end of the plurality of data fan-out lines is correspondingly connected to a plurality of data signal lines in the display area, and the other end of the plurality of data fan-out lines is located in the bonding area and is correspondingly connected to the integrated circuit through a plurality of data lead-out lines. Since the bonding area can reduce the number of diagonal traces in the fan shape, the width of the lower border of the display substrate is reduced, which is beneficial to the narrow border design of the display substrate. The data fan-out line may include a connected first fan-out line 40 and a second fan-out line 30. The first fan-out line 40 may extend along the second direction Y, and the second fan-out line 30 may extend along the first direction X. By way of example, both the first fan-out line 40 and the second fan-out line 30 include a first end and a second end disposed opposite to each other. The first end of the second fan-out line 30 is connected to the data signal line DATA, the second end of the second fan-out line 30 is connected to the first end of the first fan-out line 40, and the second end of the first fan-out line 40 may be located in the bonding area.

[0069] As Figure 5 shown, the display area may include a plurality of circuit unit rows (only the M-th unit row and the M + 1-th unit row are schematically shown) and a plurality of circuit unit columns (only the N-th unit column, the N + 1-th unit column to the N + 7-th unit column are schematically shown). The circuit unit rows include a plurality of circuit units arranged in sequence along the first direction X, the circuit unit columns include a plurality of circuit units arranged in sequence along the second direction Y, and the plurality of circuit unit rows and the plurality of circuit unit columns form an array of circuit units arranged in an array. Located in the same circuit unit column, the data signal line DATA is connected to a plurality of pixel driving circuits, and the data signal line DATA is configured to provide data signals to the connected pixel driving circuits.

[0070] As Figure 5 shown, the display area may include a plurality of data signal lines DATA and a plurality of initial signal lines. The plurality of data signal lines DATA are arranged at intervals along the first direction X and extend along the second direction Y. The plurality of initial signal lines may extend along the first direction X and be arranged at intervals along the second direction Y. The plurality of initial signal lines may at least include a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3. In the plane of the substrate, located in the same circuit unit row, the second initial signal line INIT2 is located between the first initial signal line INIT1 and the third initial signal line INIT3. The first direction X intersects with the second direction Y, and the formed plane is parallel to the plane of the substrate.

[0071] The display area may further include a plurality of first fan-out lines 40, a plurality of first power supply lines VDD, and a plurality of initial signal connection lines INIT. The plurality of first fan-out lines 40 and the plurality of initial signal connection lines INIT are arranged at intervals along the first direction X and extend along the second direction Y. At least one first fan-out line 40 and at least one initial signal connection line INIT are located between two adjacent data signal lines DATA, and two adjacent data signal lines DATA are located between two adjacent first power supply lines VDD. The plurality of first fan-out lines 40, the plurality of initial signal connection lines INIT, the plurality of first power supply lines VDD, and the plurality of data signal lines DATA are located in the same conductive layer. In the embodiments of the present disclosure, by arranging at least one first fan-out line and at least one initial signal connection line between two adjacent data signal lines and arranging two adjacent data signal lines between two adjacent first power supply lines VDD, the number of signal lines in the same conductive layer can be reduced as a whole, the distance between two adjacent signal lines can be increased, signal crosstalk can be avoided, and the display quality can be improved.

[0072] As Figure 5 shown, the plurality of initial signal connection lines INIT may at least include a first initial signal connection line 41. The first initial signal line INIT1 and the first initial signal connection line 41 are connected to each other, so that the first initial signal line INIT1 and the first initial signal connection line 41 form a mesh structure for transmitting the first initial signal on the display substrate. This can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0073] As Figure 5 shown, the plurality of initial signal connection lines INIT may at least include a second initial signal connection line 42. The second initial signal line INIT2 and the second initial signal connection line 42 are connected to each other, so that the second initial signal line INIT2 and the second initial signal connection line 42 form a mesh structure for transmitting the second initial signal on the display substrate. This can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0074] As Figure 5As shown, multiple initial signal connection lines INIT may at least include a third initial signal connection line 43. The third initial signal line INIT3 and the third initial signal connection line 43 are connected to each other, such that the third initial signal line INIT3 and the third initial signal connection line 43 form a mesh structure for transmitting the third initial signal on the display substrate. This can not only effectively reduce the resistance of the third initial signal line and decrease the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and enhance the display quality and display performance.

[0075] As Figure 5 shown, the first initial signal connection line 41, the second initial signal connection line 42, the third initial signal connection line 43, and the second initial signal connection line 42 may be alternately arranged in a cycle along the first direction X, increasing the density of the mesh structure for transmitting the second initial signal, which can match the pixel structure layout of the RGBG display substrate. Moreover, the second initial signal is beneficial for the anode reset of the light-emitting device, which can improve the display quality of the display device.

[0076] The following is an exemplary description through the manufacturing process of the display substrate. The "patterning process" in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be carried out using any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out using any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out using any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process throughout the manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0077] In some exemplary embodiments, only the M-th unit row and the (M + 1)-th unit row of the display substrate are shown schematically, and only the N-th unit column, the (N + 1)-th unit column to the (N + 7)-th unit column of the display substrate are shown schematically. The manufacturing process of the display substrate according to the embodiments of the present disclosure may include the following operations.

[0078] (11) Form a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as Figure 6 shown. The semiconductor layer pattern may at least include the active layers of the first transistor T1 to the eighth transistor T8.

[0079] As Figure 6 shown, the active layers of two adjacent circuit unit columns may be symmetrically disposed with respect to the boundary line between the two adjacent circuit unit columns. The active layers of the first transistor T1 to the seventh transistor T7 may be an integrally connected structure. The active layers of the seventh transistor T7 in two adjacent circuit unit columns may be an integrally connected structure.

[0080] (12) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as Figure 7A and Figure 7B shown, Figure 7B is Figure 7A a schematic diagram of the first conductive layer in . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0081] In some exemplary embodiments, the first conductive layer pattern may at least include a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light-emitting signal line EM, and a first electrode plate C11 of a storage capacitor. The main portions of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 may all extend along a first direction X. The first electrode plate C11 may serve as one electrode plate of the storage capacitor and the gate electrode of the third transistor T3 at the same time. The region where the third scan signal line S3 overlaps with the active layer of the first transistor T1 serves as the gate electrode of the first transistor T1. The region where the first scan signal line S1 overlaps with the active layer of the second transistor T2 serves as the gate electrode of the second transistor T2 with a double-gate structure. The region where the first scan signal line S1 overlaps with the active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. The region where the light-emitting signal line EM overlaps with the active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5. The region where the light-emitting signal line EM overlaps with the active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. The region where the second scan signal line S2 overlaps with the active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7. The region where the second scan signal line S2 overlaps with the active layer of the eighth transistor T8 serves as the gate electrode of the eighth transistor T8.

[0082] (13) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film by a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as Figure 8A and Figure 8B shown, Figure 8B is Figure 8A a schematic diagram of the second conductive layer in

[0083] In some exemplary embodiments, the second conductive layer pattern may at least include: a first initial signal line INIT1, a third initial signal line INIT3, and a second electrode plate C12 of a storage capacitor. The orthographic projection of the second electrode plate C12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C11 on the substrate, and the first electrode plate C11 and the second electrode plate C12 constitute the storage capacitor of the pixel driving circuit. The main portions of the first initial signal line INIT1 and the third initial signal line INIT3 may both extend along the first direction X.

[0084] In some exemplary embodiments, the second conductive layer pattern may at least include: a first shielding electrode 21, a second shielding electrode 22, and a third shielding electrode 23. The first shielding electrode 21 may extend along the second direction Y. The first shielding electrode 21 includes a first end and a second end which are oppositely arranged. The first end may be connected to the first initial signal line INIT1, and the second end may be located on one side of the first initial signal line INIT1 in the second direction Y. The orthographic projection of the first shielding electrode 21 on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the second transistor T2 in this circuit unit on the substrate. The first shielding electrode 21 is configured to shield the influence of data voltage jumps on the second transistor T2, avoid the influence of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0085] In some exemplary embodiments, the first shielding electrode 21, the second shielding electrode 22, and the third shielding electrode 23 may be arranged in sequence along the first direction X. The second shielding electrode 22 may extend along the second direction Y. The second shielding electrode 22 may include a first end and a second end which are oppositely arranged. The first end and the second end are respectively located on both sides of the first initial signal line INIT1. The orthographic projection of the second shielding electrode 22 on the substrate at least partially overlaps with the orthographic projection of the active layer between the second pole and the gate electrode of the first transistor T1 in this circuit unit on the substrate. The second shielding electrode 22 is configured to shield the influence of data voltage jumps on the first transistor T1, avoid the influence of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0086] In some exemplary embodiments, the third shielding electrode 23 may extend along the second direction Y. The third shielding electrode 23 includes a first end and a second end which are oppositely arranged. The first end may be connected to the first initial signal line INIT1, and the second end may be located on one side of the first initial signal line INIT1 in the second direction Y. In the plane of the substrate, the second end of the third shielding electrode 23 may be located between the second pole of the first transistor T1 and the first pole of the fourth transistor T4 in this circuit unit. The third shielding electrode 23 is configured to shield the influence of data voltage jumps on the first transistor T1 and the fourth transistor T4, avoid the influence of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0087] In some exemplary embodiments, the first transistor T1 is a transistor with a double-gate structure. The orthographic projection of the third initial signal line INIT3 on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the first transistor T1 on the substrate. A part of the third initial signal line INIT3 can be used as a shielding electrode, which can shield the influence of data voltage jumps on the first transistor T1, avoid the influence of data voltage jumps on the normal operation of the pixel driving circuit, and improve the display effect.

[0088] (14) Form a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating thin film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating thin film using a patterning process to form a fourth insulating layer covering the second conductive layer, and a plurality of vias are provided on the fourth insulating layer. As Figure 9A shown, the vias are represented by dashed lines.

[0089] (15) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the foregoing pattern is formed, patterning the third conductive thin film using a patterning process to form a third conductive layer provided on the fourth insulating layer, as Figure 9A and Figure 9B shown, Figure 9B is Figure 9A a schematic diagram of the third conductive layer in

[0090] In some exemplary embodiments, the third conductive layer may at least include a second fan-out line 30, a second initial signal line INIT2, and a plurality of connection electrodes configured to implement connections between transistors, or between a transistor and a signal line, or between signal lines. The main portions of the second fan-out line 30 and the second initial signal line INIT2 may both extend along the first direction X.

[0091] In some exemplary embodiments, the plurality of connection electrodes may at least include a first connection electrode 31, a second connection electrode 32, and a third connection electrode 33. The orthographic projection of the first connection electrode 31 on the plane of the substrate partially overlaps the orthographic projection of the first initial signal line INIT1 on the plane of the substrate, and the portion of the orthographic projection of the first connection electrode 31 on the plane of the substrate is located between the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 in the same circuit unit row on the plane of the substrate.

[0092] The first connection electrode 31 may include a first section 31-1, a second section 31-2, and a third section 31-3 that are connected to each other. The first section 31-1 and the third section 31-3 may both extend along the second direction Y, the second section 31-2 may extend along the first direction X, and the second section 31-2 is located between the first section 31-1 and the third section 31-3. The first section 31-1 of the first connection electrode 31 is connected to the first initial signal line INIT1 through a via, and the first connection electrode 31 is connected to the first pole of the first transistor T1 through a via. The first connection electrode 31 may be configured to connect the first initial signal line INIT1 and a first initial signal connection line formed subsequently to form a mesh structure for transmitting the first initial signal. For example, the third section 31-3 is configured to be connected to a first initial signal connection line formed subsequently.

[0093] In some exemplary embodiments, the positive projection of the second connection electrode 32 on the plane of the substrate is located between the positive projections of the first initial signal line INIT1 and the second initial signal line INIT2 in the same circuit unit row on the plane of the substrate. The second connection electrode 32 may extend along the second direction Y. The second connection electrode 32 includes a first end and a second end that are oppositely arranged. The first end is connected to the second initial signal line INIT2, the second end is located on one side opposite to the second direction Y of the second initial signal line INIT2, and the second end is configured to be connected to a second initial signal connection line formed subsequently. The second connection electrode 32 may be configured to connect the second initial signal line INIT2 and a second initial signal connection line formed subsequently to form a mesh structure for transmitting the second initial signal.

[0094] In some exemplary embodiments, the positive projection of the third connection electrode 33 on the plane of the substrate at least partially overlaps with the positive projection of the third initial signal line INIT3 on the plane of the substrate. The third connection electrode 33 may extend along the first direction X. The third connection electrode 33 may include a first end and a second end that are oppositely arranged. The first end is connected to the first pole of the eighth transistor T8 through a via, the second end is connected to the first pole of another eighth transistor T8 through a via, and the middle part of the third connection electrode 33 is connected to the third initial signal line INIT3 through a via. For example, the first end of the third connection electrode 33 is configured to be connected to a third initial signal connection line formed subsequently. The third connection electrode 33 may be configured to connect the third initial signal line INIT3 and a third initial signal connection line formed subsequently to form a mesh structure for transmitting the third initial signal.

[0095] (16) Form a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating thin film on the substrate on which the foregoing pattern is formed, and patterning the fifth insulating thin film using a patterning process to form a fifth insulating layer covering the third conductive layer. A plurality of vias are provided on the fifth insulating layer, as Figure 10A shown, the via is represented by a dotted line.

[0096] (17) Form a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer provided on the fifth insulating layer, as Figure 10A and Figure 10B shown. Figure 10B is Figure 10A a schematic diagram of the fourth conductive layer in

[0097] . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer. Subsequently, form a planarization layer pattern. A plurality of anode vias are provided on the planarization layer, and the anode vias expose a part of the anode connection electrode, completing the preparation of the driving circuit layer.

[0098] In some exemplary embodiments, the first fan-out line 40 is located between two adjacent data signal lines DATA, and one of the first initial signal connection line 41, the second initial signal connection line 42, and the third initial signal connection line 43 is located between the two adjacent data signal lines DATA where the first fan-out line 40 is located, and the two adjacent data signal lines DATA are located between two adjacent first power supply lines VDD. In the embodiments of the present disclosure, by designing the position of the first fan-out line 40, the first power supply line VDD can present a large block metal pattern, and the number of traces in the fourth conductive layer is reduced, and the distance between adjacent traces in the fourth conductive layer is increased, which can improve the qualification rate of the display substrate. Moreover, the first power supply line VDD presenting a large block metal pattern is beneficial to the diversification of the designed shape and facilitates the layout of the pixel structure. By reducing the width of the first power supply line VDD along the first direction X and increasing the distance between the first power supply line VDD and the adjacent data signal line DATA, the risk of crosstalk caused by the jump of the data signal line DATA can be reduced.

[0099] In some exemplary embodiments, the first power supply line VDD may at least include an extension portion 45 and a pad portion 46. The main body portion of the extension portion 45 may be in a zigzag shape extending along the second direction Y and may be a non-uniform width zigzag, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the first power supply line VDD and the data signal line DATA. The pad portion 46 may be in a block shape (such as a rectangle), and the pad portion 46 may be disposed on one side of the extension portion 45 in the first direction X or on the opposite side of the first direction X and is connected to the extension portion 45. Some adjacent two pad portions 46 may be disposed facing each other and connected together to form a large block metal pattern, which can improve the flatness of the anode formed subsequently and improve the light emission uniformity of the light-emitting device.

[0100] In some exemplary embodiments, the positive projection of the first initial signal connection line 41 and the first connection electrode 31 on the plane where the substrate is located may partially overlap, and the first initial signal connection line 41 may be connected to the first connection electrode 31 through a via hole. With such a design, the connection between the first initial signal connection line 41 and the first initial signal line INIT1 is realized, and a mesh structure for transmitting the first initial signal is realized, reducing the load of the first initial signal and improving the stability of the first initial signal transmission.

[0101] In some exemplary embodiments, the positive projection of the second initial signal connection line 42 and the second connection electrode 32 in the plane of the substrate may partially overlap, and the second initial signal connection line 42 may be connected to the second connection electrode 32 through a via hole. With such a design, the connection between the second initial signal connection line 42 and the second initial signal line INIT2 is achieved, a mesh structure for transmitting the second initial signal is realized, the load of the second initial signal is reduced, and the stability of the second initial signal transmission is improved.

[0102] In some exemplary embodiments, the positive projection of the third initial signal connection line 43 and the third connection electrode 33 in the plane of the substrate may partially overlap, and the third initial signal connection line 43 may be connected to the third connection electrode 33 through a via hole. With such a design, the connection between the third initial signal connection line 43 and the third initial signal line INIT3 is achieved, a mesh structure for transmitting the third initial signal is realized, the load of the third initial signal is reduced, and the stability of the third initial signal transmission is improved.

[0103] In some exemplary embodiments, the first initial signal connection line 41, the second initial signal connection line 42, the third initial signal connection line 43, and the second initial signal connection line 42 may be alternately arranged in a cycle along the first direction X, increasing the density of the mesh structure for transmitting the second initial signal, and can match the pixel structure layout of the display substrate RGBG.

[0104] (18) Form an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer may include: depositing an anode conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the anode conductive thin film using a patterning process to form an anode conductive layer disposed on the flat layer, as Figure 11 shown. The anode conductive layer includes a plurality of anodes 50, and the plurality of anodes 50 may be respectively connected to the pixel driving circuit of the corresponding circuit unit through anode vias K.

[0105] In some exemplary embodiments, the positive projection of at least one anode 50 and at least one pad portion 46 connected together in the plane of the substrate at least partially overlaps, which can improve the flatness of the anode 50 and is beneficial to the uniformity of light emission of the light-emitting device.

[0106] (19) Form a pixel definition layer pattern. A plurality of pixel openings 51 are provided on the pixel definition layer, and the plurality of pixel openings 51 respectively expose at least a part of the anode 50, as Figure 12 shown, Figure 12 wherein only the pixel openings are shown in the pixel definition layer. The positive projection of at least one pixel opening 51 and at least one pad portion 46 in the plane of the substrate at least partially overlaps.

[0107] Subsequently, an organic light-emitting layer is formed by vapor deposition or inkjet printing. At least a part of the organic light-emitting layer is located within the pixel opening 51. Then, a cathode is formed on the organic light-emitting layer. The cathode, the organic light-emitting layer, and the anode constitute a light-emitting device.

[0108] Subsequently, a packaging structure layer is formed. The packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer is disposed between the first packaging layer and the third packaging layer, which can ensure that external moisture cannot enter the light-emitting structure layer.

[0109] In the embodiment of the present disclosure, by arranging both the first fan-out line and the initial signal connection line between two adjacent data signal lines, and arranging two adjacent data signal lines between two adjacent first power supply lines, the number of traces of the second source-drain metal layer can be reduced as a whole, the distance between two adjacent signal lines can be increased, and signal crosstalk can be avoided.

[0110] In the embodiment of the present disclosure, by providing a first initial signal line and a first initial signal connection line, and connecting the first initial signal line and the first initial signal connection line to each other, a mesh structure for transmitting the first initial signal is formed on the display substrate by the first initial signal line and the first initial signal connection line. This can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0111] In the embodiment of the present disclosure, by providing a second initial signal line and a second initial signal connection line, and connecting the second initial signal line and the second initial signal connection line to each other, a mesh structure for transmitting the second initial signal is formed on the display substrate by the second initial signal line and the second initial signal connection line. This can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0112] In the embodiment of the present disclosure, by providing a third initial signal line and a third initial signal connection line, and connecting the third initial signal line and the third initial signal connection line to each other, a mesh structure for transmitting the third initial signal is formed on the display substrate by the third initial signal line and the third initial signal connection line. This can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0113] The preparation process of the present disclosure can be well compatible with the existing preparation processes, with simple process implementation, easy to implement, high production efficiency, low production cost, and high yield rate.

[0114] In some exemplary embodiments, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-si).

[0115] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It may be a single layer, a multi-layer, or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer and the third insulating layer are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The planarization layer may be made of an organic material, such as resin. The active layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The foregoing structures shown in the present disclosure and their preparation processes are merely exemplary illustrations. In the exemplary embodiments, the corresponding structures may be changed according to actual needs, and the patterning process may be increased or decreased. The present disclosure does not make any limitations herein.

[0116] In some exemplary embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc. The present disclosure does not make any limitations herein.

[0117] An embodiment of the present disclosure further provides a display device, which includes the display substrate of any of the foregoing embodiments. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiments of the present invention are not limited thereto.

[0118] Although the disclosed embodiments of the present invention are as described above, the above content is only an embodiment adopted for the convenience of understanding the present invention and is not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It includes a display area and a binding area located on one side of the display area; the display area includes: substrate; A plurality of data signal lines located on the substrate, the plurality of data signal lines are arranged at intervals along a first direction and extend along a second direction; the first direction intersects with the second direction and the plane formed by the first direction is parallel to the plane where the substrate is located; a plurality of initial signal connection lines located on the substrate, the plurality of initial signal connection lines being arranged at intervals along the first direction and extending along the second direction; a plurality of first fan-out lines located on the substrate, the plurality of first fan-out lines being arranged at intervals along the first direction and extending along the second direction, and the first fan-out lines being connected to the data signal lines; and a plurality of first power lines and a plurality of pixel driving circuits located on the substrate, the plurality of first power lines being arranged along the first direction and extending along the second direction, and the first power lines being configured to provide high-level signals to the pixel driving circuits; Among them, at least one of the initial signal connection lines and at least one of the first fan-out lines are located between two adjacent data signal lines, and two of the data signal lines are located between two adjacent first power lines, and the data signal lines, the initial signal connection lines, the first fan-out lines and the first power lines are located in the same conductive layer.

2. The display substrate according to claim 1, wherein: The display area further includes at least one of a first initial signal line, a second initial signal line, and a third initial signal line, and the first initial signal line, the second initial signal line, and the third initial signal line all extend along the first direction; the plurality of initial signal connection lines include at least one of the first initial signal connection line, the second initial signal connection line, and the third initial signal connection line; The first initial signal line is connected to the first initial signal connection line to form a mesh structure for transmitting the first initial signal; the second initial signal line is connected to the second initial signal connection line to form a mesh structure for transmitting the second initial signal; the third initial signal line is connected to the third initial signal connection line to form a mesh structure for transmitting the third initial signal.

3. The display substrate according to claim 2, wherein: The first initial signal connection line, the second initial signal connection line, the third initial signal connection line and the second initial signal connection line are alternately arranged in sequence along the first direction.

4. The display substrate according to claim 1, wherein: The first power line includes an extension portion and a pad portion connected to each other, and the extension portion extends along the second direction, and the pad portions of at least two adjacent first power lines are an integrated structure connected to each other; The display area also includes a plurality of light-emitting devices, and the plurality of light-emitting devices are located on a side of the plurality of first power lines away from the substrate; the light-emitting devices include a stacked anode, an organic light-emitting layer and a cathode, the anode is closer to the substrate than the cathode, and the anode is connected to the pixel driving circuit; wherein at least one anode and at least one pad portion connected to each other as an integral structure at least partially overlap in their orthographic projection on the plane where the substrate is located.

5. The display substrate according to any one of claims 1 to 4, characterized in that: The pixel driving circuit includes a compensation transistor, and the compensation transistor is a transistor with a dual-gate structure; the display area also includes at least one first shielding electrode, and the first shielding electrode and the active layer between the two gate electrodes of the compensation transistor at least partially overlap in the orthographic projection on the plane where the substrate is located.

6. The display substrate according to any one of claims 1 to 4, characterized in that: The display area also includes a first initial signal line and at least one second shielding electrode; the pixel driving circuit includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor; the second shielding electrode and the active layer between the second electrode and the gate electrode of the first initialization transistor at least partially overlap in the positive projection on the plane where the substrate is located, and the second shielding electrode and the first initial signal line are an integrated structure connected to each other.

7. The display substrate according to any one of claims 1 to 4, characterized in that: The display area also includes a first initial signal line and at least one third shielding electrode, the pixel driving circuit includes a first initialization transistor and a data writing transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the data writing transistor is connected to the data signal line; at least part of the orthographic projection of the third shielding electrode on the plane where the substrate is located is located between the second electrode of the first initialization transistor and the orthographic projection of the first electrode of the data writing transistor on the plane where the substrate is located, and the third shielding electrode and the first initial signal line are an integrated structure connected to each other.

8. The display substrate according to any one of claims 1 to 4, characterized in that: The display area also includes a first initial signal line, a second initial signal line and a third initial signal line; the first initial signal line and the third initial signal line are located in the same conductive layer, and the second initial signal line and the first initial signal line are located in different conductive layers; the first initial signal line, the second initial signal line and the initial signal connecting line are located in different conductive layers.

9. The display substrate according to claim 8, wherein: The plurality of initial signal connection lines include a first initial signal connection line; the display area further includes at least one first connection electrode, and the first connection electrode and the second initial signal line are located in the same conductive layer, and the first connection electrode and the first initial signal line overlap in the orthographic projection part of the plane where the substrate is located; The first connecting electrode includes a first segment, a second segment and a third segment that are connected to each other, the first segment and the third segment both extend along the second direction, the second segment extends along the first direction, and the second segment is located between the first segment and the third segment, the first segment is connected to the first initial signal line, and the third segment is connected to the first initial signal connection line.

10. The display substrate according to claim 8, wherein: The plurality of initial signal connection lines include a second initial signal connection line; the display area further includes at least one second connection electrode, and the second connection electrode and the second initial signal line are located in the same conductive layer; The second connecting electrode extends along the second direction and includes a first end and a second end arranged opposite to each other, the first end is connected to the second initial signal line, the second end is located on the side of the second initial signal line in the opposite direction along the second direction, and the second end is connected to the second initial signal connecting line.

11. The display substrate according to claim 8, wherein: The plurality of initial signal connection lines include a third initial signal connection line; the display area further includes at least one third connection electrode, and the third connection electrode and the second initial signal line are located in the same conductive layer; the orthographic projections of the third connection electrode and the third initial signal line on the plane where the substrate is located at least partially overlap; The third connection electrode extends along the first direction and includes a first end, a second end and a middle portion located between the first end and the second end, the middle portion is connected to the third initial signal line, and the first end is connected to the third initial signal connection line.

12. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 11.

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