Display panel and method of manufacturing the same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes: a base layer; a pixel defining film disposed on the base layer and defining a light emitting opening therein; a partition wall disposed on the pixel defining film and defining therein a partition wall opening overlapping the light emitting opening in a plan view; a plurality of light-emitting elements each including an anode, a light-emitting pattern, and a cathode, and disposed inside the light-emitting opening and the partition wall opening, in which the cathode is in contact with the partition wall; a plurality of lower encapsulation inorganic patterns respectively covering the plurality of light-emitting elements; and a common inorganic film covering the plurality of lower encapsulation inorganic patterns and filling a space between the partition wall and the plurality of lower encapsulation inorganic patterns.

Description

[0001] This application claims the priority of, and all benefits derived from, Korean Patent Application No. 10-2023-0168516, filed on November 28, 2023, the entire content of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a display panel and a method of manufacturing a display panel, and more particularly, to a display panel having improved display quality. Background Art

[0003] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablet personal computers (PCs), include a display panel that displays an image. Various display panels, such as liquid crystal display panels, organic light emitting display panels, electro-wetting display panels, and electrophoretic display panels, have been developed as display panels.

[0004] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. For each of the light emitting regions, the light emitting pattern may be separate, and the cathode may supply a common voltage to each of the light emitting regions. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display panel and a method of manufacturing a display panel that form light emitting elements without using a metal mask and have improved display quality.

[0006] According to an embodiment, a display panel includes: a base layer; a pixel defining film disposed on the base layer and defining a light emitting opening therein; a partition wall disposed on the pixel defining film and defining a partition wall opening overlapping the light emitting opening in a plan view; a plurality of light emitting elements, each including an anode, a light emitting pattern, and a cathode, and disposed inside the light emitting opening and the partition wall opening, wherein the cathode is in contact with the partition wall; a plurality of lower encapsulation inorganic patterns respectively covering the plurality of light emitting elements; and a common inorganic film covering the plurality of lower encapsulation inorganic patterns and filling a space between the partition wall and the plurality of lower encapsulation inorganic patterns.

[0007] The plurality of light emitting elements may include a first light emitting element, a second light emitting element, and a third light emitting element that emit light of different colors, and the plurality of lower encapsulation inorganic patterns may include a first lower encapsulation inorganic pattern covering the first light emitting element, a second lower encapsulation inorganic pattern covering the second light emitting element, and a third lower encapsulation inorganic pattern covering the third light emitting element.

[0008] The common inorganic film may cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic pattern after drying.

[0009] The display panel may further include: a first additional encapsulation inorganic pattern covering the dried first lower encapsulation inorganic pattern; a second additional encapsulation inorganic pattern covering the dried second lower encapsulation inorganic pattern; and a third additional encapsulation inorganic pattern covering the dried third lower encapsulation inorganic pattern.

[0010] The common inorganic film may cover the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern.

[0011] The inner region may be defined in the common inorganic film, and the inner region may be an empty space.

[0012] In a plan view, the inner region may have a shape surrounding the light-emitting opening.

[0013] In a plan view, a part of the inner region may overlap with the plurality of lower encapsulation inorganic patterns.

[0014] Each of the plurality of lower encapsulation inorganic patterns may include: an upper surface; a first side surface extending from the upper surface in the thickness direction of the base layer; a lower surface extending from the first side surface toward the center of the anode in a cross-sectional view; and a second side surface extending from the lower surface in the thickness direction of the base layer.

[0015] The common inorganic film may cover the upper surface, the first side surface, the lower surface, and the second side surface of each of the plurality of dried lower encapsulation inorganic patterns.

[0016] The common inorganic film may include an inorganic material.

[0017] The common inorganic film may include at least one of silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ).

[0018] The display panel may further include: an encapsulation organic film covering the common inorganic film; and an upper encapsulation inorganic film covering the encapsulation organic film.

[0019] According to an embodiment, a method of manufacturing a display panel includes: providing a preliminary display panel including a base layer, a pixel defining film disposed on the base layer, and a preliminary partition wall disposed on the pixel defining film; forming a partition wall having a partition wall opening defined therein by the preliminary partition wall; etching the pixel defining film to form a light-emitting opening overlapping the partition wall opening in a plan view; forming a light-emitting element and a lower encapsulation inorganic pattern covering the light-emitting element inside the light-emitting opening and the partition wall opening; and drying the outer surfaces of the partition wall and the lower encapsulation inorganic pattern.

[0020] The formation of the light-emitting element and the lower encapsulation inorganic pattern may include: forming a first light-emitting element and a first lower encapsulation inorganic pattern that covers the first light-emitting element; forming a second light-emitting element and a second lower encapsulation inorganic pattern that covers the second light-emitting element; and forming a third light-emitting element and a third lower encapsulation inorganic pattern that covers the third light-emitting element.

[0021] The method may further include: forming a common inorganic film that covers the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic pattern.

[0022] The method may further include: forming an additional encapsulation inorganic pattern that covers the lower encapsulation inorganic pattern.

[0023] The drying of the outer surface of the partition wall and the lower encapsulation inorganic pattern may include: after the formation of the first light-emitting element and the first lower encapsulation inorganic pattern, drying the outer surface of the partition wall and the outer surface of the first lower encapsulation inorganic pattern; after the formation of the second light-emitting element and the second lower encapsulation inorganic pattern, drying the outer surface of the partition wall and the outer surface of the second lower encapsulation inorganic pattern; and after the formation of the third light-emitting element and the third lower encapsulation inorganic pattern, drying the outer surface of the partition wall and the outer surface of the third lower encapsulation inorganic pattern, and the formation of the additional encapsulation inorganic pattern that covers the lower encapsulation inorganic pattern may include: forming a first additional encapsulation inorganic pattern that covers the first lower encapsulation inorganic pattern; forming a second additional encapsulation inorganic pattern that covers the second lower encapsulation inorganic pattern; and forming a third additional encapsulation inorganic pattern that covers the third lower encapsulation inorganic pattern.

[0024] The method may further include: forming a common inorganic film that covers the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern.

[0025] According to an embodiment, a display panel includes: a base layer; a pixel defining film disposed on the base layer and defining a light-emitting opening therein; a partition wall disposed on the pixel defining film and defining a partition wall opening overlapping the light-emitting opening in a plan view; a plurality of light-emitting elements each including an anode, a light-emitting pattern, and a cathode and disposed inside the light-emitting opening and the partition wall opening, wherein the cathode is in contact with the partition wall; and a plurality of lower encapsulation inorganic patterns respectively covering the plurality of light-emitting elements, wherein only an inorganic material is disposed between the plurality of lower encapsulation inorganic patterns and the upper surface of the partition wall. Description of the Drawings

[0026] The above and other aspects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0027] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure.

[0028] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0030] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0031] Figure 4 is an enlarged plan view of a part of a display area of a display panel according to an embodiment of the present disclosure.

[0032] Figure 5 is along Figure 3 a cross-sectional view taken along line I-I'.

[0033] Figure 6 is along Figure 4 a cross-sectional view taken along line II-II'.

[0034] Figures 7A to 7I and Figures 8A to 8E are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to an embodiment of the present disclosure.

[0035] Figure 9 is along Figure 4 a cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0036] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is "on", "connected to", or "coupled to" a second component means that the first component is directly on, connected to, or coupled to the second component, or means that a third component is disposed therebetween.

[0037] Like reference numerals refer to like components. Further, in the drawings, for the purpose of effectively describing the technical content, the thickness, ratio, and size of the components are exaggerated. The expression "and / or" includes one or more combinations that the related components can define.

[0038] Although terms such as "first", "second", etc. may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the claims of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Unless otherwise clearly stated in the context, the singular expression includes the plural expression.

[0039] In addition, terms such as "under", "below", "above", "over", etc. are used to describe the correlation of components illustrated in the drawings. Conceptually opposite terms are described based on the directions illustrated in the drawings.

[0040] It will be understood that terms such as "comprising", "including", "having", etc. indicate the presence of features, numbers, steps, operations, elements or components or combinations thereof described in the specification, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements or components or combinations thereof in advance.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. In addition, terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with the context of the related art, and should not be interpreted in an overly ideal or formal sense unless explicitly defined herein.

[0042] Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0043] Figure 1A is a perspective view of a display device DD according to an embodiment of the present disclosure, and Figure 1B is an exploded perspective view of the display device DD according to an embodiment of the present disclosure.

[0044] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. In addition, the display device DD may be a medium or small electronic device such as a personal computer (PC) (e.g., a laptop computer or a tablet PC), a personal digital terminal, a vehicle navigation unit, a game console, a smart phone, and a camera. However, this is illustrative, and other display devices may be employed as long as they do not deviate from the concept of the present disclosure. Figure 1A and Figure 1B illustrate by way of example that the display device DD is a smart phone.

[0045] Reference Figure 1A and Figure 1B , the display device DD may display an image IM on a display surface FS parallel to a first direction DR1 and a second direction DR2 and in a third direction DR3. The image IM may include a still image and a moving image. In Figure 1A , a clock window and an icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0046] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined with respect to the direction of the display image IM. The front surface and the rear surface may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. At the same time, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be changed to other directions. In the specification, the phrase "on a plane" may mean a state when viewed in the third direction DR3 (i.e., a plan view).

[0047] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form the appearance of the display device DD.

[0048] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define the display surface FS of the display device DD. The display surface FS may include a transmissive region TA and a border region BZA. The transmissive region TA may be an optically transparent region. For example, the transmissive region TA may be a region having a visible light transmittance of about 90% or higher.

[0049] The border region BZA may be a region having a light transmittance relatively lower than that of the transmissive region TA. The border region BZA may define the shape of the transmissive region TA. The border region BZA may be adjacent to the transmissive region TA and surround the transmissive region TA. However, this is illustrative, and the border region BZA of the window WP may be omitted. The window WP may include at least one functional layer such as an anti-fingerprint layer, a hard coat, and an anti-reflection layer, and is not limited to the embodiment.

[0050] The display module DM may be disposed under the window WP. The display module DM may be a component that substantially generates the image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by a user from the outside through the transmissive region TA.

[0051] The display module DM may include a display region DA and a non-display region NDA. The display region DA may be a region activated according to an electrical signal. The non-display region NDA may be adjacent to the display region DA. The non-display region NDA may surround the display region DA. The non-display region NDA is a region covered by the border region BZA and may not be visually recognized from the outside.

[0052] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined internal space. The display module DM may be accommodated in this internal space.

[0053] The housing HAU may include a material having a relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates made of or including glass, plastic, or metal or a combination thereof. The housing HAU can stably protect the components accommodated in the internal space of the display device DD from external shocks.

[0054] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0055] Reference Figure 2 , the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, a display device DD (see Figure 1A ) according to an embodiment of the present disclosure may further include a protection member disposed on the lower surface of the display panel DP and an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0056] The display panel DP may be a light-emitting display panel. However, this is illustrative, and the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro light-emitting diodes (LEDs). Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0057] The display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the base layer BL. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In the specification, the phrase "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0058] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. The display area DA and the non-display area NDA defined in Figure 1B may be similarly defined in the base layer BL.

[0059] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and / or driving circuits of pixels, etc.

[0060] The display element layer DP-OLED may include partition walls and light-emitting elements. The light-emitting elements may include an anode, an intermediate layer, and a cathode.

[0061] The thin film encapsulation layer TFE may include a plurality of thin films. Some of the thin films may be arranged to improve optical efficiency, and some of the thin films may be arranged to protect the organic light emitting diode.

[0062] The input sensor INS acquires coordinate information of an external input. The input sensor INS may have a multilayer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. In addition, the input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may sense an external input in a capacitive manner. However, this is illustrative, and the present disclosure is not limited thereto. For another example, in an embodiment, the input sensor INS may also sense an external input in an electromagnetic induction manner or a pressure sensing manner. Meanwhile, in an embodiment of the present disclosure, the input sensor INS may be omitted.

[0063] Figure 3 is a plan view of a display panel DP according to an embodiment of the present disclosure. As used herein, a "plan view" is a view in the thickness direction (i.e., the third direction DR3) of the base layer BL (see Figure 5 ).

[0064] Reference Figure 3 , a display area DA and a non-display area NDA around the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished depending on whether pixels PX are provided. The pixels PX may be provided in the display area DA. The driving circuit GDC and the pad portion PLD may be arranged in the non-display area NDA.

[0065] The pixels PX may be arranged in a first direction DR1 and a second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0066] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding one of the pixels among the pixels PX, and each of the data lines DL may be connected to a corresponding one of the pixels among the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0067] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0068] The pad portion PLD may be a portion to which a flexible circuit board is connected. The pad portion PLD may include pixel pads D-PD, and the pixel pads D-PD may be pads for connecting a flexible circuit board to a display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line among signal lines SGL. The pixel pads D-PD may be connected to corresponding pixels PX through the signal lines SGL. In addition, any one of the pixel pads D-PD may be connected to a driving circuit GDC.

[0069] In addition, the pad portion PLD may further include input pads. The input pads may be pads for connecting a flexible circuit board to an input sensor INS (see Figure 2 ). However, the present disclosure is not limited thereto, and in another embodiment, the input pads may be disposed in the input sensor INS (see Figure 2 ) and connected to the pixel pads D-PD and a separate circuit board. Alternatively, the input sensor INS (see Figure 2 ) may be omitted, and the input pads may not be further included.

[0070] Figure 4 is an enlarged plan view of a part of a display area DA of a display panel DP (see Figure 2 ) according to an embodiment of the present disclosure. Figure 4 The figure illustrates a plan view of a display module DM (see Figure 1B ) when viewed from a display surface IS (see Figure 1B ) of the display module DM, and illustrates the arrangement of light emitting areas PXA-R, PXA-G, and PXA-B.

[0071] Referring to Figure 4 , the display area DA may include first to third light emitting areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, and PXA-B. The first to third light emitting areas PXA-R, PXA-G, and PXA-B may respectively correspond to areas that emit light provided from light emitting elements. The first to third light emitting areas PXA-R, PXA-G, and PXA-B may be distinguished according to the color of light emitted to the outside of the display module DM (see Figure 2 ).

[0072] The first to third light emitting areas PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first to third color lights are not necessarily limited to the above examples.

[0073] Each of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region where the upper surface of the anode is exposed by a light-emitting opening described below. The peripheral region NPXA may set boundaries between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B.

[0074] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B may be provided such that their numbers are all plural, and the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may be repeatedly arranged in a specific layout form in the display area DA. For example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged in the first direction DR1 to constitute a "first group". The second light-emitting region PXA-G may be arranged in the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0075] One second light-emitting region PXA-G may be spaced apart from one first light-emitting region PXA-R or one third light-emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as the direction between the first direction DR1 and the second direction DR2.

[0076] Meanwhile, Figure 4 The illustrative example shows the layout form of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, but the present disclosure is not limited thereto and the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may be arranged in various forms. In an embodiment, as Figure 4 shown, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have a layout form. Alternatively, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may also have a stripe layout form or a diamond layout form.

[0077] On a plane, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have various shapes. For example, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have shapes such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4The illustrative diagram shows a first light-emitting region PXA-R and a third light-emitting region PXA-B having a quadrilateral shape (or a rhombus shape) on a plane, and a second light-emitting region PXA-G having an octagonal shape.

[0078] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same shape on the plane, or may have at least partially different shapes. Figure 4 The illustrative diagram shows a first light-emitting region PXA-R and a third light-emitting region PXA-B having the same shape on a plane, and a second light-emitting region PXA-G having a shape different from the shapes of the first light-emitting region PXA-R and the third light-emitting region PXA-B.

[0079] At least some of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas on the plane. In an embodiment, the area of the first light-emitting region PXA-R that emits red light may be greater than the area of the second light-emitting region PXA-G that emits green light, and may be less than the area of the third light-emitting region PXA-B that emits blue light. However, the dimensional relationship according to the color of the emitted light among the areas of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B is not limited thereto, and may be changed depending on the design of the display module DM (see Figure 2 ). In addition, the present disclosure is not limited thereto, and in another embodiment, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may also have the same area on the plane.

[0080] The shapes, areas, and / or arrangements, etc. of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B of the display module DM (see Figure 2 ) of the present disclosure may be variously designed according to the color of the emitted light or the size and structure of the display module DM (see Figure 2 ), and are not limited to Figure 4 the illustrated embodiments.

[0081] Figure 5 is a cross-sectional view of the display panel DP along line I-I' of Figure 3 . In the description of Figure 5 , it will be described with reference to Figure 2 , and the description of the same reference numerals will be omitted. Figure 5 An enlarged diagram shows one light-emitting region PXA in the display area DA (see Figure 4 ), and Figure 5 the light-emitting region PXA may correspond to one of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B of Figure 4 .

[0082] Refer toFigure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0083] The display panel DP may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and / or a plurality of signal lines, etc. The insulating layer, semiconductor layer, and conductive layer are formed by coating or deposition, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, and / or signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed.

[0084] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer to a fifth insulating layer 10, 20, 30, 40, and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0085] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the adhesion between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately laminated.

[0086] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present disclosure is not limited thereto, and in another embodiment, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 An illustrative diagram shows a part of the semiconductor pattern, and the semiconductor pattern may be further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 4 ). The semiconductor pattern may be arranged in the plurality of light emitting regions PXA-R, PXA-G, and PXA-B according to a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0087] The conductivity of the first region is greater than that of the second region, and the first region may substantially act as an electrode or a signal line. The second region may substantially correspond to the active region (or channel) of the transistor. In other words, a part of the semiconductor pattern may be the active region of the transistor, another part of the semiconductor pattern may be the source or drain of the transistor, and still another part of the semiconductor pattern may be a conductive region.

[0088] The source S, active region A, and drain D of the transistor TR1 can be formed of a semiconductor pattern. Figure 5 A part of the signal transmission region SCL formed of a semiconductor pattern is illustrated. Although not illustrated separately, the signal transmission region SCL can be connected to the drain D of the transistor TR1 in a plane.

[0089] The first insulating layer to the fifth insulating layers 10, 20, 30, 40, and 50 can be disposed on the buffer layer BFL. The first insulating layer to the fifth insulating layers 10, 20, 30, 40, and 50 can be an inorganic layer or an organic layer.

[0090] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can cover the source S, active region A, and drain D of the transistor TR1 disposed on the buffer layer BFL and the signal transmission region SCL. The gate G of the transistor TR1 can be disposed on the first insulating layer 10. The second insulating layer 20 can be disposed on the first insulating layer 10 to cover the gate G. The electrode EE can be disposed on the second insulating layer 20. The third insulating layer 30 can be disposed on the second insulating layer 20 to cover the electrode EE.

[0091] The first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal transmission region SCL through the contact hole CNT-1 passing through the first insulating layer to the third insulating layers 10, 20, and 30. The fourth insulating layer 40 can be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 can be an organic layer.

[0092] The second connection electrode CNE2 can be disposed on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through the contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 can be an organic layer.

[0093] The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED can include a light-emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, and a partition wall PW.

[0094] The light-emitting element ED can include an anode AE (or a first electrode), a light-emitting pattern EP, and a cathode CE (or a second electrode). The light-emitting element ED can be disposed in the light-emitting opening OP-E and the partition wall opening OP-P, which will be described below.

[0095] The anode AE can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined through the fifth insulating layer 50. Accordingly, the anode AE can be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element. The anode AE can include a single-layer structure or a multi-layer structure. The anode AE can include a plurality of layers including ITO and Ag. For example, the anode AE can include a layer containing ITO (hereinafter, referred to as the lower ITO layer), a layer disposed on the lower ITO layer and containing Ag (hereinafter, referred to as the Ag layer), and a layer disposed on the Ag layer and containing ITO (hereinafter, referred to as the upper ITO layer).

[0096] The sacrificial pattern SP can be disposed between the anode AE and the pixel defining film PDL. The sacrificial pattern SP can define (or have) a sacrificial opening OP-S through which a part of the upper surface of the anode AE is exposed. The sacrificial opening OP-S can overlap with the light-emitting opening OP-E in a plan view, which will be described below.

[0097] The pixel defining film PDL can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining film PDL can define (or have) a light-emitting opening OP-E. The light-emitting opening OP-E can correspond to the anode AE, and the pixel defining film PDL can expose at least a part of the anode AE through the light-emitting opening OP-E.

[0098] In addition, the light-emitting opening OP-E can correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to an embodiment, the upper surface of the anode AE can be spaced apart from the pixel defining film PDL in a cross-section, with the sacrificial pattern SP interposed between the upper surface of the anode AE and the pixel defining film PDL, and accordingly, damage to the anode AE can be prevented in the process of forming the light-emitting opening OP-E.

[0099] In a plane, the area of the light-emitting opening OP-E can be smaller than the area of the sacrificial opening OP-S. That is, the inner surface of the pixel defining film PDL defining the light-emitting opening OP-E can be closer to the center of the anode AE than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the present disclosure is not limited thereto, and in another embodiment, the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S can be substantially aligned with the inner surface of the pixel defining film PDL defining the light-emitting opening OP-E. In this case, the light-emitting region PXA can be regarded as the region of the anode AE exposed from the corresponding sacrificial opening OP-S.

[0100] The pixel defining layer PDL may include an inorganic insulating material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ). The pixel defining layer PDL may be disposed between the anode AE and the partition wall PW, and block the electrical connection between the anode AE and the partition wall PW.

[0101] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may include a light emitting layer containing a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE and the light emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light emitting layer. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0102] The light emitting pattern EP may be patterned through a tip portion defined by the partition wall PW. Its detailed description will be given in the description of the method for manufacturing a display panel. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S and the light emitting opening OP-E. However, this is illustratively shown, and the light emitting pattern EP may be disposed inside at least one of the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a part of the upper surface of the pixel defining layer PDL.

[0103] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned through a tip portion defined by the partition wall PW. At least a part of the cathode CE may be disposed in the partition wall opening OP-P. Figure 5 Illustratively shown is that the cathode CE is disposed inside the light emitting opening OP-E and the partition wall opening OP-P, but the present disclosure is not limited thereto. For another example, the cathode CE may be disposed only inside the partition wall opening OP-P.

[0104] The cathode CE may extend along the first inner surface of the first partition wall layer L1, and the distal end of the cathode CE may be in contact with the first partition wall layer L1. Figure 5 Illustratively shown is that the cathode CE is in contact with the first inner surface of the first partition wall layer L1 and the inner surface of the pixel defining layer PDL, but the present disclosure is not limited thereto. For another example, the cathode CE may be formed to be in contact with only the first inner surface of the first partition wall layer L1.

[0105] The cathode CE may be conductive. The cathode CE may be formed of various materials (e.g., metals, transparent conductive oxides (TCO), and conductive polymer materials), as long as these materials can conduct electricity. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0106] In an embodiment of the present disclosure, the display element layer DP-OLED may further include a capping pattern CP. The capping pattern CP may be disposed inside the partition wall opening OP-P and on the cathode CE. The capping pattern CP may be patterned through a tip portion defined by the partition wall PW. In an embodiment, the capping pattern CP may be omitted.

[0107] The partition wall PW may be disposed on the pixel defining film PDL. The partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may overlap with the light emitting opening OP-E in a plan view and expose at least a part of the anode AE.

[0108] The partition wall PW may include a plurality of layers laminated in sequence. For example, the partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel defining film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. As Figure 5 shown, the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2, but the present disclosure is not limited thereto.

[0109] The first partition wall layer L1 and the second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a TCO, or a combination thereof. For example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0110] In a cross section, the partition wall PW may have an undercut shape. At least one layer of the plurality of layers of the partition wall PW may be recessed compared to other layers, and accordingly, the partition wall PW may include a tip portion. For example, the first partition wall layer L1 may have an undercut shape with respect to the second partition wall layer L2. The second partition wall layer L2 may protrude toward the light emitting opening OP-E more than the first partition wall layer L1. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the light emitting region PXA may be defined as the tip portion inside the partition wall PW. That is, a second inner surface of the second partition wall layer L2 may be closer to the center of the anode AE than a first inner surface of the first partition wall layer L1.

[0111] Figure 5 Illustratively, each of the first inner surface of the first partition wall layer L1 and the second inner surface of the second partition wall layer L2 is perpendicular to the upper surface of the pixel defining film PDL, but the present disclosure is not limited thereto. Again, for example, the partition wall PW may have a tapered shape or an inverted tapered shape.

[0112] The partition wall PW can receive a driving voltage, and accordingly, the cathode CE can be electrically connected to the partition wall PW and receive the driving voltage.

[0113] The thin film encapsulation layer TFE can be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE can include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0114] The lower encapsulation inorganic pattern LIL can correspond to (or overlap with) the light-emitting opening OP-E. The lower encapsulation inorganic pattern LIL can be disposed on the capping pattern CP and cover the light-emitting element ED. A part of the lower encapsulation inorganic pattern LIL can be formed inside the partition wall opening OP-P, and another part of the lower encapsulation inorganic pattern LIL can be formed on the partition wall PW.

[0115] The lower encapsulation inorganic pattern LIL can include an upper surface U_LIL, a first side surface S1_LIL, a lower surface B_LIL, and a second side surface S2_LIL. The first side surface S1_LIL can extend from the upper surface U_LIL in the thickness direction of the base layer BL (e.g., in a direction opposite to the third direction DR3). The lower surface B_LIL can extend from the first side surface S1_LIL toward the center of the anode AE. The second side surface S2_LIL can extend from the lower surface B_LIL in the thickness direction of the base layer BL (e.g., in a direction opposite to the third direction DR3).

[0116] The common inorganic film CLIL can cover the lower encapsulation inorganic pattern LIL and fill the space between the partition wall PW and the lower encapsulation inorganic pattern LIL (e.g., the space defined by the first side surface S1_LIL, the lower surface B_LIL, the second side surface S2_LIL, and the upper surface of the second partition wall layer L2). The common inorganic film CLIL can cover the dried lower encapsulation inorganic pattern LIL. For example, since the outer surface of the lower encapsulation inorganic pattern LIL is dried, the common inorganic film CLIL can cover the lower encapsulation inorganic pattern LIL in a state without residual moisture.

[0117] The inner region ES can be defined in the common inorganic film CLIL. The inner region ES can be an empty space formed during the process of depositing the common inorganic film CLIL. For example, the inner region ES can be filled with gas. The inner region ES can have a shape surrounding the light-emitting opening OP-E in a plane. A part of the inner region ES can overlap with the lower encapsulation inorganic pattern LIL in a plane, and the inner region ES can overlap with the partition wall PW in a plane. That is, the inner region ES can be formed between the lower encapsulation inorganic pattern LIL and the partition wall PW and overlap with the lower encapsulation inorganic pattern LIL and the partition wall PW in a plan view.

[0118] The common inorganic film CLIL can cover the upper surface U_LIL, the first side surface S1_LIL, the lower surface B_LIL, and the second side surface S2_LIL of the lower encapsulation inorganic pattern LIL. That is to say, the common inorganic film CLIL can cover the outer surface of the lower encapsulation inorganic pattern LIL and can be formed by surrounding the internal region ES.

[0119] The common inorganic film CLIL can include inorganic materials. For example, the common inorganic film CLIL can include at least one of silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). That is to say, only inorganic substances can exist between the lower encapsulation inorganic pattern LIL and the upper surface of the partition wall PW.

[0120] The encapsulation organic film OL can be disposed on the common inorganic film CLIL. The encapsulation organic film OL can cover the common inorganic film CLIL and provide a flat upper surface. The upper encapsulation inorganic film UIL can be disposed on the encapsulation organic film OL. The lower encapsulation inorganic pattern LIL, the common inorganic film CLIL, and the upper encapsulation inorganic film UIL can protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL can protect the display element layer DP-OLED from foreign substances such as dust particles.

[0121] Figure 5 The illustrative drawing shows that the thin film encapsulation layer TFE includes the lower encapsulation inorganic pattern LIL, the common inorganic film CLIL, the encapsulation organic film OL, and the upper encapsulation inorganic film UIL, but the present disclosure is not limited thereto. Again, for example, in an embodiment, the thin film encapsulation layer TFE can further include additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3 (see Figure 9 ) disposed between the lower encapsulation inorganic pattern LIL and the common inorganic film CLIL. Details will be described below in Figure 9 .

[0122] According to the present disclosure, the organic substances that absorb moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW can be removed, and the residual moisture can be removed by a drying process. Therefore, the phenomenon of introducing foreign substances through the moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW can be reduced or eliminated. As a result, the pixel defects (such as dark spots or pixel shrinkage, etc.) of the display panel DP caused by foreign substances can be effectively reduced or eliminated.

[0123] In addition, in the related art, the encapsulation organic film OL is thickened so that the thin film encapsulation layer TFE has a low dielectric constant. However, in the present disclosure, an inner region ES is defined in the common inorganic film CLIL, and thus, the common inorganic film CLIL can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film OL of the present disclosure can be reduced, and the thickness of the encapsulation organic film OL can be reduced to effectively improve the touch sensitivity.

[0124] Figure 6 is a cross-sectional view taken along Figure 4 line II-II’ of. Figure 6 The enlarged view illustrates a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and Figure 5 the description of a light-emitting region PXA of can be equally applied to Figure 6 the first to third light-emitting regions PXA-R, PXA-G, and PXA-B of. In Figure 6 the description of, the same / similar reference numerals are used for Figure 5 the same / similar components described in, and the repeated description thereof will be omitted.

[0125] Referring to Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light-emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, and partition walls PW.

[0126] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 that emit light of different colors. A plurality of first light-emitting elements ED1, a plurality of second light-emitting elements ED2, and a plurality of third light-emitting elements ED3 may be provided. However, for ease of description, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 will be represented in the singular form hereinafter.

[0127] The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided as a plurality of patterns. In an embodiment, the first light-emitting pattern EP1 may provide red light, the second light-emitting pattern EP2 may provide green light, and the third light-emitting pattern EP3 may provide blue light.

[0128] The first light-emitting opening to the third light-emitting openings OP1-E, OP2-E, and OP3-E can be defined in the pixel-defining layer PDL. The first light-emitting opening OP1-E can expose at least a part of the first anode AE1. The second light-emitting opening OP2-E can expose at least a part of the second anode AE2. The third light-emitting opening OP3-E can expose at least a part of the third anode AE3.

[0129] In an embodiment, the first light-emitting region PXA-R can be defined as the region of the upper surface of the first anode AE1 that is exposed by the first light-emitting opening OP1-E. The second light-emitting region PXA-G can be defined as the region of the upper surface of the second anode AE2 that is exposed by the second light-emitting opening OP2-E. The third light-emitting region PXA-B can be defined as the region of the upper surface of the third anode AE3 that is exposed by the third light-emitting opening OP3-E.

[0130] The sacrificial patterns SP1, SP2, and SP3 can include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, and SP3 can be disposed on the upper surfaces of the first to third anodes AE1, AE2, and AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, and OP3-S that overlap the first to third light-emitting openings OP1-E, OP2-E, and OP3-E in a plan view can be defined in the first to third sacrificial patterns SP1, SP2, and SP3, respectively.

[0131] In an embodiment, the first to third partition wall openings OP1-P, OP2-P, and OP3-P that overlap the first to third light-emitting openings OP1-E, OP2-E, and OP3-E, respectively, can be defined in the partition wall PW.

[0132] In an embodiment, the first light-emitting pattern to the third light-emitting patterns EP1, EP2, and EP3 and the first cathode to the third cathodes CE1, CE2, and CE3 may be physically separated by the second partition wall layer L2 forming the tip portions, and may be formed inside the light-emitting openings OP1-E, OP2-E, and OP3-E and the partition wall openings OP1-P, OP2-P, and OP3-P. That is, the light-emitting elements ED1, ED2, and ED3 may be disposed inside the partition wall openings OP1-P, OP2-P, and OP3-P and the light-emitting openings OP1-E, OP2-E, and OP3-E. For example, the first light-emitting element ED1 may be disposed inside the first partition wall opening OP1-P and the first light-emitting opening OP1-E, the second light-emitting element ED2 may be disposed inside the second partition wall opening OP2-P and the second light-emitting opening OP2-E, and the third light-emitting element ED3 may be disposed inside the third partition wall opening OP3-P and the third light-emitting opening OP3-E.

[0133] According to the present disclosure, a plurality of first light-emitting patterns EP1 may be patterned and deposited in pixel units through the tip portions defined in the partition wall PW. That is, the first light-emitting pattern EP1 may be commonly formed using an aperture mask, but may be easily divided in pixel units by the partition wall PW.

[0134] On the other hand, when patterning the first light-emitting pattern EP1 using a fine metal mask (FMM), support spacers protruding from the conductive partition wall to support the FMM should be provided. In addition, since the FMM is spaced apart from the substrate surface on which it is patterned by the height of the partition wall PW and the spacers, the realization of high resolution may be limited. In addition, since the FMM contacts the spacers, the spacers may be damaged due to foreign substances remaining on the spacers or stamping of the FMM after the patterning process of the first light-emitting pattern EP1. Accordingly, a defective display panel may be formed.

[0135] According to an embodiment, the partition wall PW is included such that physical separation between the light-emitting elements ED1, ED2, and ED3 can be easily performed. Accordingly, current leakage or driving errors between adjacent light-emitting regions PXA-R, PXA-G, and PXA-B can be prevented, and independent driving of each of the light-emitting elements ED1, ED2, and ED3 can be performed.

[0136] Specifically, since a plurality of first light-emitting patterns EP1 are formed without using a mask corresponding to the display area DA (see Figure 1B) It is patterned in the case of a mask in contact with internal components inside, thus reducing the defect rate, and thus a display panel DP with improved process reliability can be provided. Since patterning can be performed even when a separate support spacer protruding from the partition wall PW is not provided, the areas of the light-emitting regions PXA-R, PXA-G, and PXA-B can be minimized, and thus a display panel DP that can easily achieve high resolution can be provided.

[0137] In addition, when manufacturing a large-area display panel DP, a display panel DP in which the process cost can be reduced due to the omission of the production of a large-area mask can be provided, and since the display panel DP is not affected by defects that may occur in the large-area mask, the process reliability can be improved. The description of the plurality of first light-emitting patterns EP1 can be equally applied to the plurality of second light-emitting patterns EP2 and the plurality of third light-emitting patterns EP3.

[0138] The thin-film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0139] The lower encapsulation inorganic pattern LIL may include a first lower encapsulation inorganic pattern LIL1 covering the first light-emitting element ED1, a second lower encapsulation inorganic pattern LIL2 covering the second light-emitting element ED2, and a third lower encapsulation inorganic pattern LIL3 covering the third light-emitting element ED3. In a plan view, the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may overlap the first light-emitting opening to the third light-emitting openings OP1-E, OP2-E, and OP3-E, respectively. The first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may be provided in the form of patterns spaced apart from each other.

[0140] The common inorganic film CLIL may cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, and fill the space between the partition wall PW and the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. The common inorganic film CLIL may cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 after being dried. For example, the common inorganic film CLIL may cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 in a state where there is no remaining moisture after being dried on the outer surfaces of the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0141] The internal regions ES1, ES2, and ES3 can be defined within a common inorganic film CLIL. The internal regions ES1, ES2, and ES3 can be empty spaces formed during the process of depositing the common inorganic film CLIL. For example, the internal regions ES1, ES2, and ES3 can be filled with gas. The internal regions ES1, ES2, and ES3 can include a first internal region ES1, a second internal region ES2, and a third internal region ES3.

[0142] The first internal region ES1 can have a shape surrounding the first light-emitting opening OP1-E in a plane (i.e., in a plan view). A part of the first internal region ES1 can overlap with the first lower encapsulation inorganic pattern LIL1 in a plane, and the first internal region ES1 can overlap with the partition wall PW in a plane. That is, the first internal region ES1 can be formed between the first lower encapsulation inorganic pattern LIL1 and the partition wall PW and overlap with the first lower encapsulation inorganic pattern LIL1 and the partition wall PW in a plan view.

[0143] The second internal region ES2 can have a shape surrounding the second light-emitting opening OP2-E in a plane (i.e., in a plan view). A part of the second internal region ES2 can overlap with the second lower encapsulation inorganic pattern LIL2 in a plane, and the second internal region ES2 can overlap with the partition wall PW in a plane. That is, the second internal region ES2 can be formed between the second lower encapsulation inorganic pattern LIL2 and the partition wall PW and overlap with the second lower encapsulation inorganic pattern LIL2 and the partition wall PW in a plan view.

[0144] The third internal region ES3 can have a shape surrounding the third light-emitting opening OP3-E in a plane (i.e., in a plan view). A part of the third internal region ES3 can overlap with the third lower encapsulation inorganic pattern LIL3 in a plane, and the third internal region ES3 can overlap with the partition wall PW in a plane. That is, the third internal region ES3 can be formed between the third lower encapsulation inorganic pattern LIL3 and the partition wall PW and overlap with the third lower encapsulation inorganic pattern LIL3 and the partition wall PW in a plan view.

[0145] The common inorganic film CLIL can cover the upper surface U_LIL (see Figure 5 ), the first side surface S1_LIL (see Figure 5 ), the lower surface B_LIL (see Figure 5 ), and the second side surface S2_LIL (see Figure 5)。That is to say, the common inorganic film CLIL can cover the outer surfaces of the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, and can be formed while surrounding the first inner region to the third inner regions ES1, ES2, and ES3.

[0146] Figures 7A to 7I and Figures 8A to 8E are cross-sectional views showing some of the operations of a method for manufacturing a display panel according to an embodiment of the present disclosure. In Figures 7A to 8E the description, the same / similar reference numerals will be used for the same / similar components described in FIGS. 1 to Figure 6 and the repeated description thereof will be omitted.

[0147] A method for manufacturing a display panel according to an embodiment of the present disclosure may include: an operation of providing a preliminary display panel, the preliminary display panel including a base layer, a pixel defining film provided on the base layer, and a preliminary partition wall provided on the pixel defining film; an operation of forming a partition wall in which a partition wall opening is defined by the preliminary partition wall; an operation of etching the pixel defining film to form a light-emitting opening overlapping the partition wall opening in a plan view; an operation of forming a light-emitting element and a lower encapsulation inorganic pattern covering the light-emitting element inside the light-emitting opening and the partition wall opening; and an operation of drying the outer surfaces of the partition wall and the lower encapsulation inorganic pattern.

[0148] Hereinafter, a method for forming three light-emitting elements ED1, ED2, and ED3, lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 covering the light-emitting elements ED1, ED2, and ED3, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL will be described. The display panel DP formed by Figures 7A to 8E may correspond to the display panel DP of Figures 7A to 8E . Figure 6 the display panel DP of

[0149] Referring to Figure 7A , a method for manufacturing a display panel according to the present disclosure may include providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in the embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode to a third anode AE1, AE2, and AE3, a first preliminary sacrificial pattern to a third preliminary sacrificial pattern SP1-I, SP2-I, and SP3-I, a pixel defining film PDL, and a preliminary partition wall PW-I. The preliminary partition wall PW-I may include a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0150] A circuit element layer DP-CL can be formed by a general method of manufacturing circuit elements in which an insulating layer, a semiconductor layer, and a conductive layer are formed by a coating method or a deposition method, the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned by photolithography and etching processes, and a semiconductor pattern, a conductive pattern, a signal line, etc. are formed.

[0151] The first anode AE1 and the first preliminary sacrificial pattern SP1-I can be formed by the same patterning process, the second anode AE2 and the second preliminary sacrificial pattern SP2-I can be formed by the same patterning process, and the third anode AE3 and the third preliminary sacrificial pattern SP3-I can be formed by the same patterning process. The pixel defining layer PDL can be disposed on the base layer BL. The pixel defining layer PDL can cover all of the first to third anodes AE1, AE2, and AE3 and the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I.

[0152] The first preliminary partition layer L1-I can be disposed on the pixel defining layer PDL. The first preliminary partition layer L1-I can be formed by a process of depositing a conductive material. The second preliminary partition layer L2-I can be disposed on the first preliminary partition layer L1-I. The second preliminary partition layer L2-I can also be formed by a process of depositing a conductive material. The first preliminary partition layer L1-I and the second preliminary partition layer L2-I can include a metal, a TCO, or a combination thereof. For example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In an embodiment of the present disclosure, the first preliminary partition layer L1-I can include aluminum (Al), and the second preliminary partition layer L2-I can include titanium (Ti). However, the materials of the first preliminary partition layer L1-I and the second preliminary partition layer L2-I are not limited thereto.

[0153] Thereafter, referring to Figure 7B, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a first photoresist layer PR1 on a preliminary partition wall PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-I and then patterning the preliminary photoresist layer using a photomask. First light openings OP-PR1, second light openings OP-PR2, and third light openings OP-PR3 may be formed in the first photoresist layer PR1 through a patterning process. In a plan view, the first light opening OP-PR1 may overlap with a first anode AE1, the second light opening OP-PR2 may overlap with a second anode AE2, and the third light opening OP-PR3 may overlap with a third anode AE3.

[0154] Thereafter, referring to Figure 7C and Figure 7D , the method of manufacturing a display panel according to the present disclosure may include an operation of forming a partition wall PW in which partition wall openings OP1-P, OP2-P, and OP3-P are defined by the preliminary partition wall PW-I (see Figure 7B ). The operation of forming the partition wall PW may include an operation of forming a first partition wall layer L1 and a second partition wall layer L2 in which the partition wall openings OP1-P, OP2-P, and OP3-P are defined by etching a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0155] First, as shown in Figure 7C , in the operation of initially etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may be dry-etched using the first photoresist layer PR1 as a mask. Portions of the preliminary partition wall PW-I that do not overlap with the first photoresist layer PR1 in a plan view may be etched and removed. For example, a first preliminary partition wall opening OP1-PI may be formed by removing a portion of the preliminary partition wall PW-I that overlaps with the first light opening OP-PR1, a second preliminary partition wall opening OP2-PI may be formed by removing a portion of the preliminary partition wall PW-I that overlaps with the second light opening OP-PR2, and a third preliminary partition wall opening OP3-PI may be formed by removing a portion of the preliminary partition wall PW-I that overlaps with the third light opening OP-PR3.

[0156] The initial dry-etching process in the embodiment may be performed in an etching environment in which the etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is substantially the same. Accordingly, the inner surfaces of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I that define the preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI may be substantially aligned with each other.

[0157] Thereafter, as Figure 7D shown in, in the operation of secondarily etching the first preliminary partition wall layer L1-I (see Figure 7C ), the first photoresist layer PR1 can be used as a mask to wet-etch the first preliminary partition wall layer L1-I. Accordingly, a part of the first preliminary partition wall layer L1-I can be etched to form partition wall openings OP1-P, OP2-P, and OP3-P. The partition wall openings OP1-P, OP2-P, and OP3-P can include a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P. In a plan view, the first partition wall opening OP1-P can be formed to overlap with the first anode AE1, the second partition wall opening OP2-P can be formed to overlap with the second anode AE2, and the third partition wall opening OP3-P can be formed to overlap with the third anode AE3.

[0158] The second wet etching process in the present disclosure can be performed in an environment where the etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I (see Figure 7C ) is high. Accordingly, the inner surfaces of the partition wall PW defining the partition wall openings OP1-P, OP2-P, and OP3-P can have an undercut shape in cross section. Specifically, since the etching rate of the first preliminary partition wall layer L1-I with respect to the etching solution is greater than the etching rate of the second preliminary partition wall layer L2-I with respect to the etching solution, the first preliminary partition wall layer L1-I can be mainly etched. Accordingly, the first inner surface of the first partition wall layer L1 can be recessed inward more than the second inner surface of the second partition wall layer L2. A tip portion can be formed in the partition wall PW by a portion of the second partition wall layer L2 that further protrudes from the first partition wall layer L1.

[0159] Thereafter, referring to Figure 7E , the method of manufacturing a display panel according to the present disclosure can include an operation of etching a pixel defining layer PDL to form light-emitting openings OP1-E, OP2-E, and OP3-E that overlap with the partition wall openings OP1-P, OP2-P, and OP3-P in a plan view.

[0160] In the operation of etching the pixel-defining layer PDL, the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) can be used as a mask to dry-etch the pixel-defining layer PDL. The portions of the pixel-defining layer PDL that do not overlap with the first photoresist layer PR1 and the partition wall PW in the plan view can be etched and removed. As a result, light-emitting openings OP1-E, OP2-E, and OP3-E that overlap with the partition wall openings OP1-P, OP2-P, and OP3-P in the plan view can be formed in the pixel-defining layer PDL. The light-emitting openings OP1-E, OP2-E, and OP3-E can include a first light-emitting opening OP1-E that overlaps with the first partition wall opening OP1-P, a second light-emitting opening OP2-E that overlaps with the second partition wall opening OP2-P, and a third light-emitting opening OP3-E that overlaps with the third partition wall opening OP3-P in the plan view.

[0161] Thereafter, referring to Figure 7F , the method of manufacturing a display panel according to the present disclosure can include an operation of etching the first preliminary sacrificial pattern to the third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I (see Figure 7E ) to form sacrificial patterns SP1, SP2, and SP3, and the sacrificial patterns SP1, SP2, and SP3 define sacrificial openings OP1-S, OP2-S, and OP3-S that overlap with the light-emitting openings OP1-E, OP2-E, and OP3-E in the plan view, respectively.

[0162] In the operation of etching the first preliminary sacrificial pattern to the third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I, the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) can be used as a mask to wet-etch the first preliminary sacrificial pattern to the third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I. The portions of the first preliminary sacrificial pattern to the third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I that do not overlap with the first photoresist layer PR1 and the partition wall PW in the plan view can be etched and removed. As a result, the sacrificial patterns SP1, SP2, and SP3 can be formed from the first preliminary sacrificial pattern to the third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I.

[0163] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening OP1-S overlapping with the first light-emitting opening OP1-E in a plan view may be formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S overlapping with the second light-emitting opening OP2-E in a plan view may be formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S overlapping with the third light-emitting opening OP3-E in a plan view may be formed in the third sacrificial pattern SP3.

[0164] The etching process of the sacrificial patterns SP1, SP2, and SP3 may be performed in an environment where the etching selectivity between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is high, and thus, the anodes AE1, AE2, and AE3 can be prevented from being etched together. That is, since the sacrificial patterns SP1, SP2, and SP3 having an etching rate higher than that of the anodes AE1, AE2, and AE3 are disposed between the pixel defining film PDL and the anodes AE1, AE2, and AE3, the anodes AE1, AE2, and AE3 can be prevented from being etched together and damaged during the etching process.

[0165] Thereafter, referring to Figures 7G to 8B , the method of manufacturing a display panel according to the present disclosure may include: after removing the first photoresist layer PR1 (see Figure 7F ), an operation of forming light-emitting elements ED1, ED2, and ED3 and lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 covering the light-emitting elements ED1, ED2, and ED3 inside the light-emitting openings OP1-E, OP2-E, and OP3-E and the partition openings OP1-P, OP2-P, and OP3-P.

[0166] The operation of forming the light-emitting elements ED1, ED2, and ED3 and the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may include an operation of forming a first light-emitting element ED1 and a first lower encapsulation inorganic pattern LIL1 covering the first light-emitting element ED1, an operation of forming a second light-emitting element ED2 and a second lower encapsulation inorganic pattern LIL2 covering the second light-emitting element ED2, and an operation of forming a third light-emitting element ED3 and a third lower encapsulation inorganic pattern LIL3 covering the third light-emitting element ED3. By Figures 7G to 7I describing the operation of forming the first light-emitting element ED1 and the first lower encapsulation inorganic pattern LIL1, and by Figure 8A and Figure 8B describing the operation of forming the second light-emitting element ED2 and the second lower encapsulation inorganic pattern LIL2 and the operation of forming the third light-emitting element ED3 and the third lower encapsulation inorganic pattern LIL3.

[0167] Referring toFigure 7G The operation of forming the first light-emitting element ED1 may include the operation of forming the first light-emitting pattern EP1 and the operation of forming the first cathode CE1. The operation of forming the first light-emitting pattern EP1 may include a process of depositing a light-emitting layer. For example, the operation of forming the first light-emitting pattern EP1 may include the operation of thermally evaporating the light-emitting layer. The light-emitting layer may be separated by a tip portion formed in the partition wall PW and may be deposited inside the first partition wall opening to the third partition wall openings OP1-P, OP2-P, and OP3-P and on the partition wall PW. The light-emitting layer formed in the first partition wall opening OP1-P may form the first light-emitting pattern EP1, and the light-emitting layer formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may form the first dummy layer D1. That is, the first light-emitting pattern EP1 may be formed on the first anode AE1 to overlap the first partition wall opening OP1-P in a plan view, and the first light-emitting pattern EP1 may be formed to cover the first anode AE1 and the pixel defining film PDL.

[0168] The first dummy layer D1 formed together in the operation of forming the first light-emitting pattern EP1 may include an organic material. For example, the first dummy layer D1 may include the same material as the material of the first light-emitting pattern EP1. The first dummy layer D1 may be formed simultaneously with the first light-emitting pattern EP1 by one process and separated from the first light-emitting pattern EP1 by an undercut shape of the partition wall PW.

[0169] The operation of forming the first cathode CE1 may include a process of depositing a cathode layer. For example, the operation of forming the first cathode CE1 may include the operation of sputtering the cathode layer. The cathode layer may be separated by a tip portion formed in the partition wall PW and may be deposited inside the first partition wall opening to the third partition wall openings OP1-P, OP2-P, and OP3-P and on the partition wall PW. The cathode layer formed in the first partition wall opening OP1-P may form the first cathode CE1, and the cathode layer formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may form the second dummy layer D2. That is, the first cathode CE1 may be formed on the first light-emitting pattern EP1 to overlap the first partition wall opening OP1-P in a plan view, and the first cathode CE1 may be formed to cover the first light-emitting pattern EP1. In addition, the first cathode CE1 may be in contact with the inner surface of the first partition wall layer L1 and extend along the inner surface of the first partition wall layer L1.

[0170] The second dummy layer D2 formed together in the operation of forming the first cathode CE1 may include a conductive material. For example, the second dummy layer D2 may include the same material as that of the first cathode CE1. The second dummy layer D2 may be formed simultaneously with the first cathode CE1 through one process and separated from the first cathode CE1 by the undercut shape of the partition wall PW.

[0171] The first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 may be sequentially laminated in the third direction DR3. The first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 may form the first light-emitting element ED1.

[0172] The method of manufacturing a display panel according to the present disclosure may include an operation of forming a capping pattern CP. The operation of forming the capping pattern CP may include a process of depositing a capping pattern layer. The capping pattern layer may be separated through the tip portions formed in the partition wall PW and may be deposited inside the first partition wall opening to the third partition wall openings OP1-P, OP2-P, and OP3-P and on the partition wall PW. The capping pattern layer formed in the first partition wall opening OP1-P may form the capping pattern CP, and the capping pattern layers formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may form the third dummy layer D3.

[0173] The third dummy layer D3 formed together in the operation of forming the capping pattern CP may include a conductive material. For example, the third dummy layer D3 may include the same material as that of the capping pattern CP. The third dummy layer D3 may be formed simultaneously with the capping pattern CP through one process and separated from the capping pattern CP by the undercut shape of the partition wall PW. In an embodiment of the present disclosure, the process of forming the capping pattern CP and the third dummy layer D3 may be omitted.

[0174] Thereafter, referring to Figure 7H , the operation of forming the first lower encapsulation inorganic pattern LIL1 may include an operation of depositing a first lower encapsulation inorganic layer LIL1-I. The first lower encapsulation inorganic layer LIL1-I may be formed through a deposition process. In an embodiment, the first lower encapsulation inorganic layer LIL1-I may be formed through a chemical vapor deposition (CVD) process. The first lower encapsulation inorganic layer LIL1-I may be formed to cover the first cathode CE1 (or the capping pattern CP) and the partition wall PW. A part of the first lower encapsulation inorganic layer LIL1-I may fill the first partition wall opening OP1-P.

[0175] Thereafter, the method of manufacturing a display panel according to the present disclosure may include an operation of forming a second photoresist layer PR2. In the operation of forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 may be formed in a pattern corresponding to the first light-emitting element ED1.

[0176] Reference Figure 7I , the operation of forming the first lower encapsulation inorganic pattern LIL1 may include an operation of removing a portion of the first lower encapsulation inorganic layer LIL1-I (see Figure 7H ) that does not overlap with the first light-emitting element ED1 in a plan view.

[0177] In the operation of removing the portion of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the first light-emitting element ED1 in a plan view, the first lower encapsulation inorganic layer LIL1-I may be dry-etched using the second photoresist layer PR2 as a mask. The portion of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the second photoresist layer PR2 in a plan view may be removed, and the first lower encapsulation inorganic pattern LIL1 may be formed in the remaining unetched portion of the first lower encapsulation inorganic layer LIL1-I.

[0178] Thereafter, the method of manufacturing a display panel according to the present disclosure may include an operation of removing the dummy layers D1, D2, and D3. The second dummy layer D2 and the third dummy layer D3 among the dummy layers D1, D2, and D3 may be removed by wet etching, and the first dummy layer D1 among the dummy layers D1, D2, and D3 may be removed using a stripper.

[0179] Thereafter, reference Figure 8A , in the method of manufacturing a display panel according to the present disclosure, after removing the second photoresist layer PR2 (see Figure 7I ), a second light-emitting element ED2, a capping pattern CP, and a second lower encapsulation inorganic pattern LIL2 may be formed. The processes of forming the second light-emitting element ED2, the capping pattern CP, and the second lower encapsulation inorganic pattern LIL2 may be substantially the same as the processes of forming the first light-emitting element ED1, the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 that have been described through Figures 7G to 7I .

[0180] Thereafter, reference Figure 8B , in the method of manufacturing a display panel according to the present disclosure, a third light-emitting element ED3, a capping pattern CP, and a third lower encapsulation inorganic pattern LIL3 may be formed. The processes of forming the third light-emitting element ED3, the capping pattern CP, and the third lower encapsulation inorganic pattern LIL3 may be substantially the same as the processes of forming the first light-emitting element ED1, the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 that have been described through Figures 7G to 7IThe processes of forming the first light-emitting element ED1, the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 are substantially the same.

[0181] Thereafter, referring to Figure 8C , the method of manufacturing a display panel according to the present disclosure may include an operation of drying the outer surfaces of the partition wall PW and the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. The operation of drying the outer surfaces of the partition wall PW and the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may be an operation of applying heat HT to the outer surfaces of the partition wall PW and the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 to evaporate the remaining moisture. As a result of the above process, there may be no moisture on the outer surfaces of the partition wall PW and the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0182] According to the present disclosure, an organic material (the first dummy layer D1 in Figure 7I ) that absorbs moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW is removed, and the remaining moisture can be removed through a drying process. Accordingly, the phenomenon of foreign substances being introduced through the moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW can be reduced or eliminated. As a result, pixel defects (such as dark spots or pixel shrinkage) of the display panel caused by foreign substances can be effectively reduced or eliminated.

[0183] Thereafter, referring to Figure 8D , the method of manufacturing a display panel according to the present disclosure may include an operation of forming a common inorganic film CLIL that covers the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0184] The common inorganic film CLIL may be formed to cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 after drying. The common inorganic film CLIL may cover the upper surface U_LIL (see Figure 5 ), the first side surface S1_LIL (see Figure 5 ), the lower surface B_LIL (see Figure 5 ), and the second side surface S2_LIL (see Figure 5 ) of each of the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3.

[0185] The common inorganic film CLIL can fill the space between the partition wall PW and the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. In the process of forming the common inorganic film CLIL, first internal region to third internal regions ES1, ES2, and ES3 can be formed as empty spaces. The first internal region ES1 can be formed between the first lower encapsulation inorganic pattern LIL1 and the partition wall PW and overlap with the first lower encapsulation inorganic pattern LIL1 and the partition wall PW in a plan view, the second internal region ES2 can be formed between the second lower encapsulation inorganic pattern LIL2 and the partition wall PW and overlap with the second lower encapsulation inorganic pattern LIL2 and the partition wall PW in a plan view, and the third internal region ES3 can be formed between the third lower encapsulation inorganic pattern LIL3 and the partition wall PW and overlap with the third lower encapsulation inorganic pattern LIL3 and the partition wall PW in a plan view. That is, the common inorganic film CLIL can cover the outer surfaces of the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, and can be formed while surrounding the first internal region to third internal regions ES1, ES2, and ES3.

[0186] In the related art, the encapsulation organic film OL is thickened so that the thin film encapsulation layer TFE has a low dielectric constant. However, in the present disclosure, internal regions ES are defined in the common inorganic film CLIL, and thus, the common inorganic film CLIL can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film OL of the present disclosure can be reduced, and the thickness of the encapsulation organic film OL can be reduced to improve touch sensitivity.

[0187] Thereafter, referring to Figure 8E , a method of manufacturing a display panel according to the present disclosure can include an operation of completing the display panel DP by forming the encapsulation organic film OL and the upper encapsulation inorganic film UIL. The encapsulation organic film OL can be formed by coating an organic material by an inkjet method, but the present disclosure is not limited thereto. The encapsulation organic film OL provides a flat upper surface. Thereafter, the upper encapsulation inorganic film UIL can be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE can be formed.

[0188] Figure 9 is a cross-sectional view taken along the line II-II’ of Figure 4 . Figure 9 The cross-sectional view of Figure 6 corresponds to the cross-sectional view of Figure 9 and illustrates an embodiment of the present disclosure. In the description of Figure 5 and Figure 6 , the same / similar reference numerals are used for the same / similar components described in

[0189] Reference Figure 9 , the display panel DPa may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFEa. The thin film encapsulation layer TFEa may include lower encapsulation inorganic patterns LIL1, LIL2, and LIL3, additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3, a common inorganic film CLILa, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0190] Compared with Figure 6 the thin film encapsulation layer TFE of Figure 9 , the thin film encapsulation layer TFEa may further include additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3. The additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3 may include a first additional encapsulation inorganic pattern ALIL1, a second additional encapsulation inorganic pattern ALIL2, and a third additional encapsulation inorganic pattern ALIL3.

[0191] The first additional encapsulation inorganic pattern ALIL1 may cover the dried first lower encapsulation inorganic pattern LIL1, the second additional encapsulation inorganic pattern ALIL2 may cover the dried second lower encapsulation inorganic pattern LIL2, and the third additional encapsulation inorganic pattern ALIL3 may cover the dried third lower encapsulation inorganic pattern LIL3. For example, the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3 may cover the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic pattern LIL1, LIL2, and LIL3, respectively, in a state where the outer surfaces of the first lower encapsulation inorganic pattern to the third lower encapsulation inorganic pattern LIL1, LIL2, and LIL3 are dried and there is no remaining moisture.

[0192] The first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3 may overlap with the first light-emitting opening to the third light-emitting opening OP1-E, OP2-E, and OP3-E, respectively, and the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3 may be provided in a pattern form in which the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3 are spaced apart from each other.

[0193] The common inorganic film CLILa may be disposed on the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3 to cover the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic pattern ALIL1, ALIL2, and ALIL3. The description of the common inorganic film CLILa may be substantially the same as the description of Figure 6 the common inorganic film CLIL ofFigure 9 The internal regions ES1, ES2, and ES3 are not shown (see Figure 6 ), but the internal regions ES1, ES2, and ES3 can be defined in the Figure 9 common inorganic film CLILa.

[0194] The process of manufacturing the Figure 9 display panel DPa can be partially different from the process of manufacturing the display panel DP already described in Figures 7A to 8E . The method of manufacturing the Figure 9 display panel DPa can further include the operation of forming additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3 covering the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. For example, between the operation of removing the dummy layers D1, D2, and D3 in Figure 7I and the process of forming the second light-emitting element ED2 in Figure 8A , the method can further include the operation of drying the outer surfaces of the partition wall PW and the first lower encapsulation inorganic pattern LIL1 and the operation of forming the first additional encapsulation inorganic pattern ALIL1 covering the first lower encapsulation inorganic pattern LIL1.

[0195] In addition, between the operation of forming the second light-emitting element ED2 and the second lower encapsulation inorganic pattern LIL2 in Figure 8A and the process of forming the third light-emitting element ED3 in Figure 8B , the method of manufacturing the Figure 9 display panel DPa can further include the operation of drying the outer surfaces of the partition wall PW and the second lower encapsulation inorganic pattern LIL2 and the operation of forming the second additional encapsulation inorganic pattern ALIL2 covering the second lower encapsulation inorganic pattern LIL2.

[0196] In addition, after the operation of forming the third light-emitting element ED3 and the third lower encapsulation inorganic pattern LIL3 in Figure 8B , the method of manufacturing the Figure 9 display panel DPa can further include the operation of drying the outer surfaces of the partition wall PW and the third lower encapsulation inorganic pattern LIL3 and the operation of forming the third additional encapsulation inorganic pattern ALIL3 covering the third lower encapsulation inorganic pattern LIL3.

[0197] In the method of manufacturing the Figure 9 display panel DPa, the operation of drying the partition wall PW and the outer surfaces of the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 can be omitted. In addition, the method of manufacturing the Figure 8C display panel DPa can include the operation of forming a common inorganic film CLILa covering the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3. Figure 9 display panel DPa can include the operation of forming a common inorganic film CLILa covering the first additional encapsulation inorganic pattern to the third additional encapsulation inorganic patterns ALIL1, ALIL2, and ALIL3.

[0198] According to the above description, the organic substance that absorbs and removes moisture between the lower encapsulation inorganic pattern and the partition wall can be removed, and the remaining moisture can be removed through a drying process. Therefore, the phenomenon of foreign matter being introduced through the moisture between the lower encapsulation inorganic pattern and the partition wall can be reduced or eliminated. As a result, pixel defects (such as dark spots or pixel shrinkage, etc.) of the display panel caused by foreign matter can be effectively reduced or eliminated.

[0199] In addition, in the related art, the encapsulation organic film is thickened so that the thin film encapsulation layer has a low dielectric constant. However, in the present disclosure, an internal region is defined in the common inorganic film, and thus the common inorganic film can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film in the present disclosure can be reduced, and the touch sensitivity can be improved by reducing the thickness of the encapsulation organic film.

[0200] Although the above has been described with reference to embodiments of the present disclosure, it can be understood that those skilled in the art or those with ordinary knowledge in the art can make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the claims.

Claims

1. A display panel, comprising: basal layer; a pixel defining film disposed on the base layer and defining a light emitting opening therein; a partition wall disposed on the pixel defining film and defining therein a partition wall opening overlapping the light emitting opening in a plan view; a plurality of light emitting elements, each including an anode, a light emitting pattern and a cathode, and arranged inside the light emitting opening and the partition wall opening, wherein the cathode contacts the partition wall; a plurality of lower packaging inorganic patterns, configured to cover the plurality of light emitting elements respectively; and A common inorganic film is configured to cover the plurality of lower encapsulation inorganic patterns and fill a space between the partition wall and the plurality of lower encapsulation inorganic patterns.

2. The display panel according to claim 1, wherein: The plurality of light emitting elements include a first light emitting element, a second light emitting element, and a third light emitting element configured to emit light of different colors, and The plurality of lower encapsulation inorganic patterns include a first lower encapsulation inorganic pattern configured to cover the first light emitting element, a second lower encapsulation inorganic pattern configured to cover the second light emitting element, and a third lower encapsulation inorganic pattern configured to cover the third light emitting element.

3. The display panel according to claim 2, wherein: The common inorganic film covers the first to third lower encapsulation inorganic patterns after drying.

4. The display panel according to claim 3, further comprising: a first additional encapsulation inorganic pattern configured to cover the dried first lower encapsulation inorganic pattern; a second additional encapsulation inorganic pattern configured to cover the dried second lower encapsulation inorganic pattern; as well as The third additional encapsulation inorganic pattern is configured to cover the dried third lower encapsulation inorganic pattern.

5. The display panel according to claim 4, wherein: The common inorganic film covers the first to third additional encapsulation inorganic patterns.

6. The display panel according to claim 1, wherein: An inner region is defined in the common inorganic film, and the inner region is an empty space.

7. The display panel according to claim 6, wherein: In the plan view, the inner region has a shape surrounding the light emitting opening.

8. The display panel according to claim 6, wherein: In the plan view, a portion of the inner region overlaps the plurality of lower package inorganic patterns.

9. The display panel according to claim 1, wherein: Each of the plurality of lower encapsulation inorganic patterns comprises: upper surface; a first side surface extending from the upper surface in a thickness direction of the base layer; a lower surface extending from the first side surface toward a center of the anode in a cross-sectional view; and A second side surface extends from the lower surface in the thickness direction of the base layer.

10. The display panel according to claim 9, wherein: The common inorganic film covers the upper surface, the first side surface, the lower surface, and the second side surface of each of the plurality of lower encapsulation inorganic patterns after drying.

11. The display panel according to claim 1, wherein: The common inorganic film includes an inorganic material.

12. The display panel according to claim 1, wherein: The common inorganic film includes at least one of silicon nitride and silicon oxynitride.

13. The display panel according to any one of claims 1 to 12, further comprising: an encapsulation organic film configured to cover the common inorganic film; as well as The upper encapsulation inorganic film is configured to cover the encapsulation organic film.

14. A method for manufacturing a display panel, the method comprising: Providing a preliminary display panel, the preliminary display panel comprising a base layer, a pixel defining film disposed on the base layer, and a preliminary partition wall disposed on the pixel defining film; forming a partition wall defining a partition wall opening therein from the preliminary partition wall; etching the pixel definition film to form a light emitting opening overlapping the partition wall opening in a plan view; forming a light emitting element and a lower package inorganic pattern configured to cover the light emitting element inside the light emitting opening and the partition wall opening; as well as The outer surfaces of the partition wall and the lower package inorganic pattern are dried.

15. The method according to claim 14, wherein: The forming of the light emitting element and the lower package inorganic pattern includes: forming a first light emitting element and a first lower encapsulation inorganic pattern configured to cover the first light emitting element; forming a second light emitting element and a second lower encapsulation inorganic pattern configured to cover the second light emitting element; and A third light emitting element and a third lower encapsulation inorganic pattern configured to cover the third light emitting element are formed.

16. The method according to claim 15, further comprising: A common inorganic film configured to cover the first to third lower encapsulation inorganic patterns is formed.

17. The method according to claim 15, further comprising: An additional encapsulation inorganic pattern configured to cover the lower encapsulation inorganic pattern is formed.

18. The method according to claim 17, wherein: The drying of the outer surfaces of the partition wall and the lower encapsulation inorganic pattern includes: drying the outer surface of the partition wall and the outer surface of the first lower encapsulation inorganic pattern after the forming of the first light emitting element and the first lower encapsulation inorganic pattern; drying the outer surface of the partition wall and the outer surface of the second lower encapsulation inorganic pattern after the forming of the second light emitting element and the second lower encapsulation inorganic pattern; and After the forming of the third light emitting element and the third lower encapsulation inorganic pattern, drying the outer surface of the partition wall and the outer surface of the third lower encapsulation inorganic pattern, and Wherein, the forming of the additional encapsulation inorganic pattern comprises: forming a first additional encapsulation inorganic pattern configured to cover the first lower encapsulation inorganic pattern; forming a second additional encapsulation inorganic pattern configured to cover the second lower encapsulation inorganic pattern; and A third additional encapsulation inorganic pattern configured to cover the third lower encapsulation inorganic pattern is formed.

19. The method according to claim 18, further comprising: A common inorganic film configured to cover the first to third additional encapsulation inorganic patterns is formed.

20. A display panel, comprising: basal layer; a pixel defining film disposed on the base layer and defining a light emitting opening therein; a partition wall disposed on the pixel defining film and defining therein a partition wall opening overlapping the light emitting opening in a plan view; a plurality of light emitting elements, each including an anode, a light emitting pattern, and a cathode, and arranged inside the light emitting opening and the partition wall opening, wherein the cathode is in contact with the partition wall; and A plurality of lower encapsulation inorganic patterns are configured to cover the plurality of light emitting elements respectively. Wherein, only inorganic material is disposed between the plurality of lower encapsulation inorganic patterns and the upper surface of the partition wall.

Images