Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.A display area of the display panel comprises a first reference voltage line and a second reference voltage line which are electrically connected, the first reference voltage line extends in the first direction, and the second reference voltage line extends in the second direction; the display area further comprises a first wire extending in the first direction. The display panel comprises a substrate, a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer. The first reference voltage line is located on the capacitor metal layer. The first wire is located on the second metal layer. The same second reference voltage line comprises a first sub-segment and a second sub-segment which are electrically connected, the first sub-segment is located on the second metal layer, and the orthographic projection of the second sub-segment on the substrate is partially overlapped with the orthographic projection of the first wire on the substrate; the second sub-segment is located between the second metal layer and the substrate. The display device comprises the display panel. According to the invention, the layout space of the pixels can be optimized, the pixel density is improved, and high-resolution display is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have been widely used due to their characteristics such as self-luminescence, low driving voltage, and fast response. In a display panel, a pixel circuit provides the driving current required for display to the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage, and thus becomes an indispensable element in most self-luminous display panels.

[0003] With the development of display technologies, users have higher and higher requirements for the image quality of display panels. High-end displays and gaming displays need to have characteristics such as high pixel density (Pixels Per Inch, the number of pixels contained on each inch of the screen) and high resolution (the higher the resolution, the higher the pixel density usually is). However, there are many devices in the existing pixel circuit and the layout space design is relatively complex, resulting in a relatively large layout area occupied by the pixel circuit. When the number of pixels per inch is higher, the layout space of the pixel circuit is more tense and the requirement for process accuracy is higher, which is not conducive to the realization of high pixel density and high resolution displays.

[0004] Therefore, providing a display panel and a display device that can optimize the layout space of pixels in a display device, improve pixel density, and is conducive to the realization of high resolution display is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem that the existing display device cannot further optimize the layout space of the pixel circuit and improve pixel density.

[0006] The present disclosure provides a display panel, including: a display area;

[0007] The display area includes a first reference voltage line and a second reference voltage line that are electrically connected. The first reference voltage line extends along a first direction, and the second reference voltage line extends along a second direction; wherein, the first direction and the second direction intersect in a direction parallel to the plane where the display panel is located;

[0008] The display area further includes a first wire that extends along the first direction;

[0009] The display panel includes a substrate and a first metal layer, a capacitive metal layer, a second metal layer, and a third metal layer located on one side of the substrate;

[0010] The first reference voltage line is located in the capacitor metal layer, and the first wire is located in the second metal layer;

[0011] The same second reference voltage line includes a first sub-segment and a second sub-segment that are electrically connected. The first sub-segment is located in the second metal layer, and the orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the first wire on the substrate;

[0012] The second sub-segment is located between the second metal layer and the substrate.

[0013] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above-mentioned display panel.

[0014] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0015] The present disclosure provides that the display area of the display panel includes a first reference voltage line extending in the first direction. The first reference voltage line is located in the capacitor metal layer, and further includes a second reference voltage line that is in a different layer from the first reference voltage line and is electrically connected. The second reference voltage line intersects with the first reference voltage line to form a grid structure. The display area further includes a first wire that extends in the first direction. The same second reference voltage line includes a first sub-segment and a second sub-segment that are electrically connected. The first sub-segment is located in the second metal layer, and the orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the first wire on the substrate. That is, the second sub-segment can be understood as a jumper structure where the second reference voltage line runs to the vicinity of the first wire. The second sub-segment is located between the second metal layer and the substrate, that is, the second sub-segment can be made of any metal layer on the side of the second metal layer facing the substrate. In the present disclosure, the jumper part of the second reference voltage line, that is, the second sub-segment, is made of any metal layer on the side of the second metal layer facing the substrate. Then, the via for electrically connecting one end of the second sub-segment to the first sub-segment of the second metal layer can be opened in any inorganic layer on the side of the second metal layer facing the substrate. After the second sub-segment crosses the first wire, the via for electrically connecting the other end of the second sub-segment to another first sub-segment of the second metal layer can also be opened in any inorganic layer on the side of the second metal layer facing the substrate. This avoids opening a large number of vias in the relatively thick organic layer during the manufacturing of the display panel, making the manufacturing process more efficient and convenient. And because the inorganic layer is generally thinner, the aperture of one via and the other via at both ends of the second sub-segment can be greatly reduced, which can optimize the layout space of each sub-pixel in the display panel, is beneficial to increasing the pixel density, and is beneficial to realizing high-resolution display. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 2 is Figure 1 A partial enlarged view of the J1 area in;

[0020] Figure 3 is Figure 1 A schematic cross-sectional structure view of a partial area in a sub-pixel;

[0021] Figure 4 It is a layout screenshot of a pixel circuit in a partial area of a sub-pixel of a display panel in the prior art;

[0022] Figure 5 is Figure 1 Another partial enlarged view of the J1 area in;

[0023] Figure 6 It is a schematic electrical connection structure view of a sub-pixel provided by an embodiment of the present disclosure;

[0024] Figure 7 It is another schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0025] Figure 8 is Figure 7 A partial enlarged view of the J2 area in;

[0026] Figure 9 is Figure 7 Another partial enlarged view of the J2 area in;

[0027] Figure 10 is Figure 7 Another partial enlarged view of the J2 area in;

[0028] Figure 11 is Figure 7 Another partial enlarged view of the J2 area in;

[0029] Figure 12 is Figure 7 Another partial enlarged view of the J2 area in;

[0030] Figure 13 It is a schematic plan view of a display device provided by an embodiment of the present disclosure. Detailed Implementation Modes

[0031] In order to more clearly understand the above-mentioned objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0032] Many specific details are set forth in the following description to facilitate a thorough understanding of the present disclosure, but the present disclosure may be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.

[0033] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic plan view of a display panel provided by an embodiment of the present disclosure, Figure 2 is Figure 1 a partial enlarged view of the J1 region in (for clearly showing the structure of this embodiment, transparency filling is performed in the figure). The display panel 000 provided by this embodiment includes: a display area AA;

[0034] The display area AA includes a first reference voltage line REF1 and a second reference voltage line REF2 that are electrically connected. The first reference voltage line REF1 extends along a first direction X, and the second reference voltage line REF2 extends along a second direction Y; wherein, the first direction X and the second direction Y intersect in a direction parallel to the plane where the display panel 000 is located;

[0035] The display area AA further includes a first wire L1, and the first wire L1 extends along the first direction X;

[0036] The display panel 000 includes a substrate 10 and a first metal layer 20, a capacitive metal layer 30, a second metal layer 40, and a third metal layer 50 located on one side of the substrate 10;

[0037] The first reference voltage line REF1 is located in the capacitive metal layer 30, and the first wire L1 is located in the second metal layer 40;

[0038] The same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 partially overlaps with the orthographic projection of the first wire L1 on the substrate 10;

[0039] The second sub-segment REF2B is located between the second metal layer 40 and the substrate 10.

[0040] Specifically, the display panel 000 provided in this embodiment may be an organic light-emitting diode display panel. The display panel 000 includes a display area AA. Optionally, at least part of the non-display area NA of the display panel 000 is disposed around the display area AA. The display area AA may include a plurality of sub-pixels 00. Figure 1 Among them, sub-pixels 00 of different colors are represented by different filling patterns; optionally, in this embodiment Figure 1 Taking the arrangement of a plurality of sub-pixels 00 in an array as an example for illustration, specifically in implementation, the arrangement manner of the plurality of sub-pixels 00 includes but is not limited to this. The sub-pixel 00 may include a light-emitting element 02 and a pixel circuit 01 electrically connected thereto ( Figure 1 The pixel circuit 01 is represented by a dashed box. Specifically in implementation, the electrical connection structure of the pixel circuit 01 may be set according to actual requirements). The pixel circuit 01 is used to provide a driving signal to drive the light-emitting element 02 to emit light. Optionally, the light-emitting element 02 of each sub-pixel 00 may be an organic light-emitting diode, or the light-emitting element may also be a micro light-emitting diode or a submillimeter light-emitting diode and other light-emitting devices, which are not limited in this embodiment. It can be understood that the type of the display panel 000 is not limited in this embodiment, and the structure of the display area AA may be set according to the type of the display panel 000. The design structure of the pixel circuit 01 included in the sub-pixel 00 of the specific display area AA may be understood by referring to the structure of the display panel in the related art. For example, the pixel circuit 01 may be an electrical connection structure including a plurality of thin film transistors and capacitors, which will not be elaborated herein.

[0041] When the pixel circuit 01 is disposed in the display panel 000, generally, multiple driving signal lines are required to provide driving signals for the pixel circuit. For example, a reference voltage line provides a reference voltage signal or a reset signal for the pixel circuit, a data line S provides a data voltage signal for the pixel circuit 01, and a scan line ( Figure 1 not shown in the figure) provides a scan control signal for the pixel circuit 01, and a power supply line ( Figure 1 not shown in the figure) provides a power supply voltage for the pixel circuit 01, and so on.

[0042] The display area AA of the display panel 000 in this embodiment includes a first reference voltage line REF1 and a second reference voltage line REF2 which are electrically connected. Among them, the first reference voltage line REF1 extends along a first direction X, and the second reference voltage line REF2 extends along a second direction Y. The first direction X and the second direction Y intersect in a direction parallel to the plane where the display panel 000 is located; it can be understood that in this embodiment, the first direction X is Figure 1 the horizontal direction in the figure, and the second direction Y is Figure 1Taking the longitudinal direction, the first direction X and the second direction Y being perpendicular to each other in a direction parallel to the plane of the display panel 000 as an example for illustration. The display panel 000 may include a plurality of first reference voltage lines REF1 arranged along the second direction Y, and a plurality of second reference voltage lines REF2 arranged along the first direction X to drive sub-pixels 00 in different rows or different columns.

[0043] It should be noted that in this embodiment, the first reference voltage line REF1 extends along the first direction X, and the second reference voltage line REF2 extends along the second direction Y, which means that the overall extension direction of the first reference voltage line REF1 is along the first direction X. It does not mean that the first reference voltage line REF1 is a straight line, and the second reference voltage line REF2 is a straight line. In actual production, the first reference voltage line REF1 and the second reference voltage line REF2 can be traces with bent or curved parts, as long as the overall extension direction of the first reference voltage line REF1 is the first direction X and the overall extension direction of the second reference voltage line REF2 is the second direction Y.

[0044] It can be understood that the pixel circuit 01 in this embodiment can be, for example, an electrical connection structure including 8 transistors and 1 capacitor. The electrically connected first reference voltage line REF1 and second reference voltage line REF2 can be a reset signal line electrically connected to the gate of the driving transistor of the pixel circuit 01, or the electrically connected first reference voltage line REF1 and second reference voltage line REF2 can be a reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00. The reset signal line electrically connected to the gate of the driving transistor of the pixel circuit 01 and the reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 can be the same or different. This embodiment does not limit this, and in specific implementation, it can be understood according to the structure of the pixel circuit, and this embodiment will not elaborate here.

[0045] The film layer structure of the display panel 000 includes a substrate 10 and a first metal layer 20, a capacitor metal layer 30, a second metal layer 40, and a third metal layer 50 on one side of the substrate 10. The film layer structure of the display panel 000 can be a combination of multiple conductive film layers and multiple inorganic layers, or a combination of multiple conductive film layers and multiple inorganic layers or organic layers. This embodiment does not limit this, and in specific implementation, the film layer structure of the display panel 000 can be set according to the actual design requirements of the panel. Optionally, as Figure 3 shown, Figure 3 is Figure 1 a schematic cross-sectional structure diagram of a partial area in the sub-pixel in Figure 3 (It can be understood that for the sake of clearly showing the film layer structure of the display panel, Figure 3As shown in the direction Z perpendicular to the plane where the substrate 10 is located, the film structure of the display panel 000 may include a substrate 10 and a semiconductor layer 60, a first metal layer 20, a capacitor metal layer 30, a second metal layer 40 and a third metal layer 50 located on one side of the substrate. The active portion of the thin film transistor 01T may be located in the semiconductor layer 60, the gate of the thin film transistor 01T in the pixel circuit may be located in the first metal layer 20, the capacitor plate in the pixel circuit may be located in the capacitor metal layer 30, the source and drain of the thin film transistor 01T may be located in the second metal layer 40, the power signal wiring, the data line S, etc. may be located in the third metal layer 50, and one of the source and drain of the thin film transistor 01T is electrically connected to the anode 021 of the light-emitting element 02 (organic light-emitting diode) through a connecting portion provided in the third metal layer 50. When the light-emitting element 02 is an organic light-emitting diode, the light-emitting principle is that electrons and holes migrate to the light-emitting layer through the electron and hole transport layers respectively, and meet in the light-emitting layer to form excitons and excite the light-emitting molecules.

[0046] It is understandable that this embodiment does not elaborate on the film structure and light-emitting principle of the sub-pixel 00 when the display panel 000 is an organic light-emitting diode display panel. For details, reference may be made to the film structure of the organic light-emitting diode display panel in the related art.

[0047] In this embodiment, a first reference voltage line REF1 extending along a first direction X is arranged in the capacitor metal layer 30, and a second reference voltage line REF2 extending along a second direction Y is arranged in a different layer from the first reference voltage line REF1, and the second reference voltage line REF2 intersects with and is electrically connected to the first reference voltage line REF1, so that the display panel 000 as a whole includes a plurality of first reference voltage lines REF1 and a plurality of second reference voltage lines REF2 that can form an electrically connected mesh structure (mesh, such as Figure 1 As shown in the figure), it is helpful to reduce the wiring impedance during the transmission of the overall reference voltage signal, improve the display uniformity, and ensure the display effect.

[0048] If the first reference voltage line extending along the first direction is located in the capacitor metal layer, the second reference voltage line which is in a different layer from the first reference voltage line and is electrically connected to the first reference voltage line is generally arranged in the second metal layer on the capacitor metal layer away from the substrate side. Since the second reference voltage line extends along the second direction, the display panel includes more driving lines, which must include other signal lines which also run through the second metal layer but extend along the first direction. At this time, when the second reference voltage line extending along the second direction and also located in the second metal layer is arranged near the signal line, cross-line processing is required.

[0049] like Figure 4 As shown, Figure 4It is a screenshot of the layout of the pixel circuit of the sub-pixel area of ​​the display panel in the prior art. Taking the circuit layout of the sub-pixel area in the design project of the relevant display panel as an example, the display panel of the design project includes a first reference voltage line REF1' extending along the first direction X' and located in the capacitor metal layer 30', and a second reference voltage line REF2' which is in a different layer and electrically connected to the first reference voltage line REF1' is arranged in the second metal layer 40' away from the substrate side of the capacitor metal layer 30'. Since the second reference voltage line REF2' extends along the second direction Y', and the display panel has more driving lines including the first wire L1', the first wire L1' extends along the first direction X' and the first wire L1' is located in the second metal layer 40'. At this time, when the second reference voltage line REF2' extending along the second direction Y' and also located in the second metal layer 40' is arranged near the first wire L1', the second reference voltage The line REF2' is provided with a cross-line segment REF20' which is in a different layer from the second metal layer 40' and avoids the first conductive line L1'. The cross-line segment REF20' is generally located in the third metal layer 50', that is, the same second reference voltage line REF2' extending along the second direction Y' includes a main body segment REF21' located in the second metal layer 40' and a cross-line segment REF20' located in the third metal layer 50'. The cross-line segment REF20' in different layers partially overlaps with the first conductive line L1'. One end of the cross-line segment REF20' is electrically connected to the main body segment REF21' through a via K11'. After the cross-line segment REF20' crosses over the first conductive line L1', the other end of the cross-line segment REF20' is electrically connected to another main body segment REF21' through another via K12'. Both the one via K11' and the other via K12' are vias from the second metal layer 40' to the third metal layer 50'.

[0050] In the film layer structure of a display panel, generally, the first metal layer 20' and the capacitive metal layer 30' are made of molybdenum (Mo), while the second metal layer 40' and the third metal layer 50' are generally made of titanium / aluminum / titanium (Ti / Al / Ti) metal. That is, the film thickness of the second metal layer 40' is relatively large. After patterning the second metal layer 40', in order to ensure the flatness of the subsequent third metal layer 50', an organic layer is generally provided between the second metal layer 40' and the third metal layer 50'. The organic layer can reduce the step difference of the third metal layer 50', achieving an effect similar to planarization. When the third metal layer 50' is used to make data lines, the relatively thick organic layer can reduce the signal crosstalk between the third metal layer 50' where the data lines are located and the first metal layer 20' where the scan lines are located, improving the display effect. Therefore, in the prior art, the cross-line method of the second reference voltage line REF2' as described above is generally adopted. That is, the same second reference voltage line REF2' extending along the second direction Y' includes a body segment REF21' located in the second metal layer 40' and a cross-segment REF20' located in the third metal layer 50'. The cross-segment REF20' of different layers has a partial overlapping area with the first wire L1'. One end of the cross-segment REF20' is electrically connected to the body segment REF21' through a via K11', and the other end of the cross-segment REF20' is electrically connected to another body segment REF21' through another via K12'. That is, after the second reference voltage line REF2' is cross-wired near the first wire L1', it returns to the second metal layer 40' to continue routing; Figure 4 One of the shown vias K11' and the other via K12' are both vias from the second metal layer 40' to the third metal layer 50'. At this time, in the circuit layout design of the display panel, two more vias need to be set when a second reference voltage line REF2 is cross-wired near the first wire. And one of the via K11' and the other via K12' are both vias from the second metal layer 40' to the third metal layer 50', and holes need to be drilled in the organic layer between the second metal layer 40' and the third metal layer 50'. The apertures of one of the via K11' and the other via K12' formed by drilling holes in the organic layer are both relatively large (compared with the aperture of the via set in the inorganic material insulating layer). Therefore Figure 4 the cross-line design of the second reference voltage line REF2' provided in the prior art greatly increases the space occupied by the vias, which is not conducive to the layout space design, increases the layout area occupied by the pixel circuit, and is not conducive to the realization of high pixel density and high resolution display.

[0051] It should be noted that Figure 4 it is only to illustrate that the vias used in the cross-line design of the second reference voltage line REF2' in the prior art need to occupy a relatively large layout space. Therefore, only the positions of the vias and the approximate space occupied by the vias are illustrated, and it does not represent the specific layout design of the pixel circuit.

[0052] It can be understood that in the film layer structure of the display panel, the aperture of the via formed in the organic layer is generally larger than that formed in the inorganic layer, which is restricted by the material property differences and process differences between the organic layer and the inorganic layer. For example, the material of the organic layer (such as polyimide PI) is usually softer, with lower mechanical strength and poor thermal stability, and is prone to deformation or decomposition at high temperatures. The organic material has poor tolerance to certain chemical reagents (such as etching solution). The opening process of the organic layer usually adopts dry etching (such as plasma etching) or wet etching. However, due to its poor softness and chemical stability, problems such as uneven edges or inaccurate aperture control are likely to occur during the etching process. Due to the characteristics of the organic material, a larger aperture is required during opening to ensure the feasibility and stability of the process.

[0053] To solve the above problems, in this embodiment, the display area AA of the display panel 000 is provided to include a first reference voltage line REF1 extending along the first direction X. The first reference voltage line REF1 is located in the capacitive metal layer 30. It further includes a second reference voltage line REF2 that is in a different layer from the first reference voltage line REF1 and is electrically connected thereto. It further includes a first wire L1 that extends along the first direction X. It can be understood that the first wire L1 in this embodiment can be understood as a wire that necessarily exists in the layout structure of the display panel 000, extends along the first direction X, and is provided in the second metal layer 40. For example, it can be a wire electrically connected to the data line S, and is used to directly provide the data voltage signal provided by the driving chip or flexible circuit board subsequently bonded in the non-display area NA to the data line S through the first wire L1 in the display area AA. For specific understanding, reference can be made to the description of subsequent embodiments.

[0054] In this embodiment, the same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40. The orthographic projection of the second sub-segment REF2B on the substrate 10 overlaps with the orthographic projection of the first wire L1 on the substrate 10. That is, the second sub-segment REF2B can be understood as a jumper structure where the second reference voltage line REF2 runs to the vicinity of the first wire L1. The second sub-segment REF2B is located between the second metal layer 40 and the substrate 10. That is, the second sub-segment REF2B can be made of any metal layer on the side of the second metal layer 40 facing the substrate 10. In the film layer structure of the display panel, generally, the first metal layer 20 and the capacitive metal layer 30 are made of molybdenum (Mo). The capacitive metal layer 30 is usually used to make the electrodes of the capacitor or the reference voltage line, and generally transmits constant voltage signals without considering signal crosstalk. Therefore, a relatively thin inorganic layer is generally provided between the capacitive metal layer 30 and the second metal layer 40 above it to achieve an insulating effect, and a relatively thin inorganic layer is generally provided between the capacitive metal layer 30 and the first metal layer 20 below it to achieve an insulating effect. Therefore, in this embodiment, the jumper part of the second reference voltage line REF2, that is, the second sub-segment REF2B, is made of any metal layer on the side of the second metal layer 40 facing the substrate 10. Then, a via (such as Figure 2 a via K11 shown) for electrically connecting one end of the second sub-segment REF2B to the first sub-segment REF2A of the second metal layer 40 can be opened in any inorganic layer on the side of the second metal layer 40 facing the substrate 10. After the second sub-segment REF2B crosses the first wire L1, a via (such as Figure 2 another via K12 shown) for electrically connecting the other end of the second sub-segment REF2B to another first sub-segment REF2A of the second metal layer 40 can be opened in any inorganic layer on the side of the second metal layer 40 facing the substrate 10. This avoids opening a large number of vias in the relatively thick organic layer during the manufacture of the display panel, making the manufacturing process more efficient and convenient. And because both this via K11 and another via K12 are vias opened in a certain inorganic layer below the second metal layer 40, and since the inorganic layer is generally relatively thin (such as the interlayer insulating layer), the aperture of this via K11 and another via K12 at both ends of the second sub-segment REF2B can be greatly reduced, which can optimize the layout space of each sub-pixel 00 in the display panel 000, is beneficial to increasing the pixel density, and is beneficial to realizing high-resolution display.

[0055] It should be noted that Figure 2 only schematically shows the electrical connection structure and electrical connection relationship of the first wire L1, the first reference voltage line REF1, and the second reference voltage line REF2, and does not represent the actual layout position and actual shape of each wire during the manufacture of the display panel 000. During specific implementation, it can be arranged according to the actual layout of the pixel circuit in the display panel.

[0056] It can be understood that in the film stack structure of the display panel, the aperture of the via holes formed in the inorganic layer is generally smaller than that of the via holes formed in the organic layer. The reason is that the materials of the inorganic layer (such as silicon nitride SiNx, silicon oxide SiO 2 ) are usually harder, have high mechanical strength, can withstand high-temperature processes, and have strong tolerance to chemical reagents. The via hole opening process for the inorganic layer usually adopts dry etching (such as reactive ion etching RIE), which can achieve high-precision via hole opening. The hardness and chemical stability of the inorganic material enable it to form smaller apertures with smoother edges. Therefore, in the film stack structure of the display panel, the aperture of the via holes formed in the inorganic layer is generally smaller than that of the via holes formed in the organic layer.

[0057] Such as Figure 1 , Figure 5 and Figure 6 shown, Figure 5 is Figure 1 Another partial enlarged schematic diagram of the J1 area in Figure 6 is a schematic diagram of an electrical connection structure of a sub-pixel provided by an embodiment of the present disclosure. The pixel circuit 01 of this embodiment can be, for example, an electrical connection structure including 8 transistors and 1 capacitor Cst. As Figure 6 shown, the 8 transistors can be a driving transistor DT and 7 other thin film transistors (the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7). The first reference voltage line REF1 and the second reference voltage line REF2 that are electrically connected to form a grid structure can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01. The reset signal line electrically connected to the anode of the light emitting element 02 of the sub-pixel 00 can be the third reference voltage line REF3 and the fourth reference voltage line REF4 that are electrically connected to form a grid structure. The electrical connection structure and working principle of this pixel circuit 01 and the light emitting element 02 in this embodiment will not be elaborated. During specific implementation, it can be understood according to the electrical connection structure of the sub-pixel in related technologies, and will not be elaborated here in this embodiment.

[0058] In the layout area where a sub-pixel 00 is located, the first reference voltage line REF1 and the second reference voltage line REF2 electrically connected to the pixel circuit 01 can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01. The reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 is separately provided and is a grid structure formed by the electrically connected third reference voltage line REF3 and fourth reference voltage line REF4 (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2). Compared with Figure 4 the solutions of the prior art in terms of the occupied layout space, the via occupancy space area comparison table shown in Table 1 below is obtained;

[0059] Table 1:

[0060]

[0061] As Figure 4 shown, the applicant routes the cross-segment REF20' of the second reference voltage line REF2' in the prior art on the third metal layer 50', and the cross-segment of the fourth reference voltage line REF4' also routes on the third metal layer 50'. Taking the reset signal line electrically connected to the anode of the light-emitting element of the sub-pixel as an example, which is separately provided and is a grid structure formed by the electrically connected third reference voltage line REF3' and fourth reference voltage line REF4' (the setting method of the third reference voltage line REF3' is the same as that of the first reference voltage line REF1', and the setting method of the fourth reference voltage line REF4' is the same as that of the second reference voltage line REF2'), then in the layout area of a sub-pixel in the prior art, if the cross-segment REF20' of the second reference voltage line REF2' and the cross-segment REF40' of the fourth reference voltage line REF4' are to be set, at least four vias opened in the organic layer need to be added (which are respectively the four vias K11', K12', K13', K14' opened in the organic layer in Figure 4 . The total area on the plane increased is approximately 4×5.5×5.5 = 121 μm 2 , where 5.5×5.5 represents the approximate area of a via, and the vias K11', K12', K13', K14' are basically the same size. It should be noted that in this embodiment, the shape of the orthographic projection of the via on the plane of the substrate is approximately regarded as a square for facilitating the calculation of the layout area occupied by the via.

[0062] And adopting this embodiment Figure 5After the solution, taking the grid structure formed by the third reference voltage line REF3 and the fourth reference voltage line REF4 that are separately provided and electrically connected as an example for the reset signal line electrically connected to the anode 021 of the light-emitting element 02 of the sub-pixel 00 (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2), assuming that the second sub-segment REF2B of the second reference voltage line REF2 runs through any metal layer under the second metal layer 40 (such as the first metal layer 20), and the second sub-segment REF4B of the fourth reference voltage line REF4 also runs through any metal layer under the second metal layer 40 (such as the first metal layer 20), then if the second sub-segment REF2B of the second reference voltage line REF2 and the second sub-segment REF4B of the fourth reference voltage line REF4 are to be set in the layout area where a sub-pixel 00 is located in this embodiment, at least four vias opened in the inorganic layer are required (respectively the four vias K11, K12, K13, K14 opened in the inorganic layer in Figure 5 ), and the total area increased on the plane is approximately 4×4.64×4.64 = 86.11μm 2 , where 4.64×4.64 represents the approximate area of one via, and the vias K11, K12, K13, K14 are basically the same size; after adopting the solution of this embodiment, the space occupied by the layout of a sub-pixel 00 can be saved by about 28.82%. It should be noted that in this embodiment, the orthographic projection shape of the via on the plane where the substrate is located is approximately regarded as a square for facilitating the calculation of the layout area occupied by the via.

[0063] It should be noted that only the structure of the display panel 000 is exemplarily drawn in the figure of this embodiment. In actual implementation, the structure of the display panel includes but is not limited to this. The structure of the sub-pixel in the figure of this embodiment is also only an example. In actual implementation, the structure, shape, quantity, area, etc. of the sub-pixel are only examples and can be designed according to actual requirements in actual implementation.

[0064] In some alternative embodiments, please refer to Figure 7 and Figure 8 , Figure 7 is another schematic plan view of the display panel provided by the embodiment of the present disclosure, Figure 8 is Figure 7 a partial enlarged view of the J2 area in

[0065] The display area AA includes a plurality of first data lines S1 extending along the second direction Y. The first data lines S1 are electrically connected to the fan-out traces F1 through at least one first connection line LF, and the first connection line LF is located in the display area AA.

[0066] The first connection line LF includes at least a first conductor L1. One end of the first conductor L1 is electrically connected to the first data line S1, and the first data line S1 is located in the third metal layer 50.

[0067] Optionally, the same first connection line LF includes an electrically connected second conductor L2 and first conductor L1. The extending direction of the second conductor L2 is the same as that of the first data line S1, and the second conductor L2 is located in the third metal layer 50.

[0068] This embodiment explains that the display panel 000 includes a display area AA and a non-display area NA at least partially surrounding the display area AA. The display area AA includes a plurality of first data lines S1 extending along the second direction Y. Optionally, along the first direction X, the first data lines S1 are closer to the edge of the display panel 000 than other data lines S. Optionally, the non-display area NA may include a fan-out area FNA and a bonding area BNA. A plurality of fan-out traces F1 may be provided in the fan-out area FNA, and a plurality of conductive pads may be provided in the bonding area BNA. The fan-out traces F1 are used to electrically connect the first data lines S1 in the display area AA to the conductive pads in the bonding area BNA. The conductive pads are used for subsequent bonding electrical connection with a driving chip or a flexible circuit board, so as to provide a driving signal for display for the display panel 000 through the driving chip or the flexible circuit board.

[0069] Currently, with the development of display technology, consumers' pursuit of high screen-to-body ratio for display products, especially for small and medium-sized display products, is increasing. In order to reduce the non-display area and increase the display area, it is usually designed that each fan-out trace converges towards the bonding area to form a fan-out area (i.e., Fan-out area). A large number of fan-out traces are provided in the fan-out area, which are used to output the display driving signal in the driving chip to the data lines in the display area through the fan-out traces. Therefore, the fan-out area usually occupies a large area, resulting in a large width of the fan-out area, making it impossible to further compress the border of the display panel and difficult to achieve a narrower border design. And for high-resolution and high-definition display products, the number of data signal channels is more, so that even with the most advanced process in the prior art, there is not enough space to design according to the traditional design method of connecting the fan-out traces in the fan-out area to the data lines in the display area one by one. It is necessary to find a new design solution to meet the customer's demand for a narrower border specification of the product.

[0070] In this embodiment, the fan-out area FNA of the non-display area NA is provided with a plurality of fan-out traces F1. The first data line S1 located on the third metal layer 50 is electrically connected to the fan-out trace F1 through at least one first connection line LF. The first connection line LF is located in the display area AA. Two ends of the first connection line LF are respectively connected to the fan-out trace F1 in the non-display area NA and the first data line S1 in the display area AA. Optionally, along the first direction X in the display panel 000, the display area AA includes a second display area AA2 and first display areas AA1 located on opposite sides of the second display area AA2. The first display area AA1 can be understood as the display area closer to the two side edges of the display panel 000 in the first direction X, and the second display area AA2 can be understood as the area in the display area AA closer to the central position. A plurality of first data lines S1 extending along the second direction Y in the display panel 000 are provided in the first display area AA1. The first data line S1 is electrically connected to the fan-out trace F1 in the non-display area NA through the first connection line LF located in the display area AA. The fan-out trace F1 is electrically connected to the conductive pad in the bonding area BNA, realizing signal transmission between the first data line S1 and the conductive pad. Optionally, the second display area AA2 of the display panel 000 may include a plurality of second data lines S2. One end of the second data line S2 can be directly electrically connected to other fan-out traces in the non-display area NA within the corresponding area range of the second display area AA2.

[0071] In this embodiment, the first connection line LF is arranged in the display area AA. That is, when the first data line S1 in the first display area AA1, which is closer to the two side edges of the display panel 000 in the first direction X in this embodiment, is electrically connected to the welding pad in the bonding area BNA, the electrical connection is realized through the first connection line LF located in the display area AA, which can avoid the first connection line LF occupying the space of the non-display area NA. As Figure 7 shown, the first connection line LF at least includes a first conductor L1. One end of the first conductor L1 located on the second metal layer 40 is electrically connected to the first data line S1 located on the third metal layer 50. A partial segment of the first connection line LF (such as Figure 7 the first conductor L1 shown in the figure) can gradually extend in the display area AA in the direction closer to the second display area AA2, and then extend to the boundary position between the display area AA and the non-display area NA, so that the connection position of the first connection line 10 and the fan-out trace F1 can be as far as possible from the first display area AA1 in the first direction X. Compared with the prior art solutions, the structure of arranging the first connection line LF in the display area AA in this embodiment is beneficial to reducing the width occupied by the plurality of fan-out traces F1 in the first direction X, and further can reduce the lower border of the display panel 000.

[0072] In this embodiment, the same first connecting line LF includes an electrically connected second conductive line L2 and a first conductive line L1. The optional second conductive line L2 and the first conductive line L1 may include a plurality of numbers that are alternately connected end to end, thereby gradually forming a stepped first connecting line LF. The extension direction of the second conductive line L2 is the same as the extension direction of the first data line S1. The second conductive line L2 may be located in the same layer as the first data line S1, that is, located in the third metal layer 50. The stepped first connecting line LF may gradually extend in the direction approaching the second display area AA2 within the display area AA, and then extend to the boundary position between the display area AA and the non-display area NA, so that the connection point between the first connecting line 10 and the fan-out wiring F1 can be as far away from the first display area AA1 as possible in the first direction X.

[0073] It can be understood that the design structure in which the first connecting line LF of the present embodiment is located in the display area AA can meet the high resolution requirement of the display panel 000. Even if the number of data lines included in the display area AA is greater, the first connecting line LF is routed through the display area AA, which can also reduce the space of the non-display area NA in the first direction X occupied by the fan-out line F1 connected to the first connecting line LF. Therefore, the width of the non-display area NA in the first direction X can still be further compressed, which can meet the high resolution requirement while ensuring the display function and achieving a narrower border.

[0074] Optionally, the first wire L1 of the first connection line LF located in the display area AA of this embodiment is set in the second metal layer 40, and the second wire L2 is set in the third metal layer 50. The first connection line LF is made of the conductive film layer included in the display panel 000 itself, which is conducive to saving production costs and achieving a thin design effect of the panel. In addition, in this embodiment, the first wire L1 of the first connection line LF located in the display area AA is set in the second metal layer 40, and the second wire L2 is set in the third metal layer 50. Compared with setting the first connection line LF in other metal layers such as the first metal layer 20 and the capacitor metal layer 30, the impedance is relatively small, which is conducive to improving the transmission effect of the data voltage signal on the first connection line LF.

[0075] Optional, please continue to refer to Figures 1 - 3 , Figures 5 - 8 In the film structure of the display panel 000 of this embodiment, a first inorganic layer 001 is included between the first metal layer 20 and the capacitor metal layer 30, a second inorganic layer 002 is included between the capacitor metal layer 30 and the second metal layer 40, and a first organic layer 003 is included between the second metal layer 40 and the third metal layer 50.

[0076] In this embodiment, it is explained that in the film layer structure of the display panel 000, the first metal layer 20 and the capacitive metal layer 30 are generally made of molybdenum (Mo), while the second metal layer 40 and the third metal layer 50 are generally made of titanium / aluminum / titanium (Ti / Al / Ti) metal. That is, the film thickness of the second metal layer 40' is relatively large. After patterning the second metal layer 40, in order to ensure the flatness of the subsequent third metal layer 50, generally, a first organic layer 003 is provided between the second metal layer 40 and the third metal layer 50. The first organic layer 003 is made of an organic material, which can reduce the step difference of the third metal layer 50 and achieve the effect of flattening the relatively thick second metal layer 40 after patterning. When the third metal layer 50 is used to make the data line S, the relatively thick first organic layer 003 can reduce the signal crosstalk between the third metal layer 50 where the data line S is located and the first metal layer 20 where the scan line is located, thereby improving the display effect.

[0077] A first inorganic layer 001 is included between the first metal layer 20 and the capacitive metal layer 30, and a second inorganic layer 002 is included between the capacitive metal layer 30 and the second metal layer 40. The first inorganic layer 001 and the second inorganic layer 002 can be understood as interlayer insulating layers. The same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the second sub-segment REF2B is a jumper structure where the second reference voltage line REF2 runs near the first wire L1. The second sub-segment REF2B is arranged between the second metal layer 40 and the substrate 10, that is, the second sub-segment REF2B can be made of any metal layer on the side of the second metal layer 40 facing the substrate 10. The via hole for the electrical connection between the second sub-segment REF2B and the first sub-segment REF2A can be opened in the first inorganic layer 001 or the second inorganic layer 002, without being opened in the relatively thick first organic layer 003, which can reduce the via hole diameter for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A. Since the first inorganic layer 001 and the second inorganic layer 002 are used as interlayer insulating layers, their materials such as silicon nitride SiNx and silicon oxide SiO 2 Are usually relatively hard, have high mechanical strength, can withstand high-temperature processes, and have strong tolerance to chemical reagents. The process for opening via holes usually uses dry etching, which can achieve high-precision hole opening. Therefore, the hardness and chemical stability of inorganic materials enable them to open smaller hole diameters with smoother edges. Therefore, in the film layer structure of the display panel, the via hole diameter W1 opened in the first inorganic layer 001 and the second inorganic layer 002 is generally smaller than the via hole diameter W2 opened in the first organic layer 003 (as Figure 3 Shown, it can be understood that Figure 3Only for example, the aperture W1 of the vias formed in the first inorganic layer 001 and the second inorganic layer 002 is generally smaller than the aperture W2 of the vias formed in the first organic layer 003. The apertures W1 and W2 do not represent the vias for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A in the above embodiments), which is beneficial to reducing the aperture of the vias for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A, optimizing the layout space of the sub-pixels, being beneficial to increasing the pixel density, and improving the display quality.

[0078] In some alternative embodiments, please refer to Figure 7 and Figure 9 , Figure 9 is Figure 7 Another partial enlarged schematic diagram of the J2 region in (for clearly showing the structure of this embodiment, transparency filling is performed in the figure). In this embodiment, the same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 partially overlaps with the orthographic projection of the first wire L1 on the substrate 10;

[0079] The second sub-segment REF2B is located in the capacitive metal layer 30 between the second metal layer 40 and the substrate 10.

[0080] When the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located in the capacitive metal layer 30, the first reference voltage line REF1 is electrically connected to a first sub-segment REF2A through a first via K1; the first end of the second sub-segment REF2B is electrically connected to this first sub-segment REF2A through a fifth via K5; the second end of the second sub-segment REF2B is electrically connected to another first sub-segment REF2A through a sixth via K6.

[0081] This embodiment explains that when the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located between the second metal layer 40 and the substrate 10, the second sub-segment REF2B can be located in the capacitive metal layer 30, that is, the second sub-segment REF2B is on the same layer as the first reference voltage line REF1. At this time, the first reference voltage line REF1 in the capacitive metal layer 30 and the second reference voltage line REF2 intersect to form a grid structure. The first reference voltage line REF1 in the capacitive metal layer 30 and the first sub-segment REF2A in the second metal layer 40 are electrically connected through a first via K1. The first via K1 is formed in the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and the aperture is small.

[0082] The first sub-segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first sub-segment REF2A runs near the first wire L1 which is also in the second metal layer 40, it changes to the second sub-segment REF2B in the capacitive metal layer 30. The first end of the first sub-segment REF2A in the second metal layer 40 and the second sub-segment REF2B in the capacitive metal layer 30 are electrically connected through the fifth via K5. The fifth via K5 is formed in the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and has a relatively small aperture.

[0083] The orthographic projection of the second sub-segment REF2B of the capacitive metal layer 30 on the plane where the substrate 10 is located overlaps with the orthographic projection of the first wire L1 of the second metal layer 40 on the plane where the substrate 10 is located. The second sub-segment REF2B of the capacitive metal layer 30 crosses over the first wire L1 of the second metal layer 40, and then changes to another first sub-segment REF2A of the second metal layer 40. At this time, after the second sub-segment REF2B of the capacitive metal layer 30 crosses over the first wire L1 of the second metal layer 40, it is electrically connected to another first sub-segment REF2A of the second metal layer 40 through the sixth via K6. The sixth via K6 is also formed in the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and has a relatively small aperture.

[0084] In this embodiment, when the same second reference voltage line REF2 includes the electrically connected first sub-segment REF2A and second sub-segment REF2B, setting the first sub-segment REF2A in the second metal layer 40 and the second sub-segment REF2B in the capacitive metal layer 30 is beneficial to reducing the aperture of the fifth via K5 and the sixth via K6 for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A, optimizing the layout space of the sub-pixel, being beneficial to increasing the pixel density, and improving the display quality.

[0085] In some alternative embodiments, please refer to Figure 7 and Figure 10 , Figure 10 which Figure 7 is another partial enlarged schematic diagram of the J2 region in

[0086] (for clearly showing the structure of this embodiment, transparency filling is performed in the figure). In this embodiment, the same second reference voltage line REF2 includes the electrically connected first sub-segment REF2A and second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 partially overlaps with the orthographic projection of the first wire L1 on the substrate 10;

[0087] When the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located in the capacitor metal layer 30, the first reference voltage line REF1 is electrically connected to one first sub-segment REF2A through the first via K1; the first end of the second sub-segment REF2B is also electrically connected to the first sub-segment REF2A through the first via K1; the second end of the second sub-segment REF2B is electrically connected to another first sub-segment REF2A through the second via K2.

[0088] Optionally, the second sub-segment REF2B and the first reference voltage line REF1 are of an integral structure.

[0089] At this time, the first via K1 penetrates through the second inorganic layer 002, and the second via K2 penetrates through the second inorganic layer 002.

[0090] This embodiment explains that when the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located between the second metal layer 40 and the substrate 10, the second sub-segment REF2B can be located in the capacitor metal layer 30, that is, the second sub-segment REF2B and the first reference voltage line REF1 are on the same layer. At this time, the first reference voltage line REF1 in the capacitor metal layer 30 intersects with the second reference voltage line REF2 to form a grid structure. The first reference voltage line REF1 in the capacitor metal layer 30 is electrically connected to the first sub-segment REF2A of the second metal layer 40 through the first via K1. The first via K1 is opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is small.

[0091] Moreover, the first end of the second sub-segment REF2B can also reuse the first via K1 to achieve electrical connection with the first sub-segment REF2A of this strip, that is, both the second sub-segment REF2B located in the capacitor metal layer 30 and the first reference voltage line REF1 can be an integral structure. The first sub-segment REF2A located in the second metal layer 40 is at the intersection of the first reference voltage line REF1 and the second reference voltage line REF2, and reuses the first via K1 to achieve electrical connection between the first sub-segment REF2A of the second metal layer 40 and the second sub-segment REF2B of the capacitor metal layer 30. The first sub-segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first sub-segment REF2A runs to the first reference voltage line REF1, it is electrically connected to the first reference voltage line REF1 through the first via K1, thereby forming a grid structure where the first reference voltage line REF1 and the second reference voltage line REF2 intersect. Since the second sub-segment REF2B of the capacitor metal layer 30 and the first reference voltage line REF1 are an integral structure, the second sub-segment REF2B located in the capacitor metal layer 30 continues to run on one side of the first reference voltage line REF1 facing the first wire L1. The orthographic projection of the second sub-segment REF2B of the capacitor metal layer 30 on the plane where the substrate 10 is located intersects with the orthographic projection of the first wire L1 of the second metal layer 40 on the plane where the substrate 10 is located. After the second sub-segment REF2B crosses the first wire L1 of the second metal layer 40, it changes to another first sub-segment REF2A of the second metal layer 40. At this time, after the second sub-segment REF2B of the capacitor metal layer 30 crosses the first wire L1 of the second metal layer 40, it is electrically connected to another first sub-segment REF2A of the second metal layer 40 through the second via K2. The second via K2 is also opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is relatively small.

[0092] Since in this embodiment, when the first reference voltage line REF1 extending in the first direction X and the second reference voltage line REF2 extending in the second direction Y are electrically connected, it is necessary to open the first via K1 to achieve electrical connection between the first reference voltage line REF1 of the capacitor metal layer 30 and the first sub-segment REF2A of the second metal layer 40. Therefore, when the second sub-segment REF2B and the first reference voltage line REF1 are both in the capacitor metal layer 30 and are an integral structure, the first end of the second sub-segment REF2B can reuse the first via K1 when electrically connected to the first sub-segment REF2A.

[0093] In this embodiment, when the same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B, the first sub-segment REF2A is arranged on the second metal layer 40, the second sub-segment REF2B is arranged on the capacitive metal layer 30, and the second sub-segment REF2B on the capacitive metal layer 30 and the first reference voltage line REF1 are of an integral structure, and the first via hole K1 existing in the panel itself is reused, which is beneficial to reducing the number of via holes in the sub-pixel layout space. At the same time, the aperture of the second via hole K2 for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A is also reduced, which can more effectively optimize the layout space of the sub-pixel, further improve the pixel density, and enhance the display quality.

[0094] As Figure 4 , Figure 7 , Figure 10 and Figure 11 shown, Figure 11 is Figure 7 Another partial enlarged schematic diagram of the J2 area in Figure 4 (for clearly showing the structure of this embodiment, transparency filling is performed in the figure). The applicant takes the layout area where a sub-pixel 00 is located as an example. The first reference voltage line REF1 and the second reference voltage line REF2 electrically connected to the pixel circuit 01 can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01, and the reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 is separately arranged and is a mesh structure formed by the third reference voltage line REF3 and the fourth reference voltage line REF4 that are electrically connected (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2). Comparing with

[0095] Table II:

[0096]

[0097] As Figure 4As shown, the applicant takes the example that the cross-segment REF20' of the second reference voltage line REF2' in the prior art runs on the third metal layer 50', and the cross-segment of the fourth reference voltage line REF4' also runs on the third metal layer 50'. The reset signal line electrically connected to the anode of the light-emitting element of the sub-pixel is separately provided, and the grid structure formed by the electrically connected third reference voltage line REF3' and fourth reference voltage line REF4' is taken as an example (the setting manner of the third reference voltage line REF3' is the same as that of the first reference voltage line REF1', and the setting manner of the fourth reference voltage line REF4' is the same as that of the second reference voltage line REF2'). Then, if the cross-segment REF20' of the second reference voltage line REF2' and the cross-segment REF40' of the fourth reference voltage line REF4' are to be set in the layout area where a sub-pixel in the prior art is located, at least four vias opened in the organic layer need to be added (which are the four vias K11', K12', K13', K14' opened in the organic layer in Figure 4 ), and the total area on the plane increased is approximately 4×5.5×5.5 = 121 μm 2 , where 5.5×5.5 represents the approximate area of one via, and the vias K11', K12', K13', K14' are basically the same size.

[0098] Adopting this embodiment Figure 11After the solution, taking the grid structure formed by the third reference voltage line REF3 and the fourth reference voltage line REF4 which are separately provided and electrically connected to the anode 021 of the light-emitting element 02 of the sub-pixel 00 as an example (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2), assuming that the second sub-segment REF2B of the second reference voltage line REF2 runs through the capacitive metal layer 30 under the second metal layer 40, and the second sub-segment REF4B of the fourth reference voltage line REF4 also runs through the capacitive metal layer 30 under the second metal layer 40, and the second sub-segment REF2B of the second reference voltage line REF2 and the first reference voltage line REF1 are of an integral structure on the capacitive metal layer 30. When the first end of the second sub-segment REF2B of the second reference voltage line REF2 is electrically connected to the first sub-segment REF2A, the first sub-via K1-1 required for the first reference voltage line REF1 and the second reference voltage line REF2 existing in the panel itself to form a grid structure is multiplexed. When the first end of the second sub-segment REF4B of the fourth reference voltage line REF4 is electrically connected to the first sub-segment REF4A, the second sub-via K1-2 required for the third reference voltage line REF3 and the fourth reference voltage line REF4 existing in the panel itself to form a grid structure is multiplexed. Then, if the second sub-segment REF2B of the second reference voltage line REF2 and the second sub-segment REF4B of the fourth reference voltage line REF4 are to be set in the layout area where a sub-pixel 00 is located in this embodiment, only two vias opened in the inorganic layer need to be added (the third sub-via K2-1 and the fourth sub-via K2-2 opened in the second inorganic layer 002 in Figure 11 ), and the total area on the added plane is approximately 2×4.34×4.34 = 37.67μm 2 , where 4.34×4.34 represents the approximate area of one via, and the third sub-via K2-1 and the fourth sub-via K2-2 are substantially the same in size; after adopting the solution of this embodiment, not only the number of vias in the layout space of a sub-pixel 00 can be reduced, but also the space occupied by the layout can be saved by about 68.87%, which is more conducive to improving the pixel density and enhancing the display quality.

[0099] In some alternative embodiments, please refer to Figure 7 and Figure 12 . Figure 12 is Figure 7Another partial enlarged schematic diagram of the J2 region in China (for clearly showing the structure of this embodiment, transparency filling is performed in the figure). In this embodiment, the same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 partially overlaps with the orthographic projection of the first wire L1 on the substrate 10;

[0100] The second sub-segment REF2B is located in the first metal layer 20 between the second metal layer 40 and the substrate 10.

[0101] When the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located in the first metal layer 20, the first reference voltage line REF1 is electrically connected to a first sub-segment REF2A through a first via K1;

[0102] The first end of the second sub-segment REF2B is electrically connected to a first sub-segment REF2A through a third via K3;

[0103] The second end of the second sub-segment REF2B is electrically connected to another first sub-segment REF2A through a fourth via K4.

[0104] At this time, the first via K1 penetrates through the second inorganic layer 002; the third via K3 penetrates through the second inorganic layer 002 and the first inorganic layer 001, and the fourth via K4 penetrates through the second inorganic layer 002 and the first inorganic layer 001.

[0105] This embodiment explains that when the first sub-segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second sub-segment REF2B is located between the second metal layer 40 and the substrate 10, the second sub-segment REF2B can be located in the first metal layer 20. At this time, the first reference voltage line REF1 of the capacitive metal layer 30 intersects with the second reference voltage line REF2 to form a grid structure. The first reference voltage line REF1 of the capacitive metal layer 30 is electrically connected to the first sub-segment REF2A of the second metal layer 40 through the first via K1. The first via K1 is opened in the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and the aperture is small.

[0106] The first sub-segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first sub-segment REF2A runs near the first wire L1 which is also in the second metal layer 40, it changes to the second sub-segment REF2B in the first metal layer 20. The first end of the first sub-segment REF2A in the second metal layer 40 and the second sub-segment REF2B in the first metal layer 20 are electrically connected through the third via K3. The third via K3 penetrates the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and the first inorganic layer 001 between the capacitive metal layer 30 and the first metal layer 20, and has a smaller aperture.

[0107] The orthographic projection of the second sub-segment REF2B of the first metal layer 20 on the plane where the substrate 10 is located overlaps with the orthographic projection of the first wire L1 of the second metal layer 40 on the plane where the substrate 10 is located. The second sub-segment REF2B of the first metal layer 20 crosses over the first wire L1 of the second metal layer 40, and then changes to another first sub-segment REF2A of the second metal layer 40. At this time, after the second sub-segment REF2B of the first metal layer 20 crosses over the first wire L1 of the second metal layer 40, it is electrically connected to another first sub-segment REF2A of the second metal layer 40 through the fourth via K4. The fourth via K4 also penetrates the second inorganic layer 002 between the capacitive metal layer 30 and the second metal layer 40, and the first inorganic layer 001 between the capacitive metal layer 30 and the first metal layer 20, and has a smaller aperture.

[0108] In this embodiment, when the same second reference voltage line REF2 includes the electrically connected first sub-segment REF2A and second sub-segment REF2B, the first sub-segment REF2A is located in the second metal layer 40 and the second sub-segment REF2B is located in the first metal layer 20. Even though the third via K3 needs to penetrate the second inorganic layer 002 and the first inorganic layer 001, and the fourth via K4 needs to penetrate the second inorganic layer 002 and the first inorganic layer 001, compared with opening the third via K3 and the fourth via K4 in the first organic layer 003, it is still possible to reduce the aperture of the third via K3 and the fourth via K4 for electrically connecting the second sub-segment REF2B and the first sub-segment REF2A, optimize the layout space of the sub-pixels, and is beneficial to improving the pixel density and enhancing the display quality.

[0109] In some alternative embodiments, please refer to Figure 13 , Figure 13 is a schematic plan view of a display device provided by an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 13The embodiments are described by taking a mobile phone as an example only for the display device 111. It can be understood that the display device 111 provided by the embodiments of the present invention can be other display devices 111 with a display function, such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations thereto. The display device 111 provided by the embodiments of the present invention has the beneficial effects of the display panel 000 provided by the embodiments of the present invention. For the specific description of the display panel 000, reference can be made to the above embodiments, and details are not described herein again.

[0110] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0111] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: Display area; The display area includes a first reference voltage line and a second reference voltage line that are electrically connected, the first reference voltage line extends along a first direction, and the second reference voltage line extends along a second direction; wherein the first direction and the second direction intersect in a direction parallel to a plane where the display panel is located; The display area further includes a first conductive line extending along the first direction; The display panel comprises a substrate and a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer located on one side of the substrate; The first reference voltage line is located in the capacitor metal layer, and the first conductive line is located in the second metal layer; The same second reference voltage line comprises a first sub-segment and a second sub-segment which are electrically connected, the first sub-segment is located in the second metal layer, and the orthographic projection of the second sub-segment on the substrate partially overlaps with the orthographic projection of the first wire on the substrate; The second sub-segment is located between the second metal layer and the substrate.

2. The display panel according to claim 1, characterized in that: The display panel includes a non-display area, and the non-display area includes a plurality of fan-out wirings; The display area includes a plurality of first data lines extending along the second direction, the first data lines are electrically connected to the fan-out wiring through at least one first connection line, and the first connection line is located in the display area; The first connecting line at least includes the first conductive line, one end of the first conductive line is electrically connected to the first data line, and the first data line is located in the third metal layer.

3. The display panel according to claim 2, characterized in that: The same first connecting line includes a second conductive line electrically connected to the first conductive line, the extension direction of the second conductive line is the same as the extension direction of the first data line, and the second conductive line is located in the third metal layer.

4. The display panel according to claim 1, characterized in that: A first inorganic layer is included between the first metal layer and the capacitor metal layer, a second inorganic layer is included between the capacitor metal layer and the second metal layer, and a first organic layer is included between the second metal layer and the third metal layer.

5. The display panel according to claim 4, characterized in that: The second sub-segment is located in the capacitor metal layer.

6. The display panel according to claim 5, characterized in that: The first reference voltage line is electrically connected to one of the first sub-segments through a first via hole; The first end of the second sub-segment is electrically connected to one of the first sub-segments through the first via hole; The second end of the second subsegment is electrically connected to another first subsegment through a second via.

7. The display panel according to claim 6, characterized in that: The second sub-segment and the first reference voltage line are an integral structure.

8. The display panel according to claim 6, characterized in that: The first via hole penetrates the second inorganic layer, and the second via hole penetrates the second inorganic layer.

9. The display panel according to claim 4, characterized in that: The second sub-segment is located in the first metal layer.

10. The display panel according to claim 9, characterized in that: The first reference voltage line is electrically connected to one of the first sub-segments through a first via hole; The first end of the second sub-segment is electrically connected to one of the first sub-segments through a third via hole; The second end of the second subsegment is electrically connected to another first subsegment through a fourth via.

11. The display panel according to claim 10, characterized in that: The first via hole penetrates the second inorganic layer; The third via hole penetrates the second inorganic layer and the first inorganic layer, and the fourth via hole penetrates the second inorganic layer and the first inorganic layer.

12. A display device, characterized in that: A display panel comprising any one of claims 1 to 11.

Images