Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel is provided with two opposite first frame areas and a display area; the display panel comprises a data line and a pixel circuit, and the pixel circuit comprises a storage capacitor. The data lines extend along a first direction and are arranged along a second direction; the first frame area and the display area are arranged along a second direction; the display area comprises a plurality of display sub-areas; in the second direction, the capacitance value of the display subarea is gradually increased from the first center line of the display area to the first frame area; wherein one display subarea comprises at least one pixel circuit, and the capacitance value of the display subarea is the capacitance value of any storage capacitor in the display subarea; the first centerline extends in a first direction. According to the technical scheme, the display uniformity of the display panel is improved, and then the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Display (OLED) and Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to advantages such as high image quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve the performance of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided. The display panel has two opposite first border regions and a display region. The display panel includes data lines and pixel circuits, and the pixel circuits include storage capacitors.

[0006] The data lines extend in a first direction and are arranged in a second direction. The first border regions and the display region are arranged in the second direction.

[0007] The display region includes a plurality of display sub-regions. Along the second direction, from the first center line of the display region to the first border region, the capacitance values of the display sub-regions gradually increase. Wherein, one display sub-region includes at least one of the pixel circuits, and the capacitance value of the display sub-region is the capacitance value of any storage capacitor in the display sub-region. The first center line extends in the first direction.

[0008] Optionally, the display panel further has a second border region adjacent to the first border region. The second border region and the display region are arranged in the first direction. The second border region is provided with data connection lines connected to the data lines.

[0009] Along the direction from the display region to the second border region, the capacitance values of the display sub-regions gradually decrease.

[0010] Optionally, one display sub-region includes one of the pixel circuits.

[0011] Alternatively, one display sub-region includes at least two of the pixel circuits, and in the same display sub-region, the capacitance values of different storage capacitors are the same.

[0012] Optionally, the display area is divided into a first block and a second block, and the first block is located between the second center line of the display area and the second border area; wherein, the second center line extends along the second direction;

[0013] In the first block, the absolute value of the first difference between the capacitance values of two adjacent display sub-areas along the first direction; is greater than the absolute value of the second difference between the capacitance values of two adjacent display sub-areas along the first direction in the second block;

[0014] Preferably, in the first block, the absolute value of the third difference between the capacitance values of two adjacent display sub-areas along the second direction; is greater than the absolute value of the fourth difference between the capacitance values of two adjacent display sub-areas along the second direction in the second block.

[0015] Optionally, the storage capacitor includes a first capacitor plate and a second capacitor plate;

[0016] Along the second direction, from the first center line of the display area to the first border area, in two adjacent display sub-areas, the facing area between the first capacitor plate and the second capacitor plate in the display sub-area closer to the first border area is greater than the facing area between the first capacitor plate and the second capacitor plate in the display sub-area farther from the first border area;

[0017] And / or, the distance between the first capacitor plate and the second capacitor plate in the display sub-area closer to the first border area is less than the distance between the first capacitor plate and the second capacitor plate in the display sub-area farther from the first border area.

[0018] Optionally, in the same storage capacitor, the area of the second capacitor plate is greater than the area of the first capacitor plate; along the second direction, from the first center line of the display area to the first border area, in two adjacent display sub-areas, the area of the first capacitor plate in the display sub-area closer to the first border area is greater than the area of the first capacitor plate in the display sub-area farther from the first border area;

[0019] Or, in the same storage capacitor, the area of the second capacitor plate is less than the area of the first capacitor plate; along the second direction, from the first center line of the display area to the first border area, in two adjacent display sub-areas, the area of the second capacitor plate in the display sub-area closer to the first border area is greater than the area of the second capacitor plate in the display sub-area farther from the first border area;

[0020] Alternatively, in the same storage capacitor, the area of the second capacitor plate is equal to the area of the first capacitor plate; along the second direction, from the first center line of the display area to the first border area, in two adjacent display sub-areas, the area of the second capacitor plate in the display sub-area closer to the first border area is greater than the area of the second capacitor plate in the display sub-area farther from the first border area; and the area of the first capacitor plate in the display sub-area closer to the first border area is greater than the area of the first capacitor plate in the display sub-area farther from the first border area.

[0021] Optionally, the storage capacitor includes a first capacitor plate and a second capacitor plate;

[0022] Along the first direction, in two adjacent display sub-areas, the facing area of the first capacitor plate and the second capacitor plate in the display sub-area closer to the second border area is smaller than the facing area of the first capacitor plate and the second capacitor plate in the display sub-area farther from the second border area;

[0023] And / or, the distance between the first capacitor plate and the second capacitor plate in the display sub-area closer to the second border area is greater than the distance between the first capacitor plate and the second capacitor plate in the display sub-area farther from the second border area.

[0024] Optionally, in the same storage capacitor, the area of the second capacitor plate is greater than the area of the first capacitor plate; along the first direction, in two adjacent display sub-areas, the area of the first capacitor plate in the display sub-area closer to the second border area is smaller than the area of the first capacitor plate in the display sub-area farther from the second border area;

[0025] Alternatively, in the same storage capacitor, the area of the second capacitor plate is smaller than the area of the first capacitor plate; along the first direction, in two adjacent display sub-areas, the area of the second capacitor plate in the display sub-area closer to the second border area is smaller than the area of the second capacitor plate in the display sub-area farther from the second border area;

[0026] Alternatively, in the same storage capacitor, the area of the second capacitor plate is equal to the area of the first capacitor plate; along the first direction, in two adjacent display sub-areas, the area of the second capacitor plate in the display sub-area closer to the second border area is smaller than the area of the second capacitor plate in the display sub-area farther from the second border area; and the area of the first capacitor plate in the display sub-area closer to the second border area is smaller than the area of the first capacitor plate in the display sub-area farther from the second border area.

[0027] Optionally, the pixel circuit further includes a driving transistor and a data writing transistor;

[0028] A first pole of the storage capacitor is electrically connected to a control pole of the driving transistor, and a second pole of the storage capacitor is connected to a first power supply line;

[0029] The data writing transistor is connected between the data line and the driving transistor. A control pole of the data writing transistor is connected to a first scanning line. The data writing transistor is configured to respond to a first scanning signal on the first scanning line and transmit a data voltage on the data line to the control pole of the driving transistor;

[0030] Preferably, the pixel circuit further includes a threshold compensation transistor;

[0031] The data writing transistor is connected between the data line and a first pole of the driving transistor;

[0032] The threshold compensation transistor is connected between the control pole and a second pole of the driving transistor. A control pole of the threshold compensation transistor is connected to the first scanning line. The threshold compensation transistor is configured to respond to a first scanning signal on the first scanning line and perform threshold compensation on the driving transistor;

[0033] Preferably, the pixel circuit further includes a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between an initialization signal line and the control pole of the driving transistor; the second initialization transistor is connected between the initialization signal line and a first pole of a light-emitting element corresponding to the pixel circuit; a control pole of the first initialization transistor is connected to a second scanning line, and a control pole of the second initialization transistor is connected to a third scanning line; the first initialization transistor is configured to respond to a second scanning signal on the second scanning line and initialize the control pole of the driving transistor; the second initialization transistor is configured to respond to a third scanning signal on the third scanning line and initialize the first pole of the light-emitting element; a second pole of the light-emitting element is connected to a second power supply line;

[0034] Preferably, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor is connected between the first power supply line and the first pole of the driving transistor, and the second light-emitting control transistor is connected between the second pole of the driving transistor and the first pole of the light-emitting element; a control pole of the first light-emitting control transistor and a control pole of the second light-emitting control transistor are connected to a light-emitting control signal line. The first light-emitting control transistor and the second light-emitting control transistor are configured to control whether a driving current generated by the driving transistor is transmitted to the light-emitting element.

[0035] According to another aspect of the present invention, a display device is provided, and the display device includes a display panel according to any embodiment of the present invention.

[0036] In the technical solution of the embodiment of the present invention, along the second direction, from the first center line of the display area to the first border area, the capacitance value of the display sub-area gradually increases, so that the capacitance value of the storage capacitor close to the first border area is larger, and the capacitance value of the storage capacitor located at the first center line is smaller. In this way, the closer to the first border area, the less likely the storage capacitor is to be fully charged, so that the potential of the first pole of the storage capacitor is smaller, that is, the potential of the control pole of the driving transistor is smaller, and the potential difference between the control pole of the driving transistor and the first pole of the driving transistor is larger, so that the opening degree of the driving transistor is larger, which can make up for the problem that the pixel circuit near the first border area receives the data voltage with a delay and the charging rate is low. As a result, under the same gray scale, the driving current generated by the pixel circuit near the first border area is consistent with the driving current generated by the pixel circuit near the first center line, thereby improving the display uniformity of the display panel and further improving the display performance of the display panel.

[0037] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0039] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0041] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0042] Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0043] Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0044] Figure 6 is a timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0045] Figure 7 This is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0046] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0048] As mentioned in the background art, there are problems with the performance of existing display panels that need to be improved. After research by the inventor, it is found that the reason for this problem is that the display panel includes a pixel circuit and a data line. The first end of the data line is connected to a driving chip through a connection line, and the other end of the data line is connected to the pixel circuit. The data line is used to transmit a data voltage to the pixel circuit, so that the pixel circuit can generate a driving current according to the data voltage and drive the corresponding light-emitting element to emit light. There is a delay in the voltage transmission on the data line, resulting in differences in the charging rates of pixel circuits at different positions under the same gray scale, differences in the driving currents generated by pixel circuits at different positions, and differences in the light-emitting brightness of the light-emitting elements corresponding to the pixel circuits, so that the display uniformity of the display panel is poor. The pixel circuit farther away from the driving chip receives a greater delay in the data voltage, resulting in a lower gate charging rate of the driving transistor of the pixel circuit farther away from the driving chip, a smaller opening degree of the driving transistor of the pixel circuit farther away from the driving chip, and a smaller driving current generated by the pixel circuit farther away from the driving chip, so that the light-emitting brightness of the light-emitting element farther away from the driving chip is lower. When the display brightness is high, the data voltage is small, resulting in a greater deviation rate of the data voltages received by the pixel circuit farther away from the driving chip and the pixel circuit closer to the driving chip, and a greater difference in the charging rates, resulting in a greater difference in brightness.

[0049] Moreover, the display panel has corners. The data lines at the corners are connected to the driving chip through fan-shaped connecting traces. The length of the fan-shaped connecting traces is relatively large, resulting in a large delay in the data voltage received by the data lines at the corners. There is a difference in the charging rate between the pixel circuits near the border of the display panel and the pixel circuits in the middle of the display panel. At the same gray level, there is a difference in the display brightness between the area near the corners and the middle area of the display panel, affecting the display uniformity of the display panel and making the performance of the display panel poor.

[0050] In view of the above technical problems, an embodiment of the present invention provides a display panel. Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Figure 2 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Referring to Figure 1 and Figure 2 , the display panel has two opposite first border areas B1 and a display area AA; the display panel includes data lines Data and pixel circuits 11, and the pixel circuits 11 include storage capacitors Cst.

[0051] The data lines Data extend along a first direction Y and are arranged along a second direction X; the first border areas B1 and the display area AA are arranged along the second direction X.

[0052] The display area AA includes a plurality of display sub-areas A0; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-areas A0 gradually increases; wherein, a display sub-area A0 includes at least one pixel circuit 11, and the capacitance value of the display sub-area A0 is the capacitance value of any storage capacitor Cst in the display sub-area A0; the first center line L1 extends along the first direction Y.

[0053] Among them, the pixel circuit 11 and the data line Data are disposed in the display area AA, and multiple pixel circuits 11 are arranged in an array. The pixel circuit 11 can be a 2T1C pixel circuit and its variants, or a 7T1C pixel circuit and its variants. The display panel further includes a light-emitting element, and the pixel circuit 11 is connected to the light-emitting element. The data line Data transmits a data voltage to the pixel circuit 11, so that the pixel circuit 11 generates a driving current according to the data voltage, and thus the light-emitting element connected to the pixel circuit 11 can emit light in response to the driving current, and the display area AA can display an image. The storage capacitor Cst in the pixel circuit 11 can store the data voltage transmitted by the data line Data to the pixel circuit 11, which is convenient for maintaining the driving current generated by the pixel circuit 11. For example, the pixel circuit 11 includes a driving transistor, and the driving transistor can generate a driving current according to the data voltage. The first pole of the storage capacitor Cst is connected to the control pole of the driving transistor, so that the storage capacitor Cst can maintain the potential of the control pole of the driving transistor, thereby maintaining the driving current generated by the driving transistor.

[0054] The data line Data extends along the first direction Y, and the first direction Y is, for example, the longitudinal direction commonly referred to, that is, the column direction in which the pixel circuits 11 are arranged. Multiple data lines Data are arranged along the second direction X. The second direction X can be from left to right or from right to left. The second direction X is, for example, the horizontal direction commonly referred to, that is, the row direction in which the pixel circuits 11 are arranged, and it is not limited to from left to right or from right to left. Along the second direction X, from the first center line L1 of the display area AA to the first border area B1, that is, the direction pointing from the first center line L1 horizontally to the first border area B1, includes the direction X1 pointing horizontally to the left from the first center line L1 and the direction X2 pointing horizontally to the right from the first center line L1.

[0055] Among them, a gate driving circuit can be disposed in the first border area B1. The gate driving circuit can be connected to the pixel circuit 11 to transmit a gate driving signal to the pixel circuit 11, which is convenient for controlling the conduction timing of each transistor in the pixel circuit 11. The first border area B1 can also be provided with a power line, a signal line, etc., which are not limited in this embodiment.

[0056] The display area AA can be divided into multiple display sub-areas A0. The display sub-area A0 includes at least one pixel circuit 11, that is, the display sub-area A0 includes at least one storage capacitor Cst, and the capacitance values of different storage capacitors in the same display sub-area A0 are the same. When the display sub-area A0 includes one storage capacitor Cst, the capacitance value of the display sub-area A0 is the capacitance value of the storage capacitor Cst in the display sub-area A0; when the display sub-area A0 includes at least two storage capacitors Cst, the capacitance value of the display sub-area A0 is the capacitance value of any one storage capacitor Cst in the display sub-area A0.

[0057] Specifically, along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-area A0 gradually increases, so that the capacitance value of the storage capacitor Cst near the first border area B1 is larger, and the capacitance value of the storage capacitor Cst at the first center line L1 is smaller. The larger the capacitance value of the storage capacitor Cst, the more difficult it is to be fully charged, so that the potential of the first pole of the storage capacitor Cst is smaller, that is, the potential of the control pole of the driving transistor is smaller, and the potential difference between the control pole and the first pole of the driving transistor is larger, making the opening degree of the driving transistor larger, which can compensate for the problem that the pixel circuit 11 near the first border area B1 receives the data voltage with a delay and has a low charging rate. Thus, under the same gray scale, the driving current generated by the pixel circuit 11 near the first border area B1 is made to tend to be consistent with the driving current generated by the pixel circuit 11 near the first center line L1, thereby improving the display uniformity of the display panel. Especially when the display brightness is relatively high, by setting that along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-area A0 gradually increases, so that the capacitance value of the storage capacitor Cst near the first border area B1 is larger and the capacitance value of the storage capacitor Cst near the first center line L1 is smaller, the brightness deviation caused by the deviation of the charging rate at different positions can be effectively compensated, which is convenient for improving the display uniformity of the display panel.

[0058] Moreover, the technical solution of this embodiment does not require adjusting the driving method of the display panel, which can reduce the driving adjustment time and lower the debugging cost.

[0059] In the technical solution of this embodiment, along the second direction, from the first center line of the display area to the first border area, the capacitance value of the display sub-area gradually increases, so that the capacitance value of the storage capacitor near the first border area is larger, and the capacitance value of the storage capacitor at the first center line is smaller. In this way, the closer to the first border area, the more difficult it is for the storage capacitor to be fully charged, so that the potential of the first pole of the storage capacitor is smaller, that is, the potential of the control pole of the driving transistor is smaller, and the potential difference between the control pole and the first pole of the driving transistor is larger, making the opening degree of the driving transistor larger, which can compensate for the problem that the pixel circuit near the first border area receives the data voltage with a delay and has a low charging rate. Thus, under the same gray scale, the driving current generated by the pixel circuit near the first border area is made to tend to be consistent with the driving current generated by the pixel circuit near the first center line, thereby improving the display uniformity of the display panel and further improving the display performance of the display panel.

[0060] Based on the above technical solution, Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Optionally, refer to Figure 3, the display panel further has a second border area B2 adjacent to the first border area B1, and the second border area B2 and the display area AA are arranged along the first direction Y; a data connection line F1 connected to the data line Data is provided in the second border area B2;

[0061] Along the direction Y' from the display area AA to the second border area B2, the capacitance value of the display sub-area A0 gradually decreases.

[0062] Among them, the second border area B2 can be used to set a driving chip. The first end of the data connection line F1 is electrically connected to the driving chip, and the second end of the data connection line F1 is electrically connected to the data line Data, so as to transmit the data voltage output by the driving chip to the data line Data. The data connection line F1 can include fan-shaped traces or traces having the same extending direction as the data line Data.

[0063] Specifically, by setting the direction Y' from the display area AA to the second border area B2, the capacitance value of the display sub-area A0 gradually decreases. Then, the farther away from the second border area B2, the larger the capacitance value of the display sub-area A0, and it is more difficult for the storage capacitor to be fully charged, so that the potential of the first pole of the storage capacitor is smaller, that is, the potential of the control pole of the driving transistor is smaller, and the potential difference between the control pole and the first pole of the driving transistor is larger, making the opening degree of the driving transistor larger. This can compensate for the problem that the data line Data has a delay in receiving the data voltage in the pixel circuit far from the second border area B2 and the charging rate is low. As a result, under the same gray scale, the driving current generated by the pixel circuit 11 far from the second border area B2 is made to be consistent with the driving current generated by the pixel circuit 11 close to the second border area B2, thereby improving the display uniformity of the display panel and further improving the use performance of the display panel.

[0064] Taking the example that the display area AA is divided into 9 display sub-areas A0, the display panel in the related technology (the display panel with the same capacitance value of the storage capacitor in the entire display area AA) is compared with the display panel of this embodiment (along the direction Y' from the display area AA to the second border area B2, the capacitance value of the display sub-area A0 gradually decreases; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-area A0 gradually increases).

[0065] Table 1 Point current distribution table of the display sub-area A0 in the related technology

[0066]

[0067] Table 2 Point current distribution table of the display sub-area A0 in this embodiment

[0068]

[0069]

[0070] Table 1 is a table showing the dot current distribution of sub-region A0 in the related art, and Table 2 is a table showing the dot current distribution of sub-region A0 in this embodiment. The positions in Table 1 and Table 2 are Figure 3 the positions of the shown sub-region A0. The facing area of the storage capacitor in Table 1 and Table 2 is the facing area of any one storage capacitor in the corresponding sub-region A0. When there is one storage capacitor in sub-region A0, the dot current of sub-region A0 is the current of the light-emitting element connected to the pixel circuit where the storage capacitor is located; when there are at least two storage capacitors in sub-region A0, the dot current of sub-region A0 is the average current of all the light-emitting elements in sub-region A0. As shown in Table 1 and Table 2, for the display panel of this embodiment, along the direction Y' pointing from the display area AA to the second border area B2, the capacitance value of sub-region A0 gradually decreases; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of sub-region A0 gradually increases, which can make the dot current differences corresponding to all sub-regions A0 very small, and the dot currents corresponding to all sub-regions A0 tend to be consistent, effectively improving the display uniformity of the display panel.

[0071] Based on the above technical solutions, optionally, a sub-region A0 includes one pixel circuit 11; or, a sub-region A0 includes at least two pixel circuits 11, and in the same sub-region A0, the capacitance values of different storage capacitors Cst are the same.

[0072] Specifically, a sub-region A0 can include one pixel circuit 11, that is, a sub-region A0 includes one storage capacitor Cst, which can make the capacitance value of the storage capacitor Cst gradually increase along the second direction X from the first center line L1 of the display area AA to the first border area B1; along the direction pointing from the display area AA to the second border area B2, the capacitance value of the storage capacitor Cst gradually decreases. In this way, the capacitance value of the storage capacitor can be accurately adjusted, thereby effectively improving the uniformity of the display panel.

[0073] Or, a sub-region A0 can include at least two pixel circuits 11. In the same sub-region A0, the capacitance values of different storage capacitors Cst are the same, while for different sub-regions A0, the capacitance values of the storage capacitors Cst are different. Because the positions of the storage capacitors Cst in the same sub-region A0 are close, in the same sub-region A0, the delay degrees of different pixel circuits 11 receiving data voltages are close, and the charging rates of different pixel circuits 11 are close. Therefore, by adjusting the capacitance values of different sub-regions A0, the uniformity of the display panel can be improved, and the process difficulty can be reduced, which is beneficial to reducing the process cost.

[0074] Based on the above technical solutions, Figure 4It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Optionally, referring to Figure 4 , the display area AA is divided into a first block A1 and a second block A2. The first block A1 is located between the second center line L2 of the display area AA and the second border area B2. Among them, the second center line L2 extends along the second direction X;

[0075] In the first block A1, the absolute value of the first difference in capacitance values of two adjacent display sub-areas A0 along the first direction Y; is greater than the absolute value of the second difference in capacitance values of two adjacent display sub-areas A0 along the first direction Y in the second block A2.

[0076] Among them, the second center line L2 divides the display area AA into a first block A1 and a second block A2. The first block A1 includes a plurality of display sub-areas A0, and the second block A2 includes a plurality of display sub-areas A0. The first block A1 is the block closer to the second border area B2, and the second block A2 is the block farther from the second border area B2. Then the first block A1 is closer to the driving chip in the display device formed by the display panel than the second block A2.

[0077] Specifically, by setting the absolute value of the first difference in capacitance values of two adjacent display sub-areas A0 along the first direction Y in the first block A1; to be greater than the absolute value of the second difference in capacitance values of two adjacent display sub-areas A0 along the first direction Y in the second block A2, it can be made that in the second block A2, along the direction Y' from the display area AA to the second border area B2, the capacitance values of different display sub-areas A0 vary greatly, that is, change greatly, which can more fully compensate for the problem that the pixel circuits far from the second border area B2 receive data voltages with delays and have low charging rates, facilitating further improvement of the display uniformity of the display panel.

[0078] Optionally, referring to Figure 4 , in the first block A1, the absolute value of the third difference in capacitance values of two adjacent display sub-areas A0 along the second direction X; is greater than the absolute value of the fourth difference in capacitance values of two adjacent display sub-areas A0 along the second direction X in the second block A2. In this way, it can be made that in the second block A2, along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance values of different display sub-areas A0 vary greatly, that is, change greatly, which can more fully compensate for the problem that the pixel circuits close to the first border area B1 receive data voltages with delays and have low charging rates, facilitating further improvement of the display uniformity of the display panel.

[0079] It should be noted that Figure 1 and Figure 3 show the case where the display area AA is divided into 9 display sub-areas A0, Figure 4The situation where the display area AA is divided into 12 display sub-areas A0 is shown, but it is not limited. The number of display sub-areas A0 can be set according to actual requirements. For example, when the requirement for display uniformity is relatively high, the number of display sub-areas A0 can be relatively large; when the requirement for saving process costs is relatively high, the number of display sub-areas A0 can be relatively small.

[0080] Based on the above technical solutions, the implementation manner in which the capacitance value of the display sub-area A0 gradually changes in the second direction X will be described below, but it is not a limitation to this application.

[0081] Optionally, the storage capacitor Cst includes a first capacitor plate and a second capacitor plate;

[0082] Along the second direction X, from the first center line L1 of the display area AA to the first border area B1, among two adjacent display sub-areas A0, the overlapping area between the first capacitor plate and the second capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than the overlapping area between the first capacitor plate and the second capacitor plate in the display sub-area A0 farther from the first border area B1;

[0083] And / or, the distance between the first capacitor plate and the second capacitor plate in the display sub-area A0 closer to the first border area B1 is smaller than the distance between the first capacitor plate and the second capacitor plate in the display sub-area A0 farther from the first border area B1.

[0084] Specifically, the larger the facing area between the first capacitor plate and the second capacitor plate, the larger the capacitance value of the storage capacitor Cst. The smaller the distance between the first capacitor plate and the second capacitor plate, the larger the capacitance value of the storage capacitor Cst. By setting that along the second direction X, from the first center line L1 of the display area AA to the first border area B1, in two adjacent display sub-areas A0, the facing area between the first capacitor plate and the second capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than that in the display sub-area A0 farther from the first border area B1, it can be made that the capacitance value of the display sub-area A0 closer to the first border area B1 is larger than that of the display sub-area A0 farther from the first border area B1, so that along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-area A0 gradually increases. Similarly, by setting that along the second direction X, from the first center line L1 of the display area AA to the first border area B1, in two adjacent display sub-areas A0, the distance between the first capacitor plate and the second capacitor plate in the display sub-area A0 closer to the first border area B1 is smaller than that in the display sub-area A0 farther from the first border area B1, it can be made that the capacitance value of the display sub-area A0 closer to the first border area B1 is larger than that of the display sub-area A0 farther from the first border area B1, so that along the second direction X, from the first center line L1 of the display area AA to the first border area B1, the capacitance value of the display sub-area A0 gradually increases.

[0085] Based on the above technical solution, in an embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is larger than the area of the first capacitor plate; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, in two adjacent display sub-areas A0, the area of the first capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than the area of the first capacitor plate in the display sub-area A0 farther from the first border area B1.

[0086] Specifically, the second capacitor plate of the storage capacitor Cst is connected to the first power supply line VDD. The second capacitor plate can be a part of the first power supply line VDD, so the area of the second capacitor plate is larger and larger than the area of the first capacitor plate. Therefore, it can be made that the area of the second capacitor plate remains unchanged, and the area of the first capacitor plate of the storage capacitor Cst is adjusted to realize the adjustment of the facing area between the two capacitor plates of the storage capacitor Cst, thereby realizing the change of the capacitance value of the storage capacitor Cst, which can reduce the process difficulty and the process cost.

[0087] In another embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is smaller than that of the first capacitor plate; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, among two adjacent display sub-areas A0, the area of the second capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than the area of the second capacitor plate in the display sub-area A0 farther from the first border area B1.

[0088] Specifically, the first capacitor plate of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor in the pixel circuit 11. The control electrode of the driving transistor can be multiplexed as the first capacitor plate of the storage capacitor Cst. The second capacitor plate of the storage capacitor Cst can be a separate conductive plate, so the area of the second capacitor plate is smaller and less than that of the first capacitor plate. Therefore, the area of the first capacitor plate can remain unchanged, and the area of the second capacitor plate of the storage capacitor Cst can be adjusted to realize the adjustment of the facing area of the two capacitor plates of the storage capacitor Cst, thereby realizing the change of the capacitance value of the storage capacitor Cst, which can reduce the process difficulty and the process cost.

[0089] In another embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is equal to that of the first capacitor plate; along the second direction X, from the first center line L1 of the display area AA to the first border area B1, among two adjacent display sub-areas A0, the area of the second capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than the area of the second capacitor plate in the display sub-area A0 farther from the first border area B1; and the area of the first capacitor plate in the display sub-area A0 closer to the first border area B1 is larger than the area of the first capacitor plate in the display sub-area A0 farther from the first border area B1.

[0090] Specifically, when the areas of the first capacitor plate and the second capacitor plate in the storage capacitor Cst are the same, the areas of the two capacitor plates can be adjusted simultaneously to realize the adjustment of the facing area of the two capacitor plates of the storage capacitor Cst, thereby realizing the change of the capacitance value of the storage capacitor Cst.

[0091] Based on the above technical solutions, the implementation manner of the capacitance value of the display sub-area A0 gradually changing in the first direction Y will be described below, but it is not a limitation to the present application.

[0092] Optionally, along the first direction Y, among two adjacent display sub-areas A0, the facing area of the first capacitor plate and the second capacitor plate in the display sub-area A0 closer to the second border area B2 is smaller than the facing area of the first capacitor plate and the second capacitor plate in the display sub-area A0 farther from the second border area B2;

[0093] And / or, the distance between the first capacitor plate and the second capacitor plate in the display sub-region A0 close to the second border region B2 is greater than the distance between the first capacitor plate and the second capacitor plate in the display sub-region A0 far from the second border region B2.

[0094] Specifically, by setting that in two adjacent display sub-regions A0 along the first direction Y, the facing area between the first capacitor plate and the second capacitor plate in the display sub-region A0 close to the second border region B2 is smaller than the facing area between the first capacitor plate and the second capacitor plate in the display sub-region A0 far from the second border region B2, the capacitance value of the display sub-region A0 far from the second border region B2 can be made greater than the capacitance value of the display sub-region A0 close to the second border region B2, so that along the direction Y' from the display region AA to the second border region B2, the capacitance value of the display sub-region A0 gradually decreases. Similarly, by setting that in two adjacent display sub-regions A0 along the first direction Y, the distance between the first capacitor plate and the second capacitor plate in the display sub-region A0 close to the second border region B2 is greater than the distance between the first capacitor plate and the second capacitor plate in the display sub-region A0 far from the second border region B2, the capacitance value of the display sub-region A0 far from the second border region B2 can be made greater than the capacitance value of the display sub-region A0 close to the second border region B2, so that along the direction Y' from the display region AA to the second border region B2, the capacitance value of the display sub-region A0 gradually decreases.

[0095] In one embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is greater than the area of the first capacitor plate; in two adjacent display sub-regions A0 along the first direction Y, the area of the first capacitor plate in the display sub-region A0 close to the second border region B2 is smaller than the area of the first capacitor plate in the display sub-region A0 far from the second border region B2.

[0096] Specifically, the first capacitor plate of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor in the pixel circuit 11, and the control electrode of the driving transistor can be multiplexed as the first capacitor plate of the storage capacitor Cst. The second capacitor plate of the storage capacitor Cst can be a separate conductive electrode plate, so the area of the second capacitor plate is smaller and less than the area of the first capacitor plate. Therefore, the area of the first capacitor plate can be kept unchanged, and the area of the second capacitor plate of the storage capacitor Cst can be adjusted to realize the adjustment of the facing area between the two capacitor plates of the storage capacitor Cst. In two adjacent display sub-regions A0 along the first direction Y, the area of the first capacitor plate in the display sub-region A0 close to the second border region B2 is smaller than the area of the first capacitor plate in the display sub-region A0 far from the second border region B2, so that along the direction Y' from the display region AA to the second border region B2, the capacitance value of the display sub-region A0 gradually decreases. Thus, the change of the capacitance value of the storage capacitor Cst can be realized, the process difficulty can be reduced, and the process cost can be reduced.

[0097] In another embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is smaller than that of the first capacitor plate; along the first direction Y, in two adjacent display sub-regions A0, the area of the second capacitor plate in the display sub-region A0 closer to the second border region B2 is smaller than the area of the second capacitor plate in the display sub-region A0 farther from the second border region B2.

[0098] Specifically, the first capacitor plate of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor in the pixel circuit 11. The control electrode of the driving transistor can be multiplexed as the first capacitor plate of the storage capacitor Cst. The second capacitor plate of the storage capacitor Cst can be a separate conductive plate, so the area of the second capacitor plate is smaller and less than that of the first capacitor plate. Therefore, the area of the first capacitor plate can be kept unchanged, and the area of the second capacitor plate of the storage capacitor Cst can be adjusted to realize the adjustment of the facing area of the two capacitor plates of the storage capacitor Cst, thereby realizing the change of the capacitance value of the storage capacitor Cst, reducing the process difficulty and the process cost. Along the first direction Y, in two adjacent display sub-regions A0, the area of the second capacitor plate in the display sub-region A0 closer to the second border region B2 is smaller than the area of the second capacitor plate in the display sub-region A0 farther from the second border region B2, so that the capacitance value of the display sub-region A0 farther from the second border region B2 is greater than that of the display sub-region A0 closer to the second border region B2, and the capacitance value of the display sub-region A0 gradually decreases along the direction Y' from the display area AA to the second border region B2.

[0099] In another embodiment, optionally, in the same storage capacitor Cst, the area of the second capacitor plate is equal to that of the first capacitor plate; along the first direction Y, in two adjacent display sub-regions A0, the area of the second capacitor plate in the display sub-region closer to the second border region B0 is smaller than the area of the second capacitor plate in the display sub-region A0 farther from the second border region B2; and the area of the first capacitor plate in the display sub-region closer to the second border region B2 is smaller than the area of the first capacitor plate in the display sub-region A0 farther from the second border region B2.

[0100] Specifically, when the areas of the first and second capacitor plates in the storage capacitor Cst are the same, the areas of both capacitor plates can be adjusted simultaneously to adjust the facing area of the two capacitor plates of the storage capacitor Cst, thereby realizing the change in the capacitance value of the storage capacitor Cst. The area of the second capacitor plate in the display sub-region close to the second border region B0 is smaller than the area of the second capacitor plate in the display sub-region A0 far from the second border region B2; and the area of the first capacitor plate in the display sub-region close to the second border region B2 is smaller than the area of the first capacitor plate in the display sub-region A0 far from the second border region B2, which can make the capacitance value of the display sub-region A0 far from the second border region B2 greater than the capacitance value of the display sub-region A0 close to the second border region B2, so that along the direction Y' from the display area AA to the second border region B2, the capacitance value of the display sub-region A0 gradually decreases.

[0101] Based on the above technical solutions, the possible structure of the pixel circuit 11 will be described below, but it is not a limitation to this application.

[0102] In one implementation, optionally, referring to Figure 2 , the pixel circuit 11 further includes a driving transistor T1 and a data writing transistor T2;

[0103] The first pole of the storage capacitor Cst is electrically connected to the control pole of the driving transistor T1, and the second pole of the storage capacitor Cst is connected to the first power supply line VDD;

[0104] The data writing transistor T2 is connected between the data line Data and the driving transistor T1. The control pole of the data writing transistor T2 is connected to the first scanning line S1. The data writing transistor T2 is configured to respond to the first scanning signal on the first scanning line S1 and transmit the data voltage on the data line Data to the control pole of the driving transistor T1.

[0105] Specifically, the pixel circuit 11 can be a 2T1C pixel circuit as shown in Figure 2 . The data writing transistor T2 is connected to the control pole of the driving transistor T1. The first pole of the driving transistor T1 is connected to the first power supply line VDD. The second pole of the driving transistor T1 is electrically connected to the first pole of the light-emitting element 12. The second pole of the light-emitting element 12 is connected to the second power supply line VSS. Among them, the light-emitting element 12 includes an organic light-emitting diode OLED.

[0106] When the first scan signal on the first scan line S1 is at an effective level, the data writing transistor T2 can transfer the data voltage on the data line Data to the control electrode of the driving transistor T1. The driving transistor T1 generates a driving current according to the first power supply voltage on the first power supply line VDD and the data voltage, so that the light emitting element 12 emits light in response to the driving current. The storage capacitor Cst can maintain the potential of the control electrode of the driving transistor T1, thereby maintaining the driving current generated by the driving transistor T1. Herein, the effective level can be a high level or a low level, which is not limited in this embodiment.

[0107] In another embodiment, Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present invention. Optionally, referring to Figure 5 , the pixel circuit 11 includes a driving transistor T1 and a data writing transistor T2;

[0108] The first pole of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor T1, and the second pole of the storage capacitor Cst is connected to the first power supply line VDD;

[0109] The data writing transistor T2 is connected between the data line Data and the driving transistor T1. The control electrode of the data writing transistor T2 is connected to the first scan line S1. The data writing transistor T2 is configured to respond to the first scan signal on the first scan line S1 and transfer the data voltage on the data line Data to the control electrode of the driving transistor T1;

[0110] The pixel circuit 11 further includes a threshold compensation transistor T3;

[0111] The data writing transistor T2 is connected between the data line Data and the first pole of the driving transistor T1;

[0112] The threshold compensation transistor T3 is connected between the control electrode and the second pole of the driving transistor T1. The control electrode of the threshold compensation transistor T3 is connected to the first scan line S1. The threshold compensation transistor T3 is configured to respond to the first scan signal on the first scan line S1 and perform threshold compensation on the driving transistor T1.

[0113] Specifically, when the first scan signal on the first scan line S1 is at an effective level, the data writing transistor T2 and the threshold compensation transistor T3 are turned on. The data voltage Vata on the data line Data charges the first pole of the storage capacitor Cst through the data writing transistor T2, the driving transistor T1, and the threshold compensation transistor T3 until it is charged to Vdata + Vth, where Vth is the threshold voltage of the driving transistor T1. Thus, the voltage after threshold compensation is transmitted to the control pole of the driving transistor T1, realizing the threshold compensation for the driving transistor T1. As a result, the driving transistor T1 generates a driving current according to the voltage after threshold compensation, so that the driving current will not change due to the threshold voltage fluctuation of the driving transistor T1, and the light-emitting element 12 can emit light stably.

[0114] Optionally, referring to Figure 5 , the pixel circuit 11 further includes a first initialization transistor T4 and a second initialization transistor T5. The first initialization transistor T4 is connected between the initialization signal line Vref and the control pole of the driving transistor T1. The second initialization transistor T5 is connected between the initialization signal line Vref and the first pole of the light-emitting element 12 corresponding to the pixel circuit 11. The control pole of the first initialization transistor T4 is connected to the second scan line S2, and the control pole of the second initialization transistor T5 is connected to the third scan line S3. The first initialization transistor T4 is used to initialize the control pole of the driving transistor T1 in response to the second scan signal on the second scan line S2. The second initialization transistor T5 is used to initialize the first pole of the light-emitting element 12 in response to the third scan signal on the third scan line S3. The second pole of the light-emitting element 12 is connected to the second power supply line VSS.

[0115] Specifically, when the second scan signal on the second scan line S2 is at an effective level, the first initialization transistor T4 is turned on, and the first initialization transistor T4 transmits the initialization signal on the initialization signal line Vref to the control pole of the driving transistor T1 to initialize the control pole of the driving transistor T1, facilitating the removal of the residual charge of the previous frame and enabling the driving transistor T1 to better generate a driving current according to the data voltage. When the third scan signal on the third scan line S3 is at an effective level, the second initialization transistor T5 is turned on, and the second initialization transistor T5 transmits the initialization signal on the initialization signal line Vref to the first pole of the light-emitting element 12, facilitating the light-emitting element 12 to emit light in response to the driving current.

[0116] Among them, the threshold compensation transistor T3 and the first initialization transistor T4 can be dual-gate transistors, which can reduce the leakage current of the control electrode of the driving transistor T1, thereby improving the stability of the driving current generated by the driving transistor T1. In some other embodiments, the second scan line S2 and the third scan line S3 can be the same scan line, that is, the control electrodes of the first initialization transistor T4 and the second initialization transistor T5 are connected to the same scan line, and the driving transistor T1 and the light-emitting element 12 can be initialized simultaneously.

[0117] Optionally, referring to Figure 5 , the pixel circuit 11 further includes a first light-emitting control transistor T6 and a second light-emitting control transistor T7; the first light-emitting control transistor T6 is connected between the first power supply line VDD and the first pole of the driving transistor T1, and the second light-emitting control transistor T7 is connected between the second pole of the driving transistor T1 and the first pole of the light-emitting element 12; the control electrodes of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are connected to the light-emitting control signal line EM, and the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are used to control whether the driving current generated by the driving transistor T1 is transmitted to the light-emitting element 12.

[0118] Specifically, when the light-emitting control signal on the light-emitting control signal line EM is at an effective level, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on, so that the first power supply line VDD, the first light-emitting control transistor T6, the driving transistor T1, the second light-emitting control transistor T7, the light-emitting element 12, and the second power supply line VSS can form a current loop, which is convenient for the driving transistor T1 to generate a driving current, and the driving current can be transmitted to the light-emitting element 12, so that the light-emitting element 12 emits light in response to the driving current.

[0119] It should be noted that Figure 2 and Figure 5 show the case where the transistors in the pixel circuit 11 are all P-type transistors, but it is not limited. In some other embodiments, the transistors in the pixel circuit 11 can all be N-type transistors; or, some are P-type transistors and some are N-type transistors.

[0120] Figure 6 is a timing diagram of a pixel circuit provided by an embodiment of the present invention. The working timing of the pixel circuit will be described below in conjunction with Figure 5 and Figure 6 , but it is not a limitation to the present application.

[0121] Optionally, referring to Figure 5 and Figure 6 , the working process of the pixel circuit can include the following stages:

[0122] In the first stage t1, the second scan signal Scan2 on the second scan line S2 is at an effective level, and the first initialization transistor T4 is turned on. The first scan line signal Scan1 on the first scan line S1, the third scan signal Scan3 on the third scan line S3, and the emission control signal Em on the emission control signal line EM are at ineffective levels, and the second initialization transistor T5, the data writing transistor T2, the threshold compensation transistor T3, the first emission control transistor T6, and the second emission control transistor T7 are turned off. The first initialization transistor T4 transmits the initialization signal on the initialization signal line Vref to the control electrode of the driving transistor T1 to initialize the control electrode of the driving transistor T1, facilitating the removal of the residual charge of the previous frame and enabling the driving transistor T1 to better generate a driving current according to the data voltage.

[0123] In the second stage t2, the second scan signal Scan2 on the second scan line S2 and the emission control signal Em on the emission control signal line EM are at ineffective levels, and the first initialization transistor T4, the first emission control transistor T6, and the second emission control transistor T7 are turned off. The first scan line signal Scan1 on the first scan line S1 and the third scan signal Scan3 on the third scan line S3 are at effective levels, and the second initialization transistor T5, the data writing transistor T2, and the threshold compensation transistor T3 are turned on. The second initialization transistor T5 is turned on, and the second initialization transistor T5 transmits the initialization signal on the initialization signal line Vref to the first pole of the light-emitting element 12, facilitating the removal of the residual charge of the first pole of the light-emitting element 12. The data voltage Vata on the data line Data charges the first pole of the storage capacitor Cst through the data writing transistor T2, the driving transistor T1, and the threshold compensation transistor T3 until it is charged to Vdata + Vth, thereby realizing the transmission of the threshold-compensated voltage to the control electrode of the driving transistor T1 and achieving the threshold compensation of the driving transistor T1.

[0124] In the third stage t3, the first scan line signal Scan1 on the first scan line S1, the second scan signal Scan2 on the second scan line S2, and the third scan signal Scan3 on the third scan line S3 are at an invalid level, and the first initialization transistor T4, the second initialization transistor T5, the data writing transistor T2, and the threshold compensation transistor T3 are turned off. The emission control signal Em on the emission control signal line EM is at an effective level, and the first emission control transistor T6 and the second emission control transistor T7 are turned on, so that a current loop is formed among the first power supply line VDD, the first emission control transistor T6, the driving transistor T1, the second emission control transistor T7, the light-emitting element 12, and the second power supply line VSS. The driving transistor T1 generates a driving current according to the first power supply voltage on the first power supply line VDD and the data voltage after threshold compensation, and the driving current can be transmitted to the light-emitting element 12, so that the light-emitting element 12 emits light in response to the driving current.

[0125] Among them, for example, the effective level is a high level and the invalid level is a low level; or, the effective level is a low level and the invalid level is a high level. Figure 6 The case where the effective level is a low level is shown, but it is not limited.

[0126] The embodiment of the present invention further provides a display device. Figure 7 It is a schematic structural diagram of a display device provided by the embodiment of the present invention. Refer to Figure 7 , the display device 20 includes the display panel 21 provided by any implementation scheme of the present invention. Therefore, the display device 20 has the same beneficial effects as the display panel 21 provided by any embodiment of the present invention, which will not be elaborated here. The display device 20 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, etc.

[0127] The above specific implementation manners do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: The display panel has two opposite first frame areas and a display area; the display panel includes a data line and a pixel circuit, and the pixel circuit includes a storage capacitor; The data lines extend along a first direction and are arranged along a second direction; the first frame area and the display area are arranged along the second direction; The display area includes multiple display sub-areas; along the second direction, from the first center line of the display area to the first border area, the capacitance of the display sub-area gradually increases; wherein, one of the display sub-areas includes at least one of the pixel circuits, and the capacitance of the display sub-area is the capacitance of any storage capacitor in the display sub-area; the first center line extends along the first direction.

2. The display panel according to claim 1, characterized in that: The display panel further comprises a second frame area adjacent to the first frame area, the second frame area and the display area are arranged along the first direction; the second frame area is provided with a data connection line connected to the data line; Along the direction from the display area to the second frame area, the capacitance of the display sub-area gradually decreases.

3. The display panel according to claim 1 or 2, characterized in that: The display sub-area includes one pixel circuit; Alternatively, one of the display sub-areas includes at least two of the pixel circuits, and in the same display sub-area, the capacitances of different storage capacitors are the same.

4. The display panel according to claim 2, characterized in that: The display area is divided into a first block and a second block, the first block is located between a second center line of the display area and the second frame area; wherein the second center line extends along the second direction; In the first block, an absolute value of a first difference in capacitance between two adjacent display sub-areas along the first direction is greater than an absolute value of a second difference in capacitance between two adjacent display sub-areas along the first direction in the second block; Preferably, in the first block, an absolute value of a third difference in capacitance between two adjacent display sub-areas along the second direction is greater than an absolute value of a fourth difference in capacitance between two adjacent display sub-areas along the second direction in the second block.

5. The display panel according to claim 1, characterized in that: The storage capacitor comprises a first capacitor plate and a second capacitor plate; Along the second direction, from the first center line of the display area to the first frame area, in two adjacent display sub-areas, the area directly facing the first capacitor plate and the second capacitor plate in the display sub-area close to the first frame area is larger than the area directly facing the first capacitor plate and the second capacitor plate in the display sub-area far from the first frame area; And / or, a distance between the first capacitor plate and the second capacitor plate in a display sub-area close to the first frame area is smaller than a distance between the first capacitor plate and the second capacitor plate in a display sub-area far from the first frame area.

6. The display panel according to claim 5, characterized in that: In the same storage capacitor, the area of ​​the second capacitor plate is greater than the area of ​​the first capacitor plate; along the second direction, from the first center line of the display area to the first frame area, in two adjacent display sub-areas, the area of ​​the first capacitor plate in the display sub-area close to the first frame area is greater than the area of ​​the first capacitor plate in the display sub-area far from the first frame area; Alternatively, in the same storage capacitor, the area of ​​the second capacitor plate is smaller than the area of ​​the first capacitor plate; Along the second direction, from the first center line of the display area to the first frame area, in two adjacent display sub-areas, the area of ​​the second capacitor plate in the display sub-area close to the first frame area is larger than the area of ​​the second capacitor plate in the display sub-area far from the first frame area; Alternatively, in the same storage capacitor, the area of ​​the second capacitor plate is equal to the area of ​​the first capacitor plate; Along the second direction, from the first center line of the display area to the first border area, in two adjacent display sub-areas, the area of ​​the second capacitor plate in the display sub-area close to the first border area is larger than the area of ​​the second capacitor plate in the display sub-area away from the first border area; and the area of ​​the first capacitor plate in the display sub-area close to the first border area is larger than the area of ​​the first capacitor plate in the display sub-area away from the first border area.

7. The display panel according to claim 2, characterized in that: The storage capacitor comprises a first capacitor plate and a second capacitor plate; Along the first direction, in two adjacent display sub-areas, an area directly facing each other between the first capacitor plate and the second capacitor plate in the display sub-area close to the second frame area is smaller than an area directly facing each other between the first capacitor plate and the second capacitor plate in the display sub-area far from the second frame area; And / or, a distance between the first capacitor plate and the second capacitor plate in a display sub-area close to the second frame area is greater than a distance between the first capacitor plate and the second capacitor plate in a display sub-area away from the second frame area.

8. The display panel according to claim 7, characterized in that: In the same storage capacitor, the area of ​​the second capacitor plate is larger than the area of ​​the first capacitor plate; along the first direction, in two adjacent display sub-areas, the area of ​​the first capacitor plate in the display sub-area close to the second frame area is smaller than the area of ​​the first capacitor plate in the display sub-area far from the second frame area; Alternatively, in the same storage capacitor, the area of ​​the second capacitor plate is smaller than the area of ​​the first capacitor plate; Along the first direction, in two adjacent display sub-areas, the area of ​​the second capacitor plate in the display sub-area close to the second frame area is smaller than the area of ​​the second capacitor plate in the display sub-area far from the second frame area; Alternatively, in the same storage capacitor, the area of ​​the second capacitor plate is equal to the area of ​​the first capacitor plate; Along the first direction, in two adjacent display sub-areas, the area of ​​the second capacitor plate in the display sub-area close to the second border area is smaller than the area of ​​the second capacitor plate in the display sub-area away from the second border area; and the area of ​​the first capacitor plate in the display sub-area close to the second border area is smaller than the area of ​​the first capacitor plate in the display sub-area away from the second border area.

9. The display panel according to claim 1, characterized in that: The pixel circuit also includes a driving transistor and a data writing transistor; A first electrode of the storage capacitor is electrically connected to a control electrode of the driving transistor, and a second electrode of the storage capacitor is connected to a first power line; The data writing transistor is connected between the data line and the driving transistor, the control electrode of the data writing transistor is connected to the first scanning line, and the data writing transistor is used to respond to the first scanning signal on the first scanning line and transmit the data voltage on the data line to the control electrode of the driving transistor; Preferably, the pixel circuit further includes a threshold compensation transistor; The data writing transistor is connected between the data line and the first electrode of the driving transistor; The threshold compensation transistor is connected between the control electrode of the driving transistor and the second electrode of the driving transistor, the control electrode of the threshold compensation transistor is connected to the first scanning line, and the threshold compensation transistor is used to respond to the first scanning signal on the first scanning line to perform threshold compensation on the driving transistor; Preferably, the pixel circuit further includes a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the initialization signal line and the control electrode of the driving transistor; the second initialization transistor is connected between the initialization signal line and the first electrode of the light-emitting element corresponding to the pixel circuit; the control electrode of the first initialization transistor is connected to the second scanning line, and the control electrode of the second initialization transistor is connected to the third scanning line; the first initialization transistor is used to respond to the second scanning signal on the second scanning line to initialize the control electrode of the driving transistor; The second initialization transistor is used to respond to the third scanning signal on the third scanning line to initialize the first electrode of the light emitting element; the second electrode of the light emitting element is connected to the second power line; Preferably, the pixel circuit also includes a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor is connected between the first power line and the first electrode of the driving transistor, and the second light-emitting control transistor is connected between the second electrode of the driving transistor and the first electrode of the light-emitting element; the control electrode of the first light-emitting control transistor and the control electrode of the second light-emitting control transistor are connected to a light-emitting control signal line, and the first light-emitting control transistor and the second light-emitting control transistor are used to control whether the driving current generated by the driving transistor is transmitted to the light-emitting element.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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