Display panel and method for manufacturing display panel

Abstract

A display panel and a method for manufacturing the same are provided. The display panel includes a base layer, a pixel defining film disposed on the base layer and including a light-emitting opening portion, a dam disposed on the pixel defining film, having conductivity and including a dam opening portion overlapping the light-emitting opening portion, and an anode disposed in the light-emitting opening portion and including an anode, a light emitting element including an anode, an intermediate layer disposed on the anode, and a cathode disposed on the intermediate layer, an auxiliary electrode disposed on the cathode and connected to the cathode and the dam, and an encapsulation layer covering the light emitting element. The refractive index of the auxiliary electrode is smaller than or equal to that of the packaging layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0168508, filed on November 28, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] Embodiments relate to a display device, and more particularly to a display panel having improved display quality and a display device including the display panel. Background art

[0004] Display devices (such as televisions, monitors, smartphones, and tablet computers) that provide images to a user include a display panel that displays an image. As the display panel, various display panels such as a liquid crystal display panel, an organic light - emitting display panel, an electro - wetting display panel, and an electrophoretic display panel have been developed.

[0005] The organic light - emitting display panel may include an anode, a cathode, and a light - emitting pattern. The light - emitting pattern may be separated for each light - emitting region, and the cathode may supply a common voltage to each light - emitting region. Summary of the invention

[0006] Embodiments provide a display panel capable of improving display quality and including a light - emitting element formed without using a metal mask, and a method for manufacturing the display panel.

[0007] However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0008] Embodiments provide a display panel including a base layer, a pixel - defining film disposed on the base layer and including a light - emitting opening portion, a dam disposed on the pixel - defining film, having conductivity, and including a dam opening portion overlapping the light - emitting opening portion, a light - emitting element disposed in the light - emitting opening portion and including an anode, an intermediate layer disposed on the anode, and a cathode disposed on the intermediate layer, an auxiliary electrode disposed on the cathode and connected to the cathode and the dam, and a encapsulation layer covering the light - emitting element. The refractive index of the auxiliary electrode may be less than or equal to the refractive index of the encapsulation layer.

[0009] In an embodiment, the auxiliary electrode may include a transparent conductive oxide (TCO).

[0010] In an embodiment, the auxiliary electrode may include indium tin oxide (ITO).

[0011] In an embodiment, the auxiliary electrode may further include a Group 2 element.

[0012] In an embodiment, the content of the Group 2 element included in the auxiliary electrode may be in the range of about 1 at% to about 5 at%.

[0013] In an embodiment, the content of the Group 2 element included in the auxiliary electrode may be in the range of about 1 at% to about 3 at%.

[0014] In an embodiment, the auxiliary electrode may have a thickness in the range of about 100 angstroms to about 1000 angstroms In an embodiment, the refractive index of the auxiliary electrode may be about 1.9 or less.

[0015] In an embodiment, the auxiliary electrode may have an amorphous structure.

[0016] In an embodiment, in cross-section, the dam may have an undercut shape. The dam may include a lower layer containing a conductive material and an upper layer disposed on the lower layer, and the auxiliary electrode may extend along the inner surface of the lower layer.

[0017] In an embodiment, the cathode may be in contact with the inner surface of the lower layer, and the auxiliary electrode may extend via the end of the cathode to be in contact with the inner surface.

[0018] In an embodiment, the size of the region where the auxiliary electrode contacts the inner surface of the dam may be larger than the size of the region where the cathode contacts the inner surface of the dam.

[0019] In an embodiment, the display panel may include a base layer, a pixel defining film disposed on the base layer and including a light-emitting opening portion, a dam disposed on the pixel defining film, having conductivity and including a dam opening portion overlapping the light-emitting opening portion, a light-emitting element disposed in the light-emitting opening portion and including an anode, an intermediate layer disposed on the anode, and a cathode disposed on the intermediate layer, and an auxiliary electrode disposed on the cathode and connected to each of the cathode and the dam. The auxiliary electrode may include indium tin oxide (ITO) doped with a Group 2 element.

[0020] In an embodiment, the display panel may further include a encapsulation layer covering the light-emitting element, and the refractive index of the auxiliary electrode may be less than or equal to the refractive index of the encapsulation layer.

[0021] In an embodiment, the Group 2 element may include at least one of magnesium (Mg) and calcium (Ca).

[0022] In an embodiment, the Group 2 element may include at least one of magnesium (Mg) and calcium (Ca).

[0023] In an embodiment, a method for manufacturing a display panel may include: providing a preliminary display panel including a base layer, an anode disposed on the base layer, and a preliminary pixel defining film disposed on the base layer and covering the anode; forming a dam disposed on the preliminary pixel defining film and including a dam opening portion; forming a pixel defining film by patterning the preliminary pixel defining film to form a light-emitting opening portion overlapping with the dam opening portion and exposing at least a part of the anode; forming a light-emitting layer, a cathode disposed on the light-emitting layer, and a preliminary auxiliary electrode in contact with the dam in the dam opening portion; forming an auxiliary electrode by doping the preliminary auxiliary electrode with a Group 2 element; and forming a encapsulation layer covering the dam opening portion and having a refractive index greater than or equal to that of the auxiliary electrode.

[0024] In an embodiment, the light-emitting layer and the cathode may be formed by a thermal evaporation method, and the auxiliary electrode may be formed by a method different from that of the cathode.

[0025] In an embodiment, the auxiliary electrode may be formed by a sputtering process.

[0026] In an embodiment, the preliminary auxiliary electrode may be doped with a Group 2 element such that the content of the Group 2 element included in the auxiliary electrode may be in the range of about 1 at% to about 5 at%.

[0027] In an embodiment, forming the dam may include: forming a first layer on the preliminary pixel defining film; forming a second layer on the first layer; a first etching for patterning the first layer and the second layer such that a first pattern can be formed; and a second etching for performing patterning such that an undercut can be formed in the first pattern. Description of the Drawings

[0028] The drawings are included to provide a further understanding of the present invention, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate embodiments and are used together with the description to explain the principles of the present invention. In the drawings:

[0029] Figure 1A is a schematic perspective view of a display device according to an embodiment;

[0030] Figure 1B is an exploded schematic perspective view of a display device according to an embodiment;

[0031] Figure 2 is a schematic cross-sectional view of a display module according to an embodiment;

[0032] Figure 3 is a schematic plan view of a display panel according to an embodiment;

[0033] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0034] Figure 5 is an enlarged schematic plan view of a portion of a display panel according to an embodiment;

[0035] Figure 6 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0036] Figure 7 is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0037] Figure 8 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0038] Figure 9 is an enlarged schematic cross-sectional view of a portion of a display panel according to an embodiment; and

[0039] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 10G 、 Figure 10H 、 Figure 10I and Figure 10J are schematic cross-sectional views showing some of the operations of a method for manufacturing a display panel according to an embodiment. Detailed Description

[0040] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of the apparatus or method disclosed herein. However, it will be apparent that the various embodiments may be practiced without these specific details or in the presence of one or more equivalent arrangements. Here, the various embodiments need not be exclusive and need not limit the present disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0041] Unless otherwise stated, the illustrated embodiments are to be understood as providing features of the present invention. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the scope of the present invention.

[0042] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, scale, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Also, like reference numerals denote like elements.

[0043] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly" on, "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connected" can refer to physical, electrical, and / or fluid connection with or without intervening elements. Further, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, Y-axis, and Z-axis), and can be interpreted in a broader sense. For example, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be understood to mean only A, only B, or any combination of A and B. Also, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed below could be termed the second element.

[0045] Spatial relative terms, such as "beneath", "below", "under", "lower", "above", "upper", "over", "higher", "side" (e.g., as in "sidewall"), and like terms, may be used herein for descriptive purposes and thus to describe the relationship of one element to another as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an orientation above and below. Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0046] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms. Further, when the terms "comprise", "comprising", "include", and / or "including" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and similar terms are used as approximate terms and not as terms of degree, and thus are utilized to account for the inherent variations in measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0047] The various embodiments are described herein with reference to sectional views and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of the regions shown, but will include deviations in shape resulting from, for example, manufacturing. In this manner, the regions shown in the figures are essentially schematic, and the shapes of these regions may not reflect the actual shape of the regions of the device and thus are not necessarily intended to be limiting.

[0048] Hereinafter, a display panel and a method for manufacturing the display panel according to an embodiment will be described with reference to the accompanying drawings.

[0049] Figure 1A is a schematic perspective view of a display device according to an embodiment. Figure 1B is an exploded schematic perspective view of a display device according to an embodiment.

[0050] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an outdoor billboard. For example, the display device DD may be a small electronic device and a medium-sized electronic device such as a personal computer, a notebook computer, a personal digital assistant, a vehicle navigation unit, a game console, a smart phone, a tablet computer, and a camera. However, the foregoing devices are examples, and the display device DD may also be implemented as various display devices. Figure 1A and Figure 1B show a smart phone as an example of the display device DD.

[0051] Referring to Figure 1A and Figure 1B , the display device DD may display an image IM in a third direction DR3 on a display surface FS parallel to each of a first direction DR1 and a second direction DR2. The image IM may include not only a moving image but also a still image. Figure 1A show a clock window and an icon as examples of the image IM. The display surface FS for displaying the image IM may correspond to the front surface of the display device DD.

[0052] In an embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of each component may be defined based on the direction in which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. For example, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions. The term "in a plane" or "in a plan view" as used herein may mean a state when observed in the third direction DR3.

[0053] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form the appearance of the display device DD.

[0054] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define the display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a border area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or higher.

[0055] The border area BZA may be an area having a relatively low light transmittance compared to the transmissive area TA. The border area BZA may define the shape of the transmissive area TA. The border area BZA may be adjacent to and surround the transmissive area TA. However, this is shown as an example, and the border area BZA of the window WP may be omitted. The window WP may include at least one functional layer among an anti-fingerprint layer, a hard coat, and an anti-reflection layer, and is not limited to any embodiment.

[0056] The display module DM may be disposed below the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM may be displayed on the display surface IS of the display module DM and may be externally visible to the user through the transmissive area TA.

[0057] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an area covered by the border area BZA and may not be externally visible.

[0058] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a selected internal space. The display module DM may be accommodated in the internal space.

[0059] The housing HAU may include a material having a relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates each including or made of glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the components of the display module DM accommodated in the internal space from external shock.

[0060] Figure 2 is a schematic cross-sectional view of a display module according to an embodiment.

[0061] Referring to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. For example, the display device DD according to an embodiment (see Figure 1A ) may further include a protection member disposed on the bottom surface of the display panel DP, or an anti-reflection member and / or a window member disposed on the top surface of the input sensor INS.

[0062] The display panel DP may be a light-emitting display panel. However, this is an example, and the display panel DP is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0063] The display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the base layer BL. The input sensor INS may be disposed (directly disposed) on the thin film encapsulation layer TFE. In the present disclosure, "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0064] The base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate and include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, or the like. The same / similar display area DA and non-display area NDA as described with reference to Figure 1B may be defined in the base layer BL.

[0065] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The at least one insulating layer may include at least one inorganic layer and / or at least one organic layer. The circuit elements may include signal lines, driving circuits of pixels, and the like.

[0066] The display element layer DP-OLED may include dams (or partition walls) and light-emitting elements (e.g., organic light-emitting diodes). The light-emitting elements may include anodes, intermediate layers, and cathodes.

[0067] The thin film encapsulation layer TFE may include a plurality of thin films. Some of the plurality of thin films may be arranged to improve optical efficiency, and some of the plurality of thin films may be arranged to protect the organic light-emitting diodes.

[0068] The input sensor INS may obtain coordinate information of an external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a conductive layer having a single-layer structure or a multi-layer structure. For example, the input sensor INS may include an insulating layer having a single-layer structure or a multi-layer structure. The input sensor INS may detect an external input using a capacitive method. However, this is an example, and the embodiments are not limited thereto. For example, in an embodiment, the input sensor INS may detect an external input by using an electromagnetic induction method or a pressure detection method. In another embodiment, the input sensor INS may be omitted.

[0069] Figure 3 is a schematic plan view of a display panel according to an embodiment.

[0070] Reference Figure 3 As shown in Figure 3 , a display area DA and a non-display area NDA surrounding the display area DA can be defined in the display panel DP. The display area DA and the non-display area NDA can be divided according to whether pixels PX are arranged. The pixels PX can be arranged in the display area DA. The scan driver SDV, the data driver, and the emission driver EDV can be arranged in the non-display area NDA. The data driver can be a part of the circuit included in the driving chip DIC.

[0071] The display panel DP can include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, a first control line CSL1, a second control line CSL2, a driving voltage line PL, and pads PD. For example, each of m and n is a natural number of 2 or greater.

[0072] Multiple pixels PX can be respectively connected to the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, the black scan lines GBL1 to GBLm, the emission control lines ECL1 to ECLm, and the data lines DL1 to DLn.

[0073] The initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, and the black scan lines GBL1 to GBLm can extend in a first direction DR1 to be electrically connected to the scan driver SDV. The data lines DL1 to DLn can extend in a second direction DR2 to be electrically connected to the driving chip DIC. The emission control lines ECL1 to ECLm can extend in the first direction DR1 to be electrically connected to the emission driver EDV.

[0074] The driving voltage line PL can include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 can be arranged on different layers from each other. The driving voltage line PL can supply a driving voltage to each of the pixels PX.

[0075] The first control line CSL1 can be connected to the scan driver SDV. The second control line CSL2 can be connected to the emission driver EDV.

[0076] The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 can be electrically connected to the pad PD. The flexible circuit film FCB can be electrically connected to the pad PD through the anisotropic conductive adhesive layer. The pad PD can be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD can be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1, and the second control line CSL2 (or the driving voltage line PL, the first control line CSL1, the second control line CSL2, and the driving chip DIC), respectively.

[0077] For example, the pad PD can further include an input pad. The input pad can be a pad for connecting the flexible circuit film FCB to the input sensor INS (see Figure 2 ). However, the embodiment is not limited thereto, and the input pad can be arranged in the input sensor INS (see Figure 2 ) to be connected to a circuit board separate from the pad PD. In another example, the input sensor INS (see Figure 2 ) can be omitted, and the pad PD may not further include an input pad.

[0078] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0079] As an example, Figure 4 shows an equivalent circuit of the pixel PXij among a plurality of pixels PX (see Figure 3 ). Since the pixels PX (see Figure 3 ) have the same circuit structure, the circuit structure of the pixel PXij will be described, and the specific description of the other pixels PX (see Figure 3 ) will be omitted.

[0080] Referring to Figure 3 and Figure 4 , the pixel PXij can be connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th emission control line ECLj among the emission control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. For example, i can be an integer from 1 to n, and j can be an integer from 1 to m.

[0081] The pixel PXij may include a light-emitting element ED and a pixel circuit PDC. The light-emitting element ED may be a light-emitting diode. As an example according to an embodiment, the light-emitting element ED may be an organic light-emitting diode including an organic light-emitting layer, but the embodiment is not limited thereto. The pixel circuit PDC may control the amount of current flowing through the light-emitting element ED in response to the i-th data signal Di. The light-emitting element ED may emit light having a selected brightness corresponding to the amount of current supplied from the pixel circuit PDC.

[0082] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. The configuration of the pixel circuit PDC according to an embodiment is not limited to Figure 4 the embodiment shown in Figure 4 The pixel circuit PDC shown in

[0083] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor including a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor including an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0084] For example, the first transistor T1 that directly affects the brightness of the light-emitting element ED may include a semiconductor layer made of polysilicon having high reliability, thereby realizing a display device with high resolution. Since the oxide semiconductor has a high carrier mobility and a low leakage current, although the driving time is long, the voltage drop may not be large. For example, even during low-frequency driving, the change in the color of the image due to the voltage drop may not be large, and thus low-frequency driving can be achieved. Since the oxide semiconductor has the advantage of a low leakage current as described above, at least one of the third transistor T3 and the fourth transistor T4 each connected to the gate electrode of the first transistor T1 may be implemented as an oxide semiconductor to prevent leakage current that may flow to the gate electrode and also reduce power consumption.

[0085] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors, and some of the remainder may be n-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors, and the third transistor T3 and the fourth transistor T4 may be n-type transistors.

[0086] The configuration of the pixel circuit PDC according to the embodiment is not limited to Figure 4 the embodiment shown in Figure 4 The pixel circuit PDC shown in

[0087] is only an example, and the configuration of the pixel circuit PDC can be modified and implemented. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors or n-type transistors. In another example, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be p-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be n-type transistors. Figure 1A and Figure 1B ) may have a voltage level corresponding to the image signal input to the display device DD (see

[0088] The first driving voltage line VL1 and the second driving voltage line VL2 may transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. For example, the first initialization voltage line VL3 and the second initialization voltage line VL4 may transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij, respectively.

[0089] The first transistor T1 may be connected between a first driving voltage line VL1 that receives a first driving voltage ELVDD and a light-emitting element ED. The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light-emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to an end portion (e.g., a first node N1) of a first capacitor Cst. The first transistor T1 may receive an i-th data signal Di transmitted by an i-th data line DLi according to a switching operation of a second transistor T2, and then supply a driving current to the light-emitting element ED.

[0090] The second transistor T2 may be connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to a j-th write scan line GWLj. The second transistor T2 may be turned on in response to a j-th write scan line signal GWj received through the j-th write scan line GWLj, and then transmit the i-th data signal Di received from the i-th data line DLi to the first electrode of the first transistor T1. A second capacitor Cbst may have one end portion connected to the third electrode of the second transistor T2 and the other end portion connected to the first node N1.

[0091] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to a j-th compensation scan line GCLj. The third transistor T3 may be turned on in response to a j-th compensation scan signal GCj received through the j-th compensation scan line GCLj, and then connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other so that the first transistor T1 may be diode-connected. A third capacitor Nbst may have one end portion connected to the third electrode of the third transistor T3 and the other end portion connected to the first node N1.

[0092] The fourth transistor T4 may be connected between a first initialization voltage line VL3 to which a first initialization voltage VINT is applied and a first node N1. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VL3 that transmits the first initialization voltage VINT, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 may be turned on in response to a j-th initialization scan signal GI j received through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0093] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light-emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0094] The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously in response to a j-th emission control signal EMj received through the j-th emission control line ECLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be compensated by the diode-connected first transistor T1 and then transmitted to the light-emitting element ED through the sixth transistor T6.

[0095] The seventh transistor T7 may include a first electrode connected to a second initialization voltage line VL4 to which a second initialization voltage VAINT is transmitted, a second electrode connected to the second electrode (or the second node N2) of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The voltage level of the second initialization voltage VAINT may be less than or equal to the voltage level of the first initialization voltage VINT.

[0096] The first capacitor Cst may have one end connected to the third electrode of the first transistor T1 and the other end connected to the first driving voltage line VL1. The cathode of the light-emitting element ED may be connected to a second driving voltage line VL2 that transmits a second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level smaller than the voltage level of the first driving voltage ELVDD.

[0097] Figure 5 is an enlarged schematic plan view of a part of a display area of a display panel according to an embodiment. Figure 5Shows a plan view of the display module when viewed on the display surface of the display module, and shows the arrangement of a plurality of light-emitting regions.

[0098] Referring to Figure 5 , the display area DA may include a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B, and a peripheral region NPXA surrounding the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively correspond to regions where light provided from the light-emitting elements is emitted. The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be divided according to the color of light emitted to the outside in the direction toward the display module DM (see Figure 2 ).

[0099] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may respectively provide light having first to third colors different from each other. For example, the light having the first color may be red light, the light having the second color may be green light, and the light having the third color may be blue light. However, examples of the light having the first to third colors are not limited to the foregoing examples.

[0100] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be defined as a region where the top surface of the anode is exposed through a light-emitting opening portion described later. The peripheral region NPXA may set the boundaries of each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, and prevent color mixing between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0101] Each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be formed into a plurality of them having a selected arrangement shape and repeatedly arranged within the display area DA. For example, the first light-emitting region PXA-R and the third light-emitting region PXA-B may be alternately arranged in a first direction DR1 to form a "first group". The second light-emitting region PXA-G may be arranged in the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in a plurality, and the "first group" and the "second group" may be alternately arranged in a second direction DR2.

[0102] A second light-emitting region PXA-G may be arranged to be spaced apart from a first light-emitting region PXA-R or a third light-emitting region PXA-B in a fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0103] Figure 5 Examples of the arrangement shapes of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B are shown. However, the embodiments are not limited thereto, and the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be arranged in various shapes. In an embodiment, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have the arrangement shapes as Figure 5 shown in In another example, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a stripe arrangement shape or a diamond (Diamond ) arrangement shape.

[0104] In a plan view, each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have various shapes. For example, each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have a shape such as a polygon, a circle, or an oval shape. As an example, Figure 5 Examples of the first light-emitting region PXA-R and the third light-emitting region PXA-B each having a square (or diamond) shape and the second light-emitting region PXA-G having an octagon shape in a plan view are shown.

[0105] In a plan view, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have the same shape, or at least some of them may have different shapes from each other. As an example, Figure 5 Examples of the first light-emitting region PXA-R and the third light-emitting region PXA-B having the same shape and the second light-emitting region PXA-G having a different shape from the first light-emitting region PXA-R and the third light-emitting region PXA-B in a plan view are shown.

[0106] In a plan view, at least some of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have different surface areas. In an embodiment, the surface area of the first light-emitting region PXA-R that emits red light may be greater than the surface area of the second light-emitting region PXA-G that emits green light and less than the surface area of the third light-emitting region PXA-B that emits blue light. However, the magnitude relationship between the surface areas of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B according to the color of the emitted light is not limited thereto, and may vary according to the design of the display module DM (see Figure 2 ). However, the embodiment is not limited thereto, and in a plan view, the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have the same surface area.

[0107] The shapes, surface areas, arrangements, and similar characteristics of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B of the display module DM (see Figure 2 ) according to an embodiment may be variously designed according to the color of the emitted light or the size or configuration of the display module DM (see Figure 2 ), and are not limited to the embodiment shown in Figure 5 .

[0108] Figure 6 is a schematic cross-sectional view of a part of a display panel according to an embodiment. Figure 7 is an enlarged schematic view of a part of a display panel according to an embodiment. Figure 6 is a schematic cross-sectional view taken along line I-I' in Figure 5 of a display panel according to an embodiment, and Figure 7 is an enlarged schematic view showing the region AA' in Figure 6 . In the embodiment to be described with reference to Figure 6 and Figure 7 , reference is made to Figure 5 , and components designated by similar reference numerals or symbols are not described.

[0109] Figure 6 shows an enlarged schematic view of one light-emitting region PXA in the display area DA (see Figure 5 ), and the light-emitting region PXA in Figure 6 may correspond to any one of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B in Figure 5 .

[0110] Refer to Figure 6, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0111] The display panel DP may include an insulating layer, a semiconductor pattern, a conductive pattern, signal lines, and the like. The insulating layer, semiconductor layer, and conductive layer may be formed by a coating process, a deposition process, or a similar process. Subsequently, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by a photolithography process and an etching process. The semiconductor pattern, conductive pattern, signal lines, and the like included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by such processes.

[0112] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and connection electrodes CNE1 and CNE2.

[0113] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately with each other.

[0114] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the embodiment is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 6 Only a part of the semiconductor pattern is shown, and the semiconductor pattern may be further disposed in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ). The semiconductor pattern may be arranged according to specific rules throughout the plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ). The semiconductor pattern may have different electrical properties depending on whether the semiconductor pattern is doped. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an n-type dopant or a p-type dopant. The p-type transistor may include a first region doped with a p-type dopant.

[0115] The first region may have higher conductivity than the second region and may basically be used as an electrode or a signal line. The second region may basically correspond to the active part (or channel) of the transistor. For example, a part of the semiconductor pattern may be the active part of the transistor, another part may be the source or drain of the transistor, and still another part may be a conductive region.

[0116] The source S, active part A, and drain D of the transistor TR1 may be provided from the semiconductor pattern.Figure 6 Shows a part of the signal transmission region SCL provided from a semiconductor pattern. For example, in a plan view, the signal transmission region SCL may be connected to the drain D of the transistor TR1.

[0117] The first insulating layer 10 to the fifth insulating layer 50 may be disposed on the buffer layer BFL. Each of the first insulating layer 10 to the fifth insulating layer 50 may be an inorganic layer or an organic layer.

[0118] The first insulating layer 10 may be disposed on the buffer layer BFL. The gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0119] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through the contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0120] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through the contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0121] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light-emitting element ED, a pixel defining film PDL, a dam (or partition wall) PW, and a dummy pattern DMP.

[0122] In an embodiment, the light-emitting element ED may include an anode AE (or a first electrode), a conductive pattern, a light-emitting pattern EP, and a cathode CE (or a second electrode).

[0123] The anode AE may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE may have conductivity. For example, the anode AE may be made of various materials such as a metal, a transparent conductive oxide (TCO), or a conductive polymer material as long as the anode AE can have conductivity. The anode AE may have a single-layer structure or a multi-layer structure.

[0124] In an embodiment, the anode AE may include three layers respectively including indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO). The anode AE may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 formed through and defining (or forming) in the fifth insulating layer 50. Accordingly, the anode AE may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and electrically connected to corresponding circuit elements.

[0125] According to an embodiment, the display panel DP may further include a sacrificial pattern SP. The sacrificial pattern SP may be disposed between the anode AE and the pixel defining layer PDL. A sacrificial opening portion OP-S exposing a portion of the top surface of the anode AE may be defined (or formed) in the sacrificial pattern SP. The sacrificial opening portion OP-S may overlap with a light-emitting opening portion OP-E to be described later.

[0126] The pixel defining layer PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light-emitting opening portion OP-E may be defined (or formed) in the pixel defining layer PDL. The light-emitting opening portion OP-E may correspond to the anode AE, and the pixel defining layer PDL may expose at least a portion of the anode AE through the light-emitting opening portion OP-E.

[0127] For example, the light-emitting opening portion OP-E may correspond to the sacrificial opening portion OP-S of the sacrificial pattern SP. According to an embodiment, in a cross-section, the top surface of the anode AE may be spaced apart from the pixel defining layer PDL by the sacrificial pattern SP therebetween, and accordingly, the anode AE may be protected from damage in the process of forming the light-emitting opening portion OP-E.

[0128] The width of the light-emitting opening portion OP-E in one direction may be smaller than the width of the sacrificial opening portion OP-S in that direction. The direction used herein may mean a direction perpendicular to the thickness direction (i.e., the third direction DR3) of the display panel DP. The inner surface of the pixel defining layer PDL defining the light-emitting opening portion OP-E may be adjacent (or closer) to the central portion of the anode AE than the inner surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S. However, the embodiment is not limited thereto, and the inner surface of the sacrificial pattern SP defining the sacrificial opening portion OP-S may be substantially aligned with the inner surface of the pixel defining layer PDL defining the corresponding light-emitting opening portion OP-E. For example, the light-emitting region may be considered as the region of the anode AE exposed from the corresponding sacrificial opening portion OP-S. In another example, the sacrificial pattern SP may be omitted.

[0129] The pixel defining layer PDL may include an inorganic insulating material. For example, the pixel defining layer PDL may include silicon nitride (SiN x)。The pixel defining film PDL can be disposed between the anode AE and the dam PW to block the electrical connection between the anode AE and the dam PW.

[0130] The dam PW can be disposed on the pixel defining film PDL. A dam opening portion (or a partition wall opening portion) OP-P can be defined (or formed) in the dam PW. The dam opening portion OP-P can overlap with the light emitting opening portion OP-E and expose at least a part of the anode AE.

[0131] In cross-section, the dam PW can have an undercut shape. The dam PW can include multiple layers stacked in sequence, and at least one of the multiple layers can be recessed from the layer stacked adjacent thereto. Accordingly, the dam PW can include a tip portion TP.

[0132] In an embodiment, the dam PW can include a first dam layer (or a first partition wall layer) L1 and a second dam layer (or a second partition wall layer) L2. The first dam layer L1 can be disposed on the pixel defining film PDL, and the second dam layer L2 can be disposed on the first dam layer L1. As Figure 6 shown, the first dam layer L1 can have a thickness greater than that of the second dam layer L2, but the embodiment is not limited thereto. The drawing only shows the state of the dam PW in which the first dam layer L1 and the second dam layer L2 are disposed, but the embodiment is not limited thereto. For example, a third dam layer can be disposed on the second dam layer L2, and the dam PW is not limited to any one embodiment. For example, the third dam layer can have a thickness greater than that of the second dam layer L2, but the embodiment is not limited thereto.

[0133] The dam opening portion OP-P defined (or formed) in the dam PW can include a first region A1 and a second region A2. The first dam layer L1 can have a first inner surface S-L1 defining the first region A1 of the dam opening portion OP-P. The second dam layer L2 can have a second inner surface S-L2 defining the second region A2. In cross-section, the second inner surface S-L2 of the second dam layer L2 can be adjacent (or close) to the central portion of the anode AE compared to the first inner surface S-L1 of the first dam layer L1. The first inner surface S-L1 can be recessed from the second inner surface S-L2 in a direction away from the central portion of the anode AE.

[0134] The first region A1 can have a width different from that of the second region A2. The width of the first region A1 can be greater than the width of the second region A2. For example, the second region A2 of the dam opening portion OP-P can be a region defining the tip portion TP. For example, the light emitting region PXA can be considered as the region of the anode AE exposed from the second region A2 of the corresponding dam PW.

[0135] The first dam layer L1 may be conductive. The first dam layer L1 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0136] The second dam layer L2 may be disposed on the first dam layer L1. The second dam layer L2 may include a material having an etch selectivity different from that of the first dam layer L1. As an example, the second dam layer L2 may have a lower reactivity to an etchant than the first dam layer L1.

[0137] In an embodiment, with respect to the light-emitting region PXA, the first dam layer L1 may be relatively recessed with respect to the second dam layer L2. For example, the first dam layer L1 may be undercut with respect to the second dam layer L2. A portion of the second dam layer L2 that protrudes by a protrusion length D-TP from the first dam layer L1 toward the light-emitting region PXA may define (or form) a tip portion TP in the dam PW. Figure 7 in) may define (or form) a tip portion TP in the dam PW.

[0138] The second dam layer L2 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0139] In another embodiment, the second dam layer L2 may include an insulating material. For example, the second dam layer L2 may include an inorganic insulating material and may include, for example, silicon nitride (SiN x ) or silicon oxide (SiO x ). However, this is shown as an example, and according to an embodiment, the second dam layer L2 may be omitted in the dam PW.

[0140] In an embodiment, the second inner surface S-L2 of the second dam layer L2 may be adjacent (or close) to the central portion of the anode AE compared to the first inner surface S-L1 of the first dam layer L1. For example, the first inner surface S-L1 of the first dam layer L1 may be arranged to be recessed from the second inner surface S-L2 of the second dam layer L2 in a direction away from the central portion of the anode AE. Accordingly, the second dam layer L2 may have a bottom surface exposed from the first dam layer L1.

[0141] In cross-section, the dam PW may have an undercut shape. As described above, the undercut shape of the dam PW may be defined by a stepped portion between the first inner surface S-L1 of the first dam layer L1 and the second inner surface S-L2 of the second dam layer L2. The shape of the dam PW in cross-section is not limited thereto. For example, the dam PW may have various shapes, such as an inverted conical shape or an overhang, and is not limited to any one embodiment.

[0142] Figure 6 An example is shown in which each of the first inner surface S-L1 of the first dam layer L1 and the second inner surface S-L2 of the second dam layer L2 is perpendicular to the top surface of the fifth insulating layer 50. However, the embodiment is not limited thereto.

[0143] The light-emitting pattern EP may be disposed on the anode AE. The light-emitting pattern EP may be patterned by each of the tip portions TP defined (or formed) in the dam PW. At least a part of the light-emitting pattern EP may be disposed in the light-emitting opening portion OP-E. The entire light-emitting pattern EP may be disposed in the light-emitting opening portion OP-E, or the light-emitting pattern EP may be disposed not only in each of the plurality of light-emitting opening portions OP-E but also in each of the plurality of dam opening portions OP-P. In an embodiment including the sacrificial pattern SP, the light-emitting pattern EP may also be disposed in the sacrificial opening portion OP-S.

[0144] The light-emitting pattern EP may include a light-emitting layer containing a light-emitting material. The light-emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE and the light-emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light-emitting layer. The light-emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0145] The cathode CE may be disposed on the light-emitting pattern EP. The cathode CE may be patterned by each of the tip portions TP defined (or formed) in the dam PW. At least a part of the cathode CE may be disposed in the dam opening portion OP-P. In an embodiment, depending on the thickness of the light-emitting pattern EP or the thickness of the pixel defining film PDL, a part of the cathode CE may also be disposed in the light-emitting opening portion OP-E.

[0146] The cathode CE can have electrical conductivity. For example, the cathode CE can be made of various materials such as metals, transparent conductive oxides (TCOs), or conductive polymer materials, as long as the cathode CE can have electrical conductivity.

[0147] Figure 6 The case where the end of the cathode CE contacts the dam PW is shown, but the embodiment is not limited thereto. For example, the end of the cathode CE can be spaced apart from the dam PW and is not limited to any one embodiment.

[0148] The auxiliary electrode SE can be disposed on the light-emitting element ED. For example, the auxiliary electrode SE can be disposed on the cathode CE. A part of the auxiliary electrode SE can be disposed in the dam opening portion OP-P. The auxiliary electrode SE can extend along the first inner surface S-L1 of the first dam layer L1. For example, the auxiliary electrode SE can extend in contact with the first inner surface S-L1 of the first dam layer L1. The auxiliary electrode SE can cover the end portion (e.g., the opposite end portion) of the light-emitting pattern EP and the end portion (e.g., the opposite end portion) of the cathode CE.

[0149] The auxiliary electrode SE can be in contact with the first inner surface S-L1 of the first dam layer L1 and in contact with the cathode CE. For example, the auxiliary electrode SE can be electrically connected to the dam PW and the cathode CE. The dam PW can receive the second driving voltage ELVSS (see Figure 4 ), and the auxiliary electrode SE can be electrically connected to the dam PW to receive the second driving voltage ELVSS (see Figure 4 ). Accordingly, the cathode CE electrically connected to the auxiliary electrode SE can receive the second driving voltage ELVSS.

[0150] Referring to the drawings, the auxiliary electrode SE can extend via the end of the cathode CE to be in contact with the first inner surface S-L1 of the first dam layer L1. The drawing shows a state where the auxiliary electrode SE extends via the end CE-E of the cathode CE to be in contact with the first inner surface S-L1 of the first dam layer L1 in a state where the cathode CE is in contact with the first inner surface S-L1 of the first dam layer L1. However, the embodiment is not limited thereto. For example, in a state where the cathode CE is spaced apart from the first inner surface S-L1 of the first dam layer L1, the auxiliary electrode SE can also extend via the end of the cathode CE to be in contact with the first inner surface S-L1 of the first dam layer L1 and is not limited to any one embodiment.

[0151] The auxiliary electrode SE may have a step coverage higher than that of the cathode CE. The size of the region where the auxiliary electrode SE contacts the first inner surface S-L1 of the first dam layer L1 may be larger than the size of the region where the cathode CE contacts the first inner surface S-L1 of the first dam layer L1. For example, the degree to which the auxiliary electrode SE extends along the first inner surface S-L1 to contact the first inner surface S-L1 may be greater than the degree to which the cathode CE extends along the first inner surface S-L1 to contact the first inner surface S-L1. For example, unlike the cathode CE, the auxiliary electrode SE may also contact the second dam layer L2.

[0152] The auxiliary electrode SE may have a thickness of about 100 angstroms to about 1000 angstroms In another example, the auxiliary electrode SE may have a thickness of about 100 angstroms to about 650 angstroms of thickness.

[0153] The auxiliary electrode SE may be formed into an amorphous structure. Accordingly, etching the auxiliary electrode SE can be easily performed in the wet etching process to be described later.

[0154] The auxiliary electrode SE may have conductivity. According to an embodiment, the cathode CE may be electrically connected to the dam PW through the auxiliary electrode SE without directly contacting the dam PW. Each of the adhesion force between the auxiliary electrode SE and the cathode CE and the adhesion force between the auxiliary electrode SE and the dam PW may be greater than the adhesion force between the cathode CE and the dam PW. Accordingly, the phenomenon in which foreign substances penetrate into the display element layer DP-OLED can be eliminated. This can prevent the light-emitting element ED from being damaged in the process performed after depositing the auxiliary electrode SE, can provide a display element layer DP-OLED with high durability, and can increase the lifespan of the display panel DP.

[0155] For example, the cathode CE and the dam PW may stably contact each other, and even in a state where the cathode CE and the dam PW do not contact each other, the electrical connection between the cathode CE and the dam PW can be reliably established to enhance the stability and reliability of the electrical connection between the cathode CE and the dam PW. Accordingly, the display element layer DP-OLED may have high durability, and the lifespan of the display panel DP can be increased.

[0156] For example, the cathode CE may include silver (Ag), and the dam PW may include aluminum (Al). As the process is performed, an oxide film may be formed on the aluminum (Al) of the dam PW. For example, the auxiliary electrode SE may include a transparent conductive oxide (TCO) to have a higher adhesion force to the dam PW than to the cathode CE.

[0157] The refractive index of the auxiliary electrode SE may have a refractive index less than or equal to that of the thin film encapsulation layer TFE to be described later. In another example, the refractive index of the auxiliary electrode SE may have a refractive index less than or equal to that of the lower inorganic encapsulation pattern LIL to be described later. Since the auxiliary electrode SE has a refractive index less than or equal to that of the thin film encapsulation layer TFE, interference in the propagation direction (or transmission direction) of light can be prevented from occurring between the auxiliary electrode SE and the thin film encapsulation layer TFE. For example, interference in the propagation direction of light can be prevented from occurring between the auxiliary electrode SE and the thin film encapsulation layer TFE so that deterioration of the light transmission characteristics of the light emitting region PXA can be prevented.

[0158] As an example, when the lower inorganic encapsulation pattern LIL includes silicon nitride (SiN x ) to have a refractive index of about 1.9, the refractive index of the auxiliary electrode SE can be about 1.9 or less. For example, the refractive index of the auxiliary electrode SE can be about 1.76 to about 1.89, but the embodiments are not limited thereto. For example, the refractive index of the auxiliary electrode SE can be about 1.8 or less, or the same as the refractive index of the thin film encapsulation layer TFE, and is not limited to any one embodiment.

[0159] The auxiliary electrode SE may include a transparent conductive oxide (TCO). The auxiliary electrode SE may include indium tin oxide (ITO). The auxiliary electrode SE may include indium tin oxide (ITO) doped with a Group 2 element. For example, the Group 2 element may be magnesium (Mg) or calcium (Ca), but the embodiments are not limited thereto. For example, the Group 2 element may include another Group 2 element, and is not limited to any one embodiment. For example, the auxiliary electrode SE may be doped with a plurality of different Group 2 elements. As an example, the auxiliary electrode SE may be doped with both magnesium (Mg) and calcium (Ca), and is not limited to any one embodiment.

[0160] The auxiliary electrode SE may include indium tin oxide (ITO) in which the content of the Group 2 element is about 1 at% to about 5 at%. In another example, the content of the Group 2 element relative to indium tin oxide (ITO) is about 1 at% to about 3 at%. Since the content of the Group 2 element in the auxiliary electrode SE is about 1 at% to about 5 at%, the refractive index of the auxiliary electrode SE can be about 1.76 to about 1.89. For example, since the content of the Group 2 element in the auxiliary electrode SE is about 1 at% to about 3 at%, a rapid increase in resistance during electrical connection between the auxiliary electrode SE and the dam PW can be prevented. For example, the refractive index of the auxiliary electrode SE can be less than or equal to the refractive index of the thin film encapsulation layer TFE as described above.

[0161] According to an embodiment, the display panel DP may further include a cover pattern. The cover pattern may be disposed on the cathode CE. The cover pattern may be patterned by a tip portion TP defined (or formed) in the dam PW. At least a portion of the cover pattern may be disposed in the dam opening portion OP-P.

[0162] The dummy pattern DMP may be disposed on the dam PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be stacked in order in the third direction DR3 on the top surface of the second dam layer L2 of the dam PW.

[0163] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 and the light-emitting pattern EP may include the same material as each other. The first dummy pattern D1 may be formed simultaneously with the light-emitting pattern EP by a single process, and then separated from the light-emitting pattern EP due to the undercut shape of the dam PW.

[0164] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 and the cathode CE may include the same material as each other. The second dummy pattern D2 may be formed simultaneously with the cathode CE by a single process, and then separated from the cathode CE by the undercut shape of the dam PW.

[0165] The third dummy pattern D3 may include a conductive material. For example, the third dummy pattern D3 and the auxiliary electrode SE may include the same material as each other. The third dummy pattern D3 may be formed simultaneously with the auxiliary electrode SE by a single process, and then separated from the auxiliary electrode SE due to the undercut shape of the dam PW.

[0166] In the case where the display element layer DP-OLED further includes a cover pattern, the dummy pattern DMP may further include a fourth dummy pattern. The fourth dummy pattern may include a conductive material. For example, the fourth dummy pattern and the cover pattern may include the same material as each other. The fourth dummy pattern may be formed simultaneously with the cover pattern by a single process, and then separated from the cover pattern due to the undercut shape of the dam PW.

[0167] A dummy opening portion OP-D may be defined (or formed) in the dummy pattern DMP. The dummy opening portion OP-D may overlap with the light-emitting opening portion OP-E. The dummy opening portion OP-D may include a first region to a third region arranged in order in the third direction DR3. The first region AA1 ( Figure 10F ) of the dummy opening portion OP-D may be defined by the inner surface of the first dummy pattern D1, and the second region AA2 (see Figure 10F ) may be defined by the inner surface of the second dummy pattern D2, and the third region AA3 (see Figure 10F)It may be defined by the inner surface of the third dummy pattern D3. In a plan view, each of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a closed line shape surrounding the light-emitting region PXA.

[0168] Figure 6 An example is shown in which the inner surfaces of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 are aligned with the second inner surface S-L2 of the second dam layer L2. However, the embodiments are not limited thereto, and the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may cover the second inner surface S-L2 of the second dam layer L2.

[0169] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0170] The lower inorganic encapsulation pattern LIL may be disposed on the auxiliary electrode SE. The lower inorganic encapsulation pattern LIL may be provided corresponding to the light-emitting opening portion OP-E. The lower inorganic encapsulation pattern LIL may be in direct contact with the auxiliary electrode SE. For example, a portion of the lower inorganic encapsulation pattern LIL may cover the auxiliary electrode SE in the dam opening portion OP-P.

[0171] The lower inorganic encapsulation pattern LIL may include silicon nitride (SiN x ). The lower inorganic encapsulation pattern LIL may have a refractive index of about 1.9 or about 1.89. The lower inorganic encapsulation pattern LIL may have a refractive index greater than or equal to the refractive index of the auxiliary electrode SE described above.

[0172] The organic encapsulation film OL may cover the lower inorganic encapsulation pattern LIL and provide a flat top surface. The upper inorganic encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0173] The lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture / gas, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0174] Figure 8 is a schematic cross-sectional view of a part of a display panel according to an embodiment. Figure 8 is along Figure 5 The schematic cross-sectional view taken along line II-II' in. Figure 8 An enlarged schematic view showing one first light-emitting region PXA-R, one second light-emitting region PXA-G, and one third light-emitting region PXA-B is shown. Figure 6The same / similar description of a light-emitting region PXA in [the context] can be applied to each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0175] Referring to Figure 8 , the display panel DP according to the embodiment may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light-emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, dams PW, auxiliary electrodes SE1, SE2, and SE3, and dummy patterns DMP.

[0176] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided as a plurality of patterns. In the embodiment, the first light-emitting pattern EP1 may provide (or emit) light having a red color, the second light-emitting pattern EP2 may provide (or emit) light having a green color, and the third light-emitting pattern EP3 may provide (or emit) light having a blue color.

[0177] A first light-emitting opening portion OP1-E, a second light-emitting opening portion OP2-E, and a third light-emitting opening portion OP3-E may be defined (or formed) in the pixel defining film PDL. The first light-emitting opening portion OP1-E may expose at least a part of the first anode AE1. The second light-emitting opening portion OP2-E may expose at least a part of the second anode AE2. The third light-emitting opening portion OP3-E may expose at least a part of the third anode AE3.

[0178] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be respectively disposed on the top surfaces of the first anode AE1, the second anode AE2, and the third anode AE3. First sacrificial opening portions OP1-S, second sacrificial opening portions OP2-S, and third sacrificial opening portions OP3-S overlapping with the first light-emitting opening portion OP1-E, the second light-emitting opening portion OP2-E, and the third light-emitting opening portion OP3-E may be respectively defined (or formed) in the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3.

[0179] In an embodiment, first dam opening portions OP1-P, second dam opening portions OP2-P, and third dam opening portions OP3-P that overlap with a first light-emitting opening portion OP1-E, a second light-emitting opening portion OP2-E, and a third light-emitting opening portion OP3-E may be defined (or formed) in a dam PW. A first light-emitting region PXA-R may be defined as a region of a top surface of a first anode AE1 that is exposed by the first dam opening portion OP1-P. A second light-emitting region PXA-G may be defined as a region of a top surface of a second anode AE2 that is exposed by the second dam opening portion OP2-P. A third light-emitting region PXA-B may be defined as a region of a top surface of a third anode AE3 that is exposed by the third dam opening portion OP3-P.

[0180] Each of the first dam opening portions OP1-P, the second dam opening portions OP2-P, and the third dam opening portions OP3-P may include a first region A1 (see Figure 6 ) and a second region A2 (see Figure 6 ) described above. The first dam layer L1 may have first inner surfaces S-L1 (see Figure 6 ) of the first region A1 that respectively define the first dam opening portions OP1-P, the second dam opening portions OP2-P, and the third dam opening portions OP3-P, and the second dam layer L2 may have second inner surfaces S-L2 (see Figure 6 ) of the second region A2 that respectively define the first dam opening portions OP1-P, the second dam opening portions OP2-P, and the third dam opening portions OP3-P. Figure 6 )

[0181] A first light-emitting pattern EP1 and a first cathode CE1 may be disposed in the first dam opening portion OP1-P, a second light-emitting pattern EP2 and a second cathode CE2 may be disposed in the second dam opening portion OP2-P, and a third light-emitting pattern EP3 and a third cathode CE3 may be disposed in the third dam opening portion OP3-P.

[0182] In an embodiment, the first light-emitting pattern EP1, the second light-emitting pattern EP2, and the third light-emitting pattern EP3, and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be separated (e.g., physically separated) by a second dam layer L2 providing a tip portion TP, and defined (or formed) in light-emitting opening portions OP1-E, OP2-E, and OP3-E, and dam opening portions OP1-P, OP2-P, and OP3-P. As shown in the drawing, each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be in contact with the dam PW, and the first light-emitting pattern EP1, the second light-emitting pattern EP2, and the third light-emitting pattern EP3 may be spaced apart from the dam PW in a plan view. For example, each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be in contact with a first inner surface S-L1 of the first dam layer L1. However, the embodiment is not limited thereto. For example, each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be spaced apart from the dam PW in a plan view, and is not limited to any one embodiment.

[0183] According to an embodiment, the first light-emitting pattern EP1 may be deposited by being patterned into a plurality of pixel units by a tip portion TP defined (or formed) in the dam PW. For example, the first light-emitting pattern EP1 may be commonly formed using an open mask, but is easily separated into a plurality of pixel units by the dam PW.

[0184] In the case of patterning the first light-emitting pattern EP1 using a fine metal mask (FMM), it is necessary to provide a support spacer protruding from the conductive dam to support the fine metal mask. For example, the fine metal mask is spaced apart from a base surface undergoing patterning by the height of the dam and the support spacer, such that the achievement of high resolution may be limited. In addition, when the fine metal mask comes into contact with the support spacer, foreign substances may remain on the support spacer after the process of patterning the first light-emitting pattern EP1, or the support spacer may be damaged by the pressing of the fine metal mask. Accordingly, a defective display panel may be provided.

[0185] According to an embodiment, since the dam PW is included, separation (e.g., physical separation) between the light-emitting elements ED1, ED2, and ED3 may be easily achieved. Accordingly, driving errors or current leakage between adjacent light-emitting regions PXA-R, PXA-G, and PXA-B may be prevented, and the light-emitting elements ED1, ED2, and ED3 may be capable of being driven independently of each other.

[0186] Since without being associated with the display area DA (see Figure 1B) Patterning the first light-emitting pattern EP1 in the case of a mask in contact with the internal components therein, so that the defect rate can be reduced to provide a display panel DP with improved process reliability. Since patterning is possible even without a separate support spacer protruding from the dam PW, the corresponding surface areas of the light-emitting regions PXA-R, PXA-G, and PXA-B can be reduced to provide a display panel DP that can easily achieve high resolution.

[0187] For example, since the manufacturing of a mask with a large surface area is omitted in the manufacturing of a display panel DP with a large surface area, the process cost can be reduced, and the display panel DP can be free from defects that may occur under a mask with a large surface area. Accordingly, a display panel DP with improved process reliability can be provided or realized. The same / similar description of the first light-emitting pattern EP1 can be applied to the second light-emitting pattern EP2 and the third light-emitting pattern EP3.

[0188] The auxiliary electrodes SE1, SE2, and SE3 may include a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3. The first auxiliary electrode SE1 may be disposed on the first light-emitting element ED1, the second auxiliary electrode SE2 may be disposed on the second light-emitting element ED2, and the third auxiliary electrode SE3 may be disposed on the third light-emitting element ED3. Each of the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may extend along the first inner surface S-L1 of the first dam layer L1 (see Figure 6 ), and each of the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may cover the end portions (e.g., opposite end portions) of each of the first light-emitting pattern EP1, the second light-emitting pattern EP2, and the third light-emitting pattern EP3, and the end portions (e.g., opposite end portions) of each of the first cathode CE1, the second cathode CE2, and the third cathode CE3.

[0189] The first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may be in contact with the first inner surface S-L1 of the first dam layer L1 respectively, and in contact with the first cathode CE1, the second cathode CE2, and the third cathode CE3. For example, the first auxiliary electrode SE1 may be electrically connected to the first dam layer L1 and the first cathode CE1, the second auxiliary electrode SE2 may be electrically connected to the first dam layer L1 and the second cathode CE2, and the third auxiliary electrode SE3 may be electrically connected to the first dam layer L1 and the third cathode CE3.

[0190] Since the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 are in contact with the first dam layer L1, the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 can be electrically connected to each other to receive a common voltage (e.g., a common cathode voltage). The first cathode CE1, the second cathode CE2, and the third cathode CE3 can be in contact with the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 to receive the common cathode voltage.

[0191] The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3.

[0192] In a plan view, the first dummy pattern D1 may include a (1-1) dummy pattern D11, a (1-2) dummy pattern D12, and a (1-3) dummy pattern D13 that respectively surround a first light-emitting region PXA-R, a second light-emitting region PXA-G, and a third light-emitting region PXA-B. Each of the (1-1) dummy pattern D11, the (1-2) dummy pattern D12, and the (1-3) dummy pattern D13 and a corresponding one of the first light-emitting pattern EP1, the second light-emitting pattern EP2, and the third light-emitting pattern EP3 may include the same material as each other and be formed by the same process.

[0193] In a plan view, the second dummy pattern D2 may include a (2-1) dummy pattern D21, a (2-2) dummy pattern D22, and a (2-3) dummy pattern D23 that respectively surround the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The (2-1) dummy pattern D21, the (2-2) dummy pattern D22, and the (2-3) dummy pattern D23 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 respectively may include the same material as each other and be formed by the same process (e.g., each of the (2-1) dummy pattern D21, the (2-2) dummy pattern D22, and the (2-3) dummy pattern D23 and a corresponding one of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may include the same material as each other and be formed by the same process).

[0194] In a planar view, the third dummy pattern D3 may include a (3-1)st dummy pattern D31, a (3-2)nd dummy pattern D32, and a (3-3)rd dummy pattern D33 respectively surrounding the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B. The (3-1)st dummy pattern D31, the (3-2)nd dummy pattern D32, and the (3-3)rd dummy pattern D33 may each include the same material as the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 respectively, and be formed by the same process (e.g., each of the (3-1)st dummy pattern D31, the (3-2)nd dummy pattern D32, and the (3-3)rd dummy pattern D33 and the corresponding one of the first auxiliary electrode SE1, the second auxiliary electrode SE2, and the third auxiliary electrode SE3 may include the same material as each other and be formed by the same process).

[0195] First dummy opening portions OP1-D, second dummy opening portions OP2-D, and third dummy opening portions OP3-D corresponding to the first light-emitting opening portion OP1-E, the second light-emitting opening portion OP2-E, and the third light-emitting opening portion OP3-E may be respectively defined (or formed) in the dummy pattern DMP. Each of the first dummy opening portions OP1-D, the second dummy opening portions OP2-D, and the third dummy opening portions OP3-D may include a first region AA1 (see Figure 10F ), a second region AA2 (see Figure 10F ), and a third region AA3 (see Figure 10F ) arranged in sequence in the third direction DR3. The first dummy opening portion OP1-D may be defined by the inner surfaces of the (1-1)st dummy pattern D11, the (2-1)st dummy pattern D21, and the (3-1)st dummy pattern D31, the second dummy opening portion OP2-D may be defined by the inner surfaces of the (1-2)nd dummy pattern D12, the (2-2)nd dummy pattern D22, and the (3-2)nd dummy pattern D32, and the third dummy opening portion OP3-D may be defined by the inner surfaces of the (1-3)rd dummy pattern D13, the (2-3)rd dummy pattern D23, and the (3-3)rd dummy pattern D33.

[0196] The thin film encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1, LIL2, and LIL3, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL. In an embodiment, the lower inorganic encapsulation patterns LIL1, LIL2, and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 may overlap with a first light-emitting opening portion OP1-E, a second light-emitting opening portion OP2-E, and a third light-emitting opening portion OP3-E, respectively.

[0197] The first lower inorganic encapsulation pattern LIL1 may cover the first auxiliary electrode SE1 and the (1-1)st dummy pattern D11, the (2-1)st dummy pattern D21, and the (3-1)st dummy pattern D31, and may have a portion disposed inside the first dam opening portion OP1-P. The second lower inorganic encapsulation pattern LIL2 may cover the second auxiliary electrode SE2 and the (1-2)nd dummy pattern D12, the (2-2)nd dummy pattern D22, and the (3-2)nd dummy pattern D32, and may have a portion disposed inside the second dam opening portion OP2-P. The third lower inorganic encapsulation pattern LIL3 may cover the third auxiliary electrode SE3 and the (1-3)rd dummy pattern D13, the (2-3)rd dummy pattern D23, and the (3-3)rd dummy pattern D33, and may have a portion disposed inside the third dam opening portion OP3-P. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 may be provided (or formed) in the form of patterns spaced apart from each other.

[0198] Figure 9 is an enlarged schematic cross-sectional view of a part of a display panel according to an embodiment. Figure 9 is along a display panel according to an embodiment Figure 5 in the schematic cross-sectional view taken along line I-I'. Reference will be made to Figure 9 by using the same / similar reference numerals or symbols for the same / similar components as those described with reference to Figure 6 and omitting redundant descriptions to describe the embodiment.

[0199] Reference Figure 9 , the display panel DPa may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLEDa, and a thin film encapsulation layer TFE. The display element layer DP-OLEDa may include a light-emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a dam (or partition wall) PW, an auxiliary electrode SEa, and a dummy pattern DMP. Figure 9 The shape of the auxiliary electrode SEa in Figure 6 may be different from the shape of the auxiliary electrode SE in

[0200] The auxiliary electrode SEa can be disposed on the light-emitting element ED. For example, the auxiliary electrode SEa can be disposed on the cathode CE. A part of the auxiliary electrode SEa can be disposed in the dam opening part OP-P. Figure 9 The auxiliary electrode SEa in can extend along the first inner surface S-L1 of the first dam layer L1 and the bottom surface B-L2 of the second dam layer L2, and the auxiliary electrode SEa can cover the ends (e.g., opposite ends) of the light-emitting pattern EP and the ends (e.g., opposite ends) of the cathode CE. Figure 9 An example is shown in which the auxiliary electrode SEa extends to align with the second inner surface S-L2 of the second dam layer L2. However, the embodiment is not limited thereto. For example, the auxiliary electrode SEa can only extend to the middle part of the bottom surface B-L2 of the second dam layer L2.

[0201] The auxiliary electrode SEa can have conductivity. For example, the auxiliary electrode SEa can include titanium nitride (TiN). In another embodiment, the auxiliary electrode SEa can include a transparent conductive oxide (TCO). For example, the auxiliary electrode SEa can include indium tin oxide (ITO) or indium zinc oxide (IZO). However, the embodiment is not limited thereto, and the auxiliary electrode SEa can be made of various materials such as a conductive polymer material as long as the auxiliary electrode SEa can have conductivity.

[0202] The auxiliary electrode SEa can be in contact with the first inner surface S-L1 of the first dam layer L1 and in contact with the cathode CE. For example, the auxiliary electrode SEa can be electrically connected to the dam PW and the cathode CE. The dam PW can receive a second driving voltage ELVSS (see Figure 4 ), and the auxiliary electrode SEa can be electrically connected to the dam PW to receive the second driving voltage ELVSS. Accordingly, the cathode CE electrically connected to the auxiliary electrode SEa can receive the second driving voltage ELVSS.

[0203] Figures 10A to 10J is a schematic cross-sectional view showing some of the operations of a method for manufacturing a display panel according to an embodiment. Reference will be made to Figures 10A to 10J By representing components that are the same / similar to the components described with reference to Figures 1A to 9 with the same / similar reference numerals or symbols and omitting redundant descriptions to describe the embodiment.

[0204] A method for manufacturing a display panel DP according to an embodiment may include: providing a preliminary display panel including a base layer, an anode disposed on the base layer, and a preliminary pixel defining film disposed on the base layer and covering the anode; forming a dam disposed on the preliminary pixel defining film and having a dam opening portion formed therein; patterning the preliminary pixel defining film to form a light emitting opening portion overlapping with the dam opening portion and exposing at least a part of the anode, so that a pixel defining film can be formed; forming a light emitting layer, a cathode disposed on the light emitting layer, and a preliminary auxiliary electrode in contact with the dam in the dam opening portion; doping the preliminary auxiliary electrode with a Group 2 element to form an auxiliary electrode; and forming a encapsulation layer covering the dam opening portion and having a refractive index greater than or equal to that of the auxiliary electrode.

[0205] Hereinafter, reference will be made to Figures 10A to 10J a method for forming two light emitting elements ED1 and ED2 and lower inorganic encapsulation patterns LIL1 and LIL2, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL covering the light emitting elements ED1 and ED2 will be described. An example of a display panel DP formed by the method described by reference to Figures 10A to 10J is shown as a part of the display panel DP in Figure 6 .

[0206] Referring to Figure 10A , a method for manufacturing a display panel DP according to an embodiment may include: providing a preliminary display panel DP-I. The preliminary display panel DP-I may include a base layer BL, a circuit element layer DP-CL, a first anode AE1 and a second anode AE2, a first preliminary sacrificial pattern SP1-I and a second preliminary sacrificial pattern SP2-I, a pixel defining film PDL, a first preliminary dam layer L1-I, and a second preliminary dam layer L2-I.

[0207] The circuit element layer DP-CL may be formed by a process for manufacturing circuit elements (e.g., a typical process) of forming an insulating layer, a semiconductor layer, and a conductive layer by a method such as coating or deposition and then selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process and an etching process to form semiconductor patterns, conductive patterns, signal lines, and the like.

[0208] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by the same patterning process, and the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed by the same patterning process. The pixel defining film PDL may be disposed on the base layer BL. The pixel defining film PDL may cover the first anode AE1 and the second anode AE2 and the first preliminary sacrificial pattern SP1-I and the second preliminary sacrificial pattern SP2-I. The pixel defining film PDL may cover all of the first anode AE1 and the second anode AE2 and the first preliminary sacrificial pattern SP1-I and the second preliminary sacrificial pattern SP2-I.

[0209] The first preliminary dam layer L1-I may be disposed on the pixel defining film PDL. The first preliminary dam layer L1-I may be formed by depositing a conductive material. The second preliminary dam layer L2-I may be disposed on the first preliminary dam layer L1-I. The second preliminary dam layer L2-I may be formed by depositing a conductive material. In an embodiment, the first preliminary dam layer L1-I may include aluminum (Al) or molybdenum (Mo), and the second preliminary dam layer L2-I may include titanium (Ti). However, the materials of the first preliminary dam layer L1-I and the second preliminary dam layer L2-I are not limited thereto. The first preliminary dam layer L1-I and the second preliminary dam layer L2-I may form a preliminary dam PW-I.

[0210] Subsequently, a method for manufacturing a display panel DP according to an embodiment may include: forming a first photoresist layer PR1 on the preliminary dam PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary dam PW-I and then patterning the preliminary photoresist layer using a photomask. A first light opening portion OP-PR1 and a second light opening portion OP-PR2 may be formed in the first photoresist layer PR1 through a patterning process. The first light opening portion OP-PR1 may overlap with the first anode AE1, and the second light opening portion OP-PR2 may overlap with the second anode AE2.

[0211] Then, referring to Figure 10B and Figure 10C , a method for manufacturing a display panel DP according to an embodiment may include: etching the first preliminary dam layer L1-I and the second preliminary dam layer L2-I to form a first dam layer L1 and a second dam layer L2 in which dam opening portions OP1-P and OP2-P are defined, so that a dam PW can be formed from the preliminary dam PW-I (see Figure 10A ).

[0212] As Figure 10B shown, the first etching of the first preliminary dam layer L1-I and the second preliminary dam layer L2-I may include forming preliminary dam opening portions OP1-PI and OP2-PI in the preliminary dam PW-I (see Figure 10A ) by using the first photoresist layer PR1 as a mask and dry-etching the first preliminary dam layer L1-I and the second preliminary dam layer L2-I. The preliminary dam opening portions OP1-PI and OP2-PI may include a first preliminary dam opening portion OP1-PI and a second preliminary dam opening portion OP2-PI. The first preliminary dam opening portion OP1-PI may be formed to overlap with the first anode AE1, and the second preliminary dam opening portion OP2-PI may be formed to overlap with the second anode AE2.

[0213] The first dry etching process in the embodiment can be performed in an etching environment where the etching selectivities of the first preliminary dam layer L1-I and the second preliminary dam layer L2-I are substantially the same. Accordingly, the inner surfaces of the first preliminary dam layer L1-I and the second preliminary dam layer L2-I that define the preliminary dam opening portions OP1-PI and OP2-PI can be substantially aligned with each other.

[0214] Subsequently, as Figure 10C shown in Figure 10B , the second etching of the first preliminary dam layer L1-I (see Figure 10B ) can include forming dam opening portions OP1-P and OP2-P from the preliminary dam opening portions OP1-PI and OP2-PI (see Figure 10B ) by using the first photoresist layer PR1 as a mask and wet etching the first preliminary dam layer L1-I. The dam opening portions OP1-P and OP2-P can include a first dam opening portion OP1-P and a second dam opening portion OP2-P. The first dam opening portion OP1-P can be formed to overlap with the first anode AE1, and the second dam opening portion OP2-P can be formed to overlap with the second anode AE2.

[0215] Each of the dam opening portions OP1-P and OP2-P can include a first region A1 and a second region A2 arranged in sequence in the thickness direction (e.g., the third direction DR3). The first dam layer L1 can have a first inner surface S-L1 that defines the first region A1 of each of the dam opening portions OP1-P and OP2-P, and the second dam layer L2 can have a second inner surface S-L2 that defines the second region A2.

[0216] Referring to Figure 6 , Figure 7 and Figure 10C , forming the first dam layer L1 and the second dam layer L2 can include: forming a tip portion TP that protrudes from the first dam layer L1 toward the dam opening portions OP1-P and OP2-P on the second dam layer L2. The second wet etching process in the embodiment can be performed in an etching environment where the difference in etching selectivity between the first preliminary dam layer L1-I (see Figure 10B ) and the second preliminary dam layer L2-I (see Figure 10B ) is large. Accordingly, the inner surface of the dam PW that defines each of the dam opening portions OP1-P and OP2-P in cross-section can have an undercut shape. For example, since the first dam layer L1 has a higher etching rate for the etchant than the second dam layer L2, the first dam layer L1 can be mainly etched. Accordingly, the first inner surface S-L1 of the first dam layer L1 can be formed to be recessed inward from the second inner surface S-L2 of the second dam layer L2. The tip portion TP can be formed in the dam PW and can include a portion of the second dam layer L2 that protrudes from the first dam layer L1. Herein, as Figures 10A to 10CThe pixel defining film PDL before forming the light-emitting opening portion shown in may be referred to as a preliminary pixel defining film.

[0217] Subsequently, referring to Figure 10D , a method for manufacturing a display panel DP according to an embodiment may include: etching the pixel defining film PDL; and etching the preliminary sacrificial patterns SP1-I and SP2-I (see Figure 10C ). The etching of the pixel defining film PDL may be performed using a dry etching method, and may be performed using the first photoresist layer PR1 and the dam PW (e.g., the second dam layer L2) as masks. The light-emitting opening portions OP1-E and OP2-E corresponding to the dam opening portions OP1-P and OP2-P, respectively, may be formed in the pixel defining film PDL. The light-emitting opening portions OP1-E and OP2-E may include a first light-emitting opening portion OP1-E and a second light-emitting opening portion OP2-E.

[0218] The etching of the preliminary sacrificial patterns SP1-I and SP2-I (see Figure 10C ) may be performed using a wet etching method, and may be performed using the first photoresist layer PR1 and the dam PW (e.g., the second dam layer L2) as masks. The sacrificial opening portions OP1-S and OP2-S overlapping the light-emitting opening portions OP1-E and OP2-E may be formed in the sacrificial patterns SP1 and SP2 formed by etching the preliminary sacrificial patterns SP1-I and SP2-I (see Figure 10C ).

[0219] The sacrificial patterns SP1 and SP2 may include a first sacrificial pattern SP1 and a second sacrificial pattern SP2. The first sacrificial opening portion OP1-S overlapping the first light-emitting opening portion OP1-E may be formed in the first sacrificial pattern SP1, and the second sacrificial opening portion OP2-S overlapping the second light-emitting opening portion OP2-E may be formed in the second sacrificial pattern SP2. At least a part of the first anode AE1 may be exposed from the first sacrificial pattern SP1 and the pixel defining film PDL through the first sacrificial opening portion OP1-S and the first light-emitting opening portion OP1-E. At least a part of the second anode AE2 may be exposed from the second sacrificial pattern SP2 and the pixel defining film PDL through the second sacrificial opening portion OP2-S and the second light-emitting opening portion OP2-E.

[0220] The etching of the sacrificial patterns SP1 and SP2 can be performed in an etching environment in which the difference in etching selectivity between each of the sacrificial patterns SP1 and SP2 and the corresponding one of the anodes AE1 and AE2 is large, and accordingly, the anodes AE1 and AE2 can be prevented from being etched together. For example, each of the sacrificial patterns SP1 and SP2 having an etching rate higher than that of the anodes AE1 and AE2 respectively can be disposed between the pixel defining layer PDL and the corresponding one of the anodes AE1 and AE2 so that the anodes AE1 and AE2 can be prevented from being etched and damaged together during etching.

[0221] Subsequently, referring to Figures 10E to 10H , the method for manufacturing the display panel DP according to the embodiment may include: after removing the first photoresist layer PR1 (see Figure 10D ), forming a first light-emitting pattern EP1 (or light-emitting pattern) and a first cathode CE1 (or cathode) and forming a first auxiliary electrode SE1 (or auxiliary electrode) in each of the dam opening portions OP1-P and OP2-P.

[0222] Referring to Figure 10E , forming the first light-emitting pattern EP1 (see Figure 10H ) may include depositing a light-emitting layer EP-I. The process of depositing the light-emitting layer EP-I may include a thermal evaporation process. For example, forming the first cathode CE1 (see Figure 10H ) may include depositing a cathode layer CE-I. The process of depositing the cathode layer CE-I may include a thermal evaporation process.

[0223] When forming the first light-emitting pattern EP1, the light-emitting layer EP-I may be formed on each of the anodes AE1 and AE2. The light-emitting layer EP-I may be separated by the tip portions TP formed in the dam PW and disposed in the light-emitting opening portions OP1-E and OP2-E and the dam opening portions OP1-P and OP2-P. The light-emitting layer EP-I may be formed to be spaced apart from the second dam layer L2 in each of the dam opening portions OP1-P and OP2-P in a plan view (specifically, in a cross-sectional view). When forming the first light-emitting pattern EP1, a first dummy layer D1-I spaced apart from the light-emitting layer EP-I may be formed together on the dam PW.

[0224] When forming the first cathode CE1, the cathode layer CE-I may be formed on the light-emitting layer EP-I. The cathode layer CE-I may be separated by the tip portions TP formed in the dam PW and disposed in the dam opening portions OP1-P and OP2-P. The cathode layer CE-I may be formed to be spaced apart from the second dam layer L2 in each of the dam opening portions OP1-P and OP2-P in a plan view (specifically, in a cross-sectional view). When forming the first cathode CE1, a second dummy layer D2-I spaced apart from the cathode layer CE-I may be formed together on the dam PW.

[0225] Reference Figure 10F , the method may include: depositing a preliminary auxiliary electrode SE-I on a first cathode CE1; and doping the preliminary auxiliary electrode SE-I with a Group 2 element to form an auxiliary electrode SE (see Figure 10G ).

[0226] When forming the auxiliary electrode SE (see Figure 10G ), the preliminary auxiliary electrode SE-I may be disposed on the cathode layer CE-I. The preliminary auxiliary electrode SE-I may be separated by a tip portion TP formed in a dam PW into being disposed in dam opening portions OP1-P and OP2-P. The preliminary auxiliary electrode SE-I may be formed to cover a light-emitting layer EP-I and a cathode layer CE-I. For example, the preliminary auxiliary electrode SE-I may be deposited to cover an end portion (e.g., an opposite end portion) of a subsequently formed first light-emitting pattern EP1 (see Figure 10H ) and an end portion (e.g., an opposite end portion) of a first cathode CE1 (see Figure 10H ). For example, the preliminary auxiliary electrode SE-I may extend via an end portion of the first cathode CE1 (see Figure 10H ) to contact a first inner surface S-L1 of a first dam layer L1.

[0227] When forming the auxiliary electrode SE (see Figure 10G ), a third dummy layer D3-I spaced apart from the preliminary auxiliary electrode SE-I may be formed together on the dam PW.

[0228] In an embodiment, depositing the preliminary auxiliary electrode SE-I may include a sputtering process. The preliminary auxiliary electrode SE-I may be deposited by sputtering such that an entirety of a first inner surface S-L1 of a first dam layer L1 may be covered by the preliminary auxiliary electrode SE-I. For example, since the preliminary auxiliary electrode SE-I is deposited by sputtering instead of thermal evaporation, the entirety of the first inner surface S-L1 of the first dam layer L1 may be covered to improve the reliability of electrical connection.

[0229] For example, the preliminary auxiliary electrode SE-I may be deposited by sputtering, and the cathode layer CE-I may be deposited by thermal evaporation such that the preliminary auxiliary electrode SE-I may have a higher step coverage rate than the cathode layer CE-I. As described above, a size of a region where the preliminary auxiliary electrode SE-I contacts a first inner surface S-L1 of a first dam layer L1 may be larger than a size of a region where the cathode layer CE-I contacts the first inner surface S-L1 of the first dam layer L1.

[0230] For example, in an embodiment, a preliminary auxiliary electrode SE-I may be provided at a relatively high incident angle with respect to the light-emitting layer EP-I and the cathode layer CE-I such that the preliminary auxiliary electrode SE-I can be formed to contact the first dam layer L1. The preliminary auxiliary electrode SE-I may be formed to extend along the first inner surface S-L1 of the first dam layer L1.

[0231] Figure 10F An example is shown in which the preliminary auxiliary electrode SE-I contacts the first inner surface S-L1 of the first dam layer L1. However, the embodiment is not limited thereto. For example, the preliminary auxiliary electrode SE-I may extend along the first inner surface S-L1 of the first dam layer L1 and the bottom surface B-L2 of the second dam layer L2.

[0232] The preliminary auxiliary electrode SE-I may be doped with a Group 2 element to form the auxiliary electrode SE (see Figure 10G ). The preliminary auxiliary electrode SE-I may include a transparent conductive oxide (TCO). For example, the preliminary auxiliary electrode SE-I may include indium tin oxide (ITO).

[0233] The preliminary auxiliary electrode SE-I may be doped with a Group 2 element in an amount of about 1 at% to about 5 at% to form the auxiliary electrode SE (see Figure 10G ). In another example, the Group 2 element may be doped in an amount of about 1 at% to about 3 at%.

[0234] The auxiliary electrode SE (see Figure 10G ) may have a refractive index less than or equal to that of the thin film encapsulation layer TFE (see Figure 10J ) to be described later. As an example, the refractive index of the auxiliary electrode SE (see Figure 10G ) may have a refractive index less than or equal to that of the lower inorganic encapsulation layer LIL-I (see Figure 10G ). For example, the auxiliary electrode SE (see Figure 10G ) may have a refractive index less than or equal to 1.9, which is the refractive index of the lower inorganic encapsulation layer LIL-I including silicon nitride (SiN x ) (see Figure 10G ), and the auxiliary electrode SE (see Figure 10G ) may have a refractive index of about 1.76 to about 1.89.

[0235] For example, the auxiliary electrode SE (see Figure 10G ) is not limited to the aforementioned indium tin oxide (ITO) and may include indium zinc oxide (IZO) or other transparent conductive oxides (TCOs). The auxiliary electrode SE is not limited to any one embodiment.

[0236] The auxiliary electrode SE (see Figure 10G ) may have an amorphous structure, and the auxiliary electrode SE (see Figure 10G) may have a thickness of about 100 angstroms to about 1000 angstroms

[0237] The first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I may form a dummy layer DMP-I, and dummy opening portions OP1-D and OP2-D may be formed in the dummy layer DMP-I. The dummy opening portions OP1-D and OP2-D may include a first dummy opening portion OP1-D and a second dummy opening portion OP2-D. The first dummy opening portion OP1-D may overlap with the first dam opening portion OP1-P, and the second dummy opening portion OP2-D may overlap with the second dam opening portion OP2-P.

[0238] Each of the dummy opening portions OP1-D and OP2-D may include a first region AA1, a second region AA2, and a third region AA3 arranged in sequence in the thickness direction (i.e., the third direction DR3). The first region AA1 of each of the dummy opening portions OP1-D and OP2-D may be defined by the inner surface of the first dummy layer D1-I, the second region AA2 may be defined by the inner surface of the second dummy layer D2-I, and the third region AA3 may be defined by the inner surface of the third dummy layer D3-I.

[0239] Subsequently, referring to Figure 10G , a method for manufacturing a display panel DP according to an embodiment may include forming a lower inorganic encapsulation layer LIL-I. The lower inorganic encapsulation layer LIL-I may be formed by a deposition process. In an embodiment, the lower inorganic encapsulation layer LIL-I may be formed by a chemical vapor deposition (CVD) process. The lower inorganic encapsulation layer LIL-I may be formed on the dam PW and the auxiliary electrode SE, and a portion of the lower inorganic encapsulation layer LIL-I may be formed inside the dam opening portions OP1-P and OP2-P. The lower inorganic encapsulation layer LIL-I may be formed to be in direct contact with the preliminary auxiliary electrode SE-I (specifically, the auxiliary electrode SE). The lower inorganic encapsulation layer LIL-I may have a refractive index equal to or greater than that of the auxiliary electrode SE.

[0240] Subsequently, a method for manufacturing a display panel DP may include forming a second photoresist layer PR2. When forming the second photoresist layer PR2, a preliminary photoresist layer may be formed, and then the preliminary photoresist layer may be patterned using a photomask to form the second photoresist layer PR2. The second photoresist layer PR2 may be formed in a pattern corresponding to the first light-emitting opening portion OP1-E through a patterning process.

[0241] Referring to Figure 10H , a method for manufacturing a display panel DP according to an embodiment may include: patterning the lower inorganic encapsulation layer LIL-I (see Figure 10G) such that a first lower inorganic encapsulation pattern LIL1 can be formed; patterning the auxiliary electrodes SE other than the first auxiliary electrode SE1 (see Figure 10G ); patterning the light-emitting layer EP-I (see Figure 10G ) and the cathode layer CE-I (see Figure 10G ) such that a first light-emitting pattern EP1 and a first cathode CE1 can be formed; and patterning the dummy layer DMP-I (see Figure 10G ) such that a first (1-1) dummy pattern D11, a second (2-1) dummy pattern D21, and a third (3-1) dummy pattern D31 can be formed.

[0242] When patterning the lower inorganic encapsulation layer LIL-I, the lower inorganic encapsulation layer LIL-I can be dry-etched to remove the portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the second photoresist layer PR2. For example, patterning can be performed such that the portion of the lower inorganic encapsulation layer LIL-I that does not overlap with the first anode AE1 can be removed. The first lower inorganic encapsulation pattern LIL1 overlapping with the first light-emitting opening portion OP1-E can be formed from the patterned lower inorganic encapsulation layer LIL-I.

[0243] When patterning the auxiliary electrodes SE other than the first auxiliary electrode SE1 (see Figure 10G ), the auxiliary electrodes SE exposed to the outside can be wet-etched (see Figure 10G ) to remove the portion of the auxiliary electrodes SE (see Figure 10G ) that does not overlap with the second photoresist layer PR2. For example, patterning can be performed such that the portion of the auxiliary electrodes SE (see Figure 10G ) that does not overlap with the first anode AE1 can be removed. Accordingly, a first auxiliary electrode SE1 overlapping with the first light-emitting opening portion OP1-E can be formed. However, the embodiment is not limited thereto. For example, the preliminary auxiliary electrode SE-I can be dry-etched, and it is not limited to any one embodiment.

[0244] When patterning the light-emitting layer EP-I and the cathode layer CE-I, the light-emitting layer EP-I and the cathode layer CE-I can be removed by wet etching and a stripper. The portion of each of the light-emitting layer EP-I and the cathode layer CE-I that does not overlap with the second photoresist layer PR2 can be removed. For example, patterning can be performed such that the portion of each of the light-emitting layer EP-I and the cathode layer CE-I that does not overlap with the first anode AE1 can be removed. The first light-emitting pattern EP1 and the first cathode CE1, each of which overlaps with the first light-emitting opening portion OP1-E, can be formed from the patterned light-emitting layer EP-I and cathode layer CE-I, respectively.

[0245] When patterning the dummy layer DMP-I, the first dummy layer D1-I (see Figure 10G ) and the second dummy layer D2-I (seeFigure 10G ) and a third dummy layer D3-I (see Figure 10G ) to remove portions of each of the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I that do not overlap with the second photoresist layer PR2. For example, patterning may be performed such that portions of each of the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I that do not overlap with the first anode AE1 can be removed. Each of the (1-1)st dummy pattern D11, the (2-1)st dummy pattern D21, and the (3-1)st dummy pattern D31, which are formed from the patterned first dummy layer D1-I, second dummy layer D2-I, and third dummy layer D3-I, respectively, may overlap with the first light-emitting opening portion OP1-E. Each of the (1-1)st dummy pattern D11, the (2-1)st dummy pattern D21, and the (3-1)st dummy pattern D31 may have a closed-line shape surrounding its corresponding light-emitting region PXA (see Figure 6 ) in a plan view.

[0246] The light-emitting layer EP-I, the cathode layer CE-I, the auxiliary electrode SE other than the first auxiliary electrode SE1 (see Figure 10G ), and the lower inorganic encapsulation layer LIL-I, which have been formed in the second light-emitting opening portion OP2-E and the second dam opening portion OP2-P, can be removed by the above patterning process. For example, the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I formed on the dam PW that does not overlap with the first light-emitting opening portion OP1-E can also be removed. The first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 formed in the first light-emitting opening portion OP1-E and the first dam opening portion OP1-P can constitute the first light-emitting element ED1 after the patterning process.

[0247] Subsequently, referring to Figure 10I , in the method for manufacturing the display panel DP according to the embodiment, the second light-emitting element ED2 can be formed after removing the second photoresist layer PR2 (see Figure 10H ). The process of forming the second light-emitting element ED2 can be substantially the same as the process of forming the first light-emitting element ED1 described with reference to Figures 10E to 10H .

[0248] Subsequently, referring to Figure 10J, A method for manufacturing a display panel DP according to an embodiment may include forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the display panel DP. The organic material may be applied by an inkjet process to form the organic encapsulation film OL, but the embodiment is not limited thereto. The organic encapsulation film OL may provide a planarized top surface. Subsequently, an inorganic material may be deposited to form the upper inorganic encapsulation film UIL. Accordingly, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0249] As an example, Figures 10A to 10J A method for manufacturing a display panel DP including a first light-emitting element ED1 and a second light-emitting element ED2 is shown. Between forming a second lower inorganic encapsulation pattern LIL2 overlapping with the second light-emitting element ED2 and completing the display panel DP, it may further include forming a third light-emitting element ED3 (see Figure 8 ), forming a third auxiliary electrode SE3 (see Figure 8 ), and forming a third lower inorganic encapsulation pattern LIL3 (see Figure 8 ). Accordingly, a display panel DP including a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 corresponding to the light-emitting regions PXA-R, PXA-G, and PXA-B shown in Figure 8 respectively, a first auxiliary electrode SE1, a second auxiliary electrode SE2, and a third auxiliary electrode SE3, a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3, and a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3 may be formed.

[0250] In the display panel DP and the method for manufacturing the display panel DP according to an embodiment, the light-emitting element ED may be formed without using a metal mask.

[0251] The display panel DP and the method for manufacturing the display panel DP according to an embodiment may provide a light-emitting element ED with improved process reliability.

[0252] The display panel DP and the method for manufacturing the display panel DP according to an embodiment may provide a light-emitting element ED with improved electrical connection reliability.

[0253] The display panel DP and the method for manufacturing the display panel DP according to an embodiment may provide a light-emitting element ED capable of preventing light interference between the auxiliary electrode SE and the thin film encapsulation layer TFE.

[0254] The display panel DP according to an embodiment may include an auxiliary electrode SE connected to each of the cathode CE and the dam PW.

[0255] The method for manufacturing a display panel DP according to an embodiment may provide an auxiliary electrode SE that extends from an end portion of a cathode to contact a dam.

[0256] The display panel DP according to an embodiment may include an auxiliary electrode SE having a refractive index less than or equal to that of a thin film encapsulation layer TFE.

[0257] In the method for manufacturing a display panel DP according to an embodiment, a transparent conductive oxide may be doped with a Group 2 element to form an auxiliary electrode SE having a refractive index less than or equal to that of a thin film encapsulation layer TFE.

[0258] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A display panel, comprising: Base layer; a pixel defining film disposed on the base layer and including a light emitting opening portion; a dam, the dam being arranged on the pixel definition film and having conductivity, the dam including a dam opening portion overlapping the light emitting opening portion; a light emitting element arranged in the light emitting opening portion, the light emitting element including an anode, an intermediate layer arranged on the anode, and a cathode arranged on the intermediate layer; an auxiliary electrode disposed on the cathode and connected to the cathode and the dam; as well as an encapsulation layer, the encapsulation layer covering the light emitting element, Wherein, the refractive index of the auxiliary electrode is less than or equal to the refractive index of the encapsulation layer.

2. The display panel according to claim 1, wherein: The auxiliary electrode includes a transparent conductive oxide.

3. The display panel according to claim 2, wherein: The auxiliary electrode includes indium tin oxide.

4. The display panel according to claim 3, wherein: The auxiliary electrode further includes a Group 2 element.

5. The display panel according to claim 4, wherein: The content of the Group 2 element included in the auxiliary electrode is in the range of 1 at % to 5 at %.

6. The display panel according to claim 5, wherein: The content of the Group 2 element included in the auxiliary electrode is in the range of 1 at % to 3 at %.

7. The display panel according to claim 1, wherein: The auxiliary electrode has a thickness in a range of 100 angstroms to 1000 angstroms.

8. The display panel according to claim 1, wherein: The refractive index of the auxiliary electrode is 1.9 or less.

9. The display panel according to claim 1, wherein: The auxiliary electrode has an amorphous structure.

10. The display panel according to claim 1, wherein: The dam has an undercut shape in cross section, and The dam comprises: a lower layer comprising a conductive material; and an upper layer, the upper layer being arranged on the lower layer, and The auxiliary electrode extends along the inner surface of the lower layer.

11. The display panel according to claim 10, wherein: The cathode contacts the inner surface of the lower layer, and The auxiliary electrode extends through an end portion of the cathode to contact the inner surface.

12. The display panel according to claim 1, wherein: A size of a region where the auxiliary electrode contacts an inner surface of the dam is larger than a size of a region where the cathode contacts the inner surface of the dam.

13. A display panel, comprising: Base layer; a pixel defining film disposed on the base layer and including a light emitting opening portion; a dam, the dam being arranged on the pixel definition film and having conductivity, the dam including a dam opening portion overlapping the light emitting opening portion; a light emitting element arranged in the light emitting opening portion, the light emitting element including an anode, an intermediate layer arranged on the anode, and a cathode arranged on the intermediate layer; as well as an auxiliary electrode disposed on the cathode and connected to the cathode and the dam, Wherein, the auxiliary electrode comprises indium tin oxide doped with group 2 elements.

14. The display panel according to claim 13, further comprising: an encapsulation layer, the encapsulation layer covers the light emitting element, Wherein, the refractive index of the auxiliary electrode is less than or equal to the refractive index of the encapsulation layer.

15. The display panel according to claim 13, wherein: The Group 2 element includes at least one of magnesium and calcium.

16. A method for manufacturing a display panel, the method comprising: providing a preliminary display panel including a base layer, an anode disposed on the base layer, and a preliminary pixel defining film disposed on the base layer and covering the anode; forming a dam disposed on the preliminary pixel defining film and including a dam opening portion; forming a pixel defining film by patterning the preliminary pixel defining film to form a light emitting opening portion overlapping the dam opening portion and exposing at least a portion of the anode; forming a light emitting layer, a cathode disposed on the light emitting layer, and a preliminary auxiliary electrode in contact with the dam in the dam opening portion; forming an auxiliary electrode by doping the preliminary auxiliary electrode with a Group 2 element; as well as An encapsulation layer covering the dam opening portion and having a refractive index greater than or equal to that of the auxiliary electrode is formed.

17. The method of claim 16, wherein: The light emitting layer and the cathode are formed by a thermal evaporation method, and The auxiliary electrode is formed by a different method from that of the cathode.

18. The method of claim 17, wherein: The auxiliary electrode is formed by a sputtering process.

19. The method of claim 16, wherein: The preliminary auxiliary electrode is doped with the Group 2 element such that a content of the Group 2 element included in the auxiliary electrode is in a range of 1 at % to 5 at %.

20. The method of claim 16, wherein: Forming the dam comprises: forming a first layer on the preliminary pixel defining film; forming a second layer on the first layer; patterning the first layer and the second layer to form a first etch of a first pattern; and A second etch patterning is performed to form an undercut in the first pattern.

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