Display panel and display device

Abstract

A display panel includes a substrate, a first flat layer, a conductive pattern layer, a second flat layer, and an anode conductive layer. The first flat layer is arranged on one side of the substrate, and a plurality of first grooves are formed in the side, away from the substrate, of the first flat layer. The conductive pattern layer is arranged on the side, away from the substrate, of the first flat layer and comprises a plurality of conductive patterns, parts of the conductive patterns are located in the first grooves, and the parts, located in the first grooves, of the conductive patterns are away from the surface of the substrate. And the second flat layer is approximately flush with the surface, far away from the substrate, of the first flat layer. And the second flat layer is arranged on one side, far away from the substrate, of the conductive pattern layer. The anode conducting layer is arranged on the side, away from the substrate, of the second flat layer and comprises a plurality of anodes, and the vertical projection of the anodes on the substrate is overlapped with the vertical projection of at least one first groove on the substrate.

Description

[0001] This application is a divisional application of the patent application with the application date of July 29, 2021, application number 202180002037.6, and invention title "Display Panel, Manufacturing Method Thereof, and Display Device". Technical Field

[0002] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0003] An organic light-emitting diode (OLED) display panel has advantages such as active light emission, wide viewing angle, high contrast ratio, fast response speed, low power consumption, and ultra-thinness, and thus has received wide attention. Summary of the Invention

[0004] On the one hand, a display panel is provided. The display panel includes a substrate, a first planarization layer, a conductive pattern layer, a second planarization layer, and an anode conductive layer. The first planarization layer is disposed on one side of the substrate, and a plurality of first grooves are provided on the side of the first planarization layer away from the substrate. The conductive pattern layer is disposed on the side of the first planarization layer away from the substrate, and includes a plurality of conductive patterns. At least a part of the plurality of conductive patterns is located in the plurality of first grooves, and the surface of the part of the plurality of conductive patterns located in the first grooves away from the substrate is substantially flush with the surface of the first planarization layer away from the substrate. The second planarization layer is disposed on the side of the conductive pattern layer away from the substrate. The anode conductive layer is disposed on the side of the second planarization layer away from the substrate, and includes a plurality of anodes. The vertical projection of the anode on the substrate overlaps with the vertical projection of at least one first groove on the substrate.

[0005] In some embodiments, the display panel is provided with a plurality of thin film transistors. The display panel further includes a source-drain conductive layer. The source-drain conductive layer is disposed between the substrate and the first planarization layer, and at least includes a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistors. The plurality of conductive patterns include a plurality of signal lines, and at least a part of the plurality of signal lines is located in at least one of the first grooves.

[0006] In some embodiments, the line width of each part of the signal line is equal; and along the extending direction of the signal line, the vertical projection of the first groove on the substrate penetrates through the vertical projection of the anode on the substrate.

[0007] In some embodiments, the display panel further includes a pixel definition layer disposed on a side of the anode layer away from the substrate. The pixel definition layer is provided with a plurality of first openings. The anode includes a main body portion, and a vertical projection of one of the first openings on the substrate is within a range of a vertical projection of one of the main body portions on the substrate. A vertical projection of the main body portion of the anode on the substrate is within a range of a vertical projection of the first groove on the substrate.

[0008] In some embodiments, the first groove is a frame-shaped groove connected end to end, and a line width of a portion of the signal line located in the first groove is smaller than a line width of the remaining portion of the signal line.

[0009] In some embodiments, the display panel further includes a pixel definition layer disposed on a side of the anode layer away from the substrate. The pixel definition layer has a plurality of first openings. The anode includes a main body portion, and a vertical projection of one of the first openings on the substrate is within a range of a vertical projection of one of the main body portions on the substrate. An outer boundary of a vertical projection of one of the first grooves on the substrate coincides with a boundary of a vertical projection of one of the main body portions on the substrate.

[0010] In some embodiments, a plurality of second grooves are further provided on a surface of the first planar layer away from the substrate. One of the second grooves is located between two adjacent first grooves and connects the two adjacent first grooves. A portion of the same signal line located between two adjacent first grooves is located in one of the second grooves, and a surface of the portion of the signal line located in the second groove away from the substrate is substantially flush with a surface of the first planar layer away from the substrate.

[0011] In some embodiments, the plurality of signal lines include at least one of a plurality of auxiliary data signal lines and a plurality of auxiliary voltage signal lines.

[0012] In some embodiments, the voltage signal line extends along a first direction, and the plurality of voltage signal lines are arranged at intervals along a second direction. The plurality of signal lines include a plurality of auxiliary voltage signal lines, and the plurality of auxiliary voltage signal lines are electrically connected to the plurality of voltage signal lines. The plurality of auxiliary voltage signal lines include a plurality of first auxiliary voltage signal lines and a plurality of second auxiliary voltage signal lines. The first auxiliary voltage signal line extends along the first direction, and the plurality of first auxiliary voltage signal lines are arranged at intervals along the second direction. The first flat layer also includes a plurality of first vias, an auxiliary voltage signal line is opposite to a voltage signal line, and the first auxiliary voltage signal line is electrically connected to the voltage signal line opposite thereto through at least one of the first vias. The second auxiliary voltage signal line extends along the second direction, and the plurality of second auxiliary voltage signal lines are arranged at intervals along the first direction; the plurality of second auxiliary voltage signal lines are configured to electrically connect the plurality of first auxiliary voltage signal lines.

[0013] In some embodiments, the display panel further includes a color filter layer, which is disposed on a side of the anode conductive layer away from the substrate and includes a plurality of filter portions disposed at intervals. A plurality of third grooves are also provided on the surface of the first flat layer away from the substrate, and the vertical projection of the third grooves on the substrate overlaps with the vertical projection of the filter portion on the substrate. The conductive pattern layer further includes a plurality of adapter blocks, and one adapter block is configured to electrically connect one of the anodes to a source-drain electrode pattern of a thin film transistor. At least a portion of the adapter block is located in at least one of the third grooves, and the portion of the adapter block located in the third groove is away from the surface of the substrate and is substantially flush with the surface of the first flat layer away from the substrate.

[0014] In some embodiments, the adapter block includes a first part, a vertical projection of the first part of the adapter block on the substrate is located within the range of a vertical projection of the filter part on the substrate, and the first part of the adapter block is located in one of the third grooves.

[0015] In some embodiments, an adapter block is located in one of the third grooves.

[0016] In some embodiments, when the anode includes a main body, the anode also includes a connection portion connected to the main body; a plurality of third via holes are provided in the second flat layer, and the connection portion is electrically connected to one of the adapter blocks through at least one of the third via holes. A plurality of second via holes are provided in the first flat layer, and the adapter block is electrically connected to one of the source-drain electrode patterns through at least one of the second via holes.

[0017] In some embodiments, the third groove has a depth of 0.6 μm to 0.7 μm.

[0018] In some embodiments, the thickness of the first flat layer is 1.5 μm to 3.0 μm. The depth of the first groove is 0.6 μm to 0.7 μm.

[0019] In some embodiments, the display panel is provided with a plurality of thin film transistors. The plurality of conductive patterns at least include a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistors.

[0020] Among the plurality of source-drain electrode patterns of the plurality of thin film transistors, there is a first source-drain electrode pattern. The vertical projection of the first source-drain electrode pattern on the substrate overlaps with the vertical projection of the anode on the substrate. The first source-drain electrode pattern includes a second portion. The vertical projection of the second portion on the substrate is located within the range of the vertical projection of the anode on the substrate. One of the second portions is located in one of the first grooves.

[0021] In some embodiments, the first source-drain electrode pattern further includes a third portion. The vertical projection of the third portion on the substrate is located outside the range of the vertical projection of the anode on the substrate. The second portion and the third portion of the same first source-drain electrode pattern are located in one of the first grooves.

[0022] In some embodiments, in at least one of the plurality of voltage signal lines and the plurality of data signal lines, the overlapping portion of the vertical projection on the substrate with the vertical projection of one anode on the substrate is located in one of the first grooves.

[0023] In some embodiments, at least one of the plurality of voltage signal lines and the plurality of data signal lines is located in one of the first grooves.

[0024] In some embodiments, the display panel further includes a semiconductor layer, a first gate conductive layer, and a second gate conductive layer. The semiconductor layer is disposed between the substrate and the first flat layer and includes the active layer pattern of the thin film transistor. The first gate conductive layer is disposed between the semiconductor layer and the first flat layer and includes the gate pattern of the thin film transistor. The second gate conductive layer is disposed between the first gate conductive layer and the first flat layer; a capacitor is formed between a part of the second gate conductive layer and a part of the first gate conductive layer. The side of the first flat layer close to the substrate is in direct contact with the second gate conductive layer.

[0025] In some embodiments, the material of the first flat layer includes an organic material.

[0026] On the other hand, a display device is provided. The display device includes: the display panel as described in any of the above embodiments.

[0027] On the other hand, a method for manufacturing a display panel is provided, comprising: manufacturing an insulating material film on one side of a substrate; manufacturing a plurality of first grooves on the insulating material film to form a first flat layer; manufacturing a conductive pattern layer on a side of the first flat layer away from the substrate; manufacturing a second flat layer on a side of the conductive pattern layer away from the substrate; and manufacturing an anode conductive layer on a side of the second flat layer away from the substrate. The conductive pattern layer comprises a plurality of conductive patterns, at least part of the plurality of conductive patterns is located in at least one of the first grooves, and the thickness of the conductive pattern is equal to the depth of the first groove. The anode conductive layer comprises a plurality of anodes, and the vertical projection of one anode on the substrate overlaps with the vertical projection of at least one of the first grooves on the substrate.

[0028] In some embodiments, the plurality of conductive patterns include a plurality of auxiliary voltage signal lines and a plurality of transfer blocks. Before the insulating material film is formed on one side of the substrate, the method further includes: forming a source-drain conductive layer on the substrate. The source-drain conductive layer includes at least one of a plurality of voltage signal lines, a plurality of data signal lines, and a source-drain electrode pattern of a thin film transistor.

[0029] While making a plurality of first grooves on the insulating material film, the method further includes: making a plurality of first vias and a plurality of second vias on the insulating material film. A first via exposes a portion of a voltage signal line at one end close to the substrate, and a portion of an auxiliary voltage signal line is located in at least one first via and electrically connected to a voltage signal line. A second via exposes a portion of a source-drain electrode pattern at one end close to the substrate, and a portion of a transfer block is located in at least one third via and electrically connected to a display circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1 is a schematic diagram of a display device according to some embodiments;

[0032] Figure 2A For along Figure 1 A sectional view with the center section line AA;

[0033] Figure 2B For alongFigure 1 Another sectional view of the middle sectional line A-A;

[0034] Figure 3 For Figure 1 A partial enlarged view of B in the middle;

[0035] Figure 4 For Figure 3 A partial enlarged view of C1 in the middle;

[0036] Figure 5 For Figure 4 A sectional view of the middle along the sectional line E1-E1;

[0037] Figure 6 For Figure 3 Another partial enlarged view of C1 in the middle;

[0038] Figure 7 For Figure 6 A sectional view of the middle along the sectional line E2-E2;

[0039] Figure 8 For Figure 3 A partial enlarged view of C2 in the middle;

[0040] Figure 9 For Figure 8 A sectional view of the middle along the sectional line F1-F1;

[0041] Figure 10 For Figure 3 Another partial enlarged view of C2 in the middle;

[0042] Figure 11 For Figure 10 A sectional view of the middle along the sectional line F2-F2;

[0043] Figure 12 For Figure 3 A sectional view of the middle along the sectional line D-D;

[0044] Figure 13 For Figure 1 Another partial enlarged view of B in the middle;

[0045] Figure 14A For Figure 13 A sectional view of the middle along the sectional line G-G;

[0046] Figure 14B For Figure 13 Another sectional view of the middle along the sectional line G-G;

[0047] Figure 15A For Figure 13 A sectional view of the middle along the sectional line H-H;

[0048] Figure 15B Another sectional view along the section line H-H in Figure 13 ;

[0049] Figure 16 A schematic diagram of the manufacturing steps of a display panel according to some embodiments. Detailed implementation manners

[0050] Hereinafter, the technical solutions in some embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the present disclosure.

[0051] Unless otherwise required by the context, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example" or "some examples" etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0052] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] As used herein, the use of "configured to" implies open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0055] Additionally, the use of "based on" implies open and inclusiveness, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.

[0056] As used herein, "substantially" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0057] As used herein, "parallel", "perpendicular", "equal" include the stated situations and situations similar to the stated situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, and the acceptable deviation range of approximate parallel can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, and the acceptable deviation range of approximate perpendicular can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, and within the acceptable deviation range of approximate equality, for example, the difference between the two equal ones can be less than or equal to 5% of either one.

[0058] In this article, "the vertical projection of A overlaps with the vertical projection of B" includes "the vertical projection of A completely overlaps with the vertical projection of B" and "the vertical projection of A partially overlaps with the vertical projection of B". "The vertical projection of A completely overlaps with the vertical projection of B" means that the boundary of the vertical projection of A substantially coincides with the boundary of the vertical projection of B. "The vertical projection of A partially overlaps with the vertical projection of B" means that a part of the vertical projection of A coincides with a part of the vertical projection of B, and the other part is separated from each other; or, the boundary of the vertical projection of A is located within the boundary of the vertical projection of B; or, the boundary of the vertical projection of B is located within the boundary of the vertical projection of A.

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0060] Some embodiments of the present disclosure provide a display device 1000, refer to Figure 1 , Figure 1 , which is a structural diagram of a display device; the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (abbreviation: PDA), a navigator, a wearable device, an Augmented Reality (abbreviation: AR) device, a Virtual Reality (abbreviation: VR) device, etc.

[0061] The above display device 1000 can be an electroluminescent display device or a photoluminescent display device. In the case where the display device 1000 is an electroluminescent display device, the electroluminescent display device can be an organic electroluminescent display device or a Quantum Dot Light Emitting Diodes (abbreviation: QLED) display device. In the case where the display device 1000 is a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device.

[0062] The display device 1000 includes a display panel 1100. Refer to Figure 2A , Figure 2A , which is Figure 1 a cross-sectional view of the display panel 1100 along the section line A-A in

[0063] The substrate 100 can be a flexible substrate. For example, the substrate 100 is a substrate 100 made of resin. In this way, the display panel 1100 can be a flexible display panel (capable of being bent or folded). Alternatively, the substrate 100 can be a rigid substrate. For example, the substrate 100 is a glass substrate. In this way, the display panel 1100 can be a rigid display panel (not capable of being bent and folded).

[0064] The substrate 100 may be a composite film structure in which a multi-layer film structure is stacked. For example, the substrate 100 is a rigid substrate. Figure 2A , the substrate 100 includes a glass base 110 , a resin layer 120 , and a buffer layer 130 which are stacked.

[0065] The pixel circuit layer 200 refers to a film layer where a plurality of pixel circuit arrays are located. Each pixel circuit in the pixel circuit layer 200 is configured to control a light emitting device 300 electrically connected to the pixel circuit to emit light. The pixel circuit may include a plurality of switch devices and at least one capacitor Cst.

[0066] Exemplarily, the switch device may be a thin film transistor (Thin Film Transistor, referred to as TFT) or a field effect transistor (metal oxide semiconductor, referred to as MOS). In the embodiment of the present disclosure, the switch device is described as a thin film transistor, that is, the pixel circuit includes a plurality of thin film transistors ( Figure 2A Only one thin film transistor electrically connected to the light emitting device 300 is shown as an example. The thin film transistor may be a P-type transistor or an N-type transistor. The P-type transistor is turned on under a low potential and is turned off under a high potential. The N-type transistor is turned on under a high potential and is turned off under a low potential.

[0067] The pixel circuit layer 200 includes a plurality of patterned conductive layers stacked together. The structure of the patterned conductive layer is described below by way of example.

[0068] In some embodiments of the present disclosure, the plurality of patterned conductive layers include a stacked arrangement of Figure 2A The active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, the source-drain conductive layer 240 and the conductive pattern layer 250 are shown. In this case, the thin film transistor includes an active layer pattern 11 located in the active layer 210, a gate pattern 12 located in the first gate conductive layer 220, and a source electrode 13 and a drain electrode 14 located in the source-drain conductive layer 240. The capacitor Cst includes a first electrode plate 15 located in the first gate conductive layer 220 and a second electrode plate 16 located in the second gate conductive layer 230.

[0069] Alternatively, in some other embodiments of the present disclosure, the plurality of patterned conductive layers include a stacked arrangement of Figure 2BThe active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, and the conductive pattern layer 250 are shown. In this case, the thin-film transistor includes an active layer pattern 11 located on the active layer 210, a gate pattern 12 located on the first gate conductive layer 220, and a source 13 and a drain 14 located on the conductive pattern layer 250. The capacitor Cst includes a first electrode plate 15 located on the first gate conductive layer 220 and a second electrode plate 16 located on the second gate conductive layer 230.

[0070] Among them, in the embodiments of the present disclosure, among the multiple patterned conductive layers, the patterned conductive layer farthest from the substrate 100 is the conductive pattern layer 250. In this way, in different embodiments, the conductive pattern layer 250 may refer to different film layers.

[0071] Exemplarily, in Figure 2A the embodiment shown, the source-drain conductive layer 240 is configured to arrange the signal lines of the pixel circuit and the source-drain patterns of the thin-film transistors, and the conductive pattern layer 250 is configured to arrange the auxiliary signal lines of the pixel circuit. The auxiliary signal lines are configured to be electrically connected to the signal lines, and thus the auxiliary signal lines are connected in parallel with the signal lines to reduce the resistance of the signal lines. Exemplarily, in Figure 2B the embodiment shown, the conductive pattern layer 250 is configured to arrange the traces of the pixel circuit and the source-drain patterns of the thin-film transistors.

[0072] The pixel circuit layer 200 further includes an insulating layer disposed between two adjacent patterned conductive layers, and two planarization layers located on both sides (opposite sides along the thickness direction of the conductive pattern layer 250) of the conductive pattern layer 250. The material of the insulating layer includes an inorganic material. During the manufacturing process of the display panel, the insulating layer can be formed by chemical vapor deposition. The formed insulating layer has a substantially uniform thickness, and its surface undulates with the undulation of the surface of the substrate where it is located. The material of the planarization layer includes an organic material. During the manufacturing process of the display panel, the planarization layer can be formed by a coating process, thereby forming a planarization layer with a substantially flat surface. Among them, the organic material of the planarization layer is also an electrical insulating material. In this way, the planarization layer located on the side of the conductive pattern layer 250 close to the substrate 100 can be reused as the insulating layer between the conductive pattern layer 250 and the adjacent patterned conductive layer, which is beneficial to reducing the number of film layers of the display panel 100 and making the display panel 1100 thinner and lighter.

[0073] Since each patterned conductive layer is provided with different conductive patterns, and the insulating layer is usually a film layer structure with a uniform thickness, this results in the surface of the film layer close to the planarization layer in the pixel circuit layer 200 having undulations (uneven).

[0074] During the manufacturing process of the display panel 1100, a planarization layer is fabricated through a coating process. Due to the adhesive effect of the material of the planarization layer, the surface of the planarization layer away from the substrate 100 undulates following the undulation of the surface of the substrate it is on, with the degree of undulation of the planarization layer being less than that of the surface of the substrate it is on. Herein, the surface of the substrate where the planarization layer is located refers to the surface on the side of the planarization layer close to the substrate and in direct contact with the planarization layer.

[0075] Exemplarily, referring to Figure 2A , in the case where the multiple patterned conductive layers include the active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, the source-drain conductive layer 240, and the conductive pattern layer 250 which are stacked, the pixel circuit layer 200 further includes a first gate insulating layer 261 located between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 located between the first gate conductive layer 220 and the second gate conductive layer 230, an interlayer dielectric layer 263 located between the second gate conductive layer 230 and the source-drain conductive layer 240, a first planarization layer 270 located between the source-drain conductive layer 240 and the conductive pattern layer 250, and a second planarization layer 280 located on the side of the conductive pattern layer 250 away from the substrate 100.

[0076] In this way, the surface of the first planarization layer 270 away from the substrate 100 undulates following the undulation of the surface away from the substrate 100 formed by the interlayer dielectric layer 263 and the source-drain conductive layer 240. The surface of the second planarization layer 280 away from the substrate 100 undulates following the undulation of the surface away from the substrate 100 formed by the first planarization layer 270 and the conductive pattern layer 250.

[0077] Exemplarily, referring to Figure 2B , in the case where the multiple patterned conductive layers include the active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, and the conductive pattern layer 250 which are stacked, the pixel circuit layer 200 further includes a first gate insulating layer 261 located between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 located between the first gate conductive layer 220 and the second gate conductive layer 230, a first planarization layer 270 located between the second gate conductive layer 230 and the conductive pattern layer 250, and a second planarization layer 280 located on the side of the conductive pattern layer 250 away from the substrate 100.

[0078] In this way, the surface of the first planarization layer 270 away from the substrate 100 undulates following the undulation of the surface away from the substrate 100 formed by the second gate insulating layer 262 and the second gate conductive layer 230. The surface of the second planarization layer 280 away from the substrate 100 undulates following the undulation of the surface away from the substrate 100 formed by the first planarization layer 270 and the conductive pattern layer 250.

[0079] The light-emitting device 300 is disposed on the side of the pixel circuit layer 200 away from the substrate 100. In some embodiments, the light-emitting device 300 includes an anode layer 310, a pixel defining layer 320, a light-emitting functional layer 330, and a cathode layer 340 that are stacked.

[0080] The anode layer 310 includes a plurality of separated anodes 31 ( Figure 2A only one anode 31 is exemplarily shown therein). The pixel defining layer 320 has a plurality of first openings 32, each first opening 32 is opposite to an anode 31, and the boundary of the first opening 32 is within the boundary of the anode 31 opposite thereto. Each first opening 32 defines an effective light-emitting area of a sub-pixel. At least a part of the light-emitting functional layer 330 is located within the first opening 32. The cathode layer 340 is located on the side of the light-emitting functional layer 133 away from the substrate 100. Exemplarily, the cathode layer 340 can be a whole-layer film structure.

[0081] In some embodiments, the light-emitting functional layer 330 includes a light-emitting layer. In other embodiments, in addition to the light-emitting layer, the light-emitting functional layer 330 further includes at least one of an electron transporting layer (English: Election Tansporting Layer, abbreviated as: ETL), an electron injection layer (English: Election Injection Layer, abbreviated as: EIL), a hole transporting layer (English: HoleTransporting Layer, abbreviated as: HTL), and a hole injection layer (English: Hole Injection Layer, abbreviated as: HIL).

[0082] During the manufacturing process of the display panel 1100, the anode layer 310 is fabricated by a sputtering process. In this way, the formed anodes 31 have a uniform thickness. Based on this, the surface of the anode 31 away from the substrate 100 fluctuates as the surface of its underlying substrate fluctuates.

[0083] Exemplarily, the anode layer 320 is directly disposed on the surface of the second flat layer 280. The anodes 31 included in the anode layer 320 have fluctuations as the surface of the region where the anodes 31 are located on the second flat layer 280 fluctuates. That is, when the surface of the region configured to dispose the anode 31 on the second flat layer 280 has fluctuations, the anode 31 located in this region also has fluctuations adapted to the above-mentioned fluctuations; when the surface of the region configured to dispose the anode 31 on the second flat layer 280 is a flat surface, the anode 31 located in this region is also flat.

[0084] The encapsulation layer 400 can be an encapsulation film or an encapsulation substrate, and the embodiments of the present disclosure do not make specific limitations.

[0085] In some embodiments, the display panel 1100 further includes a color filter layer 500 disposed on a side of the encapsulation layer 400 away from the substrate 100. The color filter layer 500 includes a black matrix 510 and a plurality of color filter portions 520. The black matrix 510 has a plurality of second openings 511, and at least a part of one color filter portion 520 is located within one second opening 511.

[0086] A first opening 32 is opposite to a second opening 511, and a boundary of a vertical projection of the first opening 32 on the substrate 100 is located within a boundary of a vertical projection of the second opening 511 opposite thereto on the substrate 100; so that light emitted by a light-emitting device 300 can pass through the color filter portion 520 of an opening 511 and be emitted.

[0087] The color filter portion 520 is configured to color the light emitted by the light-emitting device 300. Exemplarily, the color filter portion 520 may include a red color filter portion 520, a green color filter portion 520, and a blue color filter portion 520.

[0088] The black matrix 510 of the color filter layer 500 can reduce the reflection of the display panel 1100 on ambient light. Based on this, compared with reducing the reflection of the display panel 1100 on ambient light by setting a polarizer, when the display panel 1100 includes the color filter layer 500, the display device 1000 can reduce one polarizer, making the display device 1000 thinner and lighter, and at the same time reducing the manufacturing cost of the display device 1000.

[0089] In the related art, in the pixel circuit layer, the surface of the film layer close to the flat layer away from the substrate has undulations, resulting in undulations on the surface of the flat layer away from the substrate. The anode layer is directly disposed on the flat layer. In this way, the surface of the anode included in the anode layer may also have undulations. Moreover, the display panel uses the color filter layer to replace the polarizer to achieve the function of reducing the reflection of ambient light, so that the ambient light incident on the anode layer can pass through the color filter portion from the opening of the black matrix after being reflected by the anode layer. Due to the undulations on the surface of the anode layer, the light reflected by the anode layer will undergo color separation, that is, the light reflected by the anode layer will form a colored halo. And the greater the undulation degree of the anode layer (the worse the flatness), the more serious the color separation phenomenon of the light reflected by the anode layer, and the more obvious the generated colored halo. The light that undergoes color separation and is emitted by the color filter portion can form a colored halo on the light-emitting surface of the display panel. Especially when the display panel is in a dark state (not displaying image information), the colored halo formed on the display panel is more obvious, and the colored halo is likely to cause glare to people.

[0090] Some embodiments of the present disclosure provide a display panel 1100. Refer to Figure 2A and Figure 2B , a plurality of first grooves 271 are provided on a side of the first flat layer 270 away from the substrate 100 (whereFigure 2A and Figure 2B Only one first groove 271 is exemplarily shown in Figure 2B . The depth of the first groove 271 is less than the thickness of the first flat layer 270, so that the first groove 271 has a bottom wall substantially parallel to the substrate 100, thereby preventing the patterned conductive layers on both sides of the first flat layer 270 from being electrically connected through the first groove 271. Wherein, the depth of the first groove 271 refers to: the dimension of the first groove 271 in the direction perpendicular to the substrate 100 ( Figure 2A the vertical direction in Figure 2A ); the thickness of the first flat layer 270 refers to: the dimension of the first flat layer 270 in the direction perpendicular to the substrate 100.

[0091] The vertical projection of the anode 31 on the substrate 100 overlaps with the vertical projection of at least one first groove 271 on the substrate 100. Exemplarily, the vertical projection of one anode 31 on the substrate 100 overlaps with the vertical projection of one first groove 271 on the substrate 100.

[0092] It should be noted that the vertical projection of the first groove 271 on the substrate 100 overlapping with the vertical projection of the anode 31 on the substrate includes that the vertical projections of both (the first groove 271 and the anode 31) on the substrate 100 completely overlap, and the vertical projections of both on the substrate 100 partially overlap.

[0093] The complete overlap of the vertical projections of both on the substrate 100 means that the boundaries of the vertical projections of both on the substrate 100 substantially coincide. The partial overlap of the vertical projections of both on the substrate 100 means that a part of the vertical projections of both on the substrate 100 coincides with each other and a part is separated (non - coincident); or, the boundary of the vertical projection of one of the two on the substrate 100 is located within the boundary of the vertical projection of the other on the substrate 100, and at least part of the boundaries of the vertical projections of both on the substrate 100 do not coincide.

[0094] The conductive pattern layer 250 is located between the first flat layer 270 and the second flat layer 280 and includes a plurality of conductive patterns 251. At least part of the plurality of conductive patterns 251 is located in the first groove 271. In this way, each first groove 271 is filled with a conductive pattern 251. The surface of the part of the plurality of conductive patterns 251 located in the first groove 271 away from the substrate 100 is substantially flush with the surface of the first flat layer 270 away from the substrate 100. To improve the flatness of the surface formed by the first flat layer 270 and the conductive pattern 251 located in the first groove 271, and improve the flatness of the substrate surface where the second flat layer 280 is located.

[0095] Among them, the part of the conductive pattern 251 located in the first groove 271 is away from the surface of the substrate 100 and is substantially flush with the surface of the first flat layer 270 away from the substrate 100, which means that the thickness of the part of the conductive pattern 251 located in the first groove 271 is substantially equal to the depth of the first groove 271.

[0096] Due to the precision limitation of the manufacturing process and the error of the measurement system, it is difficult to make the depth of the first groove 271 absolutely equal to the thickness of the conductive pattern 251 in the actual production process. In the embodiments of the present disclosure, the thickness of the part of the conductive pattern 251 located in the first groove 271 being substantially equal to the depth of the first groove 271 means that the difference between the thickness of the conductive pattern 251 (the part located in the first groove 271) and the depth of the first groove 271 is within an acceptable deviation range. Exemplarily, the above-mentioned acceptable deviation range may be 5%, that is, the ratio of the difference between the thickness of the conductive pattern 251 and the depth of the first groove 271 to the preset value is less than or equal to 5% of the preset value; the preset value refers to the designed values of the thickness of the conductive pattern 251 and the depth of the first groove 271. Of course, the above-mentioned acceptable deviation range may also be 3%, 8%, etc., and the embodiments of the present disclosure do not make specific limitations here.

[0097] It should be understood that since the first groove 271 is filled with the conductive pattern 251, based on this, the boundary of the first groove 271 completely coincides with the boundary of the conductive pattern 251 located in the first groove 271. In the drawings of the present disclosure, the part indicated by the first groove 271 is the boundary of the conductive pattern 251 located in the first groove 271. Exemplarily, referring to Figure 2A , the part indicated by the first groove 271 is the boundary where the conductive pattern 251 (signal line 17) intersects with the first flat layer 270.

[0098] The display panel 1100 provided by the embodiments of the present disclosure includes a first flat layer 270, a second flat layer 280, and a conductive pattern layer 250 located between the first flat layer 270 and the second flat layer 280, and the anode layer 310 is disposed on the surface of the second flat layer 280 away from the substrate 100. By providing two flat layers (the first flat layer 270 and the second flat layer 280), the flatness of the surface of the substrate where the second flat layer 280 is located can be improved.

[0099] Meanwhile, a part of the conductive pattern 251 is embedded in the first groove 271, and the vertical projection of the first groove 271 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate 100. Based on this, at least a part of the conductive pattern 251 located in the first groove 271 coincides with the vertical projection of the anode 31 on the substrate 100 in the vertical projection on the substrate 100, that is, at least a part of the conductive pattern 251 opposite to the anode 31 is embedded in the first groove 271. The surface of the conductive pattern 251 located in the first groove 271 away from the substrate 100 is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the flatness of the area for setting the anode 31 on the second flat layer 280 can be improved, and then the flatness of the anode 31 can be improved, the degree of color separation caused by the ambient light reflected by the anode 31 can be weakened, the possibility of forming a color halo on the light-emitting surface of the display panel 1100 can be reduced, the risk of dazzling the human eye can be reduced, and the user experience can be improved.

[0100] Refer to Figure 2A , when the patterned conductive layer of the pixel circuit layer 200 includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a source-drain conductive layer 240, and a conductive pattern layer 250 arranged in layers, the source-drain conductive layer 240 is disposed between the substrate 100 and the first flat layer 270 and is in direct contact with the first flat layer 270.

[0101] Refer to Figure 3 , Figure 3 is Figure 1 a partial enlarged view of B in Figure 3 , only the source-drain conductive layer 240, the conductive pattern layer 250, and the anode layer 310 of the display panel 1100 are exemplarily shown in Figure 3 ; the source-drain conductive layer 240 at least includes a plurality of voltage signal lines VDD, a plurality of data signal lines DATA, and the source-drain electrode pattern 19 of the thin-film transistor. The plurality of conductive patterns 251 include a plurality of signal lines 17 ( Figure 3 the vdd signal line in

[0102] . At least a part of the plurality of signal lines 17 is located in at least one first groove 271, which reduces the influence of the signal lines 17 on the flatness of the second flat layer 280 and improves the flatness of the anode 31.

[0103] In some embodiments, referring to Figure 4 , Figure 4 is Figure 3 a partial enlarged view of an anode 31 (the anode 31 in the region shown as C1 in Figure 3 ) in

[0104] Exemplarily, referring to Figure 4 , the extending direction of the part of the signal line 17 located within the first groove 271 is substantially the same as the extending direction of the part located outside the first groove 271. In this way, it is beneficial to the spatial arrangement of multiple signal lines 17.

[0105] It should be noted that due to the precision of the manufacturing process and the error of the measurement system, it is very difficult for the line widths of the signal line 17 to be exactly equal everywhere. The "line widths of the signal line 17 are substantially equal everywhere" in the embodiments of the present disclosure means that: the difference between the line widths of the signal line 17 everywhere is within an acceptable deviation range. Exemplarily, the acceptable deviation range is 5%, that is, the ratio of the difference between the actual value and the designed value of the line width of the signal line 17 to the designed value is less than or equal to 5%. Of course, the acceptable deviation range can also be 2%, 7%, etc., and the embodiments of the present disclosure do not make specific limitations on this.

[0106] In the drawings provided by the present disclosure, in order to distinguish the first groove 271 and the conductive pattern 251 in the figure, there is a gap between the boundary of the first groove 271 and the boundary of the signal line 17. However, in actual production, the boundary of the signal line 17 and the boundary of the first groove 271 can be closely attached, that is, the first groove 271 is filled with the signal line. Exemplarily, referring to Figure 4 , there is a gap between the boundary of the signal line 17 along its extending direction and the boundary of the first groove 271 along the extending direction of the signal line 17. However, in the actual production process, the boundary of the signal line 17 along its extending direction coincides with the boundary of the first groove 271 along the extending direction of the signal line 17, that is, the signal line 17 is completely attached to the side wall of the first groove 271.

[0107] Referring to Figure 5 , Figure 5 is Figure 4 a cross-sectional view along the section line E1-E1 in Figure 5 in Figure 4On the basis of the film layer shown, other film layers of the display panel 1100 are added. The portion of the signal line 17 located in the first groove 271 is substantially flush with the surface of the first flat layer 270 away from the substrate 100, which can reduce or avoid the undulation between the first region of the second flat layer 280 and its peripheral region. The first region refers to the region on the second flat layer 280 that contacts the signal line in the first groove 271. The flatness of the substrate surface where the region configured to set the anode 31 on the second flat layer 280 is located can be improved, and thus the flatness of the anode 31 can be improved.

[0108] Refer to Figure 4 , along the extension direction of the signal line 17, the vertical projection of the first groove 271 on the substrate 100 penetrates the vertical projection of the anode 31 on the substrate 100. That is, along the extension direction of the signal line 17, the two ends of the vertical projection of the first groove 271 on the substrate 100 substantially coincide with the boundaries of the vertical projection of the anode 31 on the substrate 100, or at least one end of the vertical projection of the first groove 271 on the substrate 100 extends beyond the boundaries of the vertical projection of the anode 31 on the substrate 100. In this way, the portion of the signal line 271 opposite to one anode 31 can be completely located in a first groove 271, which can further reduce the influence of the portion of the signal line 271 opposite to the anode 31 on the flatness of the anode 31. Among them, the vertical projection of the portion of the signal line 271 opposite to the anode 31 on the substrate 100 completely overlaps with the vertical projection of the anode 31 on the substrate 100.

[0109] Exemplarily, the number of the signal lines 17 is multiple. On any one of the signal lines 17, the portion opposite to one anode 31 is located in a first groove 271. In this way, the influence of the signal line 271 on the flatness of the anode 31 can be reduced to the greatest extent, the flatness of all the anodes 31 included in the anode layer 310 can be improved, and the possibility of forming a color halo on the light-emitting surface of the display panel 1100 can be reduced.

[0110] Refer to Figure 8 , Figure 8 is Figure 3 a partial enlarged view of an anode 31 ( Figure 3 the anode 31 in the region shown as C2 in Figure 8 ); the anode 31 includes a main body portion 311 and a connecting portion 312 connected to the main body portion 311. As shown in Figure 9 , Figure 9 taking the dotted line L1 as the boundary, the anode 31 is divided into a main body portion 311 and a connecting portion 312. Refer to Figure 9 , Figure 9 is Figure 8 a cross-sectional view along the section line F1-F1 in Figure 9 ; and Figure 8 On the basis of the film layer shown, other film layers of the display panel 1100 are added.

[0111] The vertical projection of the first opening 32 of the pixel defining layer 320 on the substrate 100 is located within the vertical projection range of the main body 311 of the anode 31 opposite thereto on the substrate 100. The connecting portion 312 is electrically connected to the main body 311 and is configured to electrically connect the main body 311 to the pixel circuit so that the pixel circuit can control the light emitting device 300 to emit light.

[0112] Due to the errors in manufacturing precision and measurement system, in the actual production process, it is difficult to make the portion of the signal line 17 located in the first groove 271 away from the surface of the substrate 100 and completely flush with the surface of the first flat layer 270, that is, there may still be unevenness at the junction between the signal line 17 located in the first groove 271 and the first flat layer 270.

[0113] In order to overcome the above problems, in some embodiments, refer to Figure 8 and Figure 9 , when the vertical projection of the main body 312 of the anode 31 on the substrate 100 is separated from the vertical projection of the adapter block 18 on the substrate 100; the vertical projection of the main body 311 of the anode 31 on the substrate 100 can be located within the range of the vertical projection of the first groove 271 on the substrate 100. So that the vertical projection of the main body 311 on the substrate 100 is located within the range of the vertical projection of the portion of the signal line 17 located in the first groove 271 on the substrate 100. In this way, the area on the second flat layer 280 configured to carry the anode 31 can be completely located on the signal line 17 in a first groove 271. Even if there are undulations at the junction between the signal line 17 in the first groove 271 and the first flat layer 270, the flatness of the area where the anode 31 is located on the second flat layer 280 can still be ensured, that is, the flatness of the anode 31 can be ensured, thereby reducing the color separation phenomenon of the light reflected by the anode 31.

[0114] It should be understood that the vertical projection of the main body 311 on the substrate 100 is located within the range of the vertical projection of the first groove 271 on the substrate 100, and the boundaries of the vertical projections of the two (the main body 311 and the first groove 271) on the substrate 100 may coincide with each other; or the boundary of the vertical projection of the main body 311 on the substrate 100 is located within the boundary of the vertical projection of the first groove 271 on the substrate 100, and there is a gap between the boundaries of the vertical projections of the two on the substrate 100; or a part of the boundary of the vertical projection of the main body 311 on the substrate 100 has a certain gap with the boundary of the vertical projection of the first groove 271 on the substrate 100, and the other part coincides with the boundary of the vertical projection of the first groove 271 on the substrate 100.

[0115] Exemplarily, the boundary of the vertical projection of the main body portion 311 on the substrate 100 is located within the boundary of the vertical projection of the first groove 271 on the substrate 100, and there is a gap between the boundaries of their vertical projections on the substrate 100. In this way, during the manufacturing process of the display panel 1100, the requirement for the alignment accuracy between the first groove 271 and the anode 31 can be reduced, and the manufacturing difficulty of the display panel 1100 can be lowered.

[0116] It should be understood that in some embodiments, when there is no requirement for the thinness and lightness of the display panel 1100, grooves may not be provided on the surface of the first flat layer 270 away from the substrate 100, and the positive projection of the anode 31 on the substrate 100 may be directly located within the range of the vertical projection of the signal line 17 on the substrate 100. In this way, the flatness of the anode 31 can still be increased.

[0117] In some embodiments, refer to Figure 10 , Figure 10 is Figure 3 a partial enlarged view of an anode 31 ( Figure 3 the anode 31 in the area shown as C2 in

[0118] It should be understood that the first groove 271 may further include a plurality of sub-grooves arranged side by side, so that the portion of the signal line 17 located within the first groove 271 includes a plurality of sub-lines arranged in parallel, to reduce the line width of a single sub-line. There may be a gap between the plurality of sub-lines to reduce the influence of each sub-line on the flatness of the second flat layer 280, and at the same time reduce the resistance of the signal line 17.

[0119] Refer to Figure 10 and Figure 11 , Figure 11 is a cross-sectional view along the section line F2-F2 in 10, and Figure 11 in Figure 4On the basis of the shown film layer, other film layers of the display panel 1100 are added. The outer boundary of the vertical projection of a first groove 271 on the substrate 100 substantially coincides with the boundary of the vertical projection of the main body portion 311 of an anode 31 on the substrate 100, that is, the vertical projection of the first groove 271 on the substrate 100 is within the projection range of the main body portion 311 and is located at the edge position of the vertical projection of the main body portion 311. In this way, the flatness of the middle region of the main body portion 311 can be improved, and the color separation phenomenon of the reflected light in the central region of the main body portion 311 can be reduced. At the same time, since a part of the ambient light reflected by the edge region of the main body portion 311 will be directed to the region where the black matrix 510 is located, the first groove 271 is arranged around the edge of the main body portion 271 of the anode 31. Even if there are undulations in the edge region of the main body portion 311, the light with color separation emitted from the light filtering portion 520 can be reduced, and the color halo formed on the light-emitting surface of the display panel 1100 can be weakened.

[0120] It should be understood that the first groove 271 is a frame-shaped groove, the vertical projection of the first groove 271 on the substrate 100 is annular, and the above annular projection encloses a closed area. The above annular projection includes an inner boundary and an outer boundary; the inner boundary refers to the boundary enclosing the above closed area; the outer boundary refers to the boundary far from the above closed area.

[0121] Limited by the wiring space of the conductive pattern layer 250, the vertical projection of the signal line 17 on the substrate 100 usually overlaps with the vertical projection of the anode 31 on the substrate 100. That is, it is very unlikely that the vertical projection of the signal line 17 on the substrate 100 is separated from the vertical projection of the anode 31 on the substrate 100. Therefore, in some embodiments, when limited by the wiring space of the conductive pattern layer 250, the outer boundary of the first groove 271 on the substrate 100 may be within the projection range of the anode 31 on the substrate 100.

[0122] In some embodiments, refer to Figure 12 , Figure 12 For Figure 3 a cross-sectional view along the section line D-D in Figure 12 where 101 shown in

[0123] On the surface of the first flat layer 270 away from the substrate 100, a plurality of second grooves 272 are further provided. One second groove 272 is located between two adjacent first grooves 271 and connects the two adjacent first grooves 271. The portion of the same signal line 17 between two adjacent first grooves 271 is located in one second groove 272. The surface of the portion of the signal line 17 located in the second groove 272 away from the substrate is substantially flush with the surface of the first flat layer away from the substrate. In this way, the signal line 17 can be entirely disposed in the grooves, and the depths of the first grooves 271 and the second grooves 272 are substantially the same, thereby reducing the undulation of the signal line 17 in the thickness direction of the display panel 1100 and making the resistance of each part of the signal line 17 more uniform. Moreover, the flatness of the surface of the first flat layer 270 and the conductive pattern layer 250 on the side away from the substrate 100 can be further improved, the flatness of the second flat layer 280 and the anode layer 310 can be improved, and the risk of the signal line 17 breaking due to undulation changes can be reduced.

[0124] In some embodiments, the plurality of voltage signal lines VDD included in the source-drain electrode layer 240 extend along the first direction M1, and the plurality of voltage signal lines VDD are spaced apart along the second direction M2. The plurality of signal lines 17 may include at least one of a plurality of auxiliary data signal lines Data1 and a plurality of auxiliary voltage signal lines Vdd.

[0125] Exemplarily, the plurality of signal lines 17 may include a plurality of auxiliary data signal lines Data. The auxiliary data signal lines Data extend along the first direction M1, and the plurality of auxiliary data signal lines Data are spaced apart along the second direction M2 so that the plurality of auxiliary data signal lines Data are electrically insulated from each other. One auxiliary data signal line Data is opposite to one data signal line DATA of the source-drain conductive layer 240, and the auxiliary data signal line Data is electrically connected to the data signal line DATA opposite thereto through a connection via provided on the first flat layer 270, and then one auxiliary data signal line Data is connected in parallel with one data signal line DATA to reduce the resistance of the data signal line DATA.

[0126] Exemplarily, the plurality of signal lines 17 may further include a plurality of auxiliary data signal lines Data and a plurality of auxiliary voltage signal lines Vdd. The plurality of auxiliary data signal lines Data and the plurality of auxiliary voltage signal lines Vdd both extend along the first direction M1, and any two adjacent signal lines 17 are spaced apart to insulate electrically between the two adjacent signal lines 17. One auxiliary data signal line Data is opposite to one data signal line DATA, and the auxiliary data signal line Data and the data signal line DATA opposite thereto are arranged in parallel to reduce the resistance of the data signal line DATA. One auxiliary voltage signal line Vdd is opposite to one voltage signal line VDD, and the auxiliary voltage signal line Vdd and the voltage signal line VDD opposite thereto are electrically connected, that is, the auxiliary voltage signal line Vdd and the voltage signal line VDD opposite thereto are arranged in parallel to reduce the resistance of the voltage signal line VDD. Exemplarily, limited by the wiring space of the conductive pattern layer 250, in order to facilitate the arrangement of the plurality of signal lines 17, the line widths of various parts of the same signal line 17 are substantially equal.

[0127] Exemplarily, referring to Figure 3 , the plurality of signal lines 17 includes a plurality of auxiliary voltage signal lines Vdd, and the plurality of auxiliary voltage signal lines Vdd are electrically connected to the plurality of voltage signal lines VDD to connect the plurality of auxiliary voltage signal lines Vdd and the plurality of voltage signal lines VDD in parallel, thereby reducing the resistance of the plurality of voltage signal lines VDD. The voltage signal line VDD of the source-drain electrode layer 240 is used to provide a common voltage signal for the pixel circuit. Since the common voltage signal provided for each pixel circuit may be the same, based on this, the plurality of auxiliary voltage signal lines Vdd can transmit signals with the same voltage value, and the plurality of auxiliary voltage signal lines Vdd can be arranged in parallel to further reduce the resistance of the auxiliary voltage signal line Vdd.

[0128] In the case where the plurality of signal lines 17 includes a plurality of auxiliary voltage signal lines Vdd, referring to Figure 3 , the plurality of auxiliary voltage signal lines Vdd may include a plurality of first auxiliary voltage signal lines Vdd1 and a plurality of second auxiliary voltage signal lines Vdd2. The plurality of first auxiliary voltage signal lines Vdd1 and the plurality of second auxiliary voltage signal lines Vdd2 intersect with each other to form a mesh structure to reduce the overall resistance of the plurality of auxiliary voltage signal lines Vdd.

[0129] Among them, the first auxiliary voltage signal line Vdd1 extends along the first direction M1, and the plurality of first auxiliary voltage signal lines Vdd1 are spaced apart along the second direction M2; one auxiliary voltage signal line Vdd is opposite to one voltage signal line VDD; referring to Figure 13, the first flat layer 270 further includes a plurality of first vias 273, and a first auxiliary voltage signal line Vdd1 is electrically connected to a voltage signal line VDD opposite thereto through at least one first via 273. The second auxiliary voltage signal line Vdd2 extends along the second direction M2, and a plurality of second auxiliary voltage signal lines Vdd2 are arranged at intervals along the first direction M1; the plurality of second auxiliary voltage signal lines Vdd2 are configured to electrically connect the plurality of first auxiliary voltage signal lines Vdd1.

[0130] In some embodiments, referring to Figure 2A , the plurality of conductive patterns 251 of the conductive pattern layer 250 further includes a plurality of connection blocks 18. One connection block 18 is configured to electrically connect one anode 31 to a source / drain electrode pattern 19 (the drain 14 of the thin film transistor) of a thin film transistor. A plurality of second vias 274 are provided in the first flat layer 270, and the connection block 18 is electrically connected to a source / drain electrode pattern 19 through at least one second via 274. A plurality of third vias 281 are provided in the second flat layer 280, and a connection portion 312 of the anode 31 is electrically connected to a connection block 18 through at least one third via 281. The vertical projection of the second via 274 on the substrate 100 is separated from the vertical projection of the third via 281 on the substrate 100, which is beneficial to improving the connection stability between the anode 31 and the connection block 18.

[0131] Exemplarily, referring to Figure 2A , each connection block 18 is electrically connected to a source / drain electrode pattern 19 through a second via 274. And the connection portion 312 of each anode 31 is electrically connected to a connection block 18 through a third via 281. Wherein, the source / drain electrode pattern 19 includes the drain 14 of the thin film transistor. As Figure 2A shown, the connection block 18 is electrically connected to a source / drain electrode pattern 19 through a second via 274, that is, the connection block 18 is electrically connected to the drain 14 of a thin film transistor through a second via 274.

[0132] The anode 31 needs to be electrically connected to a source / drain electrode pattern 19. There are at least the first flat layer 270 and the second flat layer 280 between the anode layer 310 and the source / drain electrode pattern 19. The interval between the anode layer 310 and the source / drain electrode pattern 19 is relatively large. By means of the connection block 18, it is possible to avoid the connection via between the connection portion 312 of the anode 31 and the source / drain electrode pattern 19 from being too deep, and the connection reliability between the anode 31 and the source / drain electrode pattern 19 is improved.

[0133] Referring to Figure 4 , the vertical projection of the connection portion 312 on the substrate 100 overlaps with the vertical projection of the connection block 18 on the substrate 100, so that the connection portion 312 can be electrically connected to the connection block 18 through at least one third via.

[0134] In some embodiments, see Figure 5 , the vertical projection of the adapter block 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100. The adapter block 18 includes a first portion 181, and the vertical projection of the first portion 181 on the substrate 100 is located within the range of the vertical projection of the filter portion 520 on the substrate 100. And because the vertical projection of the filter portion 520 on the substrate 100 is located within the range of the vertical projection of the anode 31 on the substrate 100, the vertical projection of the first portion 181 of the adapter block 18 on the substrate 100 is located within the range of the vertical projection of the anode 31 on the substrate 100.

[0135] In this way, the surface formed by the first portion 181 and the first flat layer 270 affects the flatness of the anode 31. Moreover, the ambient light reflected by the portion of the anode 31 opposite to the first portion 181 can be emitted from the filter portion 520. The higher the flatness of the surface formed by the first portion 181 and the first flat layer 270, the smaller the degree of color separation of the ambient light reflected by the portion of the anode 31 opposite to the first portion 181.

[0136] Based on this, in order to improve the flatness of the portion of the anode 31 opposite to the first portion 181. Figure 4 and Figure 5 The surface of the first flat layer 270 away from the substrate 100 is also provided with a plurality of third grooves 275; wherein, Figure 4 and Figure 5 Only one third groove 275 is shown as an example. At least part of the adapter block 18 is located in at least one third groove 275, and the vertical projection of the third groove 275 on the substrate 100 overlaps with the vertical projection of the filter part 520 on the substrate 100; that is, the vertical projection of the part of the adapter block 18 located in the third groove 275 on the substrate 100 overlaps with the vertical projection of the filter part 520 on the substrate 100. Based on this, at least part of the first part 181 of the adapter block 18 is located in at least one third groove 275.

[0137] At least part of the first portion 181 is located in at least one third groove 275, and the portion of the adapter block 18 located in the third groove 275 is away from the surface of the substrate 100 and is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the flatness of the portion of the anode 31 opposite to the first portion 181 can be improved, the color separation degree of the ambient light reflected by the portion of the anode 31 opposite to the first portion 181 can be reduced, the possibility of color halo formed on the light-emitting surface of the display panel 1100 can be reduced, the risk of glare to the human eye can be reduced, and the user experience can be improved.

[0138] For example, see Figure 4 and Figure 5The first part 181 of each adapter block 18 is entirely located in a third groove 275. In this way, the color separation degree of the ambient light reflected by the part of the anode 31 opposite to the first part 181 can be minimized, thereby reducing the possibility of a color halo forming on the light-emitting surface of the display panel 1100.

[0139] It should be understood that among the multiple adapter blocks 18 included in the conductive pattern layer 250, the vertical projections of some adapter blocks 18 on the substrate 100 may overlap with the vertical projections of the filter unit 520 on the substrate 100, that is, some adapter blocks 18 may have the first portion 181. Alternatively, the vertical projections of all adapter blocks 18 on the substrate 100 may overlap with the vertical projections of the filter unit 520 on the substrate 100, that is, all adapter blocks 18 may have the first portion 181.

[0140] For example, see Figure 3 , the vertical projection of some of the plurality of adapter blocks 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100, that is, only some of the adapter blocks 18 have the first portion 181. Figure 4 The vertical projection of the adapter block 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100. In this case, the adapter block 18 includes a first portion 181. Figure 8 The vertical projection of the adapter block 18 shown on the substrate 100 is separated from the vertical projection of the main body 311 of the anode 31 on the substrate 100, that is, the vertical projection of the adapter block 18 on the substrate 100 is separated from the vertical projection of the filter part 520 on the substrate 100. At this time, the adapter block 18 does not have the first part 181.

[0141] In some embodiments, see Figure 6 and Figure 7 , each adapter block 18 can also be set in a third groove 275. In this way, the fluctuation of the adapter block 18 in the thickness direction of the display panel 1100 can be reduced, the problem of uneven resistance of the adapter block 18 (the junction between the first part 181 and the rest of the parts) can be avoided, and the risk of the adapter block 18 breaking at the junction between the first part 181 and the rest of the parts can be avoided; the alignment accuracy between the first part 181 and the filter part 520 during the manufacturing process of the display panel 1100 can also be reduced, that is, the accuracy of the setting position of the third groove 275 during the manufacturing process of the display panel 1100 can be reduced, the alignment accuracy between the conductive pattern layer 250, the anode layer 310 and the color filter layer 500 can be reduced, and the manufacturing difficulty of the display panel 1100 can be reduced.

[0142] In some embodiments, Figure 8In the case where the vertical projection of the adapter block 18 on the substrate 100 is separated from the vertical projection of the main body 311 on the substrate 100, refer to Figure 9 , the third groove 275 may not be provided, that is, the adapter block 18 is directly provided on the surface of the first planar layer 170 away from the substrate 100 .

[0143] In some embodiments, the conductive pattern layer 250 is generally formed by a sputtering process, and the thickness of the conductive pattern 251 formed by the conductive pattern layer 250 is generally 0.6 μm to 0.7 μm. For example, the thickness of the conductive pattern 251 can be 0.6 μm, 0.65 μm, or 0.7 μm, etc., which are not listed here one by one.

[0144] The depths of the first groove 271, the second groove 272 and the third groove 275 can be 0.6 μm to 0.7 μm, which is suitable for the thickness of the conductive pattern 251. For example, the depths of the first groove 271, the second groove 272 and the third groove 275 can be 0.6 μm, 0.65 μm, or 0.7 μm, etc., which are not listed here one by one.

[0145] The thickness of the conductive pattern 251, the depth of the first groove 271, the depth of the second groove 272 and the depth of the third groove 275 are approximately equal, so that the portion of the conductive pattern 251 located in the first groove 271, the portion of the conductive pattern 251 located in the second groove 272, and the portion of the conductive pattern 251 located in the third groove 275 are approximately flush with the surface of the first flat layer 270 away from the substrate 100, so that the surface formed by the first flat layer 270 and the conductive pattern layer 250 away from the substrate 100 is approximately flat, thereby improving the overall flatness of the second flat layer 280 and the flatness of the anode layer 310.

[0146] In some embodiments, the thickness of the first planar layer 270 is 1.5 μm to 3.0 μm. If the thickness of the first planar layer 270 is too thin, it is not conducive to forming a substantially flat surface of the first planar layer 270. Therefore, the thickness of the first planar layer 270 is greater than or equal to 1.5 μm.

[0147] In some embodiments, the greater the thickness of the first planar layer 270 , the flatter the first planar layer 270 is away from the surface of the substrate 100 , but this is not conducive to thinning the display panel 1100 . Therefore, the first planar layer 270 is generally less than or equal to 3.0 μm.

[0148] Thus, the thickness of the first planar layer is 1.5 μm to 3.0 μm. For example, the thickness of the first planar layer 270 may be 1.5 μm, 2.0 μm, 2.4 μm or 3.0 μm, etc., which are not listed here one by one.

[0149] In some embodiments, the thickness of the second planarization layer 280 is 1.0 μm to 2.0 μm. Exemplarily, the thickness of the second planarization layer 280 can be 1.5 μm, 2.0 μm, 2.4 μm, 3.0 μm, etc., and will not be enumerated one by one here.

[0150] In some embodiments, referring to Figure 2B , when the patterned conductive layer of the pixel circuit layer 200 includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, and a conductive pattern layer 250 that are stacked. The first planarization layer 270 is located between the second gate conductive layer 230 and the conductive pattern layer 250, and the side of the first planarization layer 270 close to the substrate 100 is in direct contact with the second gate conductive layer 230. Thus, the first planarization layer 270 is also configured to separate the regions that do not require electrical connection between the second gate conductive layer 230 and the conductive pattern layer 250.

[0151] Referring to Figure 13 , Figure 13 when the patterned conductive layer includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, and a conductive pattern layer 250 that are stacked, Figure 1 the enlarged view of B in Figure 13 , in which only the conductive pattern layer 250 and the anode layer 310 are exemplarily shown. The conductive pattern layer 250 at least includes a plurality of voltage signal lines VDD, a plurality of data signal lines DATA, and one of the source-drain electrode patterns 19 of the thin film transistor. Among the plurality of source-drain electrode patterns 19 of the plurality of thin film transistors, a first source-drain electrode pattern 191 and a second source-drain electrode pattern 192 are included.

[0152] Referring to Figure 13 , the vertical projection of the first source-drain electrode pattern 191 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate 100. And the vertical projection of a part of the first source-drain electrode pattern 191 ( Figure 13 the first source-drain electrode pattern 191A in Figure 13 ) on the substrate 100 is located within the vertical projection of the anode 31 on the substrate 100. The vertical projection of a part of the first source-drain electrode pattern 191 (

[0153] the first source-drain electrode pattern 191B in Figure 14A ) on the substrate 100 partially coincides with and is partially separated from the vertical projection of the anode 31 on the substrate 100.

[0154] Wherein, when the vertical projection of the first source-drain electrode pattern 191A on the substrate 100 is within the range of the vertical projection of the anode 31 on the substrate 100, the second portion 1911 of the first source-drain electrode pattern 191 includes all of the first source-drain electrode pattern 191. In this way, one first source-drain electrode pattern 191 is located within one first groove 271.

[0155] When the vertical projection of the first source-drain electrode pattern 191B on the substrate 100 partially overlaps and partially separates from the vertical projection of the anode 31 on the substrate 100, the first source-drain electrode pattern 191 further includes a third portion 1912. The vertical projection of the third portion 1912 on the substrate 100 is outside the range of the vertical projection of the anode 31 on the substrate 100. Exemplarily, referring to Figure 4 A, the second portion 1911 is located within one first groove 271, and the third portion 1912 may be located on the surface of the first flat layer 270 away from the substrate 100.

[0156] Referring to Figure 13 , the vertical projection of the second source-drain electrode pattern 192 on the substrate 100 is separated from the vertical projection of the anode 31 on the substrate 100. The second source-drain electrode pattern 192 may be disposed in a groove; or directly disposed on the surface of the first flat layer 270 away from the substrate 100; or partially disposed in a groove and partially disposed on the surface of the first flat layer 270 away from the substrate 100; the embodiments of the present disclosure do not make specific limitations.

[0157] In the display panel 1100 provided by the embodiments of the present disclosure, the second portion 1911 of the source-drain electrode pattern 19 is disposed in the first groove 271, and the surface of the second portion 1911 away from the substrate 100 is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the surface formed by the first flat layer 270 and the second portion 1911 away from the substrate 100 is substantially flat, which can improve the flatness of the area on the second flat layer 280 in contact with the second portion 1911, and further improve the flatness of the portion of the anode 31 opposite to the second portion 1911, weaken the degree of color separation caused by the ambient light reflected by the anode 31, reduce the possibility of forming a color halo on the light-emitting surface of the display panel 1100, reduce the risk of eye glare, and improve the user experience.

[0158] In some embodiments, referring to Figure 14B, the second part 1911 and the third part 1912 of the same first source-drain electrode pattern 191 are located within a first groove 271. In this way, the undulation of the first source-drain electrode pattern 191 in the thickness direction of the display panel 1100 can be reduced, avoiding the problem of resistance mutation at the junction between the second part 191 of the first source-drain electrode pattern 191 and the remaining part, and reducing the risk of fracture at the junction between the second part 191 of the first source-drain electrode pattern 191B and the remaining part; at the same time, during the manufacturing process of the display panel 1100, the alignment accuracy requirement between the first groove 271 and the anode 31 can also be reduced, reducing the manufacturing difficulty of the display panel 1100.

[0159] In some embodiments, referring to Figure 15A , Figure 15A , taking the data signal line DATA as an example for illustration, it can also be a voltage signal line VDD; among at least one of the multiple voltage signal lines VDD and the multiple data signal lines DATA included in the conductive pattern layer 250, the overlapping portion of the vertical projection on the substrate 100 with the vertical projection of an anode 31 on the substrate 100 is located within a first groove 271.

[0160] Exemplarily, each voltage signal line VDD includes at least one first sub-segment, and the vertical projection of each first sub-segment on the substrate 100 is within the range of the vertical projection of an anode 31 on the substrate 100; one first sub-segment is located within a first groove 271. Each data signal line DATA includes at least one second sub-segment, and the vertical projection of one second sub-segment on the substrate 100 is within the range of the vertical projection of an anode 31 on the substrate 100; one second sub-segment is located within a first groove 271.

[0161] In this way, the flatness of the area on the second flat layer 280 that contacts the voltage signal line VDD and the data signal line DATA and is configured to set the anode 31 can be improved, thereby improving the flatness of the part of the anode 31 that faces the voltage signal line VDD and the data signal line DATA, and weakening the degree of color separation caused by the ambient light reflected by the anode 31.

[0162] In some embodiments, referring to Figure 15B , at least one of the multiple voltage signal lines VDD and the multiple data signal lines DATA can also be disposed within a first groove 271, that is, at least one of an entire voltage signal line VDD and an entire data signal line DATA is disposed within a first groove 271. Among them, Figure 15B taking one data signal line DATA located within a first groove 271 as an example for illustration.

[0163] Exemplarily, each voltage signal line VDD is located in a first groove 271, and each data signal line DATA is located in a first groove 271. In this way, the undulation of the voltage signal line VDD and the data signal line DATA in the thickness direction of the display panel 1100 can be reduced, so that the resistances at various positions where the voltage signal line VDD and the data signal line DATA extend along the length direction are more uniform, and the risk of breakage of the voltage signal line VDD and the data signal line DATA can be reduced. Moreover, the requirement for the alignment accuracy between the first groove 271 and the anode 31 can be reduced.

[0164] In some embodiments, the material of the first flat layer 270 includes an organic material. In this way, the first flat layer 270 with a substantially flat surface can be formed by a coating process. The material of the second flat layer 280 may also include an organic material. In this way, the second flat layer 280 with a substantially flat surface can be formed by a coating process. Exemplarily, the materials of the first flat layer 270 and the second flat layer 280 are the same.

[0165] Some embodiments of the present disclosure also provide a method for manufacturing a display panel. Refer to Figure 16 , the manufacturing method includes:

[0166] S100, as Figure 16 (a), fabricate an insulating material film 270A on one side of the substrate 101.

[0167] The substrate 101 refers to all the film layers between the substrate 100 and the first flat layer 270 in the display panel 1100.

[0168] Exemplarily, taking the multiple patterned conductive layers including the active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, the source-drain conductive layer 240, and the conductive pattern layer 250 stacked as an example. The substrate 101 further includes a first gate insulating layer 261 between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 between the first gate conductive layer 220 and the second gate conductive layer 230, an interlayer dielectric layer 263 between the second gate conductive layer 230 and the source-drain conductive layer 240, and located at the source-drain conductive layer 240.

[0169] Exemplarily, the insulating material used for the insulating material film 270A includes an organic material. In this way, the insulating material can be fabricated into the insulating material film 270A by a coating process, and the surface of the insulating material film 270A away from the substrate 101 is substantially flat. The thickness of the insulating material film 270A can be 1.5 μm to 3.0 μm.

[0170] S200, as Figure 16 (b), fabricate a plurality of first grooves 271 on the insulating material film 270A to form the first flat layer 270.

[0171] For example, a plurality of first grooves 271 may be formed by a photolithography process (including exposure, etching, and development, etc.) The depth of the first grooves 271 may be 0.6 μm to 0.7 μm.

[0172] S300, such as Figure 16 (c) A conductive pattern layer 250 is formed on a side of the first planar layer 270 away from the substrate 100 .

[0173] The conductive pattern layer 250 includes a plurality of conductive patterns 251, at least part of which is located in the first groove 271, and the thickness of the conductive pattern 251 is substantially equal to the depth of the first groove 271, so that the portion of the conductive pattern 251 located in the first groove 271 is away from the surface of the base substrate 101 and is substantially flush with the surface of the first flat layer 270 away from the base substrate 101. In accordance with the depth of the first groove 271, the thickness of the conductive pattern 251 may be 0.6 μm to 0.7 μm.

[0174] S400, such as Figure 16 (d) A second planarization layer 280 is formed on a side of the conductive pattern layer 250 away from the substrate 100 .

[0175] Exemplarily, the insulating material used for the second planar layer 280 includes an organic material, so that the insulating material can be formed into the second planar layer 280 by a coating process, and the surface of the second planar layer 280 away from the base substrate 101 is substantially flat. The thickness of the second planar layer 280 can be 1.0 μm to 2.0 μm.

[0176] S500, such as Figure 16 (e) An anode conductive layer 310 is formed on a side of the second planar layer 280 away from the substrate 100 .

[0177] The anode conductive layer 310 includes a plurality of mutually separated anodes 31 , and a vertical projection of one anode 31 on the substrate 100 overlaps with a vertical projection of at least one first groove 271 on the substrate 100 .

[0178] The display panel 1100 obtained by the manufacturing method provided by the embodiment of the present disclosure has the same beneficial effects as the display panel 1100 described in any of the above embodiments, which will not be described in detail here.

[0179] In some embodiments, the plurality of conductive patterns 251 include a plurality of auxiliary voltage signal lines Vdd and a plurality of transfer blocks 18 .

[0180] Before forming the insulating material film 270A on one side of the base substrate 101 in S100, the method further includes:

[0181] S001. Fabricate source-drain conductive layers on a substrate to form a substrate base 101.

[0182] The source-drain conductive layer 240 includes at least multiple voltage signal lines VDD, multiple data signal lines DATA, and source-drain electrode patterns of thin film transistors.

[0183] Refer to Figure 16 , S200. When fabricating multiple first grooves 271 on the insulating material film 270A, the manufacturing method further includes:

[0184] Fabricate multiple first vias 273 and multiple second vias 274 on the insulating material film 270A. That is, S200 includes: fabricating multiple first grooves 271, multiple first vias 273, and multiple second vias 274 on the insulating material film 270A.

[0185] Exemplarily, a halftone mask can be used to etch multiple first grooves 271, multiple first vias 273, and multiple second vias 274 on the insulating material film 270A simultaneously through one photolithography process.

[0186] One end of a first via 273 close to the substrate base 101 exposes a part of a voltage signal line VDD (not shown in the figure), and a part of an auxiliary voltage signal line Vdd is located in at least one first via 273 and is electrically connected to a voltage signal line VDD.

[0187] One end of a second via 274 close to the substrate 100 exposes a part of a source-drain electrode pattern (not shown in the figure), and a part of an adapter block 18 is located in at least one second via 274 and is electrically connected to a source-drain electrode pattern of a thin film transistor.

[0188] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claimed rights.

Claims

1. A display panel, characterized in that, the display panel is provided with a plurality of thin film transistors; the display panel includes: a substrate; a source-drain conductive layer disposed on one side of the substrate, at least including a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistors; a first planarization layer disposed on the side of the source-drain conductive layer away from the substrate, and a plurality of first grooves are provided on the side of the first planarization layer away from the substrate; a conductive pattern layer disposed on the side of the first planarization layer away from the substrate, including a plurality of conductive patterns, at least a part of the plurality of conductive patterns is located in the plurality of first grooves, and the surface of the part of the plurality of conductive patterns located in the first grooves away from the substrate is substantially flush with the surface of the first planarization layer away from the substrate; a second planarization layer disposed on the side of the conductive pattern layer away from the substrate; an anode conductive layer disposed on the side of the second planarization layer away from the substrate, including a plurality of anodes, and the vertical projection of the plurality of anodes on the substrate overlaps with the vertical projection of at least one first groove on the substrate; the anode includes a main body portion; the display panel further includes a pixel defining layer, the pixel defining layer is disposed on the side of the anode conductive layer away from the substrate, and the pixel defining layer is provided with a plurality of first openings; the vertical projection of a first opening on the substrate is located within the vertical projection of one of the main body portions on the substrate; wherein, the plurality of conductive patterns include a plurality of signal lines, at least a part of the plurality of signal lines is located in at least one of the first grooves, and the vertical projection of the main body portion of the anode on the substrate is located within the vertical projection of the first groove on the substrate.

2. The display panel according to claim 1, characterized in that, a plurality of second grooves are further provided on the surface of the first planarization layer away from the substrate, one second groove is located between two adjacent first grooves and communicates the two adjacent first grooves; the part of the same signal line located between two adjacent first grooves is located in one second groove, and the surface of the part of the signal line located in the second groove away from the substrate is substantially flush with the surface of the first planarization layer away from the substrate.

3. The display panel according to claim 1, characterized in that, the plurality of signal lines include at least one of a plurality of auxiliary data signal lines and a plurality of auxiliary voltage signal lines.

4. The display panel according to claim 3, characterized in that, the voltage signal lines extend in a first direction, and the plurality of voltage signal lines are spaced apart in a second direction; the plurality of signal lines include a plurality of auxiliary voltage signal lines, and the plurality of auxiliary voltage signal lines are electrically connected to the plurality of voltage signal lines; the plurality of auxiliary voltage signal lines include: a plurality of first auxiliary voltage signal lines, the first auxiliary voltage signal lines extend in the first direction, and the plurality of first auxiliary voltage signal lines are spaced apart in the second direction; one auxiliary voltage signal line is opposite to one voltage signal line; a plurality of second auxiliary voltage signal lines, the second auxiliary voltage signal lines extending along the second direction, and the plurality of second auxiliary voltage signal lines being arranged at intervals along the first direction; the plurality of second auxiliary voltage signal lines being configured to electrically connect the plurality of first auxiliary voltage signal lines; The first planar layer further includes a plurality of first via holes, and the first auxiliary voltage signal line is electrically connected to the voltage signal line opposite thereto through at least one of the first via holes.

5. The display panel according to claim 1, It is characterized in that The display panel further comprises a color filter layer, which is arranged on a side of the anode conductive layer away from the substrate and comprises a plurality of filter portions arranged at intervals; A plurality of third grooves are further provided on the surface of the first flat layer away from the substrate, and a vertical projection of the third grooves on the substrate overlaps with a vertical projection of the filter portion on the substrate; The conductive pattern layer also includes a plurality of adapter blocks, one adapter block being configured to electrically connect one of the anodes to a source-drain electrode pattern of a thin film transistor; at least a portion of the adapter block is located in at least one of the third grooves, and the portion of the adapter block located in the third groove is away from the surface of the substrate and is substantially flush with the surface of the first planar layer away from the substrate.

6. The display panel according to claim 5, It is characterized in that The adapter block includes a first part, a vertical projection of the first part of the adapter block on the substrate is located within the range of a vertical projection of the filter part on the substrate, and the first part of the adapter block is located in one of the third grooves.

7. The display panel according to claim 5, It is characterized in that A transfer block is located in one of the third grooves.

8. The display panel according to claim 5, It is characterized in that In the case where the anode includes a main body, the anode further includes a connecting portion connected to the main body; A plurality of second via holes are provided in the first planar layer, and the adapter block is electrically connected to one of the source-drain electrode patterns through at least one second via hole; A plurality of third via holes are provided in the second planar layer, and the connecting portion is electrically connected to one of the transfer blocks through at least one third via hole.

9. The display panel according to claim 5, It is characterized in that The depth of the third groove is 0.6 μm to 0.7 μm.

10. The display panel according to claim 1, It is characterized in that The thickness of the first flat layer is 1.5 μm to 3.0 μm; The depth of the first groove is 0.6 μm to 0.7 μm.

11. The display panel according to claim 1, It is characterized in that The plurality of conductive patterns at least include a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistor; Among the source-drain electrode patterns of the multiple thin-film transistors, a first source-drain electrode pattern is included. The vertical projection of the first source-drain electrode pattern on the substrate overlaps with the vertical projection of the anode on the substrate. The first source-drain electrode pattern includes a second portion, and the vertical projection of the second portion on the substrate is within the range of the vertical projection of the anode on the substrate. One of the second portions is located in one of the first grooves.

12. The display panel according to claim 11, wherein, the first source-drain electrode pattern further includes a third portion, and the vertical projection of the third portion on the substrate is outside the range of the vertical projection of the anode on the substrate; the second portion and the third portion of the same first source-drain electrode pattern are located in one of the first grooves.

13. The display panel according to claim 11 or 12, wherein, in at least one of the multiple voltage signal lines and the multiple data signal lines, the overlapping portion of the vertical projection on the substrate with the vertical projection of one anode on the substrate is located in one of the first grooves.

14. The display panel according to claim 11 or 12, wherein, at least one of the multiple voltage signal lines and the multiple data signal lines is located in one of the first grooves.

15. The display panel according to claim 11, wherein, the display panel further includes: a semiconductor layer, disposed between the substrate and the first flat layer, including the active layer pattern of the thin-film transistor; a first gate conductive layer, disposed between the semiconductor layer and the first flat layer, including the gate pattern of the thin-film transistor; a second gate conductive layer, disposed between the first gate conductive layer and the first flat layer; a capacitor is formed between a part of the second gate conductive layer and a part of the first gate conductive layer; the side of the first flat layer close to the substrate is in direct contact with the second gate conductive layer.

16. The display panel according to claim 15, wherein, the material of the first flat layer includes an organic material.

17. A display panel, wherein, the display panel is provided with multiple thin-film transistors; the display panel includes: a substrate; a source-drain conductive layer, disposed on one side of the substrate, at least including multiple voltage signal lines, multiple data signal lines, and one of the source-drain electrode patterns of the thin-film transistor; a first flat layer, disposed on the side of the source-drain conductive layer away from the substrate, and multiple first grooves are provided on the side of the first flat layer away from the substrate; a conductive pattern layer, disposed on the side of the first flat layer away from the substrate, including multiple conductive patterns, at least part of the multiple conductive patterns is located in the multiple first grooves, and the surface of the part of the multiple conductive patterns located in the first grooves away from the substrate is substantially flush with the surface of the first flat layer away from the substrate; a second flat layer, disposed on the side of the conductive pattern layer away from the substrate; The anode conductive layer is disposed on a side of the second flat layer away from the substrate, and includes a plurality of anodes. A vertical projection of the plurality of anodes on the substrate overlaps a vertical projection of at least one first groove on the substrate. Wherein, the plurality of conductive patterns include a plurality of signal lines, and at least a part of the plurality of signal lines is located in at least one of the first grooves; line widths of the signal lines are substantially equal everywhere; and along an extending direction of the signal lines, a vertical projection of the first groove on the substrate penetrates through a vertical projection of the anode on the substrate.

18. A display device Characterized in that it includes the display panel according to any one of claims 1 to 16, or includes the display panel according to claim 17.

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