Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, and the display panel comprises a substrate, a light-emitting function layer and a plurality of isolation columns. The light-emitting functional layer is arranged on one side of the substrate and comprises a first flat layer and a pixel limiting layer; the pixel limiting layer is provided with a plurality of pixel openings, the plurality of pixel openings are configured to accommodate a plurality of sub-pixels, and each sub-pixel comprises an anode, a light-emitting layer and a cathode which are sequentially arranged in the direction away from the substrate; the first flat layer and the pixel defining layer further comprise a plurality of isolation column openings, and each isolation column opening is located between every two adjacent pixel openings. And each isolation column in the plurality of isolation columns is located in the isolation column opening between the two adjacent pixel openings, and the isolation columns are configured to isolate the light emitting layers of the two adjacent sub-pixels and connect the cathodes of the two adjacent sub-pixels. According to the display panel provided by the embodiment of the invention, the isolation columns are arranged, so that crosstalk caused by connection of the light-emitting layers of the two adjacent sub-pixels is prevented.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, under-screen cameras have become a development trend. The display panel in the related art has a display area and a peripheral area surrounding the display area. The display area includes an under-screen camera area and a normal display area located on at least one side of the under-screen camera area. Both the under-screen camera area and the normal display area have multiple sub-pixels. The light-emitting layers of adjacent sub-pixels are connected, which will cause crosstalk and lead to poor display. Summary of the invention

[0003] The purpose of the embodiments of the present invention is to provide a display panel and a display device to prevent the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect. The specific technical solution is as follows:

[0004] An embodiment of the first aspect of the present application proposes a display panel, which includes a display area and a peripheral area surrounding the display area, the display area including a first display area and a second display area, and the second display area is located on at least one side of the first display area; the display panel includes a substrate, a light-emitting functional layer and a plurality of isolation columns; the light-emitting functional layer is arranged on one side of the substrate, including a first flat layer and a pixel defining layer; the pixel defining layer has a plurality of pixel openings, and the plurality of pixel openings are configured to accommodate a plurality of sub-pixels, and the sub-pixels include an anode, a light-emitting layer and a cathode arranged in sequence in a direction away from the substrate; the first flat layer and the pixel defining layer also include a plurality of isolation column openings, each of the isolation column openings is located between two adjacent pixel openings; each of the plurality of isolation columns is located in the isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels.

[0005] In some embodiments of the present application, the isolation column opening includes: a first opening penetrating the first planar layer and a second opening penetrating the pixel defining layer, and the first opening is connected to the second opening;

[0006] The isolation column is located in the first opening.

[0007] In some embodiments of the present application, the isolation column includes: a first sub-isolation layer, a second sub-isolation layer, a third sub-isolation layer, and a fourth sub-isolation layer, which are sequentially arranged in a direction away from the substrate;

[0008] In a first direction, the second sub-isolation layer is indented inward relative to the first sub-isolation layer; the third sub-isolation layer is indented inward relative to the second sub-isolation layer and the fourth sub-isolation layer, forming an undercut structure;

[0009] The second sub-isolation layer is a conductive structure, and the cathodes of two adjacent sub-pixels are connected through the second sub-isolation layer.

[0010] In some embodiments of the present application, the orthographic projection of the fourth sub-isolation layer on the substrate covers the orthographic projection of the first sub-isolation layer on the substrate.

[0011] In some embodiments of the present application, the sides of the first sub-isolation layer and the second sub-isolation layer are sloped surfaces;

[0012] In the first direction, the cross-sections of the first sub-isolation layer and the second sub-isolation layer are both upright trapezoidal structures.

[0013] In some embodiments of the present application, the isolation column includes: a fifth sub-isolation layer, a sixth sub-isolation layer, and a seventh sub-isolation layer arranged in sequence along a direction away from the substrate;

[0014] In a first direction, the sixth sub-isolation layer is indented inward relative to the fifth sub-isolation layer and the seventh sub-isolation layer, forming an undercut structure;

[0015] The fifth sub-isolation layer is a conductive structure, and the cathodes of two adjacent sub-pixels are connected through the fifth sub-isolation layer.

[0016] In some embodiments of the present application, the side of the fifth sub-isolation layer is a sloped surface or a vertical surface;

[0017] The side of the sixth sub-isolation layer is a sloped surface;

[0018] In the first direction, the cross-section of the fifth sub-isolation layer is an upright trapezoidal structure or a rectangular structure; the cross-section of the sixth sub-isolation layer is an upright trapezoidal structure.

[0019] In some embodiments of the present application, each isolation column surrounds a sub-pixel; the isolation columns of two adjacent sub-pixels are connected to each other.

[0020] In some embodiments of the present application, the display panel further includes: a driving circuit layer;

[0021] The driving circuit layer is disposed between the substrate and the light-emitting functional layer; the driving circuit layer includes a plurality of thin-film transistors; the plurality of thin-film transistors are electrically connected to the anodes of the plurality of sub-pixels in a one-to-one correspondence; the driving circuit layer further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer that are sequentially disposed in a direction away from the substrate;

[0022] The thin-film transistor includes: a first electrode, a second electrode, a gate, and an active layer;

[0023] The active layer is disposed between the substrate and the first gate insulating layer;

[0024] The gate is disposed between the first gate insulating layer and the second gate insulating layer;

[0025] The first electrode and the second electrode are disposed in the same layer on a side of the interlayer insulating layer away from the substrate;

[0026] A plurality of first through-holes are formed in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, and the first electrode and the second electrode are respectively connected to the active layer through different ones of the first through-holes.

[0027] In some embodiments of the present application, the driving circuit layer further includes: a passivation layer, a plurality of data lines, and a conductive connection layer;

[0028] The passivation layer is disposed on a side of the first electrode and the second electrode away from the substrate;

[0029] The plurality of data lines are disposed in the same layer as the gate;

[0030] The conductive connection layer is disposed between the passivation layer and the light-emitting functional layer;

[0031] A plurality of second through-holes are formed in the second gate insulating layer, the interlayer insulating layer, and the passivation layer, and adjacent data lines are respectively electrically connected to the conductive connection layer through different ones of the second through-holes.

[0032] In some embodiments of the present application, the driving circuit layer includes: a second planarization layer;

[0033] The second planarization layer is disposed between the first planarization layer and the conductive connection layer;

[0034] The plurality of spacer posts are disposed on a side of the second planarization layer away from the substrate and are in contact with the second planarization layer.

[0035] In some embodiments of the present application, the display panel further includes: a first inorganic layer and a buffer layer;

[0036] The first inorganic layer is formed on a side of the cathode away from the substrate and covers the cathode; the first inorganic layer extends to a side of the isolation column and is disconnected at the isolation column;

[0037] The buffer layer is disposed between the substrate and the active layer.

[0038] In some embodiments of the present application, the plurality of sub-pixels are respectively located in the first display area and the second display area, and a pixel density of the sub-pixels in the first display area is less than or equal to a pixel density of the sub-pixels in the second display area.

[0039] In some embodiments of the present application, the transmittance of the first display area is greater than the transmittance of the second display area.

[0040] An embodiment of the second aspect of the present application provides a display device, comprising a display panel implemented in any one of the first aspects, and a sensor located on a non-display surface side of the display panel, wherein the sensor's orthographic projection on the display panel at least partially overlaps with the first display area.

[0041] Beneficial effects of the embodiments of the present invention:

[0042] The display panel of the embodiment of the present application has a display area and a peripheral area surrounding the display area, and the display area includes a first display area and a second display area; the display panel includes a substrate, a light-emitting functional layer and a plurality of isolation columns, and since the first display area and the second display area both have display functions, the first display area and the second display area both have a plurality of sub-pixels; each isolation column is located in an isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels; the cathodes of two adjacent sub-pixels are connected through the isolation column, thereby ensuring the normal light emission of the display panel; the light-emitting layers of two adjacent sub-pixels are isolated by the isolation column, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0043] The display device of the embodiment of the present application includes a display panel whose isolation column is configured to isolate the light-emitting layer of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels; the cathodes of two adjacent sub-pixels are connected through the isolation column, thereby ensuring normal light emission of the display panel; the light-emitting layers of two adjacent sub-pixels are isolated by the isolation column, preventing the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0044] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0046] Figure 1 Top view of the display panel according to an embodiment of the present application;

[0047] Figure 2a Structural schematic diagram of the display panel according to the first embodiment of the present application;

[0048] Figure 2b For Figure 2a Partial enlarged schematic diagram;

[0049] Figure 3 For Figure 2a Structural schematic diagram of the isolation pillar in the embodiment shown;

[0050] Figure 4a Position relationship diagram of the isolation pillar and the sub-pixel in the first embodiment of the present application;

[0051] Figure 4b For Figure 1 Partial enlarged schematic diagram at the first display area of

[0052] Figure 4c For Figure 4b Position relationship diagram of the isolation pillar and the sub-pixel in the display island area in

[0053] Figure 5 Structural schematic diagram of the display panel according to the second embodiment of the present application;

[0054] Figure 6 For Figure 5 Structural schematic diagram of the isolation pillar in the embodiment shown;

[0055] Figure 7 Structural schematic diagram of the display panel according to the third embodiment of the present application;

[0056] Figure 8 Flowchart of the preparation method of the display panel according to the embodiment of the present application;

[0057] Figure 9 Process flowchart of the preparation of the display panel according to the first embodiment of the present application (steps 142 to 145);

[0058] Figure 10 Process flowchart of the preparation of the display panel according to the first embodiment of the present application (steps 146 to 148);

[0059] Figure 11 Process flow chart for preparing the display panel according to the first embodiment of the present application (Steps 149 to 151);

[0060] Figure 12 Process flow chart for preparing the display panel according to the second embodiment of the present application;

[0061] Figure 13 Schematic structural diagram of the display device according to the embodiment of the present application.

[0062] Description of reference numerals:

[0063] Display panel 10; Sensor 20; Display area AA; First display area A1; Display island area A11; Light-transmitting area A12; Second display area A2; Peripheral area BB; Isolation column opening W; First set of holes H1; Second set of holes H2; Third set of holes H3; Fourth set of holes H4; Via hole H5; Sub-pixel P; Red sub-pixel P1; Green sub-pixel P2; Blue sub-pixel P3; Substrate 100; Light-emitting functional layer 200; Pixel defining layer 210; Pixel opening 211; Second opening 212; Cathode 220; Light-emitting layer 230; Red light-emitting layer 231; Green light-emitting layer 232; Anode 240; First planar layer 250; First opening 251; Isolation column 300; Conductive structure 301; First sub-isolation layer 311; Second sub-isolation layer 312; Third sub-isolation layer 313; Fourth sub-isolation layer 314; Fifth sub-isolation layer 315; Sixth sub-isolation layer 316; Seventh sub-isolation layer 317; Driving circuit layer 400; Pixel circuit 401; Thin film transistor 410; First electrode 411; Second electrode 412; Gate 413; Active layer 414; First electrode contact area 4141; Semiconductor area 4142; Second electrode contact area 4143; Third electrode 415; First gate insulating layer 420; Second gate insulating layer 430; Interlayer insulating layer 440; Passivation layer 450; Data line 460; Conductive connection layer 470; Second planar layer 480; First inorganic layer 500; Buffer layer 600; First sub-isolation film layer 710; Second sub-isolation film layer 720; Third sub-isolation film layer 730; Fourth sub-isolation film layer 740; Sixth sub-isolation film layer 760; Seventh sub-isolation film layer 770; Red sub-light-emitting film layer 810; First cathode film layer 820; First inorganic film layer 830; Inorganic layer 831 corresponding to the red sub-pixel; Green sub-light-emitting film layer 840; Second cathode film layer 850; Second inorganic film layer 860; Inorganic layer 861 corresponding to the green sub-pixel; PR glue 910. Detailed description of the embodiments

[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0065] The display panel in the related art has a display area and a peripheral area surrounding the display area, the display area includes an under-screen camera area and a normal display area located on at least one side of the under-screen camera area; the under-screen camera area and the normal display area both have multiple sub-pixels, and the light-emitting layers between adjacent sub-pixels are connected, which may cause crosstalk and result in poor display. The embodiment of the present application proposes a display panel and a display device to prevent the occurrence of crosstalk caused by the connection of the light-emitting layers of two adjacent sub-pixels, thereby improving the display effect.

[0066] like Figures 1 to 2b As shown, Figure 1 is a top view of the display panel 10 according to an embodiment of the present application. Figure 2a Schematic diagram of the structure of the display panel 10 according to the first embodiment of the present application. Figure 2b for Figure 2a A partial enlarged schematic diagram; The embodiment of the first aspect of the present application provides a display panel 10, the display panel 10 includes a display area AA and a peripheral area BB surrounding the display area AA, the display area AA includes a first display area A1 and a second display area A2, the second display area A2 is located on at least one side of the first display area A1; Figure 2a and Figure 2b As shown, the display panel 10 includes a substrate 100, a light-emitting functional layer 200 and a plurality of isolation columns 300; the light-emitting functional layer 200 is disposed on one side of the substrate 100, and includes a first planar layer 250 and a pixel defining layer 210; the pixel defining layer 210 has a plurality of pixel openings 211, and the plurality of pixel openings 211 are configured to accommodate a plurality of sub-pixels P, and the sub-pixels P include an anode 240 (AND), a light-emitting layer 230 (EL) and a cathode 220 sequentially disposed in a direction away from the substrate 100; the first planar layer 250 and the pixel defining layer 210 also include a plurality of isolation column openings W (such as Figure 2b (as shown in the dashed box in the middle), each isolation column opening W is located between two adjacent pixel openings 211; each isolation column 300 among the multiple isolation columns 300 is located in the isolation column opening W between two adjacent pixel openings 211, and the isolation column 300 is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathode 220 of two adjacent sub-pixels P.

[0067] The display panel 10 of the embodiment of the present application has a display area AA and a peripheral area BB surrounding the display area AA, the display area AA includes a first display area A1 and a second display area A2; the display panel 10 includes a substrate 100, a light-emitting functional layer 200 and a plurality of isolation columns 300, and since the first display area A1 and the second display area A2 both have display functions, the first display area A1 and the second display area A2 both have a plurality of sub-pixels P; each isolation column 300 is located in an isolation column opening W between two adjacent pixel openings 211, and the isolation column 300 is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathode 220 of two adjacent sub-pixels P; the cathode 220 of two adjacent sub-pixels P is connected through the isolation column 300, thereby ensuring the normal light emission of the display panel 10; the light-emitting layer 230 of two adjacent sub-pixels P is isolated by the isolation column 300, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layer 230 of two adjacent sub-pixels P, thereby improving the display effect.

[0068] like Figure 1 In the embodiment shown, the first display area A1 may be located at the top center of the display area AA; the second display area A2 may surround the first display area A1. In other embodiments of the present application, the first display area A1 may also be located at other positions such as the upper left corner, lower left corner, lower right corner or upper right corner of the display area AA; the second display area A2 may surround at least one side of the first display area A1.

[0069] Multiple sub-pixels P are respectively located in the first display area A1 and the second display area A2. When the first display area A1 is the Full Display With Camera (FDC) area and the second display area A2 is the normal display area, the pixel density of the sub-pixels P in the first display area A1 may be less than or equal to the pixel density of the sub-pixels P in the second display area A2. When the pixel density of the sub-pixels P in the first display area A1 is less than the pixel density of the sub-pixels P in the second display area A2, it is beneficial to improve the transmittance of the first display area A1, thereby facilitating the operation of the camera corresponding to the first display area A1. When the pixel densities of the first display area A1 and the second display area A2 are equal, the display difference between the two can be reduced, thereby improving the display effect.

[0070] In the first embodiment of the present application, the light transmittance of the first display area A1 may be greater than the light transmittance of the second display area A2, thereby facilitating the stable operation of the camera arranged corresponding to the first display area A1.

[0071] It can be understood that since the cathode 220 is a semi-transparent material, the cathodes 220 of two adjacent sub-pixels P are connected by the isolation pillars 300, which is equivalent to replacing part of the cathode 220 with the isolation pillars 300. For a top-emitting display panel, light needs to exit through the cathode 220. Thus, when the light transmittance of the isolation pillar 300 is greater than that of the cathode 220, for example, the isolation pillar 300 is made of a transparent material, the light transmittance of the display panel 10 can be increased, which is beneficial to the stable operation of the camera corresponding to the first display area A1.

[0072] In the first embodiment of the present application, as Figure 2b shown, the isolation pillar opening W includes a first opening 251 penetrating the first flat layer 250 and a second opening 212 penetrating the pixel defining layer 210, and the first opening 251 and the second opening 212 communicate; the isolation pillar 300 is located in the first opening 251. In some other embodiments of the present application, the first opening 251 of the first flat layer 250 may also be a groove that does not penetrate the first flat layer 250, and it can be set according to actual needs. The present application does not limit this.

[0073] In the first embodiment of the present application, as Figure 3 and Figure 4a shown, Figure 3 is Figure 2a a schematic structural diagram of the isolation pillar 300 in the shown embodiment, Figure 4a is a positional relationship diagram of the isolation pillar 300 and the sub-pixel P in the first embodiment of the present application. The isolation pillar 300 includes a first sub-isolation layer 311, a second sub-isolation layer 312, a third sub-isolation layer 313, and a fourth sub-isolation layer 314 arranged in sequence along the direction away from the substrate 100 (PI, polyimide); in the first direction (as Figure 4a shown by the dotted line), the first direction can be the width direction of the isolation pillar 300; the second sub-isolation layer 312 is indented inward relative to the first sub-isolation layer 311; the third sub-isolation layer 313 is indented inward relative to the second sub-isolation layer 312 and the fourth sub-isolation layer 314 to form an undercut structure (as Figure 3 shown by the dotted line frame), and the undercut structure is a groove formed by the third sub-isolation layer 313 indenting inward relative to the fourth sub-isolation layer 314; it can effectively disconnect the light-emitting layers 230 of two adjacent sub-pixels P; as Figure 2aAs shown, each light-emitting layer 230 is formed within the corresponding pixel opening 211 and extends outward from within the pixel opening 211 to the side of the isolation pillar 300. The light-emitting layers 230 of adjacent sub-pixels P are disconnected at the isolation pillar 300, and the top surface of the isolation pillar 300 is not provided with a light-emitting layer 230, thereby avoiding poor display caused by the connection of the light-emitting layers 230 of adjacent sub-pixels P. Specifically, the light-emitting layers 230 of multiple sub-pixels P may include a red light-emitting layer 231, a green light-emitting layer 232, and a blue light-emitting layer (not shown in the figure).

[0074] As Figure 2a shown, each cathode 220 is formed within the corresponding pixel opening 211 and extends outward from within the pixel opening 211 to the side of the second sub-isolation layer 312; the second sub-isolation layer 312 is a conductive structure 301, and the cathodes 220 of two adjacent sub-pixels P are connected through the second sub-isolation layer 312; thereby ensuring the normal display of the display panel 10.

[0075] It can be understood that in some other embodiments of the present application, the conductive structure 301 may also be other film layers of the isolation pillar 300, and the cathode 220 is in contact with any one of the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313, and the fourth sub-isolation layer 314 of the isolation pillar 300, then this film layer should be used as the conductive structure 301 and has conductivity, which can be set according to the actual situation, and the present application does not make any limitations in this regard.

[0076] Optionally, the materials of the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313, and the fourth sub-isolation layer 314 may be Mo (molybdenum), Al (aluminum), Mo (molybdenum), and ITO (indium tin oxide) in sequence. In this way, all the film layers of the isolation pillar 300 have conductivity, and the cathode 220 can be in contact with any one of the film layers.

[0077] In the first embodiment of the present application, as Figure 3 shown, the orthographic projection of the fourth sub-isolation layer 314 on the substrate 100 is within the range of the orthographic projection of the first sub-isolation layer 311 on the substrate 100. In this way, the light-emitting layers 230 of adjacent sub-pixels P can be effectively disconnected.

[0078] In some other embodiments of the present application, the orthographic projection of the fourth sub-isolation layer 314 on the substrate 100 covers the orthographic projection of the first sub-isolation layer 311 on the substrate 100. Such a setting can achieve a better disconnection effect.

[0079] In the first embodiment of the present application, as Figure 3As shown, the sides of the first sub-isolation layer 311 and the second sub-isolation layer 312 are slope surfaces; in the first direction, the cross-sections of the first sub-isolation layer 311 and the second sub-isolation layer 312 are both positive trapezoidal structures. The first sub-isolation layer 311 forms a first trapezoidal sharp corner, the second sub-isolation layer 312 forms a second trapezoidal sharp corner, the third sub-isolation layer 313 is etched and shrinks inward, and the fourth sub-isolation layer 314 is etched to cooperate with the third sub-isolation layer 313 to form an undercut structure, ensuring effective disconnection of the light-emitting layer 230.

[0080] Optionally, as Figure 3 shown, the distance a by which the third sub-isolation layer 313 indents inward relative to the fourth sub-isolation layer 314 satisfies: a = 0.5 μm - 1 μm; the distance b by which the third sub-isolation layer 313 indents inward relative to the top surface of the second sub-isolation layer 312 satisfies: b = 0.2 μm - 0.5 μm; the range of the slope angle α of the side surface of the second sub-isolation layer 312 satisfies: α > 65°

[0081] In the first embodiment of the present application, as Figure 4a shown, multiple sub-pixels P may include a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3; each isolation pillar 300 is disposed around one sub-pixel P; the isolation pillars 300 of two adjacent sub-pixels P are connected to each other; thereby, multiple sub-pixels P can be effectively separated, avoiding poor display caused by the connection of the light-emitting layers 230 of multiple sub-pixels P.

[0082] In some other embodiments of the present application, multiple isolation pillars 300 may also be independent of each other and spaced apart from each other, and the present application does not limit this.

[0083] It can be understood that Figure 4a in the shown embodiment, since the isolation pillars 300 of two adjacent sub-pixels P are connected to each other, the space between adjacent sub-pixels P can be saved, which is beneficial to improving the pixel density.

[0084] In the first embodiment of the present application, as Figure 2a shown, the display panel 10 further includes a driving circuit layer 400; the driving circuit layer 400 is disposed between the substrate 100 and the light-emitting functional layer 200; the driving circuit layer 400 includes multiple thin-film transistors 410; the multiple thin-film transistors 410 are electrically connected to the anodes 240 of the multiple sub-pixels P in a one-to-one correspondence. The multiple thin-film transistors 410 may correspond to multiple pixel circuits, and the pixel circuits may be configured to provide a driving current to drive the corresponding sub-pixels P to emit light.

[0085] In the first embodiment of the present application, as Figure 1 and Figure 4b shown, Figure 4b For Figure 1A partial enlarged schematic view of the first display area A1, where the first display area A1 may include a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array; the light-transmitting areas A12 are used to improve the light transmittance of the first display area A1. Specifically, only the substrate 100 may be provided in the light-transmitting areas A12, and no other film layers are provided; in the second direction, the display island areas A11 and the light-transmitting areas A12 may be alternately arranged; in the third direction, a plurality of display island areas A11 may be continuously arranged. The shapes and sizes of the plurality of light-transmitting areas A12 may be substantially the same; the shapes and sizes of the plurality of display island areas A11 may be substantially the same. The second direction may be the width direction of the display panel 10, and correspondingly, the third direction is the length direction of the display panel 10. The second direction may also be the length direction of the display panel 10, and correspondingly, the third direction is the width direction of the display panel 10.

[0086] Further, as Figure 4b shown, each sub-pixel P may correspond to a pixel circuit 401; each display island area A11 may include four sub-pixels P and four pixel circuits 401, and the four sub-pixels P and the four pixel circuits 401 are arranged in one-to-one correspondence. The four pixel circuits 401 in each display island area A11 may be arranged in sequence along the second direction; the four sub-pixels P may include one red sub-pixel P1, two green sub-pixels P2, and one blue sub-pixel P3.

[0087] As Figure 4c shown, Figure 4c is Figure 4b a positional relationship diagram of the isolation column 300 and the sub-pixel P in the display island area A11 in Figure 4a The embodiments shown in Figure 4c and the embodiments shown in Figure 4a reflect different pixel arrangement methods on the pixel island area A11. In the embodiment shown in Figure 4c the pixel opening 211 is hexagonal, and the isolation column 300 surrounds each sub-pixel P; in the embodiment shown in

[0088] In the first embodiment of the present application, as Figure 2aAs shown, the driving circuit layer 400 further includes a first gate insulating layer 420 (GI1), a second gate insulating layer 430 (GI2), and an interlayer insulating layer 440 (ILD) sequentially arranged in a direction away from the substrate 100; the thin film transistor 410 includes a first electrode 411, a second electrode 412, a gate 413, and an active layer 414; the active layer 414 is disposed between the substrate 100 and the first gate insulating layer 420 and is covered by the first gate insulating layer 420; the gate 413 is disposed between the first gate insulating layer 420 and the second gate insulating layer 430 and is covered by the second gate insulating layer 430; the first electrode 411 and the second electrode 412 are arranged in the same layer on the side of the interlayer insulating layer 440 away from the substrate 100; a plurality of first through holes H1 are formed in the first gate insulating layer 420, the second gate insulating layer 430, and the interlayer insulating layer 440, and the first electrode 411 and the second electrode 412 are respectively connected to the active layer 414 through different first through holes H1.

[0089] A plurality of thin film transistors 410 are electrically connected to the anodes 240 of a plurality of sub-pixels P one by one, so as to drive the sub-pixels P to emit light one by one. Specifically, the first electrode 411 may be a source electrode, the second electrode 412 may be a drain electrode, or the first electrode 411 may be a drain electrode and the second electrode 412 may be a source electrode; the active layer 414 may include a first electrode contact region 4141, a second electrode contact region 4143, and a semiconductor region 4142. The first electrode contact region 4141 is in contact with the first electrode 411, the second electrode contact region 4143 is in contact with the second electrode 412, and the semiconductor region 4142 is disposed between the first electrode 411 and the second electrode 412.

[0090] In the first embodiment of the present application, as Figure 2a shown, the driving circuit layer 400 further includes a passivation layer 450, a plurality of data lines 460, and a conductive connection layer 470; the passivation layer 450 is disposed on the side of the first electrode 411 and the second electrode 412 away from the substrate 100 and covers the first electrode 411, the second electrode 412, and the interlayer insulating layer 440; the plurality of data lines 460 are arranged in the same layer as the gate 413; the conductive connection layer 470 is disposed between the passivation layer 450 and the light-emitting functional layer 200; a plurality of second through holes H2 are formed in the second gate insulating layer 430, the interlayer insulating layer 440, and the passivation layer 450, and adjacent data lines 460 are respectively electrically connected to the conductive connection layer 470 through different second through holes H2.

[0091] Optionally, the material of the data line 460 may be the same as the material of the gate 413, so that the data line 460 and the gate 413 can be formed by one preparation, which is beneficial to improving production efficiency; the material of the conductive connection layer 470 may be ITO, and ITO is a transparent material, which is beneficial to improving the light transmittance of the display panel 10.

[0092] In the first embodiment of the present application, as Figure 2a shown, the driving circuit layer 400 further includes a second planar layer 480; the second planar layer 480 is disposed between the first planar layer 250 and the conductive connection layer 470, and covers the passivation layer 450 and the conductive connection layer 470; a plurality of isolation posts 300 are disposed on a side of the second planar layer 480 away from the substrate 100 and are in contact with the second planar layer 480.

[0093] A plurality of third through holes H3 are formed in the first planar layer 250, the second planar layer 480, and the passivation layer 450, and the anodes 240 of the plurality of sub-pixels P are respectively electrically connected to the second electrodes 412 of the thin film transistors 410 through different third through holes H3.

[0094] Optionally, as Figure 2b shown, both the pixel defining layer 210 and the first planar layer 250 are disconnected at the isolation posts 300 to form a nested opening (as shown by the dashed line box in Figure 2b ), that is, the isolation post opening W. The orthographic projection of the isolation post opening W on the substrate 100 covers the orthographic projection of the isolation posts 300 on the substrate 100, so that the bottom surface of the isolation posts 300 is in contact with the top surface of the second planar layer 480.

[0095] In the first embodiment of the present application, as Figure 2a shown, the display panel 10 further includes a first inorganic layer 500 (CVD) and a buffer layer 600 (Buffer); the first inorganic layer 500 is formed on a side of the cathode 220 away from the substrate 100 and covers the cathode 220; the first inorganic layer 500 extends to the side surface of the isolation posts 300 and is disconnected at the isolation posts 300; the buffer layer 600 is disposed between the substrate 100 and the active layer 414. The first inorganic layer 500 can be used as a packaging layer to block water and oxygen and protect the display panel 10. Since the first inorganic layer 500 is disconnected at the isolation posts 300, when the isolation posts 300 are arranged as Figure 4a shown, the first inorganic layer 500 can achieve separate packaging of the plurality of sub-pixels P.

[0096] The difference between the display panel 10 of the second embodiment of the present application and the display panel 10 of the first embodiment of the present application is that the structure of the isolation posts 300 is different. The isolation posts 300 in the display panel 10 of the first embodiment of the present application are of a four-layer structure, and the isolation posts 300 in the display panel 10 of the second embodiment of the present application are of a three-layer structure.

[0097] In the second embodiment of the present application, as Figure 5 and Figure 6 shown, Figure 5 is a schematic structural diagram of the display panel 10 of the second embodiment of the present application, Figure 6 is Figure 5Schematic structural diagram of the isolation column 300 in the illustrated embodiment. The isolation column 300 includes a fifth sub-isolation layer 315, a sixth sub-isolation layer 316, and a seventh sub-isolation layer 317, which are sequentially arranged in a direction away from the substrate 100. In the first direction, the sixth sub-isolation layer 316 is indented inward relative to the fifth sub-isolation layer 315 and the seventh sub-isolation layer 317 to form an undercut structure. Each cathode 220 is formed in the corresponding pixel opening 211, extends outward from the pixel opening 211 to the side of the isolation column 300, and is in contact with the edge of the fifth sub-isolation layer 315. The fifth sub-isolation layer 315 is a conductive structure 301. Forming the undercut structure can effectively disconnect the light-emitting layer 230. The fifth sub-isolation layer 315 connects the cathodes 220 of adjacent sub-pixels P, thereby ensuring the normal display of the display panel 10.

[0098] Optionally, the materials of the fifth sub-isolation layer 315 and the seventh sub-isolation layer 317 can be ITO; the materials of the sixth sub-isolation layer 316 and the first planarization layer 250 can be the same, both being organic substances. In this way, the sixth sub-isolation layer 316 and the first planarization layer 250 can be formed by one preparation. The isolation column 300 can be prepared with a transparent material, thereby improving the light transmittance of the display panel 10. Ensure the light transmittance of the first display area A1 at a high PPI (pixel density), which is beneficial to the normal operation of the camera disposed in the first display area A1.

[0099] In the second embodiment of the present application, as Figure 6 shown, the sides of the fifth sub-isolation layer 315 and the sixth sub-isolation layer 316 are sloped surfaces. In the first direction, the cross-sections of the fifth sub-isolation layer 315 and the sixth sub-isolation layer 316 are inverted trapezoidal structures.

[0100] In some other embodiments of the present application, the side of the fifth sub-isolation layer 315 can also be a vertical surface. In the first direction, the cross-section of the fifth sub-isolation layer 315 is a rectangular structure.

[0101] Optionally, as Figure 6 shown, the distance c by which the top surface of the sixth sub-isolation layer 316 is indented inward relative to the seventh sub-isolation layer 317 satisfies: c = 0.5 μm - 1 μm; the distance d by which the bottom surface of the sixth sub-isolation layer 316 is indented inward relative to the top surface of the fifth sub-isolation layer 315 satisfies: d > 1 μm; the range of the slope angle β of the side surface of the sixth sub-isolation layer 316 satisfies: β > 65°.

[0102] The display panel 10 of the third embodiment of the present application is different from the display panel 10 of the first embodiment of the present application in that, as Figure 7 shown, Figure 7Schematic diagram of the structure of the display panel 10 according to the third embodiment of the present application. The driving circuit layer 400 in the display panel 10 according to the third embodiment of the present application further includes a third electrode 415 connected to the second electrode 412, and the third electrode 415 is not provided in the display panel 10 according to the first embodiment of the present application.

[0103] In the third embodiment of the present application, as Figure 7 shown, the driving circuit layer 400 further includes a second planarization layer 480 (PLN2); the second planarization layer 480 is disposed between the light-emitting functional layer 200 and the conductive connection layer 470, and covers the passivation layer 450 (PVX) and the conductive connection layer 470; a plurality of isolation pillars 300 are disposed on a side of the second planarization layer 480 away from the substrate 100 and are in contact with the second planarization layer 480; the light-emitting functional layer 200 further includes a first planarization layer 250 (PLN1); the first planarization layer 250 is disposed between the anode 240 and the second planarization layer 480; the first planarization layer 250 is disconnected at the isolation pillars 300; the thin-film transistor 410 further includes a third electrode 415; the third electrode 415 is formed between the second planarization layer 480 and the first planarization layer 250; the third electrode 415 is respectively connected to the corresponding second electrode 412 and the anode 240. Optionally, the first planarization layer 250 and the second planarization layer 480 may be organic insulating layers, and the passivation layer 450 may be an inorganic insulating layer.

[0104] Optionally, the materials of the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313, and the fourth sub-isolation layer 314 may be Mo (molybdenum), Al (aluminum), Mo (molybdenum), and ITO (indium tin oxide) in sequence. When the third stage is divided into three layers, and the materials of the three layers are Mo, Al, and Mo in sequence along the direction away from the substrate 100, after depositing the three layers of Mo, Al, and Mo in sequence, the first sub-isolation layer 311, the second sub-isolation layer 312, the third sub-isolation layer 313, and the third electrode 415 can be formed by one etching, saving process steps and without adding additional film layers; at this time, the top surface height of the third electrode 415 can be the same as the superposition height of the first sub-isolation layer 311, the second sub-isolation layer 312, and the third sub-isolation layer 313; when the material of the anode 240 is also ITO, the fourth sub-isolation layer 314 and the anode 240 can be formed by one etching after depositing the ITO layer, saving process steps and without adding additional film layers.

[0105] As Figure 7 shown, a fourth set of holes H4 are formed on the second planarization layer 480 and the passivation layer 450; the third electrode 415 is electrically connected to the second electrode 412 through the fourth set of holes H4; a plurality of vias H5 are formed on the first planarization layer 250, and the anodes 240 of the plurality of sub-pixels P are respectively electrically connected to the third electrode 415 of the thin-film transistor 410 through different vias H5.

[0106] Multiple first electrodes 411 and multiple second electrodes 412 constitute a first source-drain metal layer (SD1), and multiple third electrodes 415 constitute a second source-drain metal layer (SD2). By setting a double-layer source-drain metal layer, more wiring can be arranged compared to setting only one first source-drain metal layer, thereby facilitating the display panel 10 to realize more functions.

[0107] like Figure 8 As shown, Figure 8 Flow chart of a method for preparing a display panel 10 according to an embodiment of the present application. An embodiment of the second aspect of the present application provides a method for preparing a display panel 10, which is used to prepare the display panel 10 according to any embodiment of the first aspect, including:

[0108] S1, providing a substrate 100;

[0109] S2, preparing a light-emitting functional layer 200 and a plurality of isolation columns 300 on the substrate 100;

[0110] like Figure 2a As shown, the light-emitting functional layer 200 is disposed on one side of the substrate 100, and includes a first flat layer 250 and a pixel defining layer 210; the pixel defining layer 210 has a plurality of pixel openings 211, and the plurality of pixel openings 211 are configured to accommodate a plurality of sub-pixels P, and the sub-pixels P include an anode 240, a light-emitting layer 230, and a cathode 220 sequentially disposed in a direction away from the substrate 100; the first flat layer 250 and the pixel defining layer 210 further include a plurality of isolation column openings W, and each isolation column opening W is located between two adjacent pixel openings 211;

[0111] Each of the plurality of isolation columns 300 is located in an isolation column opening W between two adjacent pixel openings 211 . The isolation column 300 is configured to isolate the light emitting layer 230 of two adjacent sub-pixels P and connect the cathodes 220 of two adjacent sub-pixels P.

[0112] By the method for preparing the display panel 10 of the embodiment of the present application, a display panel 10 is prepared, in which the isolation column 300 is configured to isolate the light-emitting layer 230 of two adjacent sub-pixels P and connect the cathode 220 of two adjacent sub-pixels P; the cathode 220 of two adjacent sub-pixels P is connected through the isolation column 300, thereby ensuring the normal light emission of the display panel 10; the light-emitting layer 230 of two adjacent sub-pixels P is isolated by the isolation column 300, thereby preventing the occurrence of crosstalk caused by the connection of the light-emitting layer 230 of two adjacent sub-pixels P, thereby improving the display effect.

[0113] The following describes the manufacturing methods of the display panel 10 of the first embodiment, the display panel 10 of the second embodiment, and the display panel 10 of the third embodiment of the present application respectively.

[0114] As shown in Figures 9 to 11 the figure below Figure 9 is a process flow chart of the preparation of the display panel 10 according to the first embodiment of the present application (steps 142 to 145); Figure 10 is a process flow chart of the preparation of the display panel 10 according to the first embodiment of the present application (steps 146 to 148); Figure 11 is a process flow chart of the preparation of the display panel 10 according to the first embodiment of the present application (steps 149 to 151). The preparation method of the display panel 10 according to the first embodiment of the present application Figure 2a shown in the figure

[0115] Step 11: Provide a substrate 100;

[0116] Step 12: Prepare a buffer layer 600 on the substrate 100;

[0117] Step 13: Prepare a driving circuit layer 400 on the buffer layer 600, including: sequentially preparing an active layer 414, a first gate insulating layer 420, a gate 413, a data line 460, a second gate insulating layer 430, an interlayer insulating layer 440, a first electrode 411 and a second electrode 412, a passivation layer 450, a conductive connection layer 470, and a second planarization layer 480;

[0118] Step 14: Prepare a light-emitting functional layer 200 and a plurality of isolation posts 300 on the driving circuit layer 400, including:

[0119] Step 141: As shown in Figure 9 the figure below, prepare a first planarization layer 250 on the second planarization layer 480. A plurality of first openings 251 are provided on the first planarization layer 250;

[0120] Step 142: As shown in Figure 9 the figure below, sequentially deposit a first sub-isolation film layer 710, a second sub-isolation film layer 720, a third sub-isolation film layer 730, and a fourth sub-isolation film layer 740; wherein, the first sub-isolation film layer 710, the second sub-isolation film layer 720, and the third sub-isolation film layer 730 are formed within the first openings 251, and the fourth sub-isolation film layer 740 covers the third sub-isolation film layer 730 and the first planarization layer 250 and fills the third set of holes H3 formed on the passivation layer 450, the second planarization layer 480, and the first planarization layer 250, and is connected to the second electrode 412;

[0121] Step 143: As shown in Figure 9 the figure below, etch the fourth sub-isolation film layer 740 to form a fourth sub-isolation layer 314 and an anode 240;

[0122] Step 144: As shown in Figure 9As shown, the first sub-isolation film layer 710, the second sub-isolation film layer 720, and the third sub-isolation film layer 730 are etched to form the first sub-isolation layer 311, the second sub-isolation layer 312, and the third sub-isolation layer 313. The first sub-isolation layer 311, the second sub-isolation layer 312, and the third sub-isolation layer 313 together with the fourth sub-isolation layer 314 form the isolation column 300;

[0123] Step 145, as Figure 9 shown, a pixel defining layer 210 is prepared on the anode 240. The pixel defining layer 210 has a plurality of pixel openings 211; the pixel defining layer 210 is disconnected at the isolation column 300 to form a second opening 212; the second opening 212 and the first opening 251 form the isolation column opening W;

[0124] Step 146, as Figure 10 shown, a red sub-light emitting film layer 810, a first cathode film layer 820, and a first inorganic film layer 830 are sequentially prepared on the plurality of isolation columns 300 and the pixel defining layer 210; among them, the red sub-light emitting film layer 810 and the first cathode film layer 820 are disconnected at the isolation column 300;

[0125] Optionally, the red sub-light emitting film layer 810 and the first cathode film layer 820 can be prepared by evaporation, and the first inorganic film layer 830 can be prepared by deposition;

[0126] Step 147, as Figure 10 shown, a PR glue 910 is deposited on the first sub-inorganic film layer, and the PR glue 910 is patterned. The PR glue 910 covers the area corresponding to the red sub-pixel P1 and plays a protective role;

[0127] Step 148, as Figure 10 shown, the red sub-light emitting film layer 810, the first cathode film layer 820, and the first inorganic film layer 830 are etched to form a red light emitting layer 231, a cathode 220 corresponding to the red sub-pixel P1, and an inorganic layer 831 corresponding to the red sub-pixel. The red sub-pixel P1 is prepared;

[0128] Step 149, as Figure 11 shown, a green sub-light emitting film layer 840, a second cathode film layer 850, and a second inorganic film layer 860 are sequentially prepared on the plurality of isolation columns 300, the pixel defining layer 210, and the red sub-pixel P1; among them, the green sub-light emitting film layer 840 and the second cathode film layer 850 are disconnected at the isolation column 300;

[0129] Optionally, the green sub-light emitting film layer 840 and the second cathode film layer 850 can be prepared by evaporation, and the second inorganic film layer 860 can be prepared by deposition;

[0130] Step 150, asFigure 11 As shown, a PR glue 910 is deposited on the second inorganic film layer 860, and the PR glue 910 is patterned. The PR glue 910 covers the area corresponding to the green sub-pixel P2;

[0131] Step 151: As Figure 11 shown, the green sub-light-emitting film layer 840, the second cathode film layer 850, and the second inorganic film layer 860 are etched to form a green light-emitting layer 232, a cathode 220 corresponding to the green sub-pixel P2, and an inorganic layer 861 corresponding to the green sub-pixel;

[0132] Step 152: A blue sub-light-emitting film layer (not shown in the figure), a third cathode film layer (not shown in the figure), and a third inorganic film layer (not shown in the figure) are sequentially prepared on the plurality of isolation posts 300, the pixel defining layer 210, the red sub-pixel P1, and the green sub-pixel P2; wherein, the blue sub-light-emitting film layer and the third cathode film layer are disconnected at the isolation posts 300;

[0133] Optionally, the blue sub-light-emitting film layer and the third cathode film layer are prepared by evaporation, and the third inorganic film layer is prepared by deposition;

[0134] Step 153: A PR glue 910 is deposited on the third sub-inorganic film layer, and the PR glue 910 is patterned. The PR glue 910 covers the area corresponding to the blue sub-pixel P3, playing a protective role;

[0135] Step 154: The blue sub-light-emitting film layer, the third cathode 220 film layer, and the third inorganic film layer are etched to form a blue light-emitting layer, a cathode 220 corresponding to the blue sub-pixel P3, and an inorganic layer (not shown in the figure) corresponding to the blue sub-pixel;

[0136] The inorganic layer 831 corresponding to the red sub-pixel, the inorganic layer 861 corresponding to the green sub-pixel, and the inorganic layer corresponding to the blue sub-pixel are arranged in the same layer, jointly constituting the first inorganic layer 500;

[0137] The preparation is completed.

[0138] It can be understood that in the preparation method of the display panel 10 in the first embodiment of the present application, taking the sequential preparation of the red sub-pixel P1, the green sub-pixel P2, and the blue sub-pixel P3 as an example, in some other embodiments of the present application, other sequences can also be adopted, and the present application does not limit this.

[0139] As Figure 12 shown, Figure 12 is the process flow chart of the preparation of the display panel 10 in the second embodiment of the present application. The preparation method of the display panel 10 in the second embodiment of the present application ( Figure 5 shown in the embodiment) includes the following steps:

[0140] Step 21: Provide a substrate 100;

[0141] Step 22: Prepare a buffer layer 600 on the substrate 100;

[0142] Step 23: Prepare a driving circuit layer 400 on the buffer layer 600, including: successively preparing an active layer 414, a first gate insulating layer 420, a gate 413 and a data line 460, a second gate insulating layer 430, an interlayer insulating layer 440, a first electrode 411 and a second electrode 412, a passivation layer 450, a conductive connection layer 470 and a second planarization layer 480;

[0143] Step 24: Prepare a light-emitting functional layer 200 and a plurality of isolation pillars 300 on the driving circuit layer 400, including:

[0144] Step 241: As shown in Figure 12 Prepare a fifth sub-isolation film layer (not shown in the figure) on the second planarization layer 480, and etch the fifth sub-isolation film layer to form a fifth sub-isolation layer 315;

[0145] Step 242: Prepare a sixth sub-isolation film layer 760 on the fifth sub-isolation layer 315, and etch to form a third set of holes H3 penetrating through the passivation layer 450, the second planarization layer 480 and the sixth sub-isolation film layer 760;

[0146] Step 243: As shown in Figure 12 Prepare a seventh sub-isolation film layer 770 on the sixth sub-isolation film layer 760, and the seventh sub-isolation film layer 770 is connected to the second electrode 412 of the thin film transistor 410 through the third set of holes H3;

[0147] Step 244: As shown in Figure 12 Etch the seventh sub-isolation film layer 770 to form a seventh sub-isolation layer 317 and an anode 240;

[0148] Step 245: As shown in Figure 12 Etch the sixth sub-isolation film layer 760 to form a sixth sub-isolation layer 316 and a first planarization layer 250; The sixth sub-isolation layer 316, the seventh sub-isolation layer 317 and the fifth sub-isolation layer 315 together constitute the isolation pillar 300; A plurality of first openings 251 are provided on the planarization layer 250; The isolation pillar 300 is formed in the first opening 251;

[0149] The steps of subsequently preparing other film layers of the light-emitting functional layer 200 and the first inorganic layer 500 are the same as those in the preparation method of the display panel 10 in the first embodiment of the present application, and will not be described herein again.

[0150] The preparation method of the display panel 10 according to the third embodiment of the present application includes the following steps:

[0151] Step 11: Provide a substrate 100;

[0152] Step 12: Prepare a buffer layer 600 on the substrate 100;

[0153] Step 13: Prepare a driving circuit layer 400 on the buffer layer 600, including: sequentially preparing an active layer 414, a first gate insulating layer 420, a gate 413 and a data line 460, a second gate insulating layer 430, an interlayer insulating layer 440, a first electrode 411 and a second electrode 412, a passivation layer 450, a conductive connection layer 470, a second planarization layer 480 and a third electrode 415;

[0154] The subsequent steps of preparing a light-emitting functional layer 200 and a plurality of isolation pillars 300 on the driving circuit layer 400 are the same as those in the preparation method of the display panel 10 in the first embodiment of the present application, and will not be described in detail here.

[0155] In the related art, the display panel 10 is usually prepared by using the FMM (Fine Metal Mask) technology, which has the disadvantages of high cost and low pixel density. The preparation method of the display panel 10 in the embodiment of the present invention does not require the use of FMM, which is beneficial to improving the pixel density of the display panel 10 and reducing the cost.

[0156] As Figure 13 shown, Figure 13 is a schematic structural diagram of a display device according to an embodiment of the present application. A third aspect of the present application provides a display device, including the display panel 10 of any one of the first aspect embodiments, and a sensor 20 located on the non-display surface side of the display panel 10. The orthographic projection of the sensor 20 on the display panel 10 overlaps at least partially with the first display area A1.

[0157] In the display device according to the embodiment of the present application, the isolation pillars 300 of the display vertical panel included therein are configured to partition the light-emitting layers 230 of two adjacent sub-pixels P and connect the cathodes 220 of two adjacent sub-pixels P; the cathodes 220 of two adjacent sub-pixels P are connected through the isolation pillars 300, thereby ensuring the normal light emission of the display panel 10; the light-emitting layers 230 of two adjacent sub-pixels P are partitioned by the isolation pillars 300, preventing the occurrence of crosstalk caused by the connection of the light-emitting layers 230 of two adjacent sub-pixels P, thereby improving the display effect.

[0158] It can be understood that, as Figure 13 shown in the perspective, the display surface side of the display panel 10 is the upper side, which is the light-emitting side of the display panel 10, and the non-display surface side is the lower side. The sensor 20 can be hardware such as a camera. Preferably, as Figure 13As shown, the orthographic projection of the sensor 20 on the display panel 10 may be within the range of the first display area A1 of the display panel 10. Such a setting facilitates the normal operation of the sensor 20. As Figure 1 and Figure 13 shown, the first display area A1 may be circular, and the size of the orthographic projection of the sensor 20 on the display panel 10 may be smaller than the size of the first display area A1. In some other embodiments of the present application, the size of the orthographic projection of the sensor 20 on the display panel 10 may also be equal to the size of the first display area A1, and the present application does not limit this.

[0159] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0160] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0161] The above is only the preferred embodiment of the present invention and is not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A display panel, It is characterized in that The display panel comprises a display area and a peripheral area surrounding the display area, the display area comprises a first display area and a second display area, and the second display area is located at least on one side of the first display area; the display panel comprises: substrate; a light-emitting functional layer, the light-emitting functional layer being arranged on one side of the substrate, comprising a first flat layer and a pixel defining layer; the pixel defining layer having a plurality of pixel openings, the plurality of pixel openings being configured to accommodate a plurality of sub-pixels, the sub-pixels comprising an anode, a light-emitting layer and a cathode sequentially arranged in a direction away from the substrate; the first flat layer and the pixel defining layer further comprising a plurality of isolation column openings, each of the isolation column openings being located between two adjacent pixel openings; A plurality of isolation columns, each of the plurality of isolation columns is located in the isolation column opening between two adjacent pixel openings, and the isolation column is configured to isolate the light-emitting layers of two adjacent sub-pixels and connect the cathodes of two adjacent sub-pixels.

2. The display panel according to claim 1, It is characterized in that The isolation column opening includes: a first opening penetrating the first planar layer and a second opening penetrating the pixel defining layer, and the first opening is connected to the second opening; The isolation column is located in the first opening.

3. The display panel according to claim 1, It is characterized in that The isolation column comprises: a first sub-isolation layer, a second sub-isolation layer, a third sub-isolation layer and a fourth sub-isolation layer which are sequentially arranged in a direction away from the substrate; In a first direction, the second sub-isolating layer is retracted inwardly relative to the first sub-isolating layer; the third sub-isolating layer is retracted inwardly relative to the second sub-isolating layer and the fourth sub-isolating layer to form an undercut structure; The second sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the second sub-isolating layer.

4. The display panel according to claim 3, It is characterized in that The orthographic projection of the fourth sub-isolation layer on the substrate covers the orthographic projection of the first sub-isolation layer on the substrate.

5. The display panel according to claim 3, It is characterized in that The side surfaces of the first sub-isolating layer and the second sub-isolating layer are sloped surfaces; In the first direction, cross sections of the first sub-isolating layer and the second sub-isolating layer are both upright trapezoidal structures.

6. The display panel according to claim 1, It is characterized in that The isolation column comprises: a fifth sub-isolation layer, a sixth sub-isolation layer and a seventh sub-isolation layer which are sequentially arranged in a direction away from the substrate; In the first direction, the sixth sub-isolating layer is retracted inwardly relative to the fifth sub-isolating layer and the seventh sub-isolating layer to form an undercut structure; The fifth sub-isolating layer is a conductive structure, and cathodes of two adjacent sub-pixels are connected through the fifth sub-isolating layer.

7. The display panel according to claim 6, It is characterized in that The side surface of the fifth sub-isolating layer is a slope surface or a vertical surface; The side surface of the sixth sub-isolation layer is a slope surface; In the first direction, the cross-section of the fifth sub-isolation layer is a right trapezoidal structure or a rectangular structure; the cross-section of the sixth sub-isolation layer is a right trapezoidal structure.

8. The display panel according to any one of claims 1 to 7, wherein, each of the isolation pillars surrounds one of the sub-pixels; the isolation pillars of two adjacent sub-pixels are connected to each other.

9. The display panel according to claim 8, wherein, the display panel further includes: a driving circuit layer; the driving circuit layer is disposed between the substrate and the light-emitting functional layer; the driving circuit layer includes a plurality of thin-film transistors; the plurality of thin-film transistors are electrically connected to the anodes of the plurality of sub-pixels in a one-to-one correspondence; the driving circuit layer further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer that are sequentially disposed in a direction away from the substrate; the thin-film transistor includes: a first pole, a second pole, a gate, and an active layer; the active layer is disposed between the substrate and the first gate insulating layer; the gate is disposed between the first gate insulating layer and the second gate insulating layer; the first pole and the second pole are disposed in the same layer on a side of the interlayer insulating layer away from the substrate; a plurality of first through-holes are formed in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, and the first pole and the second pole are respectively connected to the active layer through different ones of the first through-holes.

10. The display panel according to claim 9, wherein, the driving circuit layer further includes: a passivation layer, a plurality of data lines, and a conductive connection layer; the passivation layer is disposed on a side of the first pole and the second pole away from the substrate; the plurality of data lines are disposed in the same layer as the gate; the conductive connection layer is disposed between the passivation layer and the light-emitting functional layer; a plurality of second through-holes are formed in the second gate insulating layer, the interlayer insulating layer, and the passivation layer, and adjacent data lines are respectively electrically connected to the conductive connection layer through different ones of the second through-holes.

11. The display panel according to claim 10, wherein, the driving circuit layer includes: a second planarization layer; the second planarization layer is disposed between the first planarization layer and the conductive connection layer; the plurality of isolation pillars are disposed on a side of the second planarization layer away from the substrate and are in contact with the second planarization layer.

12. The display panel according to claim 9, wherein, the display panel further includes: a first inorganic layer and a buffer layer; the first inorganic layer is formed on a side of the cathode away from the substrate and covers the cathode; the first inorganic layer extends to the side surface of the isolation pillar and is disconnected at the isolation pillar; the buffer layer is disposed between the substrate and the active layer.

13. The display panel according to claim 1, wherein, the plurality of sub-pixels are respectively located in the first display area and the second display area, and the pixel density of the sub-pixels in the first display area is less than or equal to the pixel density of the sub-pixels in the second display area.

14. The display panel according to claim 1, wherein, The light transmittance of the first display area is greater than that of the second display area.

15. A display device, characterized in that it includes the display panel according to any one of claims 1 to 14, and a sensor located on the non-display surface side of the display panel, and the orthographic projection of the sensor on the display panel at least partially overlaps with the first display area.

Images