Display driving apparatus for reducing power consumption and operating method thereof

Abstract

A display driving apparatus is disclosed. The display driving apparatus includes a reception circuit configured to receive first display data including a first set of data values, a transmission control circuit configured to output the first display data or output second display data including a second set of data values according to a result of comparing the first set of data values with target data values, and a data processing circuit configured to process the first display data or the second display data output from the transmission control circuit, wherein the transmission control circuit includes an inversion circuit configured to bypass the first display data to the data processing circuit if the first set of data values are not identical to the target data values, respectively, and configured to convert the first set of data values to the second set of data values, respectively, and output the second display data including the second set of data values to the data processing circuit if the first set of data values are identical to the target data values, respectively, the second set of data values having values complementary to the first set of data values, respectively.

Description

Technical Field

[0001] This invention relates to semiconductor integrated circuits, and more particularly to display driving devices for display devices.

[0002] For the sake of simplicity, this specification describes a source driver integrated circuit (IC) as an example of a display driving device, but the present invention can be applied to any type of display driving device. Background Technology

[0003] Source driver integrated circuits (ICs) used to drive data lines included in display devices include digital-to-analog converters (DACs, hereinafter referred to as "DACs") and level shifters.

[0004] In order to control the on or off state of each switch included in the DAC and consuming dynamic current, each level shifter shifts the voltage level of each input digital video signal to generate an output digital video signal with a shifted voltage level.

[0005] In response to an output digital video signal with a shifted voltage level from a level shifter, a switch in the DAC outputs one of the grayscale voltages generated by a grayscale voltage generator to one of the data lines.

[0006] However, as the resolution of display devices increases, the number of source driver ICs also increases proportionally, and with the increase in the number of source driver ICs, the number of level shifters also increases. This leads to an increase in current consumption due to level shifters, resulting in an increase in the power consumption of the source driver ICs. Summary of the Invention

[0007] Technical issues

[0008] To address the aforementioned problems, the present invention aims to provide a source driver IC capable of reducing power consumption by inverting specific display data values, a display device including the source driver IC, and a method for reducing the power consumption of the source driver IC.

[0009] Technical solution

[0010] According to one aspect of the present invention, a display driving device for overcoming the above-mentioned technical problems includes: a receiving circuit configured to receive first display data including a first set of data values; a transmission control circuit configured to output the first display data or second display data including a second set of data values ​​based on a comparison result between the first set of data values ​​and a target data value; and a data processing circuit configured to process the first display data or the second display data output from the transmission control circuit, wherein the transmission control circuit includes an inversion circuit configured to bypass the first display data to the data processing circuit when the first set of data values ​​is not identical to the target data value, to convert the first set of data values ​​into second set of data values ​​complementary to the first set of data values ​​when the first set of data values ​​is identical to the target data value, and to output the second display data including the second set of data values ​​to the data processing circuit.

[0011] According to another aspect of the present invention, an operation method of a display driving device for overcoming the above-mentioned technical problems includes: receiving first display data including a first set of data values; determining whether the first set of data values ​​is the same as target data values; bypassing the first display data when the first set of data values ​​is not the same as the target data values ​​respectively; and outputting second display data including a second set of data values ​​instead of the first set of data values ​​when the first set of data values ​​is the same as the target data values ​​respectively, wherein the second set of data values ​​is complementary to the first set of data values ​​respectively.

[0012] Beneficial effects

[0013] According to the present invention, by dynamically inverting specific display data values, the power consumption of the digital-to-analog converter (DAC) can be reduced, and by reducing the power consumption of the DAC, the power consumption of the source driver IC can be reduced. Attached Figure Description

[0014] Figure 1 This is a block diagram of a display device including a source driver IC according to an embodiment of the present invention.

[0015] Figure 2 yes Figure 1 The block diagram shown is of the source driver IC.

[0016] Figure 3 This is a timing diagram illustrating the operation of a latch circuit that latches data provided to... Figure 2 Odd and even data of the source driver IC.

[0017] Figure 4 Showing includes Figure 2An example of a circuit diagram of the inverting circuit in the transfer control circuit of a source driver IC.

[0018] Figure 5 It is used for explanation Figure 4 An example of displaying data for the operation of the inverting circuit shown.

[0019] Figure 6 It is used for explanation Figure 4 Another embodiment of the operation of the inverting circuit shown displays data.

[0020] Figure 7 Showing includes Figure 2 An example of a transfer control circuit in a source driver IC, which includes a determining circuit and an inverting circuit.

[0021] Figure 8a It is shown Figure 7 The table shown illustrates the operation of the selection signal generation circuit.

[0022] Figure 8b It is shown Figure 2 The table shows the input and output signals of each of the first and second data processing circuits.

[0023] Figure 8c Exemplary Figure 2 The level of each grayscale voltage shown.

[0024] Figure 9 Is included Figure 2 The circuit diagram of the first level shifter in the source driver IC.

[0025] Figure 10 Is included Figure 2 The circuit diagram of the second level shifter in the source driver IC.

[0026] Figure 11 This is a flowchart illustrating the operation of a transmission control circuit according to an embodiment of the present invention.

[0027] Figure 12 It is shown Figure 7 The flowchart shown illustrates the operation of the transmission control circuit. Detailed Implementation

[0028] Throughout this specification, the same reference numerals denote substantially the same parts. In the following description, detailed descriptions of configurations and features known in the art may be omitted if they are not relevant to the core configuration of the invention. The terminology used in this specification should be understood as follows.

[0029] The advantages and features of the present invention, as well as methods of implementing them, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but can be implemented in various different forms; rather, these embodiments are provided to make the description of the invention complete and to allow those skilled in the art to fully understand the scope of the invention, which is limited only by the scope of the appended claims.

[0030] The shapes, dimensions, proportions, angles, quantities, etc., shown in the accompanying drawings for illustrative purposes are merely examples, and the invention is not limited thereto. Throughout the specification, the same reference numerals may denote the same parts. Furthermore, in describing the invention, detailed descriptions of known related technologies may be omitted if it is deemed unnecessary to obscure the essence of the invention.

[0031] Terms such as “including,” “having,” and “containing” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise specified, references to components of a singular noun include the plural of that noun.

[0032] When interpreting components, they are interpreted as including a tolerance range, even if not explicitly stated.

[0033] When describing positional relationships, such as “on top of,” “above,” “below,” or “beside,” one or more other parts may be located between the two parts unless “immediately adjacent” or “directly” is used.

[0034] When describing temporal context, such as “after,” “following,” “next,” or “before,” non-continuous cases can also be included unless “immediately following” or “directly” is used.

[0035] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the scope of the inventive concept, the "first component" mentioned herein can also be the "second component."

[0036] It should be understood that the term "at least one" includes any combination that can be presented from one or more related items. For example, "at least one of the first, second, and third items" can mean each of the first, second, and third items, as well as any combination of two or more items that can be presented from the first, second, and third items.

[0037] Each feature of the various embodiments of the present invention may be coupled or combined with each other in whole or in part, and may be technically interlocked and operated in various ways, and each embodiment may be performed independently or in combination with each other.

[0038] In the following, embodiments of this application will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram of a display device including a source driver IC according to an embodiment of the present invention.

[0040] refer to Figure 1 The display device 1000 includes a display panel 1100, a source driver IC block 1200, a gate driver IC block 1300, and a timing controller 1400.

[0041] Display device 1000 may be a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, or an active-matrix organic light-emitting diode (AMOLED) display. For example, display device 1000 may be a notebook computer, but is not limited thereto.

[0042] The display panel 1100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels PX. The multiple pixels PX are connected to each of the gate lines GL and each of the data lines DL, and are arranged in a matrix.

[0043] The source driver IC block 1200 includes multiple source driver ICs 100 and 100_1 that drive the data lines DL. In one embodiment, the data lines DL can be referred to as channels, and the source driver ICs 100 and 100_1 can be referred to as data driver ICs.

[0044] For example, the first source driver IC 100 drives the first group of data lines DL1 in the data line DL, and the second source driver IC 100_1 drives the second group of data lines DL2 in the data line DL. Assume that the source driver ICs 100 and 100_1 have the same structure.

[0045] Gate driver IC block 1300 includes multiple gate driver ICs 1301 and 1302 that generate gate drive signals to drive gate line GL.

[0046] For example, the first gate driver IC 1301 generates a first gate drive signal for driving the first group of gate lines GL1 in the gate lines GL, and the second gate driver IC 1302 generates a second gate drive signal for driving the second group of gate lines GL2 in the gate lines GL. Assume that the gate driver ICs 1301 and 1302 have the same structure.

[0047] The timing controller 1400 generates gate drive control signals GCTL for controlling the operation of each of the multiple gate driver ICs 1301 and 1302, and outputs them to the multiple gate driver ICs 1301 and 1302.

[0048] In addition, the timing controller 1400 generates clock signal CLK, display data DATA, and source drive control signal SCTL, and outputs them to multiple source driver ICs 100 and 100_1.

[0049] Figure 2 yes Figure 1 The block diagram shown is of the source driver IC.

[0050] refer to Figure 1 and Figure 2 Since the source driver ICs 100 and 100_1 have the same structure, the reference will be used. Figures 1 to 11 The structure and operation of the first source driver IC 100 are described in detail.

[0051] The first source driver IC (or first source driver IC package) 100 includes a control logic circuit 202, a first data processing circuit (or odd data processing circuit) 205_1, a second data processing circuit (or even data processing circuit) 205_2, and a grayscale voltage generation circuit 300.

[0052] The control logic circuit 202 includes a receiving circuit 203 and a transmission control circuit 400. Although Figure 2 Not shown, but the control logic circuit 202 may also include a configuration for generating a first latch enable signal EN1 and a second latch enable signal EN2 using the source drive control signal SCTL.

[0053] The receiving circuit 203 uses the clock signal CLK to receive display data (e.g., RGB data) DATA and transmits the received display data to the transmission control circuit 400. In this case, the display data may be first display data including a first set of data values.

[0054] When the first display data is received from the receiving circuit 203, based on the comparison result between the first set of data values ​​and the target data value, the transmission control circuit 400 outputs the first display data to the first data processing circuit 205_1 or the second data processing circuit 205_2, or outputs the second display data including the second set of data values ​​to the first data processing circuit 205_1 or the second data processing circuit 205_2. In one embodiment, the transmission control circuit 400 may include a determining circuit 400B and an inverting circuit 400A.

[0055] In the following text, reference will be made to Figure 11 Briefly describe the operation of the transmission control circuit 400 of the present invention. Figure 11 This is a flowchart illustrating the operation of a transmission control circuit according to an embodiment of the present invention. (Reference) Figure 2 and Figure 11 The transmission control circuit 400 receives first display data DATA including a first set of data values ​​from the receiving circuit 203 (S110), and determines whether the first set of data values ​​is the same as the target data value (S120). If it is determined that the first set of data values ​​is different from the target data value ("No" in S120), the transmission control circuit 400 will display the first display data DATA (=ODDi) as... <n:1>or EVENI <n:1>The data is bypassed to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S130). On the other hand, as a result of the determination in step S120, if the first set of data values ​​is the same as the target data value ("Yes" in step S120), the transmission control circuit 400 will include the second set of data values ​​instead of the first set of data values ​​as the second display data ODDi. <n:1>or EVENI <n:1>The data is output to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S140).

[0056] For example, even if the first data processing circuit 205_1 receives the first display data ODDi including the first set of data values <n:1>Or include the second set of data values ​​in the second display data ODDi <n:1>The first data processing circuit 205_1 also outputs the gray voltage corresponding to the first set of data values ​​from the first set of gray voltages VGMA_VH0 to VGMA_VH255 as the first output signal OUT1.

[0057] Furthermore, even if the second data processing circuit 205_2 receives the first display data EVENI including the first set of data values... <n:1>Or include the second set of data values ​​in the second display data EVENI <n:1>The second data processing circuit 205_2 also outputs the grayscale voltages from the second set of grayscale voltages VGMA_VL0 to VGMA_VL255 that correspond to the data values ​​in the first set as the second output signal OUT2.

[0058] exist Figure 8c The image exemplarily shows the level of each of the first set of grayscale voltages VGMA_VH0 to VGMA_VH255 and the level of each of the second set of grayscale voltages VGMA_VL0 to VGMA_VL255.

[0059] According to an embodiment, the data value can be either data 1 or data 0.

[0060] According to the embodiment, the target data values ​​can all be the same. For example, when N is 8 and the target data value that is the same as the first set of data values ​​is 00000000 (or 11111111), the second set of data values ​​is 11111111 (or 00000000).

[0061] According to an embodiment, when only one of the target data values ​​is one of data 1 and data 0, each of the remaining target data values ​​can be the other of data 1 and data 0.

[0062] For example, when N is 8 and the target data values ​​that are the same as the first set of data values ​​are 00000001, 00000010, 00000100, 00001000, 00100000, 0100000, or 10000000, the second set of data values ​​are 11111110, 11111101, 11111011, 11110111, 11101111, 11011111, 10111111, or 01111111.

[0063] The second set of data values ​​is complementary to the first set of data values. For example, data 1 (also known as logic 1) and data 0 (also known as logic 0) are considered to be complementary to each other.

[0064] Figure 3 This is a timing diagram illustrating the operation of a latch circuit that latches data provided to... Figure 2 Odd and even data of the source driver IC.

[0065] From the perspective of timing the display data DATA input to the control logic circuit 202, Figure 3 Each of the displayed data ODD1 is shown <n:1>、EVEN1 <n:1>、ODD2 <n:1>、EVEN2 <n:1>... means displaying data continuously (or serially) (or displaying a data stream).

[0066] For example, each display data ODD1 <n:1>、EVEN1 <n:1>、ODD2 <n:1>、EVEN2 <n:1>... represents N-bit serial display data, where each of the N bits is either data 1 or data 0, with data 1 having a high voltage level and data 0 having a low voltage level.

[0067] refer to Figure 2 and Figure 3 The transmission control circuit 400 of the control logic circuit 202 uses the clock signal CLK to extract (or separate) odd data ODDi from the serial input display data DATA. <n:1>And even data EVENI <n:1>And the extracted data ODDi is divided in a time-division manner. <n:1>or EVENI <n:1>The output is sent to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0068] Therefore, assuming that in response to the first latch enable signal EN1, when the first data processing circuit 205_1 operates, the second data processing circuit 205_2 does not operate, and when the second data processing circuit 205_2 operates, the first data processing circuit 205_1 does not operate.

[0069] The first data processing circuit 205_1 receives odd-numbered data ODDi output from the transmission control circuit 400. <n:1>The data is processed (e.g., sequentially performing latch operations, serial-to-parallel conversion operations, voltage level shifting operations, and digital-to-analog conversion operations), and the processing result OUT1 is output to one of the first data lines DL1. Here, N and i are natural numbers.

[0070] The second data processing circuit 205_2 receives even-numbered data EVENI output from the transmission control circuit 400. <n:1>The data is processed (e.g., sequentially performing latching operations, serial-to-parallel conversion operations, voltage level shifting operations, and digital-to-analog conversion operations), and the processing result OUT2 is output to another line in the first data line DL1.

[0071] The first data processing circuit 205_1 includes a first latch circuit 210_1, a second latch circuit 220_1, a first level shifter circuit 230_1, a first DAC 240_1, and a first output buffer 250_1.

[0072] The first latch circuit 210_1 includes first latches 212_1 to 212_8, and latches (or converts) 8-bit serial odd data ODDi<8:1> into 8-bit parallel odd data LH1_1 to LH1_8 in response to the first latch enable signal EN1.

[0073] In one embodiment, each of the first latches 212_1 to 212_8 can be a D flip-flop capable of latching a 1-bit data value, and the first latch enable signal EN1 can be a parallel signal that starts at different timings, such as... Figure 3 As shown.

[0074] During the first operation time TI1, when the 8-bit first odd serial data ODD1<8:1> is sequentially input to the first latch circuit 210_1, the first latches 212_1 to 212_8 latch the corresponding data ODD1 in response to the corresponding first latch enable signal EN1. <1> To ODD1 <8> And output the latched data LH1_1 to LH1_8 to the second latch circuit 220_1.

[0075] The second latch circuit 220_1 includes second latches 222_1 to 222_8, and the second latches 221_1 to 222_8 latch corresponding data LH1_1 to LH1_8 in response to the second latch enable signal EN2, and output the latched data 2LH1_1 to 2LH1_8 to the first level shifter circuit 230_1.

[0076] The second data processing circuit 205_2 includes a third latch circuit 210_2, a fourth latch circuit 220_2, a second level shifter circuit 230_2, a second DAC 240_2, and a second output buffer 250_2.

[0077] The third latch circuit 210_2 includes third latches 214_1 to 214_8, and latches (or converts) 8-bit serial even data EVENi<8:1> into 8-bit parallel even data LH2_1 to LH2_8 in response to the first latch enable signal EN1.

[0078] For example, each of the third latches 214_1 to 214_8 can be a D flip-flop capable of latching a 1-bit data value, and the first latch enable signal EN1 can be a parallel signal that starts at different timings, such as... Figure 3 As shown.

[0079] The start timing of each first latch enable signal EN1 provided to the first latch circuit 210_1 is different from the start timing of each first latch enable signal EN1 provided to the third latch circuit 210_2. Therefore, when the first latch circuit 210_1 operates, the third latch circuit 210_2 does not operate.

[0080] During the second operation time TI2, when the 8-bit first even-numbered serial data EVEN1<8:1> is sequentially input to the third latch circuit 210_2, the third latches 214_1 to 214_8 latch the corresponding data EVEN1 in response to the corresponding first latch enable signal EN1. <1> To EVEN1 <8> And output the latched data LH2_1 to LH2_8 to the fourth latch circuit 220_2.

[0081] The fourth latch circuit 220_2 includes fourth latches 224_1 to 224_8, and the fourth latches 224_1 to 224_8 latch corresponding data LH2_1 to LH2_8 in response to the second latch enable signal EN2, and output the latched data 2LH2_1 to 2LH2_8 to the second level shifter circuit 230_2.

[0082] Process and reference for handling the 8-bit second odd serial data ODD2<8:1> during the third operation time TI3 Figure 3 The process for processing the first 8-bit odd serial data ODD1<8:1> during the first operation time TI1 is the same or similar. Therefore, the description of the process for processing the second 8-bit odd serial data ODD2<8:1> is omitted.

[0083] Furthermore, the process of processing the 8-bit second even-numbered serial data EVEN2<8:1> during the fourth operation time TI4 is the same as or similar to the process of processing the 8-bit first even-numbered serial data EVEN1<8:1> during the second operation time TI2. Therefore, the description of the process of processing the 8-bit second even-numbered serial data EVEN2<8:1> is omitted.

[0084] The process and reference for processing each data EVEN1<8:1>, ODD2<8:1>, EVEN2<8:1>, ... Figure 3 The process for disposing of the data ODD1<8:1> is the same or similar, so its description is omitted.

[0085] The grayscale voltage generation circuit 300 receives a first operating voltage VDDH and a second operating voltage HVDD, and uses the first operating voltage VDDH and the second operating voltage HVDD to generate a first set of grayscale voltages VGMA_VH0 to VGMA_VH255. The grayscale voltage generation circuit 300 outputs the generated grayscale voltages VGMA_VH0 to VGMA_VH255 to the first DAC 240_1.

[0086] The grayscale voltage generation circuit 300 uses a second operating voltage HVDD and a ground voltage to generate a second set of grayscale voltages VGMA_VL0 to VGMA_VL255, and outputs the generated grayscale voltages VGMA_VL0 to VGMA_VL255 to the second DAC240_2. In one embodiment, the second operating voltage HVDD can be half of the first operating voltage VDDH.

[0087] Figure 4 Showing includes Figure 2 An example circuit diagram of the inverting circuit in the transfer control circuit of a source driver IC. Figure 5 It is used for explanation Figure 4 An example of displaying data for the operation of the inverting circuit shown.

[0088] refer to Figure 3 , Figure 4 and Figure 5 The inversion circuit 400A includes a first target data value detection circuit 410, a second target data value detection circuit 420, a logic gate circuit 430, and a selection circuit 440. The selection circuit 440 can be implemented as a multiplexer.

[0089] Assume that the first target data value detection circuit 410 is designed to output a high-level output signal S1 only when the first set of data values ​​8'b00000000 is the same as the target data value 8'b00000000, and the second target data value detection circuit 420 is designed to output a high-level output signal S2 only when the first set of data values ​​8'b11111111 is the same as the target data value 8'b111111111. Also assume that the first reference data REFD1 is 8'b11111111, and the second reference data REFD2 is 8'b00000000. The target data value can refer to a specific display data value included in the data DATA.

[0090] 1-1. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b00000000

[0091] For example, the first target data value detection circuit 410 can be implemented as a NOR gate circuit, and when each of the first set of data values ​​(8'b00000000) is data 0, it outputs an output signal S1 with a high level H.

[0092] The second target data value detection circuit 420 can be implemented as an AND gate circuit, and when each of the first group of data values ​​(8'b11111111) is data 1, it outputs an output signal S2 with a high level H.

[0093] When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b00000000, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0094] In response to a first output signal S1 having a high level H, a second output signal S2 having a low level L, and a third output signal S3 having a low level L, the multiplexer 440 outputs the first reference data REFD1 (=8'b111111111) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0095] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1>) which includes the second set of data values ​​(REFD1 = 8'b11111111).

[0096] For example, even if the first data processing circuit 205_1 receives the second set of data values ​​(REFD1 = 8'b11111111), the first data processing circuit 205_1 does not output the grayscale voltage VGMA_VH255 corresponding to the second set of data values ​​(REFD1 = 8'b11111111) as the first output signal OUT1. Instead, it outputs the grayscale voltage VGMA_VH0 corresponding to the first set of data values ​​8'b00000000 as the first output signal OUT1.

[0097] That is, the first data processing circuit 205_1 outputs the grayscale voltage VGMA_VH0 corresponding to the first group of data values ​​8'b00000000 included in the original first display data DATA (=ODD1<8:1>) as the first output signal OUT1.

[0098] 1-2. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b11111111

[0099] When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0100] In response to a first output signal S1 having a low level L, a second output signal S2 having a high level H, and a third output signal S3 having a low level L, the multiplexer 440 outputs the second reference data REFD2 (=8'b00000000) input through the second input terminal IN2 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0101] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1>) which includes the second set of data values ​​(REFD2 = 8'b00000000).

[0102] For example, even if the first data processing circuit 205_1 receives the second set of data values ​​(REFD2 = 8'b00000000), the first data processing circuit 205_1 does not output the grayscale voltage VGMA_VH0 corresponding to the second set of data values ​​(REFD2 = 8'b00000000) as the first output signal OUT1. Instead, it outputs the grayscale voltage VGMA_VH255 corresponding to the first set of data values ​​8'b111111111 as the first output signal OUT1.

[0103] That is, the first data processing circuit 205_1 outputs the grayscale voltage VGMA_VH255 corresponding to the first set of data values ​​8'b11111111 included in the first display data DATA (=ODD1<8:1>) as the first output signal OUT1.

[0104] 1-3. In the case where the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0105] When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a high level H.

[0106] In response to a first output signal S1 having a low level L, a second output signal S2 having a low level L, and a third output signal S3 having a high level H, the multiplexer 440 outputs the first set of data values ​​input through the third input terminal IN3 to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0107] Only the first data processing circuit 205_1 receives and processes the first display data (DOUT = ODD1<8:1>), which includes the first set of data values.

[0108] 2-1. When the first set of data values ​​included in the first display data DATA (=EVEN1<8:1>) is 8'b00000000

[0109] When the first set of data values ​​included in the first display data DATA (=EVEN1<8:1>) is 8'b00000000, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0110] In response to a first output signal S1 having a high level H, a second output signal S2 having a low level L, and a third output signal S3 having a low level L, the multiplexer 440 outputs the first reference data REFD1 (=8'b111111111) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0111] Only the second data processing circuit 205_2 receives and processes the second display data (DOUT=EVEN1<8:1>) which includes the second set of data values ​​(REFD1=8'b11111111).

[0112] For example, even if the second data processing circuit 205_2 receives the second set of data values ​​(REFD1 = 8'b11111111), the second data processing circuit 205_2 does not output the grayscale voltage VGMA_VL255 corresponding to the second set of data values ​​(REFD1 = 8'b11111111) as the second output signal OUT2. Instead, it outputs the grayscale voltage VGMA_VL0 corresponding to the first set of data values ​​8'b00000000 as the second output signal OUT2.

[0113] That is, the second data processing circuit 205_2 outputs the grayscale voltage VGMA_VL0 corresponding to the first set of data values ​​8'b00000000 included in the original first display data DATA (=EVEN1<8:1>) as the second output signal OUT2.

[0114] 2-2. When the first set of data values ​​included in the first display data DATA (=EVEN1<8:1>) is 8'b11111111

[0115] When the first set of data values ​​included in the first display data DATA (=EVEN1<8:1>) is 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0116] In response to a first output signal S1 having a low level L, a second output signal S2 having a high level H, and a third output signal S3 having a low level L, the multiplexer 440 outputs the second reference data REFD2 (=8'b00000000) input through the second input terminal IN2 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0117] Only the second data processing circuit 205_2 receives and processes the second display data (DOUT=EVEN1<8:1>) which includes the second set of data values ​​(REFD2=8'b00000000).

[0118] For example, even if the second data processing circuit 205_2 receives the second set of data values ​​(REFD2 = 8'b00000000), the second data processing circuit 205_2 does not output the grayscale voltage VGMA_VL0 corresponding to the second set of data values ​​(REFD2 = 8'b00000000) as the second output signal OUT2. Instead, it outputs the grayscale voltage VGMA_VL255 corresponding to the first set of data values ​​8'b11111111 as the second output signal OUT2.

[0119] That is, the second data processing circuit 205_2 outputs the grayscale voltage VGMA_VL255 corresponding to the first set of data values ​​8'b11111111 included in the original first display data DATA (=EVEN1<8:1>) as the second output signal OUT2.

[0120] 2-3. In the case where the first set of data values ​​included in the first display data DATA (=EVEN1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0121] When the first set of data values ​​is neither 8'b00000000 nor 8'b11111111, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a high level H.

[0122] In response to the first output signal S1 with a low level L, the second output signal S2 with a low level L, and the third output signal S3 with a high level H, the multiplexer 440 outputs the first set of data values ​​input through the third input terminal IN3 as is to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0123] Only the second data processing circuit 205_2 receives and processes the first display data (DOUT = EVEN1<8:1>), which includes the first set of data values.

[0124] Figure 6 It is used for explanation Figure 4 Another embodiment of the operation of the inverting circuit shown displays data.

[0125] Reference Figure 3 , Figure 4 and Figure 6 Describes the operation of the transmission control circuit 400 when only one of the target data values ​​is data 1 and data 0, and each of the remaining target data values ​​is the other one of data 1 and data 0.

[0126] For example, suppose the first target data value detection circuit 410 is designed to output a first output signal with a high level only when the first set of data values ​​8'b00000001 is the same as the target data value 8'b00000001, and the second target data value detection circuit 420 is designed to output a second output signal with a high level only when the first set of data values ​​8'b11111110 is the same as the target data value 8'b11111110. Also suppose the first reference data REFD1 is 8'b11111110 and the second reference data REFD2 is 8'b00000001.

[0127] Here, when a specific data value is input to the corresponding detection circuit 410 or 420 and the corresponding detection circuit 410 or 420 generates an output signal S1 or S2 with a high level, the specific data value is called the target data value.

[0128] According to an embodiment, the first target data value detection circuit 410 can also be designed to output a first output signal with a high level only when the first set of data values ​​8'b10000000 is the same as the target data value 8'b10000000, and the second target data value detection circuit 420 can also be designed to output a second output signal with a high level only when the first set of data values ​​8'b01111111 is the same as the target data value 8'b01111111. In this case, the first reference data REFD1 can be set to 8'b01111111, and the second reference data REFD2 can be set to 8'b10000000.

[0129] 3-1. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b00000001

[0130] The first target data value detection circuit 410 uses the first set of data values ​​8'b00000001 to output a first output signal S1 with a high level H.

[0131] The second target data value detection circuit 420 uses the first set of data values ​​8'b11111110 to output a second output signal S2 with a high level H.

[0132] When the first set of data values ​​is 8'b00000001, the first target data value detection circuit 410 generates a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0133] In response to a first output signal S1 having a high level H, a second output signal S2 having a low level L, and a third output signal S3 having a low level L, the multiplexer 440 outputs the first reference data REFD1 (=8'b11111110) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0134] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1>) which includes the second set of data values ​​(REFD1 = 8'b11111110).

[0135] 3-2. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b11111110

[0136] When the first set of data values ​​is 8'b11111110, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0137] In response to a first output signal S1 having a low level L, a second output signal S2 having a high level H, and a third output signal S3 having a low level L, the multiplexer 440 outputs the second reference data REFD2 (=8'b00000001) input through the second input terminal IN2 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0138] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1>) which includes the second set of data values ​​(REFD2 = 8'b00000001).

[0139] 3-3. In the case where the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is neither 8'b00000001 nor 8'b11111110

[0140] When the first set of data values ​​is neither 8'b00000001 nor 8'b11111110, the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a high level H.

[0141] In response to a first output signal S1 having a low level L, a second output signal S2 having a low level L, and a third output signal S3 having a high level H, the multiplexer 440 outputs the first set of data values ​​input through the third input terminal IN3 to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0142] Only the first data processing circuit 205_1 receives and processes the first display data (DOUT = ODD1<8:1>), which includes the first set of data values.

[0143] Figure 7 Showing includes Figure 2 An example of a transfer control circuit in a source driver IC, which includes a determining circuit and an inverting circuit. Figure 8a It is shown Figure 7 The table shown illustrates the operation of the selection signal generation circuit.

[0144] refer to Figure 7 The transmission control circuit 400 includes a determining circuit 400B and a reversing circuit 400A.

[0145] The determining circuit 400B determines whether the first displayed data is an inverted target data type. The determining circuit 400B includes a register 402, a selection signal generation circuit 404, and a multiplexer 406.

[0146] Register 402 stores information indicating whether the inverted target data type corresponds to odd or even data.

[0147] The selection signal generation circuit 404 generates the selection signal SEL based on the information stored in register 402 and whether the display data DATA is odd data ODDi<8:1> or even data EVENi<8:1>.

[0148] like Figure 8a As shown, when the target data type is odd and the display data DATA is odd (ODDi<8:1>), the selection signal generation circuit 404 generates a selection signal SEL with a low level (L). When the target data type is odd and the display data DATA is even (EVENi<8:1>), the selection signal generation circuit 404 generates a selection signal SEL with a high level (H).

[0149] In another example, when the inverted target data type is even data and the displayed data DATA is odd data ODDi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL with a high level H, and when the inverted target data type is even data and the displayed data DATA is even data EVENi<8:1>, the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0150] When the selection signal SEL is at a high level H, the multiplexer 406 will bypass the display data DATA to the first data processing circuit 205_1 and the second data processing circuit 205_2.

[0151] However, when the selection signal SEL is at a low level L, the multiplexer 406 transmits the display data DATA to the inverting circuit 400A.

[0152] The inversion circuit 400A includes a first target data value detection circuit 410, a second target data value detection circuit 420, a logic gate circuit 430, and a multiplexer 440, and is connected with... Figure 4 The same applies as shown. Therefore, its detailed description is omitted.

[0153] Figure 12 It is shown Figure 7 The flowchart shown illustrates the operation of the transmission control circuit.

[0154] refer to Figure 3 , Figure 7 , Figure 8a , Figure 8b and Figure 12 Describe the operation of the transmission control circuit 400. In this case, assuming the target data type is odd, the first target data value detection circuit 410 is designed to output a first output signal S1 with a high level only when the first set of data value 8'b00000000 is input, and the second target data value detection circuit 420 is designed to output a second output signal with a high level only when the first set of data value 8'b11111111 is input, the first reference data REFD1 is 8'b11111111, and the second reference data REFD2 is 8'b00000000.

[0155] First, the signal generation circuit 404 selects the first display data DATA, which includes the first set of data values ​​8'b00000000, i.e., the first odd data ODD1<8:1> (S210), from the receiving circuit 203.

[0156] The selection signal generation circuit 404 determines whether the first display data DATA (=ODD1<8:1>=8'b00000000) is an inverted target data type (S220).

[0157] When the first display data DATA (=ODD1<8:1>=8'b00000000) is an inverted target data type, that is, when the first display data DATA (=ODD1<8:1>) is an odd number ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0158] The multiplexer 406 transmits the first display data DATA (=ODD1<8:1>=8'b00000000) to the inverting circuit 400A in response to the selection signal SEL with a low level L.

[0159] 4-1. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b00000000

[0160] When the first set of data value 8'b00000000 is the same as the target data value 8'b00000000, that is, when the first set of data value 8'b00000000 is received ("Yes" in step S240), the first target data value detection circuit 410 outputs a first output signal S1 with a high level H, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0161] In response to the first output signal S1 with a high level H, the second output signal S2 with a low level L, and the third output signal S3 with a low level L, the multiplexer 440 outputs the first reference data REFD1 (=8'b111111111) input through the first input terminal IN1 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S250).

[0162] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1>) which includes the second set of data values ​​(REFD1 = 8'b11111111).

[0163] In another example, the selection signal generation circuit 404 receives first display data DATA (=ODD1<8:1>) (S210) from the receiving circuit 203, which includes the first set of data values ​​8'b111111111.

[0164] The selection signal generation circuit 404 determines whether the first display data DATA (=ODD1<8:1>=8'b11111111) is an inverted target data type (S220).

[0165] When the first display data DATA (=ODD1<8:1>=8'b11111111) is an inverted target data type, that is, when the first display data DATA (=ODD1<8:1>=8'b11111111) is an odd number ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0166] The multiplexer 406, in response to the selection signal SEL with a low level L, transmits the first display data DATA (=ODD1<8:1>=8'b11111111) to the inverting circuit 400A.

[0167] 4-2. When the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is 8'b11111111

[0168] When the first set of data values ​​8'b11111111 is the same as the target data value 8'b11111111, that is, when the first display data DATA (=ODD1<8:1>=8'b11111111) is received ("Yes" in step S240), the first target data value detection circuit 410 outputs a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a high level H, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a low level L.

[0169] In response to the first output signal S1 with a low level L, the second output signal S2 with a high level H, and the third output signal S3 with a low level L, the multiplexer 440 outputs the second reference data REFD2 (=8'b00000000) input through the second input terminal IN2 as output data DOUT to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S250).

[0170] Only the first data processing circuit 205_1 receives and processes the second display data (DOUT = ODD1<8:1> = 00000000) which includes the second set of data values ​​(REFD2 = 8'b00000000).

[0171] In another example, the selection signal generation circuit 404 receives from the receiving circuit 203 the first display data DATA (=ODD1<8:1>) (S210), which includes a first set of data values ​​(e.g., neither 8'b00000000 nor 8'b11111111).

[0172] The selection signal generation circuit 404 determines whether the first display data DATA (=ODD1<8:1>) is an inverted target data type (S220).

[0173] When the first display data DATA (=ODD1<8:1>) is an inverted target data type, that is, when the first display data DATA (=ODD1<8:1>) is an odd number ("Yes" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a low level L.

[0174] The multiplexer 406 transmits the first display data DATA (=ODD1<8:1>) to the inverting circuit 400A in response to the selection signal SEL with a low level L.

[0175] 4-3. In the case where the first set of data values ​​included in the first display data DATA (=ODD1<8:1>) is neither 8'b00000000 nor 8'b11111111

[0176] Since the first set of data values ​​is different from the target data value ("No" in step S240), the first target data value detection circuit 410 generates a first output signal S1 with a low level L, the second target data value detection circuit 420 generates a second output signal S2 with a low level L, and the logic gate circuit 430, which is implemented as a NOR gate circuit, generates a third output signal S3 with a high level H.

[0177] In response to the first output signal S1 with a low level L, the second output signal S2 with a low level L, and the third output signal S3 with a high level H, the multiplexer 440 bypasses the first set of data values ​​(neither 8'b00000000 nor 8'b11111111) input through the third input terminal IN3 to the first data processing circuit 205_1 and the second data processing circuit 205_2 as is (S230).

[0178] Only the first data processing circuit 205_1 receives and processes the first display data (DOUT = ODD1<8:1>), which includes the first set of data values.

[0179] In another example, the selection signal generation circuit 404 receives first display data DATA, which includes a first set of data values, from the receiving circuit 203, namely, the first even data EVEN1<8:1> (S210).

[0180] The selection signal generation circuit 404 determines whether the first display data DATA (=EVEN1<8:1>) is an inverted target data type (S220).

[0181] When the first display data DATA (=EVEN1<8:1>) is not an inverted target data type, that is, when the first display data DATA (=EVEN1<8:1>) is not an odd number ("No" in step S220), the selection signal generation circuit 404 generates a selection signal SEL with a high level H.

[0182] In response to a selection signal SEL with a high level H, the demultiplexer 406 bypasses the first display data DATA (=EVEN1<8:1>) as is to the first data processing circuit 205_1 and the second data processing circuit 205_2 (S230).

[0183] Only the second data processing circuit 205_2 receives and processes the first display data (DOUT = EVEN1<8:1>), which includes the first set of data values.

[0184] Figure 8b It is shown Figure 2 The table shows the input and output signals of each of the first and second data processing circuits.

[0185] When the target data type to be reversed is an even number, EVENI <n:1>Furthermore, when the target data values ​​are 8'b00000000 and 8'b11111111, the transmission control circuit 400 will transmit the odd-numbered data ODDi. <n:1>Bypass to the first data processing circuit 205_1.

[0186] like Figure 8b As shown, the first data processing circuit 205_1 outputs the first group of grayscale voltages VGMA_VH<0:255>, which are included in the odd data ODDi. <n:1>The grayscale voltage VGMA_VH<0:255> corresponding to the first set of data values ​​is used as the first output signal OUT1 (S260).

[0187] However, when the input includes even data EVENI containing the first set of data values ​​8'b00000000 <n:1>At that time, the transmission control circuit 400 inverts the first set of data values ​​into the second set of data values ​​8'b11111111, and then transmits the even-numbered data EVENI including the second set of data values ​​8'b111111111. <n:1>The data is transmitted to the second data processing circuit 205_2.

[0188] However, even including the even-numbered data EVENI of the second set of data values ​​8'b11111111 <n:1>The data is transmitted to the second data processing circuit 205_2. The second DAC 240_2 of the second data processing circuit 205_2 does not output the gray voltage VGMA_VL255 corresponding to the second group data value 8'b11111111 in the second group of gray voltages VGMA_VL<0:255> as the second output signal OUT2. Instead, it outputs the gray voltage VGMA_VL0 corresponding to the first group data value 8'b00000000 in the second group of gray voltages VGMA_VL<0:255> as the second output signal OUT2 (S260).

[0189] To this end, a second DAC 240_2 can be manufactured such that the grayscale voltage VGMA_VL0 is input into an internal path for outputting the grayscale voltage VGMA_VL255. Specifically, the second DAC 240_2 can be designed such that the grayscale voltage VGMA_VL0 is input to the input terminal of the typical DAC that inputs the grayscale voltage VGMA_VL255, and the grayscale voltage VGMA_VL255 is input to the input terminal of the grayscale voltage VGMA_VL0.

[0190] When the input includes even-numbered data such as EVENI containing the first set of data values ​​8'b11111111, <n:1>At that time, the transmission control circuit 400 inverts the first group of data values ​​8'b11111111 to the second group of data values ​​8'b00000000, and then transmits the even-numbered data EVENI including the second group of data values ​​8'b00000000. <n:1>The data is transmitted to the second data processing circuit 205_2.

[0191] Even including the even-numbered data EVENI with the second set of data value 8'b00000000 <n:1>The data is transmitted to the second data processing circuit 205_2. The second DAC 240_2 of the second data processing circuit 205_2 does not output the gray voltage VGMA_VL0 corresponding to the second group data value 8'b00000000 in the second group of gray voltages VGMA_VL<0:255> as the second output signal OUT2. Instead, it outputs the gray voltage VGMA_VL225 corresponding to the first group data value 8'b11111111 in the second group of gray voltages VGMA_VL<0:255> as the second output signal OUT2 (S260).

[0192] As described above, since the second DAC 240_2 is designed so that the grayscale voltage VGMA_VL255 is input to the input terminal of the grayscale voltage VGMA_VL0 in a typical DAC structure, even when the second set of data value 8'b00000000 is input, a grayscale voltage VGMA_VL255 that matches the path of the grayscale voltage VGMA_VL0 can be output as the second output signal OUT2.

[0193] When the input includes even data such as 8'b000000001 or 11111111 (the first group of data values ​​is neither 8'b00000001 nor 8'b11111111), EVENI <n:1>At that time, the even-numbered data EVENI output from the transmission control circuit 400 includes the first set of data values ​​8'b00000001 or 11111110. <n:1>It is transmitted to the second data processing circuit 205_2.

[0194] The second DAC 240_2 of the second data processing circuit 205_2 outputs the gray voltage VGMA_VL1 or VGMA_VL254 in the second group of gray voltage VGMA_VL<0:255> that corresponds to the first group of data values ​​8'b00000001 or 11111110 as the second output signal OUT2 (S260).

[0195] As mentioned above, Figure 2 Each of the DACs 240_1 and 240_2 is designed to have the ability to perform Figure 11 Step S150 and Figure 12 The structure of step S260.

[0196] Figure 9 Is included Figure 2 The circuit diagram of the first level shifter in the source driver IC.

[0197] The first level shifter circuit 230_1 includes multiple first level shifters 232_1 to 232_8. Since the first level shifters 232_1 to 232_8 have the same structure and operation, reference is made to... Figure 9 The structure and operation of the first level shifter 232_1 are described in a representative manner.

[0198] Transistors MP1_1, MP1_3, and MN1_1 are connected in series between the first grayscale voltage transmission line 301, which transmits the first intermediate grayscale voltage VGMAO1 (=VGMA_VH255), and the ground GND, which provides the ground voltage VSSH. Transistors MP1_2, MP1_4, and MN1_2 are also connected in series between the first grayscale voltage transmission line 301 and the ground GND. Figure 8c As shown, the first intermediate grayscale voltage VGMAO1 can be the voltage closest to the first operating voltage VDDH (or the voltage that is lower than the first operating voltage VDDH and has the smallest level difference with the first operating voltage VDDH).

[0199] Because a low-level bias voltage LSP is provided to the gate of each of the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2, the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2 are turned on. The first PMOS transistor MP1_1 and the second PMOS transistor MP1_2 can be kept in a continuously on state by the bias voltage LSP provided to their gates. When the bias voltage LSP is provided to the gate of the first PMOS transistor MP1_1 and the gate of the second PMOS transistor MP1_2 to turn on the first PMOS transistor MP1_1 and the second PMOS transistor MP1_2, the current flowing through the third PMOS transistor MP1_3 and the fourth PMOS transistor MP1_4 is limited.

[0200] The gate of the third PMOS transistor MP1_3 is connected to the second node ND2, the first terminal of the third PMOS transistor MP1_3 is connected to the first node ND1, and the second terminal of the third PMOS transistor MP1_3 is connected to the first PMOS transistor MP1_1. The gate of the fourth PMOS transistor MP1_4 is connected to the first node ND1, the first terminal of the fourth PMOS transistor MP1_4 is connected to the second node ND2, and the second terminal of the fourth PMOS transistor MP1_4 is connected to the second PMOS transistor MP1_2.

[0201] The output signal (also called "first input data" or "first bit") 2LH1_1 of the second latch 222_1 included in the second latch circuit 220_1 is input to the gate of the first NMOS transistor MN1_1. The first inverter INV1 inverts the output signal 2LH1_1 of the second latch 222_1, and the inverted output signal 2LHB1_1 is input to the gate of the second NMOS transistor MN1_2.

[0202] For example, when the level of signal 2LH1_1 input to the gate of the first NMOS transistor MN1_1 is high and the level of signal 2LHB1_1 input to the gate of the second NMOS transistor MN1_2 is low, the first NMOS transistor MN1_1 is turned on and the second NMOS transistor MN1_2 is turned off.

[0203] When the first NMOS transistor MN1_1 is turned on, the voltage DB1_1 at the first node ND1 is pulled down to the ground voltage VSSH, and the fourth PMOS transistor MP1_4 is turned on, causing the voltage D1_1 at the second node ND2 to be pulled up to the level of the first operating voltage (VGMAO1 = VGMA_VH255). Therefore, the third PMOS transistor MP1_3 is turned off, so that the voltage DB1_1 at the first node ND1 remains at the ground voltage VSSH.

[0204] Conversely, when the level of signal 2LH1_1 input to the gate of the first NMOS transistor MN1_1 is low and the level of signal 2LHB1_1 input to the gate of the second NMOS transistor MN1_2 is high, the first NMOS transistor MN1_1 is turned off and the second NMOS transistor MN1_2 is turned on.

[0205] When the second NMOS transistor MN1_2 is turned on, the voltage D1_1 at the second node ND2 is pulled down to the ground voltage VSSH, and the third PMOS transistor MP1_3 is turned on, causing the voltage DB1_1 at the first node ND1 to be pulled up to the level of the first operating voltage (VGMAO1 = VGMA_VH255). Therefore, the fourth PMOS transistor MP1_4 is turned off, so that the voltage D1_1 at the second node ND2 remains at the ground voltage VSSH.

[0206] The voltage level DB1_1 of the first node ND1 is complementary to the voltage level D1_1 of the second node ND2.

[0207] The output voltage swing range of voltage levels DB1_1 and D1_1 is between the highest grayscale voltage (VGMAO1=VGMA_VH255) in the first set of grayscale voltages VGMA_VH0 to VGMA_VH255 and the ground voltage VSSH.

[0208] The first level shifters 232_1 to 232_8 will pair the complementary signals.<D1_1,DB1_1> to<D1_8,DB1_8> Output to the first DAC 240_1.

[0209] For example, the voltage swing range of the output signals D1_1 to D1_8 of the first level shifters 232_1 to 232_8 is greater than the voltage swing range of the input / output signals of each of the latches 212_1 to 212_8 and 222_1 to 222_8.

[0210] Figure 10 Is included Figure 2 The circuit diagram of the second level shifter in the source driver IC.

[0211] The second-level shifter circuit 230_2 includes multiple second-level shifters 234_1 to 234_8. Since the second-level shifters 234_1 to 234_8 have the same structure and operation, reference is made to... Figure 10 The structure and operation of the second level shifter 234_1 are described in a representative manner.

[0212] For example, when describing two level shifters 232_j and 234_j (where j≤8), the first level shifter can refer to level shifter 232_j, and the second level shifter can refer to level shifter 234_j.

[0213] Each of the second level shifters 234_1 to 234_8 and each of the first level shifters 232_1 to 232_8 operates independently of each other. Furthermore, the first level shifters 232_1 to 232_8 operate independently of each other, and the second level shifters 234_1 to 234_8 operate independently of each other.

[0214] For example, the output signal of any one of the first level shifters 232_1 to 232_8 and the second level shifter 234_1 to 234_8 has no effect on the input signal of each of the remaining level shifters.

[0215] like Figure 8c As shown, transistors MP2_1, MP2_3, and MN2_1 are connected in series between the second grayscale voltage transmission line 303, which transmits the second intermediate grayscale voltage VGMAO8 (=VGMA_VL0), and the ground GND, which provides the ground voltage VSSH. Transistors MP2_2, MP2_4, and MN2_2 are connected in series between the second grayscale voltage transmission line 303 and the ground GND. The second intermediate grayscale voltage VGMAO8 can be the voltage closest to the second operating voltage HVDD (=0.5VDDH) (or a voltage lower than the second operating voltage HVDD and with the smallest level difference from the second operating voltage HVDD).

[0216] Because a low-level bias voltage LSP is provided to the gate of each of the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2, the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 are turned on. The first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 can be kept in a continuously on state by the bias voltage LSP provided to their gates. When the bias voltage LSP is provided to the gate of the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2 to turn on the first PMOS transistor MP2_1 and the second PMOS transistor MP2_2, the current flowing through the third PMOS transistor MP2_3 and the fourth PMOS transistor MP2_4 is limited.

[0217] The gate of the third PMOS transistor MP2_3 is connected to the fourth node ND4, the first terminal of the third PMOS transistor MP2_3 is connected to the third node ND3, and the second terminal of the third PMOS transistor MP2_3 is connected to the first PMOS transistor MP2_1. The gate of the fourth PMOS transistor MP2_4 is connected to the third node ND3, the first terminal of the fourth PMOS transistor MP2_4 is connected to the fourth node ND4, and the second terminal of the fourth PMOS transistor MP2_4 is connected to the second PMOS transistor MP2_2.

[0218] The output signal (also called "second input data" or "second bit") 2LH2_1 of the fourth latch 224_1 included in the fourth latch circuit 220_2 is input to the gate of the first NMOS transistor MN2_1. The second inverter INV2 inverts the output signal 2LH2_1 of the fourth latch 224_1, and the inverted output signal 2LHB2_1 is input to the gate of the second NMOS transistor MN2_2.

[0219] For example, when the level of signal 2LH2_1 input to the gate of the first NMOS transistor MN2_1 is high and the level of signal 2LHB2_1 input to the gate of the second NMOS transistor MN2_2 is low, the first NMOS transistor MN2_1 is turned on and the second NMOS transistor MN2_2 is turned off.

[0220] When the first NMOS transistor MN2_1 is turned on, the voltage DB2_1 at the third node ND3 is pulled down to the ground voltage VSSH, and the fourth PMOS transistor MP2_4 is turned on, causing the voltage D2_1 at the fourth node ND4 to be pulled up to the level of the second intermediate grayscale voltage (VGMAO8). Therefore, the third PMOS transistor MP2_3 is turned off, so that the voltage DB2_1 at the third node ND3 remains at the ground voltage VSSH.

[0221] Conversely, when the level of signal 2LH2_1 input to the gate of the first NMOS transistor MN2_1 is low and the level of signal 2LHB2_1 input to the gate of the second NMOS transistor MN2_2 is high, the first NMOS transistor MN2_1 is turned off and the second NMOS transistor MN2_2 is turned on.

[0222] When the second NMOS transistor MN2_2 is turned on, the voltage D2_1 at the fourth node ND4 is pulled down to the ground voltage VSSH, and the third PMOS transistor MP2_3 is turned on, causing the voltage DB2_1 at the third node ND3 to be pulled up to the level of the second intermediate grayscale voltage (VGMAO8). Therefore, the fourth PMOS transistor MP2_4 is turned off, so that the voltage D2_1 at the fourth node ND4 remains at the ground voltage VSSH.

[0223] The voltage level DB2_1 of the third node ND3 is complementary to the voltage level D2_1 of the fourth node ND4.

[0224] The output voltage swing range of voltage levels DB2_1 and D2_1 is between the highest grayscale voltage VGMAO8 = VGMA_VL0 and the ground voltage VSSH in the second set of grayscale voltages VGMA_VL0 to VGMA_VL255.

[0225] For reference Figure 10 The second level shifters 234_1 to 234_8 will pair the complementary signals.<D2_1,DB2_1> to<D2_8,DB2_8> Output to the second DAC 240_2.

[0226] For example, the voltage swing range of the output signals D2_1 to D2_8 of the second level shifters 234_1 to 234_8 is greater than the voltage swing range of the input / output signals of each of the latches 214_1 to 214_8 and 224_1 to 224_8, and less than the voltage swing range of the output signals D1_1 to D1_8 of the first level shifters 232_1 to 232_8.

[0227] like Figure 2 As shown, the first level shifters 232_1 to 232_8 operate independently of the second level shifters 234_1 to 234_8.

[0228] Return to reference Figure 2 The first DAC 240_1 responds to the complementary signal pair output from the first level shifters 232_1 to 232_8<D1_1,DB1_1> to<D1_8,DB1_8> The first set of grayscale voltages, from VGMA_VH0 to VGMA_VH255, is output as the first output signal DAC1O.

[0229] For example, when the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 is 00000000, the first DAC 240_1 outputs a first grayscale voltage VGMA_VH0 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 is 00000001, the first DAC 240_1 outputs a second grayscale voltage VGMA_VH1 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 is 11111110, the first DAC 240_1 outputs the 255th grayscale voltage VGMA_VH254 as the first output signal DAC1O. When the 8-bit parallel data D1_1 to D1_8 output from the first level shifter circuit 230_1 is 11111111, the first DAC 240_1 outputs the 256th grayscale voltage VGMA_VH255 as the first output signal DAC1O.

[0230] The first output buffer 250_1 buffers the first output signal DAC10 of the first DAC 240_1 and outputs the buffered first output signal OUT1 to at least one of the first data lines DL1.

[0231] refer to Figure 2 The second DAC 240_2 responds to the complementary signal pair output from the second level shifters 234_1 to 234_8<D2_1,DB2_1> to<D2_8,DB2_8> The second set of grayscale voltages, from VGMA_VL0 to VGMA_VL255, is output as the second output signal DAC2O.

[0232] For example, when the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 is 00000000, the second DAC 240_2 outputs the first grayscale voltage VGMA_VL0 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 is 00000001, the second DAC 240_2 outputs the second grayscale voltage VGMA_VL1 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 is 11111110, the second DAC 240_2 outputs the 255th grayscale voltage VGMA_VL254 as the second output signal DAC2O. When the 8-bit parallel data D2_1 to D2_8 output from the second level shifter circuit 230_2 is 11111111, the second DAC 240_2 outputs the 256th grayscale voltage VGMA_VL225 as the second output signal DAC2O.

[0233] The second output buffer 250_2 buffers the second output signal DAC2O of the second DAC 240_2 and outputs the buffered second output signal OUT2 to another line in the first data line DL1.

[0234] According to the above embodiment, when the first set of data values ​​is the same as the target data value, even if the first set of data values ​​is changed to the second set of data values, the first DAC 240_1 or the second DAC 240_2 outputs a grayscale voltage corresponding to the first set of data values ​​instead of a grayscale voltage corresponding to the second set of data values. In this case, since the first DAC 240_1 or the second DAC 240_2 is manufactured such that the grayscale voltage VGMA_VH0 or VGMA_VL0 is input into the internal path for outputting the grayscale voltage VGMA_VH255 or VGMA_VL255, and the grayscale voltage VGMA_VH255 or VGMA_VL255 is input into the internal path for outputting the grayscale voltage VGMA_VH0 or VGMA_VL0, even if the data values ​​are inverted, the DAC outputs a grayscale voltage corresponding to the original data values, and the number of transistors requiring state transitions during display data switching can be reduced.

[0235] The grayscale voltage corresponding to the first display data including the first set of data values ​​is output, instead of the grayscale voltage corresponding to the second display data including the second set of data values.

[0236] Therefore, the peak current generated due to the state transition of the transistors in the first DAC 240_1 or the second DAC 240_2 is reduced, thereby allowing the load balance in the first DAC 240_1 or the second DAC 240_2 to be adjusted appropriately.

[0237] Those skilled in the art will understand that the present invention can be implemented in other specific forms without altering its technical concept or essential features.

[0238] Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the invention. The scope of the invention is defined by the following claims rather than the specific embodiments described above, and should be interpreted as including all changes or modifications derived from the meaning and scope of the claims and their equivalents within the scope of the invention.

[0239] Implementation of the invention

[0240] Various embodiments for implementing the present invention have been fully described in the preceding table of contents.

[0241] Industrial applicability

[0242] This invention can be applied to any type of display device, and therefore its industrial applicability is recognized.

Claims

1. A display driving device, comprising: A receiving circuit configured to receive first display data including a first set of data values; A transmission control circuit is configured to output the first display data or second display data including the second set of data values ​​based on a comparison result between the first set of data values ​​and the target data value. as well as A data processing circuit, configured to process either the first display data or the second display data output from the transmission control circuit, The transmission control circuit includes an inversion circuit, which is configured as follows: Determine whether the first set of data values ​​is the same as the target data value; Based on the determination result, when the first set of data values ​​is not the same as the target data value, the first display data is bypassed to the data processing circuit; Based on the determined results, when the first set of data values ​​is the same as the target data value, the first set of data values ​​is converted into a second set of data values ​​that are complementary to the first set of data values; and The second display data, including the second set of data values, is output to the data processing circuit.

2. The display driving device according to claim 1, wherein, The target data values ​​are all equal.

3. The display driving device according to claim 1, wherein: Only one of the target data values ​​is either data 1 or data 0. Each of the remaining target data values ​​is another one of data 1 and data 0.

4. The display driving device according to claim 1, wherein, The inversion circuit includes: A first NOR gate circuit is configured to output a first output signal at a high level when each of the first group of data values ​​is data 0. An AND gate circuit, the AND gate circuit being configured to output a second output signal at a high level when each of the first group of data values ​​is a data 1; A second NOR gate circuit is configured to output a third output signal at a high level when the levels of the first output signal and the second output signal are the same, and to output the third output signal at a low level when the levels of the first output signal and the second output signal are different; and A multiplexer configured to output second display data in response to a first output signal at a high level, a second output signal at a low level, and a third output signal at a low level, wherein each of the second set of data values ​​is data 1; to output second display data in response to the first output signal at a low level, the second output signal at a high level, and the third output signal at a low level, wherein each of the second set of data values ​​is data 0; and to output the first display data in response to the first output signal at a low level, the second output signal at a low level, and the third output signal at a high level.

5. The display driving device according to claim 1, wherein, The transmission control circuit further includes a determining circuit configured to determine whether the first displayed data is an inverted target data type. Specifically, when the first displayed data is not the inverted target data type, the determining circuit bypasses the first displayed data to the data processing circuit, and when the first displayed data is the inverted target data type, the determining circuit outputs the first displayed data to the inverting circuit.

6. The display driving device according to claim 5, wherein, The determining circuit includes: A register configured to store information indicating whether the inverted target data type is odd or even; A selection signal generation circuit is configured to generate a low-level selection signal when the first display data corresponds to the information stored in the register, and to generate a high-level selection signal when the first display data does not correspond to the information stored in the register; and A demultiplexer is configured to bypass the first display data to the data processing circuit when the selection signal is high, and to output the first display data to the inversion circuit when the selection signal is low.

7. The display driving device according to claim 5, wherein, The data processing circuit includes a first data processing circuit configured to process odd-numbered data and a second data processing circuit configured to process even-numbered data. When the inverted target data type corresponds to the even data in the odd data and even data, if the first displayed data is not the inverted target data type, the determining circuit enables the first data processing circuit and disables the second data processing circuit; if the first displayed data is the inverted target data type, the determining circuit disables the first data processing circuit and enables the second data processing circuit.

8. The display driving device according to claim 7, wherein, When the inverted target data type corresponds to the odd data among the odd data and the even data, if the first displayed data is not the inverted target data type, the determining circuit disables the first data processing circuit and enables the second data processing circuit; if the first displayed data is the inverted target data type, the determining circuit enables the first data processing circuit and disables the second data processing circuit.

9. The display driving device according to claim 1, wherein, The data processing circuit includes a digital-to-analog converter, which is configured to output a first grayscale voltage corresponding to the first set of data values ​​in the grayscale voltage for the first display data and the second display data by using an internal path for outputting a second grayscale voltage corresponding to the second set of data values.

10. A method of operating a display driving device, comprising: Receive the first display data, which includes the first set of data values; Determine whether the first set of data values ​​is the same as the target data value; Based on the determination results, when the first set of data values ​​is not the same as the target data values, the first displayed data is bypassed. as well as Based on the determined results, when the first set of data values ​​is the same as the target data value, the output includes second display data that includes the second set of data values ​​instead of the first set of data values. The second set of data values ​​is complementary to the first set of data values.

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