3d memory including hollow epitaxial channel

Abstract

The present disclosure illustrates a method for fabricating a 3D NAND flash memory structure including a hollow epitaxial channel. A method for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers on a substrate, the alternating material layers arranged in a vertically stacked manner, etching a channel hole extending through the plurality of alternating material layers to the substrate, and forming a tunnel layer around the channel hole to contact the plurality of alternating material layers. The method may further include forming a channel liner along the tunnel layer, forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate between the tunnel layer and the core gap material through the channel hole.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 429,867, filed on December 2, 2022, entitled "3D Memory Including Hollow Epitaxial Channels", which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to the processing of NAND devices and, more particularly, to methods for fabricating 3D NAND flash memory structures including hollow epitaxial channels. Background Art

[0004] A memory design known as NAND memory is a non-volatile flash memory storage architecture that maintains the data it stores without power. NAND flash memory is used in many products such as solid state devices and portable sub-products. To increase the density of NAND memory and reduce its size, traditional two-dimensional NAND architectures have moved to three-dimensional NAND stacks. Unlike individual memory cells of 2D planar NAND technology stacked on individual horizontal substrates, 3D NAND is a vertical stack of multiple alternating conductive and dielectric materials with cross vertical channels.

[0005] Polysilicon is commonly used as the channel material for 3D NAND. However, as the channel length increases, the mobility limitations imposed by polysilicon can have an adverse impact on device performance. In view of these and other considerations, the present disclosure has been made. Summary of the Invention

[0006] In view of the above, in some methods, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers disposed on the silicon substrate in a vertically stacked manner, wherein channel holes extend through the plurality of alternating material layers to the silicon substrate, and the channel holes are perpendicular to the plurality of alternating material layers. The 3D NAND memory structure may further include a channel disposed within the channel holes, wherein the channel includes a tunneling layer surrounding the interior of the channel holes to contact the plurality of alternating material layers, and a hollow epitaxial silicon core within the tunneling layer, wherein the hollow epitaxial silicon core contacts the silicon substrate.

[0007] In some methods, the method may include forming a plurality of alternating material layers disposed on a substrate in a vertically stacked manner, and etching a channel hole that extends through the plurality of alternating material layers to the substrate. The method may further include forming a tunnel layer around the channel hole to contact the plurality of alternating material layers, and forming a channel liner along the tunnel layer. The method may further include forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core between the tunnel layer and the core gap material from the substrate through the channel hole.

[0008] In some methods, a way to fabricate a hollow epitaxial silicon core of a three-dimensional (3D) NAND memory structure may include forming a plurality of alternating material layers on a silicon substrate, the alternating material layers being disposed in a vertically stacked manner, etching a channel hole that extends through the plurality of alternating material layers to the silicon substrate, and forming a tunnel layer around the channel hole, wherein the tunnel layer contacts the plurality of alternating material layers. In some embodiments, the method may further include forming a channel liner around the tunnel layer, forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core between the tunnel layer and the core gap material from the silicon substrate through the channel hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a further understanding of the nature and advantages of the various embodiments, reference may be made to the remaining portions of the specification and the drawings, in which like reference numerals are used throughout several views to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of similar components. When referring to a reference numeral without specifically identifying an existing sub-label, it is intended to refer to all of these plurality of similar components.

[0010] Figure 1 A top view of a processing system according to some embodiments is shown.

[0011] Figures 2A through 2R An incremental stage of generating a 3D NAND flash memory cell array having a hollow epitaxial channel according to some embodiments is shown.

[0012] Figure 3A A portion of a memory array according to some embodiments is shown.

[0013] Figure 3B A portion of a memory array according to some embodiments is shown, where some channels are used as support structures to facilitate a hollow epitaxial channel core.

[0014] Figures 4A through 4N An incremental stage of generating a 3D NAND flash memory cell having a hollow epitaxial channel according to some embodiments is shown.

[0015] Figures 5A through 5H Illustrates an incremental stage of generating 3D NAND flash memory cells with a hollow epitaxial channel according to some embodiments.

[0016] Figure 6 Illustrates a flowchart of a method of fabricating a 3D NAND memory structure according to some embodiments.

[0017] These diagrams are not necessarily to scale. These diagrams are merely illustrative and are not intended to depict specific parameters of the disclosure. These diagrams are intended to illustrate exemplary embodiments of the disclosure and should not be regarded as limiting the scope.

[0018] In addition, certain elements in some of the figures may be omitted or presented out of proportion to achieve clarity. Cross-sectional views may appear in the form of "slices" or "close-up" cross-sectional views, omitting certain background lines visible in a "true" cross-sectional view to enhance clarity. Additionally, for clarity, some reference numerals may be omitted in certain figures. Detailed Description

[0019] The methods, systems, and devices according to the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. These methods, systems, and devices may be implemented in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0020] The embodiments described herein are directed to 3D NAND devices, including a hollow epitaxial silicon channel formed according to a bottom punch-through scheme that opens a channel in a substrate. More specifically, the embodiments herein provide a reference for growing an epitaxial channel that penetrates an alternating layer stack and that presents a hollow or "macaroni" shape. In some embodiments, this bottom punch-through is performed in conjunction with a side etching technique to overcome interlayer alignment issues due to a high channel aspect ratio. Advantageously, using the macaroni-shaped epitaxial channel growth of the present disclosure, the volume of epitaxial silicon can be reduced, which reduces the sensitivity of the threshold voltage to trap density fluctuations. The embodiments herein further prevent stack collapse during side etching through a support structure, thus providing a low-cost solution for providing an epitaxial reference for crystal channel growth.

[0021] Figure 1FIG. 0 shows a plan view of an embodiment of a deposition, etching, baking, and curing chamber processing system 100 according to some embodiments. As shown, a pair of front-opening unified pods 102 provide substrates of different sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106, and then into a series of substrate processing chambers 108a to 108f located in segmented areas 109a to 109c. A second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to and from the substrate processing chambers 108a to 108f. Each of the substrate processing chambers 108a to 108f can be configured to perform a variety of substrate processing operations, including the etching processes described in this document, as well as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processing processes.

[0022] The substrate processing chambers 108a to 108f can include one or more system components for depositing, annealing, hardening, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, such as 108c to 108d and 108e to 108f, may be used to deposit a material on the substrate, while a third pair of processing chambers, such as 108a to 108b, may be used to harden, anneal, or process the deposited film. In another configuration, all three pairs of chambers, such as 108a to 108f, may be configured to deposit and harden a film on the substrate simultaneously. Any one or more of the foregoing processes may be performed in other chambers separate from the manufacturing system in different embodiments. It should be understood that additional deposition, etching, annealing, and hardening chamber configurations for material films are contemplated in the processing system 100. In addition, any number of other processing systems may also be used in conjunction with the present technology, and these systems may include chambers for performing any specific operation. In some embodiments, a chamber system leading to multiple processing chambers may be provided while maintaining a vacuum environment in each section, such as the holding and transfer areas described above, which may allow operations to be performed in multiple chambers while maintaining a specific vacuum environment between different processes.

[0023] The processing system 100, or more specifically, the chambers incorporated into the processing system 100 or other processing systems, can be used to produce structures according to some embodiments of the present disclosure. For example, the processing system 100 can produce a memory array by performing operations such as deposition, etching, sputtering, polishing, cleaning, etc. in each of the substrate processing chambers 108.

[0024] Figure 2A FIG. 10 shows a side cross-sectional view of a memory device 200 (hereinafter referred to as "device") in an early stage of processing according to one or more embodiments described herein. The device 200 can be a partial stack of alternating oxide-nitride layers formed for a 3D NAND flash memory array. For example,Figure 2A Each layer shown in Figure 2A can be incrementally formed layer by layer using any deposition or layer formation technique, i.e., forming a layer on top of the previous layer. In this example, these layers can be formed on a substrate 201 of a silicon substrate, such as an epitaxial silicon or single crystal silicon wafer. A silicon oxide layer 202 can be formed on the substrate 201, followed by a silicon nitride layer 204. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 can represent the initial layers on the substrate 201, and the thicknesses of these layers may be greater than the alternating oxide-nitride layers formed thereon. Next, alternating silicon oxide layers 206 and silicon nitride layers 208 can be formed stacked together.

[0025] The progressive formation of the substrate 201, the silicon oxide layer 206, the silicon nitride layer 208, and other materials described below in Figures 2A through 2R can be collectively referred to as the stack 224. As shown in Figure 2A , the stack 224 may initially have a limited height. For example, the completed stack 224 may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, initially forming all of these layers may cause the stack 224 to have an aspect ratio that is too high to reliably form narrow channel holes and other vias that penetrate the entire stack 224. Therefore, the stack 224 can be formed in layers, where the alternating silicon oxide layers 206 and silicon nitride layers 208 correspond to the first layer 205. Figures 2A through 2R The progressive formation of the substrate 201, the silicon oxide layer 206, the silicon nitride layer 208, and other materials described below in Figures 2A through 2R can be collectively referred to as the stack 224. As shown in Figure 2A , the stack 224 may initially have a limited height. For example, the completed stack 224 may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, initially forming all of these layers may cause the stack 224 to have an aspect ratio that is too high to reliably form narrow channel holes and other vias that penetrate the entire stack 224. Therefore, the stack 224 can be formed in layers, where the alternating silicon oxide layers 206 and silicon nitride layers 208 correspond to the first layer 205. Figure 2A As shown in Figure 2A , the stack 224 may initially have a limited height. For example, the completed stack 224 may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, initially forming all of these layers may cause the stack 224 to have an aspect ratio that is too high to reliably form narrow channel holes and other vias that penetrate the entire stack 224. Therefore, the stack 224 can be formed in layers, where the alternating silicon oxide layers 206 and silicon nitride layers 208 correspond to the first layer 205.

[0026] As shown in Figure 2A , the stack 224 can be etched to form a plurality of channel holes 203 that pass through the alternating silicon oxide layers 206 and silicon nitride layers 208. The channel holes 203 can be formed by laminating a mask (not shown) on a portion of the stack and performing an etching process to remove the material exposed by the mask. Any etching process can be used, and some embodiments may use dielectric etching. Etching through the alternating silicon oxide layers 206 and silicon nitride layers 208 benefits from dielectric etching because the required aspect ratio of the channel holes 203 of the device channels is relatively high (i.e., the vertical depth of the channel holes 203 is relatively large compared to the horizontal width of the channel holes 203). Generally, the depth of the channel holes 203 can be controlled according to the number of silicon oxide layers 206 and silicon nitride layers 208 to be etched. For example, the time allowed for the etching process can be determined according to the number of silicon oxide layers 206 and silicon nitride layers 208 of these layers and their thicknesses. For example, some embodiments may etch the channel holes 203 to the silicon nitride layer 204. Other embodiments may etch the channel holes 203 to the silicon oxide layer 202, or to the top of the substrate 201. Figure 2A As shown in Figure 2A , the stack 224 can be etched to form a plurality of channel holes 203 that pass through the alternating silicon oxide layers 206 and silicon nitride layers 208. The channel holes 203 can be formed by laminating a mask (not shown) on a portion of the stack and performing an etching process to remove the material exposed by the mask. Any etching process can be used, and some embodiments may use dielectric etching. Etching through the alternating silicon oxide layers 206 and silicon nitride layers 208 benefits from dielectric etching because the required aspect ratio of the channel holes 203 of the device channels is relatively high (i.e., the vertical depth of the channel holes 203 is relatively large compared to the horizontal width of the channel holes 203). Generally, the depth of the channel holes 203 can be controlled according to the number of silicon oxide layers 206 and silicon nitride layers 208 to be etched. For example, the time allowed for the etching process can be determined according to the number of silicon oxide layers 206 and silicon nitride layers 208 of these layers and their thicknesses. For example, some embodiments may etch the channel holes 203 to the silicon nitride layer 204. Other embodiments may etch the channel holes 203 to the silicon oxide layer 202, or to the top of the substrate 201. Figure 2A The non-limiting example shown in Figure 2A stops etching at the top of the silicon nitride layer 204.

[0027] Figure 2BIllustrates how, according to some embodiments, bottom impact is used to penetrate substrate 201 to expose the silicon of substrate 201. In Figure 2B the dielectric etch used may stop the channel hole etch before etching through substrate 201. Some embodiments may then perform a second etch process such that the channel holes 203 extend into substrate 201. This additional etch may be a directional etch vertically towards the bottom of the channel holes 203, commonly referred to as "bottom impact" etch. The bottom impact etch may expose the silicon material of substrate 201 at the bottom of the channel holes 203. In some embodiments, the bottom impact etch may be separate from the etch used to form the channel holes 203. For example, the bottom impact etch may be performed in a conductor etch chamber rather than a dielectric etch chamber, which may provide better critical dimension uniformity and profile control than the dielectric etch initially used to form the channel holes 203 of the device channels. Thus, the bottom impact etch may extend the channel holes 203 into substrate 201 to expose the silicon material. For example, the bottom impact etch may extend to the top surface of substrate 201, or alternatively penetrate substrate 201 below the top surface of substrate 201. Alternatively, other embodiments may etch the entire length of the channel holes 203 in a single etch process such that Figures 2A through 2B the results are combined into a single-step process. The exposed silicon material of substrate 201 may be used in subsequent steps to epitaxially grow silicon by forming the channels of 3D NAND flash memory cells.

[0028] Figure 2C Illustrates how the stack 224 is extended by adding a second layer 213 over the first layer 205, where the second layer 213 may include additional silicon oxide layer 207 and silicon nitride layer 209. These additional layers may be formed stepwise over the first layer 205. After adding the additional silicon oxide layer 207 and silicon nitride layer 209 of the second layer 213, as shown, a plurality of holes 211, 219 may be etched in the second layer 213. Note that these holes 211, 219 may be formed using a mask similar to that previously used to etch the channel holes 203 in the first layer 205. By stepwise etching these layer sets, very high aspect ratios can be achieved even though the depth of the holes 211, 219 is large throughout the stack 224.

[0029] In practice, the stack 224 may include a large number of layers, a large number of channel holes, and may be used to form hundreds of 3D NAND flash memory cells. However, these figures have been simplified to show a single epitaxial silicon channel and adjacent support structures or slits in the memory array. For example, an actual stack may include thousands of channels, over 100 alternating oxide and nitride layers, and multiple slits and support structures. These layers may be formed in multiple processes, and the etching operations are performed stepwise on each batch of layers added to the partial stack. Thus, althoughFigure 2B Only two partially stacked combinations are shown, but it should be understood that many other partial stacks can also be stacked and etched to form the channel hole 203 through the stack 224. For example, some embodiments may include a combination of two partial stacks, each partial stack having approximately 128 alternating oxide-nitride layers, for a total of 256 alternating oxide-nitride layers.

[0030] Figure 2D A support member 210 according to some embodiments is shown and can be formed within a certain hole, such as hole 211, to provide support for the stack 224 in subsequent steps of the process. The support member 210 can be selectively deposited within the hole to form a rigid structure between the first layer 205 and the second layer 213. For example, some embodiments may use a metal, such as tungsten, to form the support member 210. Some embodiments may use a dielectric filler, such as SiOx or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack, as the support member 210. Any deposition process can be used to form the support member 210. Note that the support member 210 can extend into the substrate 201 through the etching process described above, which extends beyond the final silicon oxide layer 202. As will be shown later in this disclosure, the support member 210 can prevent the layers of the stack 224 from collapsing when the silicon nitride layer 204 is removed. In addition, extending the support member 210 into the substrate 201 can prevent any movement of the upper layers of the stack 224 when the silicon nitride layer 204 is removed later.

[0031] Figure 2E An initial epitaxial silicon layer 212 within the hole 219 according to some embodiments is shown. As mentioned previously, the additional depth of the bottom erosion into the substrate 201 exposes the silicon material of the substrate 201 into the channel hole 219. Since the single-crystalline silicon of the substrate 201 has been exposed, an epitaxial silicon layer 212 can be grown in the channel hole through an epitaxial process such as silicon epitaxial deposition or growing a thin layer of single-crystalline silicon on the single-crystalline silicon substrate 201. For example, some embodiments may perform the epitaxial process through chemical vapor deposition. Chemical source materials for silicon, such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other silicon-based materials, can be supplied to the deposition chamber to gradually form the epitaxial silicon 212 grown on the substrate 201. The height of the epitaxial silicon 212 may be higher than the silicon oxide layer 202 but lower than the next silicon oxide layer 206 in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204.

[0032] Figure 2FDepiction of depositing a tunnel layer 214 in a via 219 is shown. Since the via 219 can now be used to form vertical columns of 3D NAND memory cells, this via 219 may also be referred to as a channel via 219 in this description. The tunnel layer 214 can be formed by depositing a blocking dielectric or oxide, a charge trapping nitride (such as silicon nitride), and a tunneling dielectric or oxide. These three layers may be collectively referred to as the "tunnel layer" 214 in this disclosure. The oxide layer in the tunnel layer 214 can provide an offset between the conduction band and the valence band for the transistor device of the memory cell.

[0033] In some embodiments, a layer of silicon nitride may be encapsulated between inner and outer layers of silicon oxide. The various layers of the tunnel layer 214 can be formed using atomic layer deposition, so the layers of the tunnel layer 214 may be relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process may cause the tunnel layer 214 to grow along the sidewalls of the channel via 219 and above the bottom of the channel via over the epitaxial silicon 212. Since the epitaxial silicon 212 stops before the alternating silicon oxide layers 206 and silicon nitride layers 208, the interior of the channel of the 3D NAND memory cell can be covered by the tunnel layer 214.

[0034] Figure 2G Depiction of the deposition of a channel liner 217 formed above the tunnel layer 214 within the channel via 219 is shown. The channel liner 217 may be aluminum oxide (AlO) formed using atomic layer deposition, so it may be relatively thin compared to the alternating oxide-nitride layers of the stack 224. This process may cause the channel liner 217 to grow on the tunnel layer 214.

[0035] Figure 2H Depiction of how the channel via 219 may be filled with a core spacer material 216 in some embodiments is shown. To protect the tunnel layer 214 and the channel liner 217 during subsequent etching processes, the channel via 219 may be filled with the core spacer material 216, which may be SiO. As shown, the core spacer material 216 can be formed directly above the channel liner 217.

[0036] Figure 2I Depiction of a slit 218 that can be etched in the stack 224 according to some embodiments is shown. The slit 218 can represent a relatively long trench that is etched in the stack 224 such that the slit 218 is adjacent to the channel vias 219, 211 along the length of the slit 218. Compared to the etching processes used to form the channel vias 211 and 219, the slit 218 can be etched using a single process that passes through all the layers of the stack 224. More specifically, the slit 218 can extend into the silicon nitride layer 204. The use of a single process is possible because the width of the slit 218 may be greater than that of the channel via. Therefore, the aspect ratio may be smaller and thus can be achieved in a single process.

[0037] Figure 2J Shows a slit liner 220 deposited inside the slit 218 to protect the internal silicon oxide layer 206 and silicon nitride layer 208 of the first layer 205, and to protect the additional silicon oxide layer 207 and silicon nitride layer 209 of the second layer 213 from the subsequent chemical etching process using the slit 218. For example, the slit liner 220 can be deposited on the sidewalls and bottom of the slit 218, and subsequent etching can be used to remove the slit liner 220 from the bottom of the slit 218 to expose the silicon nitride layer 204. The slit 218 can be used in the memory arrays of two independent memory blocks. In subsequent processes, the slit 218 can also provide access to all the nitride layers in the access stack 224, enabling these nitride layers to be removed and replaced with tungsten (or any other conductive material) to form the conductive channels of each memory cell. These conductive channels can later form the word lines or gates of the memory cells. For example, wet etching using hot phosphoric acid can be used to remove the nitride layers in the stack 224, and then the slit 218 can provide access for precursors, enabling tungsten to be grown in the pores left by the removed nitride layers using atomic layer deposition process. In some embodiments, the slit liner 220 can be amorphous silicon (a-Si).

[0038] Figure 2K Shows the selective removal of the silicon nitride layer 204 in the stack 224 according to some embodiments ( Figure 2J ). To grow epitaxial silicon 212 in the channel holes, it may be necessary to remove the silicon nitride layer 204 to expose portions of the tunnel layer 214 and channel liner 217 that need to be removed, so that the epitaxial silicon 212 can be exposed to the channel holes again. In this example, wet etching, such as hot phosphoric acid chemical etching, may be used. The wet etching can access the silicon nitride layer 204 through the slit 218 and selectively remove the silicon nitride layer 204. The slit liner 220 can protect the internal nitride layers from the etching process. Other embodiments may use dry etching or other processes designed to selectively remove the silicon nitride layer 204.

[0039] Figure 2L Shows a mask layer 232 formed on the stack 224, including above the core gap filling material 216 within the channel hole 219 and above the support feature 210 within the channel hole 211. As shown, the mask layer 232 may provide openings 233 penetrating therethrough, where the openings 233 are aligned with the slit 218.

[0040] Figure 2MIt shows that the tunnel layer 214 and the channel liner 217 are selectively removed from the bottom of the channel hole 219 to form a gap 230 between the epitaxial silicon 212 and the bottom silicon oxide layer 206. A lateral wet etching process may be used to selectively remove the tunnel layer 214 and the channel liner 217. As shown, the channel liner 217 may also be partially recessed into the channel hole 219. The partial removal of the channel liner 217 causes the channel hole 219 to be covered by the tunnel layer 214 and exposed to the epitaxial silicon 212.

[0041] Note that the gap 230 left from the removal of the nitride layer, the tunnel layer 214, and the channel liner 217 is covered by oxide layers (e.g., the oxide layer 202 and the bottom silicon oxide layer 206) both above and below. These oxide layers may be formed slightly thicker than the other oxide layers in the stack 224. However, since the oxide and nitride layers in the tunnel layer 214 and the channel liner 217 may be formed as atomic layer deposition layers, these layers will be relatively thin and thus can be removed without removing a significant portion of the other oxide layers that may be exposed to the etching process.

[0042] Figure 2N It shows the growth of the epitaxial silicon 212 according to some embodiments. The epitaxial process may be performed as described above. However, since the slit 218 and the channel hole 219 are exposed to the epitaxial silicon 212, an epitaxial silicon layer 236 may be grown to fill the gap 230 ( Figure 2M ), and start to fill the channel hole 219. More specifically, the epitaxial silicon layer 236 may extend along the tunnel layer 214 to form an epitaxial core layer 242 at the lower part of the channel hole 219. When reaching the channel liner 217, the growth of the epitaxial silicon layer 236 may stop to prevent the slit 218 from also being filled by the epitaxial silicon layer 236.

[0043] Figure 2O It shows the selective removal of the portion 243 of the epitaxial silicon layer 236 at the bottom of the slit 218. An etching process may be used to remove the portion 243 of the epitaxial silicon layer 236 to perform the bottom "punching" as described above. This etching may remove the portion 243 of the epitaxial silicon layer 236 until the bottom oxide layer 202 is exposed. Alternatively, the etching may penetrate the bottom oxide layer 202 into the substrate 201.

[0044] Figure 2P It shows the deposition of a sacrificial gap filling material 240 in the slit 218 according to some embodiments. The sacrificial gap filling material 240 may be deposited in the slit 218, including within the portion 243 of the epitaxial silicon layer 236, such that the epitaxial silicon 236 can grow in the channel hole 219 without filling the slit 218. In some embodiments, the sacrificial gap filling material 240 is directly formed above the bottom oxide layer 202.

[0045] Figure 2Q shows the remaining portion of the channel liner 217 ( Figure 2P ) being removed from the channel hole 219. As shown, the channel liner 217 is removed along from the tunnel layer 214 in the region above the epitaxial core layer 242. In some embodiments, the core gap fill material 216 remains in place while the channel liner 217 is removed from above the channel hole 219.

[0046] Figure 2R shows the epitaxial growth of epitaxial silicon 236 through the channel hole 219 according to some embodiments. The epitaxial process can be performed as described above to further grow the epitaxial core layer 242 in the region vacated by the channel liner 217 in the channel hole 219. The final structure can include a stack 224 with the channel hole 219 filled with a hollow epitaxial silicon core 244 having a "through-plane" structure. The hollow epitaxial silicon core (hereinafter referred to as "epi-core") 244 can be formed between the tunnel layer 214 and the core gap fill material 216. As shown, the epi-core 244 can be physically connected to the substrate 201, the epitaxial silicon 212, and the tunnel layer 214.

[0047] Still referring to Figure 2R , the device 200 (e.g., a 3D NAND memory structure) can include a silicon substrate 201, which may be made of single-crystalline silicon. The device can also include a plurality of alternating material layers 275 arranged in a vertical stack on the silicon substrate 201. The alternating material layers 275 can include alternating layers of an oxide material and a nitride material (e.g., silicon oxide and silicon nitride). At a later stage in the manufacturing process, the alternating material layers 275 may be changed to include alternating layers of an oxide material and a metal (such as tungsten). For example, the nitride material may be selectively removed and replaced with a metal to form the gate electrode of each memory cell in the memory structure.

[0048] The channel hole 219 may extend through the plurality of alternating material layers 275 to the silicon substrate 201. This channel hole 219 can be formed using any process described in the present disclosure. As shown, the channel hole 219 may be nearly perpendicular to the plurality of alternating material layers 275. The device 200 can also include a channel 248 located within the channel hole 219. The channel can include a tunnel layer 214 around the inside of the channel hole 219 (and thus also around the outside of the channel), using the layers described above. The channel 248 can also include an epi-core 244 located inside the tunnel layer 214 and contacting the silicon substrate 201. In some cases, the epi-core 244 may extend into the silicon substrate 201 such that the epi-core 244 starts its epitaxial growth below the top level of the silicon substrate 201. In some embodiments, the channel 248 may further include a core gap fill material 216 located within the epi-core 244.

[0049] The apparatus 200 may also include an epitaxial silicon layer 236 that extends beyond the channel hole 219, and the epitaxial silicon layer 236 is parallel to the plurality of alternating material layers 275. Although Figure 2R only one channel among the numerous channels in the device 200 is shown, the epitaxial silicon layer 236 may connect the epi core 244 of the shown channel 248 to the other multiple channels in the apparatus 200. For example, the epi cores of each channel connected by the epitaxial silicon layer 236 may be grown simultaneously from the epitaxial silicon layer 236 in the same epitaxial process.

[0050] The above process can be used to selectively grow the epi core 244 using the single-crystalline silicon of the substrate 201. The 3D NAND flash memory cell using the hollow "macaroni"-shaped epi core 244 is beneficial for reducing the volume of the epitaxial silicon and reducing the sensitivity of the threshold voltage to the trap density fluctuation.

[0051] Further processes may be performed on the stack 224 to complete the memory array. Although these operations are beyond the scope of the present disclosure, they may include removing the sacrificial gap-fill material 240 from the slit, removing the nitride layer in the stack 224, depositing a conductive metal (e.g., tungsten) at the position of the nitride layer to form a gate electrode, performing a stepped etch on the stack 224, etc.

[0052] Figure 3A A portion of a memory array 300 according to some embodiments is shown. A portion of this memory array 300 may represent a single memory frame having offset channel 256 rows. The slits 250, 252 may be used to separate this memory frame from other memory frames. This embodiment uses 24 channels arranged in offset columns between the slits 250, 252. This portion of the memory array 300 may use a conventional oxide or polysilicon core as the channel. Therefore, no support structure is required, and each channel hole can be used to implement a memory cell.

[0053] In contrast, Figure 3B A portion of a memory array 301 according to some embodiments is shown, where some channels are used as support structures to facilitate the epitaxial silicon channel core. As described above, the process for growing the epitaxial silicon channel for the memory cells in the memory array 301 may use a process in which some channel holes are used as support structures 254 to prevent the memory array 301 from collapsing when removing the sacrificial nitride layer to make room for the epitaxial silicon layer. These support structures 254 may be evenly spaced in the memory array to provide sufficient support for the layer stacking in the array during the manufacturing process. Note that Figure 3BThe intervals shown are for illustration only and are not restrictive. In this example, the intervals of the support structure 254 are approximately every four channel holes and every other column. This configuration does slightly reduce the bit density per unit area of the memory array 301 because some of the channel holes that would otherwise be used for memory cells are used as the support structure 254.

[0054] As described above, some embodiments may utilize channel holes to provide support structures during the manufacturing process. The advantage of using channel holes as support structures is the ability to increase or decrease the intervals of the support structures as needed. However, some embodiments may instead use slits rather than channel holes to form the same epitaxial silicon channels to provide support structures. These embodiments make a trade-off between the amount of support in the memory frame and the increase in channel density.

[0055] Figures 4A through 4N Shown are the step-by-step steps during the manufacturing process of a memory structure according to some embodiments, which utilize slits that divide the memory frame and use these slits as support structures when growing epitaxial silicon channels for individual memory cells. Figure 4A Shown are the channel holes 401 in the stack 400 according to some embodiments, where the channel holes 401 have epitaxial silicon 406 grown from the substrate 404. The channel holes 401 and the epitaxial silicon 406 can be formed using the processes described above, Figures 2A through 2E which are related. In some embodiments, the epitaxial silicon 406 can be formed after the channel holes 401 are formed in the first set of oxide / nitride layers and before the upper oxide / nitride layers are formed and etched to extend the channel holes 401. For example, going back Figure 2B , after the channel holes 203 are etched and the channel holes 203 are extended to the substrate 201 using bottom via etching, the epitaxial silicon 406 can grow from the exposed substrate 201 in the channel holes 203 at this stage. After the epitaxial silicon 406 is formed in the holes 203, the upper alternating oxide layers 207 and nitride layers 209 can be added and etched to increase the number of device layers and the depth of the channel holes 203, ultimately forming Figure 4A the structure shown. Alternatively, the epitaxial silicon 406 can be grown after the channel holes 401 are completely formed, or can be grown at any stage after the silicon of the substrate 404 is exposed.

[0056] Figure 4B Shown is the situation of the channel holes 401 after being lined with the tunnel layer 408. The tunnel layer 408 can be formed as detailed above Figure 2H in. Figure 4C Shown is the situation of the channel holes 401 after being further lined with the channel liner 417. The channel liner 417 can be formed as detailed above Figure 2G in. Figure 4DShows a channel hole 401 filled with a sacrificial gap-fill material 410, which can be formed as described in detail above Figure 2H as detailed above.

[0057] Figure 4E Shows slits 412, 413 formed on both sides of a memory cell block according to some embodiments. It should be understood that although only two channel holes are shown, there may be many additional channels between the slits 412, 413. For example, the slits 412, 413 can surround a memory cell block that is 24 channels wide. These channels can be arranged in a honeycomb pattern, forming two offset rows of 12 channels each. There may be multiple pairs of these 24-channel offset rows within the block. As shown, the etch depth of slit 413 is below the first oxide layer 427 and is located within the sacrificial nitride layer 415. However, in order to provide a support structure during subsequent fabrication of the epitaxial silicon layer and the channel core, the slit may undergo an additional or extended etching process to increase the depth of the slit. For example, slit 412 may be etched below the top of the substrate 404 using bottom impact etching. This enables slit 412 to serve as a support structure fixed to the substrate 404 rather than floating above the substrate 404.

[0058] Figure 4F Shows slit 412 filled with a gap-fill material 414 according to some embodiments. In this embodiment, alternating slits can be used as support structures in the memory array. Thus, slit 413 may remain at a shallower depth while slit 412 may be etched to a depth below the substrate 404 and filled with a gap-fill material 414, which can serve as a support structure during subsequent epitaxial silicon layer growth.

[0059] Figure 4G Shows a slit liner 418 that can be deposited inside slit 413 and subsequently etched to remove the slit liner 418 at the bottom of slit 413 to expose the sacrificial nitride layer 415. The formation of the slit liner 418 is as Figure 2J described in detail above.

[0060] Figure 4H Shows the removal of the sacrificial nitride layer 415 according to some embodiments. As described above in Figure 2K the sacrificial nitride layer 415 can be exposed to an etching process through slit 413 to selectively remove the sacrificial nitride layer 415. Removing the sacrificial nitride layer 415 exposes the lower portion 419 of the tunnel layer 408 in the region above the epitaxial silicon 406 grown on the substrate 404.

[0061] Figure 4IA mask layer 432 is shown formed on top of the device 400, and the sacrificial nitride layer 415 is removed. In some embodiments, the channel liner 417 may be partially indented into the channel hole 401. The removal of the sacrificial nitride layer 415 and the channel liner 417 is as Figure 2M described in detail. After removing the exposed portion 419 of the tunnel layer 408 at the bottom of the channel hole 401 ( Figure 4H ) and the channel liner 417, the gap filling material 414 can provide a support structure to keep the stack 400 from collapsing after the gap 416 between the exposed substrate 404 and the first oxide layer 427.

[0062] Figure 4J The epitaxial growth of the epitaxial silicon layer 420 in the gap 416 is shown. As described above, the epitaxial silicon layer 420 can be grown to the extent of starting to fill the channel hole 401, for example, in the area where the channel liner 417 is removed. In a more specific case, the epitaxial silicon layer 420 can extend along the tunnel layer 408 to form an epitaxial core layer 442 in the lower part of the channel hole 401.

[0063] Figure 4K The formation of holes 422 in the epitaxial silicon layer 420 is shown to expand the slit 413 using a bottom impact etching process, while Figure 4L the filling of the slit 413 with the gap filling material 424 is shown. These steps can be carried out as Figure 2O and Figure 2P described in detail.

[0064] Figure 4M The process of further removing the channel liner 417 from the channel hole 401 is shown, while Figure 4N the upward growth of the epitaxial silicon layer 420 in the channel hole 401 according to some embodiments is shown. The epitaxial process can be carried out as described above to further grow the epitaxial core layer 442 into the channel hole 401, for example, in the area vacated by the channel liner 417. The resulting structure may include a hollow epitaxial silicon core 444 having a "macaroni" structure. This hollow epitaxial silicon core (hereinafter referred to as "epi core") 444 can be formed between the tunnel layer 408 and the sacrificial gap filling material 410. As shown, the epi core 444 can be physically connected to the substrate 404 and the tunnel layer 408.

[0065] Located Figure 4N in the final stack 400 shown, the channel can be connected to Figure 2RThe channels of the final stack 224 shown are substantially the same, each having alternating material layers 475 and channel holes 401, with each channel hole lined internally with a tunnel layer 408 and filled with an epi core 444. As further shown, sacrificial gap fill 410 material may be present within the epi core 444. However, in a memory structure including this stack 400, none of the channels need to be retained as a support structure. Instead, by using slits as a support structure during manufacturing, the maximum channel density can be achieved. As described above, additional process steps outside the scope of this disclosure may subsequently be performed on the stack 400 to complete the manufacture of the memory structure, such as removing alternating nitride layers, forming conductor layers (e.g., tungsten layers) to form gate electrodes, performing staircase etching, etc.

[0066] Figures 5A through 5H Illustrated are step - by - step steps in the manufacturing process of a memory structure, where in some embodiments, when growing an epitaxial silicon channel for an individual memory cell, slits separating memory blocks are used as a support structure. Figure 5A Illustrated is the use of the above - described Figures 4A through 4F - related process to form a stack 500. As further shown, a first channel hole 501 may be formed through the layers of the stack 500 and then filled with a support structure 509. A second channel hole 501 may be filled with a gap fill material 510, a tunnel layer 508, and a channel liner 517 that separates the gap fill material 510 from the epitaxial silicon 511 grown on the substrate 504. The stack 500 may also include slits 513 and 523. Note that there may also be many channel holes in the stack 500 that are Figure 5A not visible in

[0067] As Figure 5B shown, a slit liner 520 may be located within the slit 513, and the slit liner 520 is etched to a level above the substrate 504 to contact a layer of sacrificial nitride layer 518. The slit 523 may be filled with a gap fill material 588 and may extend to the substrate 504 to serve as a support structure.

[0068] The remaining steps of growing epitaxial silicon into the channels of the stack 500 can be performed in detail as described above. For example, Figure 5C illustrated is the removal of the sacrificial nitride layer 518 to expose the gap 539 while the stack 500 is supported by the support structure. Figure 5D Illustrated is the removal of portions of the tunnel layer 508 and the channel liner 517 exposed in the gap 539. The channel liner 517 may be recessed into the second channel hole 501. Figure 5E Illustrated is the growth of an epitaxial silicon layer 516 in the gap 539, while Figure 5F illustrated is the result of bottom penetration of the epitaxial silicon layer 516, followed by the formation of a gap fill material 520 in the slit 513.Figure 5F Further shown is an epitaxial core layer 542 partially grown in the first channel hole 501. Figure 5G Shown is the removal of the channel liner 517, while Figure 5H shown is the further growth of the epitaxial core layer 542 to form a hollow epitaxial silicon core 544.

[0069] Figure 6 Shown is a method flow chart 600 for manufacturing a 3D NAND memory structure according to some embodiments. The method may be performed in various processing chambers in a semiconductor processing system, for example, as Figure 1 shown.

[0070] In block 601, the method may include forming a plurality of alternating material layers on a substrate, the alternating material layers being arranged in a vertically stacked manner. In some embodiments, the alternating material layers include alternating layers of an oxide material and a nitride material. In some embodiments, the alternating material layers include alternating layers of an oxide material and a metal, where the metal forms a gate electrode of a single memory cell.

[0071] In block 602, the method may include etching channel holes that extend through the plurality of alternating material layers to the substrate.

[0072] In block 603, the method may include forming a tunnel layer around the channel holes to contact the plurality of alternating material layers. In some embodiments, the tunnel layer may include a blocking dielectric layer or oxide layer, a charge trapping nitride layer, and a dielectric layer or oxide layer.

[0073] In block 604, the method may include forming a channel liner along the tunnel layer. In some embodiments, the channel liner may be AlO deposited by atomic layer deposition (ALD).

[0074] In block 605, the method may include forming a core gap material within the channel liner. In some embodiments, the core gap material may be SiO and is used to fill the channel holes.

[0075] In block 606, the method may include removing the channel liner from the channel holes. In some embodiments, removing the channel liner from the channel holes includes recessing a first portion of the channel liner from a lower section of the channel holes.

[0076] In block 607, the method may include epitaxially growing a hollow epitaxial silicon core from the substrate through the channel holes, the core being located between the tunnel layer and the core gap material. In some embodiments, the epitaxial core layer is first grown within the lower section of the channel holes after removing the first portion of the channel liner.

[0077] It should be understood that Figure 6The specific steps shown provide a particular method of manufacturing a 3D NAND memory structure according to various embodiments. According to other alternative embodiments, other orders of steps may also be performed. For example, alternative embodiments may perform the above steps in a different order. Additionally, Figure 6 each of the steps shown may include a plurality of sub-steps, which may be performed in various orders depending on the requirements of the specific step. Additionally, depending on the particular application, additional steps may be added or removed. Many variations, modifications, and alternatives are also within the scope of the present disclosure.

[0078] In various embodiments, design tools may be provided and configured to create a data set for patterning a device semiconductor layer, for example, as described herein. For example, a data set may be created to generate a photomask used in a lithography operation to pattern a structural layer as described herein. These design tools may include a collection of one or more modules and may also be composed of hardware, software, or a combination thereof. Thus, for example, a tool may be a collection of one or more software modules, hardware modules, software / hardware modules, or any combination or arrangement. As another example, a tool may be a computing device or other device running software, or implemented in hardware.

[0079] For convenience and clarity, terms such as "upper", "lower", "upper part", "lower part", "vertical", "horizontal", "lateral", and "longitudinal" will be used in this document to describe the relative positions and orientations of components and their parts in the figures. The term will include the specifically mentioned words, their derivative forms, and synonyms.

[0080] Furthermore, it is noted that individual embodiments may have been described as processes, which are shown in the form of flowcharts, process schematics, data flow diagrams, structure diagrams, or block diagrams. Although a flowchart may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. When the operations of a process are completed, the process terminates, but there may be other steps not included in the figure. A process may correspond to a method, function, program, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0081] An element or operation used herein that is expressed in the singular form and preceded by the word "a" or "an" should be understood to include plural elements or operations, unless explicitly excluded. Additionally, a reference to "one embodiment" of the present disclosure is not intended to be limiting. Other embodiments may also include the described features.

[0082] In addition, the terms "substantially" or "substantially", and "approximately" or "approximately", may be used interchangeably in some embodiments and may be described in terms of any relative measure acceptable to one of ordinary skill in the art. For example, these terms may be used as a comparison of reference parameters to indicate a deviation that provides the desired function. Although not limiting, the deviation from the reference parameter may be, for example, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.

[0083] In addition, one of ordinary skill in the art will understand that when an element such as a layer, region, or substrate is referred to as being "on", "above", or "over" another element, the element can be directly on the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly on", "directly above", or "directly over" another element, there are no intervening elements.

[0084] The scope of the present disclosure should not be limited to the specific embodiments described herein. In fact, in addition to these specific embodiments, various other embodiments and modifications of the present disclosure will be apparent to one of ordinary skill in the art from the foregoing description and the accompanying drawings. Accordingly, these other embodiments and modifications are intended to be included within the scope of the present disclosure. In addition, the present disclosure is described herein with respect to specific embodiments in a specific environment and for a specific purpose. Those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be advantageously implemented in any number of environments and for any number of purposes. Accordingly, the following claims should be construed in the context of the full scope and spirit of the present disclosure.

Claims

1. A three-dimensional (3D) NAND memory structure, the 3D NAND memory structure comprises: a silicon substrate; a plurality of alternating material layers arranged in a vertically stacked manner on the silicon substrate, wherein channel holes extend through the plurality of alternating material layers to the silicon substrate, and wherein the channel holes are perpendicular to the plurality of alternating material layers; and a channel located within the channel holes, wherein the channel comprises: a tunnel layer surrounding the interior of the channel holes, the tunnel layer contacting the plurality of alternating material layers; and a hollow epitaxial silicon core portion located within the tunnel layer, wherein the hollow epitaxial silicon core portion contacts the silicon substrate.

2. The 3D NAND memory structure according to claim 1, wherein the silicon substrate comprises single-crystalline silicon, and the hollow epitaxial silicon core portion is grown through the channel holes.

3. The 3D NAND memory structure according to claim 1, wherein the plurality of alternating material layers comprise alternating oxide materials and nitride materials.

4. The 3D NAND memory structure according to claim 1, wherein the plurality of alternating material layers comprise alternating oxide materials and metals, and wherein the metals form gate electrodes of individual memory cells.

5. The 3D NAND memory structure according to claim 1, wherein the hollow epitaxial silicon core portion extends into the silicon substrate.

6. The 3D NAND memory structure according to claim 1, the 3D NAND memory structure further comprising an epitaxial silicon layer extending beyond the channel holes, the epitaxial silicon layer being located between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer connecting the hollow epitaxial silicon core portion to a plurality of other channels.

7. The 3D NAND memory structure according to claim 6, the 3D NAND memory structure further comprising a support structure passing through the plurality of alternating material layers and the epitaxial silicon layer, wherein the support structure extends into the silicon substrate.

8. A method for manufacturing a three-dimensional (3D) NAND memory structure, the method comprises: forming a plurality of alternating material layers on a substrate, the plurality of alternating material layers being arranged in a vertically stacked manner; etching channel holes, the channel holes extending through the plurality of alternating material layers to the substrate; forming a tunnel layer around the channel holes, the tunnel layer contacting the plurality of alternating material layers; forming a channel liner along the tunnel layer; forming a core gap material within the channel liner; removing the channel liner from the channel holes; and epitaxially growing a hollow epitaxial silicon core portion from the substrate through the channel holes between the tunnel layer and the core gap material.

9. The method according to claim 8, the method further comprising etching slits in the memory structure, wherein the slits extend through the plurality of alternating material layers and into a sacrificial nitride layer, and wherein the sacrificial nitride layer is located above the substrate.

10. The method according to claim 9, wherein the method further comprises selectively etching the sacrificial nitride layer to expose portions of the tunnel layer and the channel liner.

11. The method according to claim 10, wherein the method further comprises removing the portions of the tunnel layer and the channel liner.

12. The method according to claim 10, wherein the method further comprises epitaxially growing an epitaxial silicon layer over the substrate after removing the portions of the tunnel layer and the channel liner.

13. The method according to claim 8, wherein the method further comprises: etching a second channel hole that passes through the plurality of alternating material layers, wherein the second channel hole extends to the substrate; and filling the second channel hole with a gap-fill material to support the vertical stack.

14. The method according to claim 8, wherein removing the channel liner from the channel hole comprises recessing a first portion of the channel liner from a lower section of the channel hole, and wherein an epitaxial core layer is epitaxially grown inside the lower section of the channel hole.

15. A method for fabricating a hollow epitaxial silicon core of a three-dimensional (3D) NAND memory structure, the method comprises: forming a plurality of alternating material layers on a silicon substrate, the plurality of alternating material layers being arranged in a vertical stack; etching a channel hole that extends through the plurality of alternating material layers to the silicon substrate; forming a tunnel layer around the channel hole, wherein the tunnel layer contacts the plurality of alternating material layers; forming a channel liner layer around the tunnel layer; forming a core gap material within the channel liner layer; removing the channel liner layer from the channel hole; and epitaxially growing the hollow epitaxial silicon core from the silicon substrate through the channel hole between the tunnel layer and the core gap material.

16. The method according to claim 15, wherein the method further comprises etching a slit in the memory structure, the slit passing through the plurality of alternating material layers, wherein the slit extends to a sacrificial nitride layer, and wherein the sacrificial nitride layer is located above the silicon substrate.

17. The method according to claim 16, wherein the method further comprises selectively etching the sacrificial nitride layer to expose portions of the tunnel layer and the channel liner.

18. The method according to claim 17, wherein the method further comprises removing the portions of the tunnel layer and the channel liner to form a gap between the silicon substrate and the channel liner.

19. The method according to claim 18, wherein the method further comprises epitaxially growing an epitaxial silicon layer from the silicon substrate, wherein the epitaxial silicon layer extends into the gap.

20. The method according to claim 15, wherein removing the channel liner from the channel hole comprises recessing a first portion of the channel liner from a lower section of the channel hole, and wherein an epitaxial core layer is grown epitaxially inside the lower section of the channel hole.

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