Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device that is easy to miniaturize. Provided is a semiconductor device in which parasitic capacitance is reduced. In the semiconductor device, an insulating layer serving as a first spacer is provided between a lower electrode of one of a source electrode and a drain electrode of a transistor and an upper electrode of the other, and an insulating layer serving as a second spacer is provided on the upper electrode. The first spacer, the upper electrode, and the second spacer are provided with a first opening that reaches the lower electrode. A semiconductor layer forming a channel is provided inside the first opening so as to connect the lower electrode and the upper electrode. A gate insulating layer and a gate electrode are provided inside the first opening so as to overlap the semiconductor layer. An interlayer insulating layer including a second opening portion reaching the gate electrode is provided over the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode. The gate electrode has a region in contact with the wiring on the interlayer insulating layer inside the second opening.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device, and also relates to methods for manufacturing these.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. Examples of the technical fields of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and methods for driving or manufacturing these devices. A semiconductor device refers to any device that operates by utilizing semiconductor characteristics. Background Art

[0003] In recent years, semiconductor devices have been developed, with CPUs (Central Processing Units), memories, and other LSIs (Large Scale Integration) being the main components of these devices. A CPU is an aggregate of semiconductor elements that includes a semiconductor integrated circuit (including at least transistors and memory) formed into a chip by processing a semiconductor wafer, and electrodes serving as connection terminals.

[0004] A CPU, a memory, and a semiconductor circuit (IC chip) of an LSI other than the above are mounted on a circuit board such as a printed wiring board, and are used as one of the components of various electronic devices.

[0005] In addition, technology for forming transistors using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (abbreviated as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, and oxide semiconductors are attracting attention as other materials.

[0006] It is known that transistors using oxide semiconductors have extremely low leakage current in their non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes this low leakage current characteristic. Furthermore, Patent Document 2 discloses a storage device capable of retaining stored data for a long period of time.

[0007] In addition, in recent years, with the miniaturization and lightweighting of electronic devices, the demand for further high-density integrated circuits has increased. In addition, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked to provide multiple memory cells in an overlapping manner, thereby increasing the density of the integrated circuit.

[0008] Furthermore, if vertical transistors can be realized, integrated circuits can be made more dense. For example, Patent Document 4 discloses a vertical transistor in which the side surfaces of an oxide semiconductor are covered with a gate electrode via a gate insulating layer.

[0009] [Prior technical literature]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0013] [Patent Document 3] International Publication No. 2021 / 053473

[0014] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0015] [Non-patent literature]

[0016] [Non-Patent Literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm,” IEDM Tech. Dig., 2019, pp. 50-53 Summary of the Invention

[0017] Technical problem to be solved by the invention

[0018] As semiconductor devices become increasingly miniaturized, the effects of parasitic capacitance cannot be ignored. For example, when parasitic capacitance increases, the operating speed of the semiconductor device may decrease.

[0019] One object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced parasitic capacitance. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that exhibits excellent electrical characteristics.

[0020] One object of one embodiment of the present invention is to provide a method for manufacturing a miniaturized semiconductor device. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with reduced parasitic capacitance. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that operates at high speed. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high reliability. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high yield. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that exhibits good electrical characteristics.

[0021] One object of one embodiment of the present invention is to provide a semiconductor device, memory device, display device, or electronic device having a novel structure. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, memory device, display device, or electronic device having a novel structure. Another object of one embodiment of the present invention is to alleviate at least one of the problems of prior art.

[0022] Note that the inclusion of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not necessarily achieve all of the above objectives. Note that objectives other than those listed above may be extracted from the description of the specification, drawings, claims, etc.

[0023] Means of solving technical problems

[0024] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, a second insulating layer, a third insulating layer and a wiring, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a fourth insulating layer, the first insulating layer is arranged on the first conductive layer, the second conductive layer is arranged on the first insulating layer, and the second insulating layer is arranged on the second conductive layer, the first insulating layer, the second conductive layer and the second insulating layer include a first opening portion reaching the first conductive layer, the semiconductor layer is located inside the first opening portion and has a region in contact with the first conductive layer and a region in contact with the second conductive layer, the fourth insulating layer is arranged between the semiconductor layer and the third conductive layer inside the first opening portion, the third conductive layer is arranged in a manner filling the first opening portion, the third insulating layer is arranged on the second insulating layer, the semiconductor layer, the fourth insulating layer and the third conductive layer and includes a second opening portion reaching the third conductive layer, the wiring has a region in contact with the third conductive layer inside the second opening portion and has a region overlapping with the semiconductor layer via the third insulating layer.

[0025] In addition, one embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a wiring, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a fourth insulating layer, the first insulating layer is provided on the first conductive layer, the second conductive layer is provided on the first insulating layer, the first insulating layer and the second conductive layer include a first opening reaching the first conductive layer, the second insulating layer is provided on the second conductive layer, the second insulating layer includes a second opening reaching the second conductive layer and having a region overlapping with the first opening, the semiconductor layer is located inside the first opening and inside the second opening and has a region in contact with the first conductive layer and a region in contact with the second conductive layer, the fourth insulating layer is provided between the semiconductor layer and the third conductive layer inside the first opening and inside the second opening, the third conductive layer is provided so as to fill the first opening and the second opening, the third insulating layer is provided on the second insulating layer, the semiconductor layer, the fourth insulating layer, and the third conductive layer and includes a third opening reaching the third conductive layer, and the wiring has a region in contact with the third conductive layer inside the third opening and has a region overlapping with the semiconductor layer via the third insulating layer.

[0026] In addition, in the above embodiment, the semiconductor layer may have a region in contact with the top surface of the second conductive layer.

[0027] In addition, in the above embodiment, the heights of the top surfaces of the second insulating layer, the semiconductor layer, the fourth insulating layer, and the third conductive layer may be consistent or substantially consistent with each other.

[0028] In the above embodiment, the semiconductor layer may also include a metal oxide. The metal oxide may include two or three selected from In, element M, and Zn, and element M may be one or more selected from Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.

[0029] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a first opening in the second insulating layer, the first conductive layer, and the first insulating layer; forming a semiconductor layer having an area in contact with the first conductive layer, a third insulating layer on the semiconductor layer, and a second conductive layer on the third insulating layer inside the first opening; forming a fourth insulating layer on the second insulating layer, the semiconductor layer, the third insulating layer, and the second conductive layer; forming a second opening reaching the second conductive layer in the fourth insulating layer; and forming wiring in a manner having an area in contact with the second conductive layer inside the second opening and having an area overlapping with the semiconductor layer via the fourth insulating layer.

[0030] In addition, the above method may also include the following steps: after forming the first opening portion, forming a semiconductor film, an insulating film on the semiconductor film, and a conductive film on the insulating film in a manner having an area located inside the first opening portion and an area overlapping with the second insulating layer; and forming a semiconductor layer, a third insulating layer, and a second conductive layer by flattening the conductive film, the insulating film, and the semiconductor film to expose the top surface of the second insulating layer.

[0031] Effects of the Invention

[0032] According to one embodiment of the present invention, a miniaturized semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with reduced parasitic capacitance can be provided. According to one embodiment of the present invention, a semiconductor device that operates at high speed can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device exhibiting excellent electrical characteristics can be provided.

[0033] According to one embodiment of the present invention, a method for manufacturing a miniaturized semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with reduced parasitic capacitance can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device that operates at high speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device that exhibits excellent electrical characteristics can be provided.

[0034] According to one embodiment of the present invention, a semiconductor device, a memory device, a display device, or an electronic device having a novel structure can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device, a memory device, a display device, or an electronic device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0035] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A and Figure 1B It is a perspective view showing a structural example of a semiconductor device.

[0037] Figure 2A is a plan view showing a structural example of a semiconductor device. Figure 2B and Figure 2C is a cross-sectional view showing a structural example of a semiconductor device.

[0038] Figure 3A and Figure 3B is a cross-sectional view showing a structural example of a semiconductor device.

[0039] Figure 4A is a cross-sectional view showing a structural example of a semiconductor device. Figure 4B is a plan view showing a structural example of a semiconductor device.

[0040] Figure 5A is a plan view showing a structural example of a semiconductor device. Figure 5B and Figure 5C is a cross-sectional view showing a structural example of a semiconductor device.

[0041] Figure 6A is a plan view showing a structural example of a semiconductor device. Figure 6B and Figure 6C is a cross-sectional view showing a structural example of a semiconductor device.

[0042] Figure 7A is a plan view showing a structural example of a semiconductor device. Figure 7B and Figure 7C is a cross-sectional view showing a structural example of a semiconductor device.

[0043] Figure 8A is a plan view showing a structural example of a semiconductor device. Figure 8B and Figure 8C is a cross-sectional view showing a structural example of a semiconductor device.

[0044] Figure 9A is a plan view showing a structural example of a semiconductor device. Figure 9B and Figure 9C is a cross-sectional view showing a structural example of a semiconductor device.

[0045] 10A to 10C is a cross-sectional view showing a structural example of a semiconductor device.

[0046] Figures 11A to 11C is a plan view showing a structural example of a semiconductor device.

[0047] Figure 12A is a plan view showing a structural example of a semiconductor device. Figure 12B and Figure 12C is a cross-sectional view showing a structural example of a semiconductor device.

[0048] 13A to 13D is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0049] Figure 14A and Figure 14B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0050] Figure 15A and Figure 15B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0051] Figure 16A and Figure 16B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0052] Figure 17A and Figure 17B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0053] Figure 18A and Figure 18B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0054] Figure 19A and Figure 19B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0055] Figure 20 is a circuit diagram showing a structural example of a storage device.

[0056] Figure 21A1 and Figure 21A2 is a plan view showing a structural example of a storage device. Figure 21B and Figure 21C is a cross-sectional view showing a structural example of a storage device.

[0057] Figure 22A is a plan view showing a structural example of a storage device. Figure 22B and Figure 22C is a cross-sectional view showing a structural example of a storage device.

[0058] Figure 23A is a plan view showing a structural example of a storage device. Figure 23B is a cross-sectional view showing a structural example of a storage device.

[0059] Figure 24A is a plan view showing a structural example of a storage device. Figure 24B is a cross-sectional view showing a structural example of a storage device.

[0060] Figure 25A is a plan view showing a structural example of a storage device. Figure 25B is a cross-sectional view showing a structural example of a storage device.

[0061] Figure 26 is a cross-sectional view showing a structural example of a storage device.

[0062] Figure 27 is a block diagram showing a structural example of a storage device.

[0063] Figure 28A It is a perspective view showing a structural example of a storage device. Figure 28B A perspective view and a circuit diagram showing a structural example of a storage device.

[0064] Figure 29A is a circuit diagram showing a structural example of a storage device. Figure 29B is a block diagram showing a structural example of a storage device. Figure 29C is a circuit diagram showing a structural example of a storage device. Figure 29D is a block diagram showing a structural example of a storage device.

[0065] Figure 30 is a block diagram showing a structural example of a storage device.

[0066] Figure 31A and Figure 31B It is a perspective view showing a structural example of a display device.

[0067] Figure 32 is a cross-sectional view showing a structural example of a display device.

[0068] Figure 33 is a cross-sectional view showing a structural example of a display device.

[0069] Figure 34 is a cross-sectional view showing a structural example of a display device.

[0070] Figure 35A It is a plan view showing a structural example of a display device. Figure 35B and Figure 35C is a cross-sectional view showing a structural example of a display device.

[0071] Figure 36A and Figure 36B is a cross-sectional view showing a structural example of a display device.

[0072] Figures 37A to 37D is a diagram illustrating an example of an electronic device.

[0073] Figures 38A to 38F is a diagram illustrating an example of an electronic device.

[0074] Figures 39A to 39G is a diagram illustrating an example of an electronic device.

[0075] Figure 40A and Figure 40B This is a diagram showing an example of an electronic component.

[0076] Figures 41A to 41C This is a diagram showing an example of a mainframe computer.

[0077] Figure 42A This is a diagram showing an example of space equipment. Figure 42B This is a diagram showing an example of a data center. DETAILED DESCRIPTION

[0078] The following describes the embodiments with reference to the accompanying drawings. However, those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0079] Note that in the structure of the invention described below, the same symbols are used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a special symbol.

[0080] Note that in the drawings described in this specification, the size of each component, layer thickness, or region may be exaggerated to facilitate understanding. Therefore, the present invention is not limited to the dimensions shown in the drawings.

[0081] Note that ordinal numbers such as “first” and “second” used in this specification and the like are provided to avoid confusion among constituent elements and are not intended to limit the number of constituent elements.

[0082] A transistor is a type of semiconductor element that can amplify current or voltage, control conduction or non-conduction, etc. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

[0083] In addition, when transistors of different polarities are used or when the direction of current changes during circuit operation, the functions of "source" and "drain" may be interchanged. Therefore, in this specification, "source" and "drain" may be used interchangeably.

[0084] Throughout this specification, "electrically connected" includes connection via "an element having some electrical function." This "element having some electrical function" is not particularly limited as long as it enables transmission and reception of electrical signals between the connected objects. For example, "element having some electrical function" includes switching elements such as transistors, resistors, coils, capacitors, and other components with various functions, in addition to electrodes and wiring.

[0085] In this specification, the top surface shape of a component refers to the outline shape of the component when viewed in plan view. In addition, plan view refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0086] Note that in this specification and other contexts, "substantially identical top surface shapes" refers to situations where at least a portion of the outlines of each layer in the stack overlap. For example, this includes situations where the upper and lower layers are processed using the same mask pattern, or where portions of the upper and lower layers are processed using the same mask pattern. However, strictly speaking, "substantially identical top surface shapes" can also be used in situations where the outlines do not overlap and the upper layer is positioned inside or outside the lower layer.

[0087] Note that, below, the terms "upper" and "lower" and other directional expressions generally follow the directions in the accompanying drawings. However, for simplicity, the directions indicated by "upper" or "lower" in this specification may not correspond to the directions in the accompanying drawings. For example, when describing the stacking order (or formation order) of a laminate, even if the surface on which the laminate is to be disposed (the surface to be formed, the supporting surface, the bonding surface, or the flat surface, etc.) in the accompanying drawings is located on the upper side of the laminate, this direction may be described as "lower," or the opposite direction may be described as "upper," etc.

[0088] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" or "insulating layer" may be interchanged with "conductive film" or "insulating film," respectively.

[0089] (Implementation 1)

[0090] In this embodiment, a structural example and a manufacturing method example of a semiconductor device according to one embodiment of the present invention are described.

[0091] In this specification, storage devices and display devices are one form of semiconductor devices. Furthermore, in this specification, all devices including circuits containing semiconductor elements, all devices that utilize semiconductor properties, and all devices containing semiconductor materials are considered semiconductor devices. For example, computing devices and imaging devices are one form of semiconductor devices.

[0092] In a transistor included in a semiconductor device according to one embodiment of the present invention (also referred to as a transistor according to one embodiment of the present invention), a source electrode and a drain electrode are located at different heights, and current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a height-direction (vertical) component, and the transistor according to one embodiment of the present invention may also be referred to as a vertical transistor, a vertical channel transistor, or the like.

[0093] More specifically, an insulating layer serving as a first spacer is provided between a lower electrode, which serves as one of the source and drain electrodes of the transistor, and an upper electrode, which serves as the other. An insulating layer serving as a second spacer is provided on the upper electrode. Note that in the following description, the insulating layer serving as a spacer may be simply referred to as a spacer, but the term "spacer" may also be used interchangeably.

[0094] A first opening that reaches the lower electrode is provided between the first spacer, the upper electrode, and the second spacer. Furthermore, a semiconductor layer forming a channel is provided within the first opening to connect the lower and upper electrodes. A gate insulating layer and a gate electrode are provided within the first opening to overlap with the semiconductor layer. Because the source electrode, semiconductor layer, and drain electrode can be arranged in an overlapping manner, the footprint can be significantly reduced compared to so-called planar transistors in which the semiconductor layer is arranged on a flat surface.

[0095] The second spacer, semiconductor layer, gate insulating layer, and gate electrode are planarized so that their top surfaces are uniform or substantially uniform in height. Furthermore, an interlayer insulating layer is provided over the second spacer, semiconductor layer, gate insulating layer, and gate electrode. A second opening is provided in the interlayer insulating layer, reaching the gate electrode. The gate electrode has a region within the second opening that contacts a wiring disposed on the interlayer insulating layer.

[0096] Note that in this specification, etc., "highly consistent or approximately consistent" refers to a structure in which the height from a reference surface (for example, a flat surface such as a substrate surface) is equal when viewed from a cross section. For example, in the manufacturing process of a storage device, the surface of one or more layers is sometimes exposed by a flattening process such as CMP (Chemical Mechanical Polishing). In this case, the height of the processed surface by the CMP process is equal from the reference surface. However, depending on the processing device, processing method, or material of the processed surface during the CMP process, the heights of multiple layers may sometimes be different. In this specification, etc., "highly consistent or approximately consistent" also includes the above-mentioned situation. For example, when including layers with two heights relative to the reference surface (referred to herein as the first layer and the second layer), the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20nm or less, which can also be said to be "highly consistent or approximately consistent."

[0097] Here, the channel length of the transistor can be precisely controlled according to the thickness of the insulating layer used as the first spacer, and the unevenness of the channel length can be made extremely small compared to planar transistors. In addition, by thinning the insulating layer, transistors with extremely small channel lengths can be manufactured. For example, transistors with a channel length of less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm and greater than 5 nm, greater than 7 nm, or greater than 10 nm can be manufactured. Thus, transistors with extremely small channel lengths that cannot be achieved by exposure devices for mass production can be realized. In addition, transistors with a channel length of less than 10 nm can be realized without using very expensive exposure devices used for the most advanced LSI technology.

[0098] A transistor according to one embodiment of the present invention can achieve the following effects: extremely short channel length; reduced occupied area; flow of large current; reduced parasitic capacitance; and high-speed operation.

[0099] Hereinafter, more specific examples will be described with reference to the drawings.

[0100] [Structure example]

[0101] Figure 1A and Figure 1B Each of the perspective schematic diagrams shows a semiconductor device according to one embodiment of the present invention. Figure 1B It was cut off Figure 1A In addition, Figure 1A and Figure 1B In the figure, only the outlines of some components (such as interlayer insulating layers) are shown with dotted lines.

[0102] exist Figure 1A and Figure 1B The arrows in FIG. 1 show the X direction, Y direction, and Z direction. Figure 1A and Figure 1B The same X, Y, and Z signs are used, but their directions do not need to be consistent.

[0103] in addition, Figure 2A An example of a planar structure of a semiconductor device according to one embodiment of the present invention is shown. Figure 2B and Figure 2C Shown separately Figure 2A Example of cross-sectional structure of the cut line A1-A2 and the cut line B1-B2 in FIG. Figure 2A In the example, some components (such as the insulating layer) are omitted. Figure 2A Likewise, some components are omitted in subsequent drawings showing examples of planar structures.

[0104] A semiconductor device according to one embodiment of the present invention includes a transistor 10, an insulating layer 11, an insulating layer 41, an insulating layer 42, an insulating layer 44, an insulating layer 45, an insulating layer 46, an insulating layer 49, and a conductive layer 33. Transistor 10 is provided on insulating layer 11 on a substrate (not shown). Insulating layer 11 serves as an interlayer insulating layer.

[0105] Transistor 10 includes conductive layer 31 serving as one of a source electrode and a drain electrode, conductive layer 32 serving as the other of the source electrode and the drain electrode, semiconductor layer 21, insulating layer 22 serving as a gate insulating layer, and conductive layer 23 serving as a gate electrode. Conductive layer 31 and conductive layer 32 also serve as wiring.

[0106] Conductive layer 31 and insulating layer 44 are provided on insulating layer 11. Insulating layer 41 is provided on conductive layer 31 and insulating layer 44. Conductive layer 32 and insulating layer 45 are provided on insulating layer 41. Insulating layer 41 and conductive layer 32 include opening 20a reaching conductive layer 31.

[0107] Insulating layer 42 is provided on conductive layer 32 and insulating layer 45. Insulating layer 42 includes opening 20b that reaches conductive layer 32 and has an area overlapping with opening 20a. The diameter of opening 20b may be larger than the diameter of opening 20a. In this case, the entire opening 20a may overlap with opening 20b. Furthermore, since opening 20b has an area overlapping with opening 20a, opening 20a and opening 20b can be considered as a single opening 20.

[0108] The insulating layer 41 is used as a first spacer, and the insulating layer 42 is used as a second spacer. Alternatively, the insulating layer 42 may be used as a first spacer, and the insulating layer 41 may be used as a second spacer. Furthermore, the insulating layer 41 and the insulating layer 42 may be used as interlayer insulating layers.

[0109] Semiconductor layer 21 is located within opening 20. Semiconductor layer 21 is provided along the sidewalls of opening 20. Semiconductor layer 21 has a region in contact with conductive layer 31 within opening 20a. Furthermore, semiconductor layer 21 has one or both of a region in contact with the side surfaces of conductive layer 32 within opening 20a and a region in contact with the top surface of conductive layer 32 within opening 20b. Furthermore, semiconductor layer 21 may have a region in contact with the side surfaces of insulating layer 41 within opening 20a, or a region in contact with the side surfaces of insulating layer 42 within opening 20b.

[0110] The opening 20b may also reach not only the conductive layer 32 but also the insulating layer 45. In this case, the insulating layer 45 preferably uses an insulating material that can improve the selectivity of the etching rate with the insulating layer 42. Specifically, the insulating layer 45 preferably uses an insulating film whose composition or density is different from that of the insulating layer 42. Thus, it is possible to suppress the insulating layer 45 from being unintentionally processed when the insulating layer 42 is processed. In addition, an insulating layer used as an etching stop layer when the opening 20b is formed in the insulating layer 42 may also be provided between the insulating layer 45 and the insulating layer 42. In this case, an insulating film having the same composition or density can be used for the insulating layer 45 and the insulating layer 42, thereby expanding the range of material selection for the insulating layer 45 and the insulating layer 42. In addition, the insulating layer used as an etching stop layer may be included in the insulating layer 45, for example. In this case, the uppermost portion of the insulating layer 45 may be provided as an insulating layer used as an etching stop layer.

[0111] The insulating layer 22 is located inside the opening 20 and is provided along the shape of the semiconductor layer 21. The insulating layer 22 may have a region in contact with the semiconductor layer 21 inside the opening 20.

[0112] The conductive layer 23 is provided on the insulating layer 22 so as to fill the opening 20 . Thus, the insulating layer 22 is provided between the semiconductor layer 21 and the conductive layer 23 in the opening 20 .

[0113] The top surfaces of the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are flattened so that the heights of the top surfaces can be made uniform or substantially uniform. Specifically, the top surface of the insulating layer 42, the topmost surface of the semiconductor layer 21, the topmost surface of the insulating layer 22, and the top surface of the conductive layer 23 can be made uniform or substantially uniform.

[0114] An insulating layer 46 is provided on the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23. An insulating layer 49 is provided on the insulating layer 46. The insulating layer 46 and the insulating layer 49 serve as interlayer insulating layers.

[0115] Insulating layer 46 includes opening 26 that reaches conductive layer 23. Insulating layer 49 includes opening 29 that reaches insulating layer 46 and has a region overlapping with opening 26. Since opening 29 has a region overlapping with opening 26, opening 26 and opening 29 can be considered as a single opening.

[0116] Opening 26 can be formed, for example, by processing insulating layer 46 using an etching method. Opening 29 can also be formed, for example, by processing insulating layer 49 using an etching method. In this case, insulating layer 49 can be formed using an insulating material that can improve the etching rate selectivity with insulating layer 46. This prevents the insulating layer 46 from being unintentionally processed during processing of insulating layer 49, thereby preventing, for example, the top surface of semiconductor layer 21 from being exposed and contacting conductive layer 33. Consequently, a highly reliable semiconductor device can be realized.

[0117] The insulating layer 49 uses an insulating film having a composition or density at least different from that of the insulating layer 46. Alternatively, the insulating layer 46 and the insulating layer 49 may include the same constituent elements.

[0118] Here, an insulating layer serving as an etching stop layer when forming opening 29 in insulating layer 49 may be provided between insulating layer 46 and insulating layer 49. In this case, insulating films having the same composition and density may be used for insulating layer 46 and insulating layer 49, thereby expanding the range of material choices for insulating layer 46 and insulating layer 49. Furthermore, the insulating layer serving as an etching stop layer may be included in insulating layer 46, for example. In this case, the uppermost portion of insulating layer 46 may be provided as the insulating layer serving as the etching stop layer.

[0119] The conductive layer 33 is used as a wiring, specifically, as a routing wiring (also called gate wiring) for the gate electrode of the transistor 10. The conductive layer 33 is provided in a manner that fills the opening 26 and the opening 29. The conductive layer 33 may have a region in contact with the conductive layer 23 inside the opening 26. Here, when the area of ​​the top surface of the conductive layer 23 is large, for example, the opening 26 can be prevented from reaching the semiconductor layer 21 and the conductive layer 33 can be prevented from contacting the semiconductor layer 21. Specifically, when the diameter of the opening 20b is made larger than the diameter of the opening 20a, for example, the width of the conductive layer 32 ( Figure 2AThe length of the region in the Y direction excluding the opening 20a is increased, thereby increasing the area occupied by the transistor 10 and increasing the area of ​​the top surface of the conductive layer 23. As described above, a semiconductor device with high reliability can be realized while miniaturizing the transistors included in the semiconductor device.

[0120] Conductive layer 33 has a region located on insulating layer 46. In this region, conductive layer 33 has regions that overlap with insulating layer 42, semiconductor layer 21, insulating layer 22, and conductive layer 23, respectively, via insulating layer 46. Specifically, conductive layer 33 has regions that overlap with the top surface of insulating layer 42, the topmost surface of semiconductor layer 21, the topmost surface of insulating layer 22, and the top surface of conductive layer 23, respectively, via insulating layer 46. The height of the top surface of conductive layer 33 is the same as or substantially the same as the height of the top surface of insulating layer 49.

[0121] Here, conductive layer 31 is embedded in insulating layer 44, and conductive layer 32 is embedded in insulating layer 45. Furthermore, their top surfaces are flattened so that the heights of the conductive layer and the top surface of the insulating layer are roughly the same. This structure is preferred because it eliminates the effects of steps. Insulating layer 44 and insulating layer 45 serve as interlayer insulating layers. Insulating layers 11, 42, 44, 45, 46, and 49, which serve as interlayer insulating layers, are preferably made of an inorganic insulating material with a low dielectric constant, such as silicon oxide or silicon oxynitride. Materials that can be used for insulating layer 41 will be described later.

[0122] In this specification, etc., an oxynitride refers to a material containing more oxygen than nitrogen. Also, a nitride oxide refers to a material containing more nitrogen than oxygen.

[0123] Here, as described above, when the composition of insulating layer 46 is different from that of insulating layer 49, for example, an insulating material containing oxygen may be used for insulating layer 46, and an insulating material containing nitrogen may be used for insulating layer 49. For example, silicon oxide may be used for insulating layer 46, and silicon nitride may be used for insulating layer 49. Alternatively, for example, an insulating material containing nitrogen may be used for insulating layer 46, and an insulating material containing oxygen may be used for insulating layer 49.

[0124] In the transistor 10 having the structure described above, the source electrode and the drain electrode are located at different heights, so the current flowing through the semiconductor flows in the height direction. In other words, it can be said that the channel length direction has a height (vertical) component, so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor: vertical field effect transistor), a vertical transistor, or a vertical channel transistor. The transistor 10 can arrange the source electrode, semiconductor, and drain electrode in an overlapping manner, so that the occupied area can be greatly reduced compared to the so-called planar transistor (also called a lateral transistor or LFET (Lateral FET)) in which the semiconductor is arranged on a plane.

[0125] In addition, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41, so that the unevenness of the channel length between the plurality of transistors 10 can be minimized compared to planar transistors. Moreover, by thinning the insulating layer 41, transistors with extremely small channel lengths can be manufactured. For example, transistors with a channel length of less than 50 nm, less than 30 nm, or less than 20 nm and greater than 5 nm, greater than 7 nm, or greater than 10 nm can be manufactured. Thus, even when using existing exposure equipment for mass production, transistors with a channel length of less than 10 nm can be realized without the need for very expensive exposure equipment used for the most advanced LSI technology.

[0126] The semiconductor layer 21 can be made of various semiconductor materials, but an oxide semiconductor containing a metal oxide is particularly preferred. By using an oxide semiconductor formed under appropriate conditions, a transistor having both high on-state current and extremely low off-state current can be realized at low cost. Unless otherwise specified, the following describes a suitable structural example in which the semiconductor layer 21 uses an oxide semiconductor.

[0127] The top surfaces of the conductive layers 31 and 32 can be in contact with the semiconductor layer 21. Therefore, when an oxide semiconductor is used for the semiconductor layer 21, there is a concern that the exposed surfaces of the conductive layers 31 and 32 may be oxidized during the deposition process of the semiconductor film to be the semiconductor layer 21 or due to the effects of subsequent heating, thereby forming an insulating oxide film between the conductive layers 31 and 32 and the semiconductor layer 21, thereby increasing the contact resistance. Therefore, an oxide conductor containing a conductive oxide is preferably used for at least the uppermost portions of the conductive layers 31 and 32. This prevents an increase in contact resistance caused by oxidation of the surfaces of the conductive layers 31 and 32.

[0128] Conductive layer 31 can be used as either a source wiring or a drain wiring. Alternatively, conductive layer 32 can be used as the other of the source wiring and the drain wiring. Thus, when one or both of conductive layer 31 and conductive layer 32 are used as wiring, the resistance is preferably low. Therefore, it is preferable to use a material having a higher conductivity than an oxide conductor, such as a metal, alloy, or nitride thereof. It is particularly preferable that one or both of conductive layer 31 and conductive layer 32 have a stacked structure comprising layers of such a highly conductive material, with at least the uppermost portion thereof being made of the aforementioned oxide conductor.

[0129] Here, transistor 10 is provided at the intersection of a conductive layer 33 serving as a gate wiring and a conductive layer 32 serving as a source wiring or a drain wiring. Thus, parasitic capacitance is generated in the region where the conductive layers 33 and 32 overlap at their intersection. However, in one embodiment of the present invention, insulating layers 42 and 46 are provided between conductive layers 33 and 32. Therefore, parasitic capacitance is significantly reduced compared to a case where insulating layers 42 and 46 are not provided (for example, a case where there is a region where the conductive layers 33 and 32 overlap only with insulating layer 22 interposed therebetween). Consequently, a semiconductor device that operates at high speed can be realized.

[0130] By increasing the thickness of insulating layer 42 and insulating layer 46, the parasitic capacitance between conductive layer 33 and conductive layer 32 can be appropriately reduced. For example, the total thickness of insulating layer 42 and insulating layer 46 can be greater than the thickness of insulating layer 22. In addition, the total thickness of insulating layer 42 and insulating layer 46 is preferably greater than at least one of the thicknesses of insulating layer 44, insulating layer 45, and insulating layer 49. The greater the thickness of insulating layer 42 and insulating layer 46, the more the parasitic capacitance between conductive layer 33 and conductive layer 32 can be reduced, which is preferable. However, the thickness can be set in consideration of the generation rate. The total thickness of insulating layer 42 and insulating layer 46 can be, for example, less than or equal to twice or less than three times the thickness of insulating layer 41.

[0131] Figure 3A and Figure 3B They are shown respectively Figure 2B and Figure 2C The semiconductor device shown is a cross-sectional view of an example in which an insulating layer 43 is provided between a conductive layer 32 and an insulating layer 42 . Figure 3A and Figure 3B The planar structure of the semiconductor device shown can be referred to Figure 2A .

[0132] exist Figure 3A and Figure 3B In the semiconductor device shown, the insulating layer 43 includes an opening 20 a . In addition, the insulating layer 42 includes an opening 20 b that reaches the insulating layer 43 and has a region overlapping with the opening 20 a .

[0133] exist Figure 3A and Figure 3B In the semiconductor device shown, semiconductor layer 21 has a region in contact with the side surface of conductive layer 32 within opening 20 a. Alternatively, semiconductor layer 21 may have a region in contact with the side surface of insulating layer 43 within opening 20 a, or a region in contact with the top surface of insulating layer 43 within opening 20 b.

[0134] exist Figure 3A and Figure 3B In the semiconductor device shown, an insulating layer 43 is provided between the conductive layer 32 and the conductive layer 23 in the region where the top surface of the conductive layer 32 overlaps with the conductive layer 23, in addition to the semiconductor layer 21 and the insulating layer 22. Figure 2B and Figure 2C Compared with the semiconductor device shown in FIG. 1 , the parasitic capacitance in the region where the top surface of the conductive layer 32 overlaps the conductive layer 23 can be further reduced. Figure 2B and Figure 2C In the semiconductor device shown, the semiconductor layer 21 has a region that contacts not only the side surface of the conductive layer 32 but also the top surface of the conductive layer 32. Figure 3A and Figure 3B Compared with the semiconductor device shown in FIG. 1 , the conductive layer 32 can obtain good contact with the semiconductor layer 21 .

[0135] The opening 20a included in the insulating layer 43 can be formed, for example, by processing the insulating layer 43 using an etching method. In addition, the opening 20b included in the insulating layer 42 can be formed, for example, by processing the insulating layer 42 using an etching method. In this case, the insulating layer 43 can use an insulating material that can improve the selectivity ratio of the etching rate with the insulating layer 42. The insulating layer 43 uses an insulating film whose composition or density is at least different from that of the insulating layer 42. Note that the insulating layer 42 and the insulating layer 43 can also contain the same constituent elements. For example, the insulating layer 42 can use the same material as the material that can be used for the insulating layer 49, and the insulating layer 43 can use the same material as the material that can be used for the insulating layer 46. In addition, the insulating layer 42 can use the same material as the material that can be used for the insulating layer 46, and the insulating layer 43 can use the same material as the material that can be used for the insulating layer 49.

[0136] Here, an insulating layer serving as an etching stopper when forming opening 20 b in insulating layer 42 may be provided between insulating layer 43 and insulating layer 42. In this case, insulating films having the same composition and density may be used for insulating layer 43 and insulating layer 42, thereby expanding the range of material choices for insulating layer 43 and insulating layer 42. Note that the insulating layer serving as an etching stopper may also be included in insulating layer 43, for example. In this case, the uppermost portion of insulating layer 43 may be provided as the insulating layer serving as the etching stopper.

[0137] exist Figure 2B 、 Figure 2C 、 Figure 3A and Figure 3B In the example shown, a laminated film of an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c is used as the insulating layer 41. Figure 4A yes Figure 2B Magnified image of .

[0138] The semiconductor layer 21 can be provided in a manner having an area in contact with the side surface of the opening 20a of the insulating layer 41b. The insulating layer 41b is preferably an oxide insulating film. In particular, an oxide insulating film that releases oxygen upon heating is preferably used. In addition, a structure in which the insulating layer 41b is sandwiched between the insulating layer 41a and the insulating layer 41c having oxygen barrier properties is preferably adopted. In this way, the oxygen in the insulating layer 41b can be confined in the area surrounded by the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21, which can suppress the release of oxygen in the insulating layer 41b during the process and reduce the amount of oxygen, thereby more efficiently supplying oxygen to the semiconductor layer 21.

[0139] The region of the semiconductor layer 21 that contacts the insulating layer 41b is a region where oxygen vacancies are reduced, and thus can be said to be an i-type region. On the other hand, the region that is not in contact with the insulating layer 41b is preferably an n-type region having a large number of carriers. That is, the region of the semiconductor layer 21 that contacts the insulating layer 41b can be called a channel formation region, and the region outside it can be called a low resistance region (also called a source region or a drain region). Figure 4A In FIG. 1 , the channel formation region 21 i and the low resistance region 21 n of the semiconductor layer 21 are indicated by being hatched differently.

[0140] At this time, if Figure 4A As shown, the channel length L of transistor 10 can be said to be the length of the region of semiconductor layer 21 that contacts conductive layer 31 and the region that contacts conductive layer 32, along the shortest path connecting the region of semiconductor layer 21 that contacts conductive layer 31 and the region of semiconductor layer 21 that contacts conductive layer 32, and that contacts insulating layer 41b. When the angle (θ) of the sidewall of opening 20a in insulating layer 41b is 90 degrees, channel length L is equal to the thickness of insulating layer 41b. By increasing θ, channel length L can be increased.

[0141] On the other hand, the channel width W of the transistor 10 depends on the shape of the opening 20 a . Figure 4B From the Z direction, along Figure 4A A plan view of a cross section cut along the cutoff line C1-C2 at the height of the insulating layer 41b. Here, a case where the opening portion 20a has a cylindrical shape is shown. When the outline of the opening portion 20a is a circle with a diameter R, the channel width W can be regarded as the circumference of the opening portion 20a (i.e., π×R). Here, when the angle θ of the side wall of the opening portion 20a of the insulating layer 41b is staggered from 90 degrees, the circumference of the opening portion 20a varies according to the height. In this case, the circumference of the height when the diameter of the opening portion 20a is the smallest can be regarded as the channel width W, and the circumference of the height of the upper end of the opening portion 20a can be regarded as the channel width W. Note that in this specification, etc., a circle is not limited to a perfect circle.

[0142] The semiconductor layer 21 and the insulating layer 22 are formed along the side surfaces in the opening 20a of the insulating layer 41b, so the thickness of the region is sometimes reduced depending on the deposition method. For example, when using a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD), there is a tendency for a film deposited on a surface inclined or perpendicular to the substrate surface to be thinner than a film deposited on a surface parallel to the substrate surface. On the other hand, when using a deposition method such as atomic layer deposition (ALD) or thermal CVD (TCVD), a film of uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle θ of the side surfaces in the opening 20a of the insulating layer 41b is greater than 75 degrees, greater than 80 degrees, or greater than 85 degrees, it is preferred to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0143] [About the components]

[0144] <Substrate>

[0145] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (for example, yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Furthermore, substrates containing metal nitrides and metal oxides can also be used. Furthermore, there are substrates in which an insulating substrate is provided with a conductive layer or a semiconductor layer, substrates in which a semiconductor substrate is provided with a conductive layer or an insulating layer, and substrates in which a conductive substrate is provided with a semiconductor layer or an insulating layer. Alternatively, the above-mentioned substrates provided with elements can also be used. Examples of the element provided on the substrate include a capacitor, a resistor, a switching element, a light-emitting element (also referred to as a light-emitting device), and a memory element (also referred to as a storage device).

[0146] <Semiconductor Layer>

[0147] The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0148] As metal oxides that can be used for the semiconductor layer 21, for example, In oxide, Ga oxide, and Zn oxide can be mentioned. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M, and Zn. Note that element M is a metal element or semi-metal element with a high bond energy with oxygen, for example, a metal element or semi-metal element with a higher bond energy with oxygen than In. As element M, specifically Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb can be mentioned. The element M contained in the metal oxide is preferably any one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, and more preferably Ga. Note that the metal oxide containing In, element M, and Zn is sometimes referred to as In-M-Zn oxide below. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0149] When an In-M-Zn oxide is used as the metal oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, or compositions close thereto. Note that the close composition range includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of In in the metal oxide, the on-state current and field-effect mobility of the transistor can be improved.

[0150] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of the element M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions thereabouts. Increasing the atomic ratio of M in the metal oxide can suppress the formation of oxygen vacancies.

[0151] The semiconductor layer 21 may be made of, for example, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, or In-Ga-Al-Zn oxide. Alternatively, Ga-Zn oxide may be used.

[0152] In addition, the metal oxide may also replace In or contain one or more metal elements with a large period number in addition to In. There is a trend that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, when a metal element with a large period number is included, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As such metal elements, specifically Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm and Eu can be cited. Note that La, Ce, Pr, Nd, Pm, Sm and Eu are referred to as light rare earth elements.

[0153] Furthermore, the metal oxide may contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0154] The metal oxide can be formed using sputtering or atomic layer deposition (ALD) as appropriate. Note that when forming the metal oxide using sputtering, the composition of the deposited metal oxide may differ from that of the target. In particular, the zinc content of the deposited metal oxide may be reduced to approximately 50% of the zinc content in the target.

[0155] In this specification, etc., the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of the element to the total number of atoms of the metal element contained in the metal oxide. For example, a metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide is A, respectively. X 、A Y 、A Z When the content of metal element X is expressed as A X / (A X +A Y +A Z ). In addition, when the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is expressed as B X :B Y :B Z When the content of metal element X is expressed as B X / (B X +B Y +B Z ).

[0156] For example, when a metal oxide containing In is used, a transistor with a large on-state current can be realized by increasing the In content.

[0157] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability in response to positive bias can be realized. In other words, a transistor with minimal fluctuation in threshold voltage during a PBTS (Positive Bias Temperature Stress) test can be realized. Furthermore, when using a metal oxide containing Ga, the Ga content is preferably lower than the In content. This allows for the realization of a transistor with high mobility and reliability.

[0158] On the other hand, increasing the Ga content can achieve transistors with high reliability against light. Specifically, transistors with minimal fluctuation in threshold voltage during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, metal oxides with a Ga atomic ratio greater than that of In have a larger band gap, reducing the fluctuation in threshold voltage during NBTIS testing of transistors.

[0159] Furthermore, by increasing the zinc content, a highly crystalline metal oxide is formed, which can suppress the diffusion of impurities in the metal oxide. This can suppress variations in the electrical characteristics of the transistor and improve reliability.

[0160] The semiconductor layer 21 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 21 may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different stacked compositions may also be adopted. In addition, by utilizing the ALD method, a metal oxide layer whose composition continuously changes in the film thickness direction can be formed. Thus, not only is the range of design options expanded compared to the case of using a film with a fixed composition, but the generation of interface states between two layers with different compositions can also be prevented, thereby improving electrical characteristics and reliability.

[0161] In the case where the semiconductor layer 21 has a two-layer structure, it is preferred that a material having a higher mobility than that of the first layer (a material with high conductivity) be used for the second layer, that is, closer to the gate electrode side. Thus, a normally closed transistor with a large on-state current can be realized. Therefore, low power consumption and high performance can be achieved at the same time. Alternatively, a material having a higher mobility than that of the second layer can be used for the first layer, that is, in contact with the source electrode and the drain electrode side. Thus, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced to reduce the parasitic resistance, and a transistor with a large on-state current can be realized.

[0162] When the semiconductor layer 21 has a three-layer structure, it is preferable to use a material having higher mobility than the first and third layers for the second layer. This can realize a transistor with high on-state current and high reliability.

[0163] The above-mentioned differences in mobility and conductivity can be replaced by, for example, the content of indium. In addition, the presence or content of elements other than indium that contribute to the improvement of conductivity also affects mobility and conductivity. As an example of a material with high mobility, for example, In:Ga:Zn=4:3:2 [atomic ratio] and materials in the vicinity thereof, In:Zn=1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=4:1 [atomic ratio] and materials in the vicinity thereof, In:Sn:Zn=40:X:10 [atomic ratio] (X is greater than 0.1 and less than 5, typically X=1) and materials in the vicinity thereof, etc. On the other hand, as materials having lower mobility or conductivity than the above-mentioned materials, there can be cited materials having In:Ga:Zn=1:3:2 [atomic ratio] and its vicinity, materials having In:Ga:Zn=1:3:4 [atomic ratio] and its vicinity, materials having In:Ga:Zn=2:2:1 [atomic ratio] and its vicinity, materials having In:Ga:Zn=1:1:1 [atomic ratio] and its vicinity, materials having In:Ga:Zn=1:1:2 [atomic ratio] and its vicinity, etc.

[0164] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used. Using a crystalline metal oxide layer for the semiconductor layer 21 can reduce the defect state density in the semiconductor layer 21, thereby achieving a highly reliable semiconductor device.

[0165] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the lower the defect state density in the semiconductor layer 21. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0166] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, the leakage current between the source and drain of an OS transistor in the off state (hereinafter also referred to as off-state current) is extremely small, allowing the charge stored in the capacitor connected in series with the transistor to be retained for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of semiconductor devices.

[0167] A semiconductor device according to one embodiment of the present invention can be applied to a display device, for example. When increasing the brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased, thereby improving the brightness of the light-emitting device.

[0168] When the transistor operates in the saturation region, the OS transistor can make the change in source-drain current smaller in response to changes in gate-source voltage compared to the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This can increase the number of grayscales in the pixel circuit. In addition, even if the electrical characteristics (such as resistance) of the light-emitting device fluctuate or the electrical characteristics are non-uniform, a stable current can be passed.

[0169] As described above, by using an OS transistor as a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black blur," "increase in luminance," "multi-gradation," and "suppression of the influence of uneven characteristics of light-emitting devices."

[0170] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability with respect to radiation. For example, OS transistors can be appropriately used as pixel circuits of flat-panel detectors for X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0171] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As semiconductors composed of a single element, silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon) or germanium can be mentioned. As compound semiconductors, for example, gallium arsenide and silicon germanium can be mentioned. As compound semiconductors, organic semiconductors, nitride semiconductors, or oxide semiconductors can be mentioned. Note that these semiconductor materials may also contain impurities as dopants.

[0172] Alternatively, the semiconductor layer 21 may also include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds such as van der Waals forces that are weaker than covalent and ionic bonds. A layered material has high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be realized.

[0173] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0174] There are no particular restrictions on the crystallinity of the semiconductor material used for the semiconductor layer 21. An amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. Using a crystalline semiconductor is preferred because it can suppress degradation of transistor characteristics.

[0175] <Gate Insulation Layer>

[0176] The insulating layer 22 is used as a gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as the film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum oxynitride can also be used as the insulating layer 22. In addition, the insulating layer 22 can also have a stacked structure, for example, it can have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0177] <Conductive Layer>

[0178] As the conductive layer 31 and the conductive layer 32, for example, preferably used are tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxidized, and therefore are preferred.

[0179] Furthermore, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide can be used as conductive layers 31 and 32. In particular, conductive oxides containing indium are preferably used because they have high conductivity.

[0180] Conductive layer 23 is used as a gate electrode and can be made of various conductive materials. As conductive layer 23, for example, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, as well as alloys containing these metal elements, are preferably used. In addition, nitrides of the above-mentioned metals or alloys or oxides of the above-mentioned metals or alloys can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferably used. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0181] Alternatively, the nitride and oxide that can be used for the conductive layer 31 and the conductive layer 32 described above can also be used for the conductive layer 23 .

[0182] Conductive layers 31 and 32 are used as wiring, so they can be laminated with low-resistance conductive materials. Furthermore, the lower the resistance of conductive layer 33, the better. For conductive layers 31, 32, and 33, the same conductive materials as those used for conductive layer 23 can be used.

[0183] <Insulation layer>

[0184] The insulating layer 41 (or insulating layer 41b) has a region in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 41, an oxide is preferably used in at least the region in contact with the semiconductor layer 21 in the insulating layer 41. For example, silicon oxide or silicon oxynitride can be suitably used.

[0185] Furthermore, it is more preferable to use a film that releases oxygen when heated for the insulating layer 41. Thus, oxygen can be supplied to the semiconductor layer 21 by the heat applied during the manufacturing process of the transistor 10, which can reduce oxygen vacancies in the semiconductor layer 21 and improve reliability. Examples of methods for supplying oxygen to the insulating layer 41 include heat treatment in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, oxygen can be supplied to the insulating layer 41 by depositing an oxide film on the top surface of the insulating layer 41 in an oxygen atmosphere using a sputtering method. This oxide film can then be removed.

[0186] The insulating layer 41 is preferably formed using a deposition method such as sputtering or plasma CVD. In particular, by using sputtering as a deposition method that does not use hydrogen as a deposition gas, a film containing an extremely low amount of hydrogen can be formed. This suppresses the supply of hydrogen to the semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0187] Insulating layer 41a and insulating layer 41c are preferably formed of a film that is not easily diffused with oxygen. This prevents oxygen in insulating layer 41b from being transmitted through insulating layer 41a toward insulating layer 11 and from being transmitted through insulating layer 41c toward insulating layer 22 due to heating. In other words, by sandwiching insulating layer 41b above and below with insulating layers 41a and 41c that are not easily diffused with oxygen, oxygen in insulating layer 41b can be confined. This allows for efficient oxygen supply to semiconductor layer 21.

[0188] As the insulating layer 41a and the insulating layer 41c, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon nitride oxide are particularly suitable for the insulating layer 41a and the insulating layer 41c because they rarely release impurities (such as water and hydrogen) and do not easily allow oxygen and hydrogen to pass through.

[0189] [Deformation example]

[0190] Hereinafter, an example in which a part of the structure is different from the above-mentioned example will be described. Note that the description of the example that is repeated with the above-mentioned example will be omitted as appropriate. Figures 2A to 2C This modification example is also applicable to Figure 3A and Figure 3B The structure example shown.

[0191] <Deformation Example 1>

[0192] Figure 5A 、 Figure 5B and Figure 5C The example in which the side wall of the opening 20a and the side wall of the opening 20b are provided on the same surface (also referred to as aligned) is shown. Figures 5A to 5CIn the semiconductor device shown in FIG. 1 , the opening 20a and the opening 20b are formed using the same process, thereby Figures 2A to 2C The manufacturing process can be simplified compared to the semiconductor device shown. Figures 2A to 2C In the semiconductor device shown in FIG. 1 , for example, the occupied area of ​​the transistor 10 can be reduced. As a result, the transistor included in the semiconductor device can be connected to the transistor 10 in FIG. Figures 5A to 5C The semiconductor device shown in the figure has a more miniaturized transistor than the semiconductor device, and a more reliable semiconductor device is realized. Figures 2A to 2C In the semiconductor device shown, semiconductor layer 21 has a region that contacts not only the side surfaces but also the top surface of conductive layer 32. This allows conductive layer 32 and semiconductor layer 21 to have good contact, resulting in a highly reliable semiconductor device.

[0193] <Deformation Example 2>

[0194] Figure 6A 、 Figure 6B and Figure 6C An example is shown in which the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have regions located outside the opening 20. Figures 6A to 6C In the example shown, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 have regions located on the insulating layer 42. Figure 6B and Figure 6C The example in which the insulating layer 22 is provided so as to cover the side surfaces outside the opening 20 of the semiconductor layer 21 is shown. Figures 6A to 6C The example in which the side surface outside the opening 20 of the conductive layer 23 is located outside the side surface outside the opening 20 of the semiconductor layer 21 (on the opposite side of the opening 20) is shown. Alternatively, the side surface outside the opening 20 of the conductive layer 23 may be located inside the side surface outside the opening 20 of the semiconductor layer 21 (on the side of the opening 20). Figures 6A to 6C Although the insulating layer 22 is not patterned, the insulating layer 22 may be patterned. For example, the insulating layer 22 and the conductive layer 23 may be formed using the same pattern. In this case, the side surfaces outside the opening 20 of the insulating layer 22 may be aligned with the side surfaces outside the opening 20 of the conductive layer 23. Figures 6A to 6C In the semiconductor device shown, the conductive layer 23 serving as the gate electrode can be guided even without providing the insulating layer 46, the insulating layer 49, and the conductive layer 33. Furthermore, by providing a planarized insulating layer (also referred to as a planarization layer) so as to cover the conductive layer 23, steps formed by the conductive layer 23 can be reduced.

[0195] <Deformation Example 3>

[0196] Figure 7A 、 Figure 7B and Figure 7C An example is shown in which the side wall of the opening 20a is tapered. 7A to 7C In the transistor 10 shown, the diameter of the upper end (opening diameter) of the opening 20 a is larger than the diameter of the lower end (opening diameter).

[0197] In this specification, etc., a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to the substrate surface or the surface being formed. For example, it is preferable to have a region where the angle formed by the inclined side surface and the substrate surface or the surface being formed (also called a taper angle) is less than 90 degrees. Note that the side surface, substrate surface, and surface being formed of a component do not necessarily need to be completely flat; they may also be approximately planar with slight curvature or have slight irregularities.

[0198] When the sidewalls of the opening 20a have a tapered shape, for example, coverage of the semiconductor layer 21 is improved, thereby suppressing the generation of defects such as low-density regions in the film even when using a deposition method such as sputtering. For example, the angle θ can be set to 45 degrees or more and 90 degrees or less, 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. In addition, when using a deposition method with extremely high coverage such as ALD, the angle θ can be greater than 90 degrees.

[0199] When the sidewalls of the opening 20a have a tapered shape, the diameter of the opening 20a corresponding to the channel width of the transistor 10 increases from the conductive layer 31 side toward the insulating layer 42 side. In this case, the amount of current flowing through the transistor 10 is limited by the region with the smallest diameter. Thus, the channel width of the transistor 10 can be considered as the perimeter of the region with the smallest diameter. Therefore, when the sidewalls of the opening 20a have a tapered shape, a transistor 10 can be manufactured with a channel width that is smaller than the diameter of the upper end of the opening 20a.

[0200] exist Figures 8A to 8C In the example shown, in addition to the side wall of the opening 20a, the side wall of the opening 20b also has a tapered shape. Figures 8A to 8C In the transistor 10 shown, the diameter of the upper end (opening diameter) is larger than the diameter of the lower end (opening diameter) in both the opening 20 a and the opening 20 b.

[0201] like Figure 8B and Figure 8C As shown, when the diameter of the upper end of the opening 20b is larger than the diameter of the lower end, the contact area between the conductive layer 23 and the conductive layer 33 can be increased, which is preferable.

[0202] <Deformation Example 4>

[0203] Figure 9A 、 Figure 9B and Figure 9CAn example is shown in which the transistor 10 includes a conductive layer 27 and an insulating layer 28 .

[0204] Conductive layer 27 serves as a second gate electrode (or back gate electrode). Furthermore, insulating layer 28 is located between conductive layer 27 and semiconductor layer 21 and serves as a second gate insulating layer (or back gate insulating layer). A fixed potential or an arbitrary signal can be supplied to conductive layer 27. By providing conductive layer 27 and supplying a fixed potential to conductive layer 27, the potential on the back channel side of semiconductor layer 21 can be fixed, thereby reducing variations in electrical characteristics. Furthermore, conductive layer 27 can be electrically connected to any one of conductive layer 31, conductive layer 32, and conductive layer 33.

[0205] Conductive layer 27 is embedded in insulating layer 41b. Thus, conductive layer 27 is disposed between insulating layer 41a and insulating layer 41c. Insulating layer 28 is disposed along the side surfaces of insulating layer 41a, conductive layer 27, insulating layer 41c, and conductive layer 32. For example, insulating layer 28 can be formed by forming openings in conductive layer 32, insulating layer 41c, conductive layer 27, and insulating layer 41a, depositing an insulating film covering the openings using a high-coverage deposition method, and then performing anisotropic etching. Here, by having a region of semiconductor layer 21 in contact with the top surface of conductive layer 32, semiconductor layer 21 and conductive layer 32 can be electrically connected.

[0206] Figures 9A to 9C An example is shown in which conductive layers 31 and 32 extend in the X direction, and conductive layers 27 and 33 extend in the Y direction. Extending conductive layers 31 and 27 in different directions reduces parasitic capacitance between conductive layers 31 and 27, compared to extending them in the same direction. Furthermore, extending conductive layers 27 and 32 in different directions reduces parasitic capacitance between conductive layers 27 and 32, compared to extending them in the same direction. Alternatively, conductive layers 31 and 27 can be extended in either the same or the same direction. Here, increasing the thickness of insulating layer 41a reduces parasitic capacitance between conductive layers 31 and 27, and increasing the thickness of insulating layer 41c reduces parasitic capacitance between conductive layers 27 and 32.

[0207] <Variation Example 5>

[0208] exist Figure 10A and Figure 10B In the example shown, Figure 2B and Figure 2C The conductive layer 31 shown is provided with a recess. Figure 2A .in addition, Figure 10C yes Figure 10A and Figure 10B An enlarged view of the conductive layer 31 and its surrounding area is shown.

[0209] exist Figure 10A and Figure 10B In the transistor 10 shown in FIG. 1 , the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are provided along the concave portion of the conductive layer 31. Figure 10C As shown, the height of the bottom surface of the conductive layer 23 is preferably lower than the height of the topmost surface of the conductive layer 31 .

[0210] exist Figure 10A and Figure 10B In the transistor 10 shown in FIG. 1 , the region of the semiconductor layer 21 in contact with the conductive layer 31 is a region having lower resistance than the channel formation region. Figure 10C As shown, when the bottom surface of the conductive layer 23 is located lower than the top surface of the conductive layer 31, a gate electric field can be uniformly applied to the entire channel formation region of the semiconductor layer 21, thereby preventing the formation of a high resistance region (bias region) due to difficulty in applying the gate electric field to the semiconductor layer 21. Therefore, a transistor with improved on-state current can be realized. To achieve the above structure, for example, the thickness of the conductive layer 31 is greater than the sum of the thicknesses of the semiconductor layer 21 and the insulating layer 22.

[0211] <Variation Example 6>

[0212] Figure 11A Show Figure 2A The shapes of the openings 20a and 20b shown in the figure are ellipses when viewed from a plane. Figure 11A Although an example is shown in which the major axis of the ellipse is parallel to the X direction, it may be parallel to the Y direction or may not be parallel to the X direction and the Y direction.

[0213] Figure 11B Show Figure 2A The shapes of the openings 20a and 20b shown in FIG. 2 are quadrangular when viewed from a plane. Figure 11B The shape of the middle opening 20a and the opening 20b when viewed from above is a square, but the shape of the opening 20a and the opening 20b when viewed from above is not limited to this. For example, the shape of the opening 20a and the opening 20b when viewed from above may be a rectangle, a rhombus, or a parallelogram. In addition, the shape of the opening 20a and the opening 20b when viewed from above may be a triangle, a polygon with a pentagon or larger, or a star.

[0214] Figure 11C Show Figure 11B The corners of the opening 20a and the opening 20b shown are curved. In other words, Figure 11CThe example in which the shapes of the openings 20a and 20b when viewed from a plane are quadrilaterals with curved corners is shown. Figure 11C The shape of the middle opening 20a and the opening 20b when viewed from a plane is a square with curved corners, but the shape of the opening 20a and the opening 20b when viewed from a plane is not limited to this. For example, it can be a rectangle with curved corners, a rhombus with curved corners, a parallelogram with curved corners, a triangle with curved corners, a polygon with a pentagon or more with curved corners, or a star with curved corners.

[0215] In addition, Figure 2A and Figures 11A to 11C In the examples shown in FIG. 1 and FIG. 2 , the shape of the opening 20b when viewed from above is the same as the shape of the opening 20a when viewed from above. However, the type of shape of the opening 20a when viewed from above may be different from the type of shape of the opening 20b when viewed from above. For example, the shape of the opening 20a when viewed from above may be circular or elliptical, while the shape of the opening 20b when viewed from above may be a quadrilateral or a quadrilateral with curved corners. Furthermore, the shape of the opening 20a when viewed from above may be a quadrilateral, while the shape of the opening 20b when viewed from above may be a quadrilateral with curved corners, a circle, or an ellipse.

[0216] <Variation Example 7>

[0217] Figure 12A 、 Figure 12B and Figure 12C The example in which the shape of the opening 20a provided in the insulating layer 41 when viewed from the plane is inconsistent with the shape of the opening 20a provided in the conductive layer 32 when viewed from the plane is shown. 12A to 12C In FIG. 4 , the opening 20a provided in the insulating layer 41 is referred to as the opening 20a1 and the opening 20a provided in the conductive layer 32 is referred to as the opening 20a2. 12A to 12C In the example shown, the shape of the opening 20a2, when viewed from above, is a circle with a larger radius than that of the opening 20a1. Alternatively, one or both of the shapes of the opening 20a1 and the opening 20a2, when viewed from above, may not be circular. For example, one or both of the shapes of the opening 20a1 and the opening 20a2, when viewed from above, may be an ellipse, a square, or a square with curved corners, among other shapes that the opening 20a can have.

[0218] 12A to 12CAlthough the example in which the area of ​​the opening 20a2 is larger than the area of ​​the opening 20a1 is shown, the area of ​​the opening 20a2 may be smaller than the area of ​​the opening 20a1. In this case, the conductive layer 32 has a region protruding toward the side wall of the opening 20a1.

[0219] For example, if the opening 20a1 and the opening 20a2 are formed using different processes, the planar shape of the opening 20a1 may differ from the planar shape of the opening 20a2. Furthermore, even if the opening 20a1 and the opening 20a2 are formed using the same process, if, for example, the etching rate of the conductive layer 32 in the X and Y directions differs from the etching rate of the insulating layer 41 in the X and Y directions, the planar shape of the opening 20a1 may differ from the planar shape of the opening 20a2. For example, if the etching rate of the conductive layer 32 in the X and Y directions is faster than the etching rate of the insulating layer 41 in the X and Y directions, even if the opening 20a1 and the opening 20a2 are formed using the same process, the planar area of ​​the opening 20a2 may be larger than the planar area of ​​the opening 20a1.

[0220] The above is an explanation of the modified examples. The above-described structures can be combined as appropriate for implementation.

[0221] [Manufacturing method example 1]

[0222] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Figure 2B and Figure 2C An example of a method for manufacturing transistor 10 is shown.

[0223] Figures 13A to 16B The following is a cross-sectional view of each step of the method for manufacturing a semiconductor device. Figure 2B The cross section on the right shows the Figure 2C cross section.

[0224] Next, the insulating material for forming the insulating layer, the conductive material for forming the conductive layer, and the semiconductor material for forming the semiconductor layer can be appropriately deposited using sputtering, CVD, MBE (Molecular Beam Epitaxy), PLD (Pulsed Laser Deposition), or ALD.

[0225] Examples of sputtering methods include RF (Radio Frequency) sputtering, which uses a high-frequency power source for the sputtering power supply; DC (Direct Current) sputtering, which utilizes a direct current power source; and pulsed DC sputtering, which varies the voltage applied to the electrodes in a pulsed manner. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metallic conductive films. Furthermore, pulsed DC sputtering is primarily used for depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0226] Note that CVD methods can be categorized into plasma CVD using plasma, thermal CVD using heat, and photo CVD using light. Furthermore, CVD methods can be categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0227] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not utilize plasma, plasma damage to the substrate is minimized. Furthermore, thermal CVD eliminates plasma damage during formation, resulting in films with fewer defects.

[0228] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0229] Unlike sputtering, CVD and ALD are deposition methods that offer excellent step coverage and are less susceptible to the shape of the substrate being processed. ALD, in particular, offers excellent step coverage and thickness uniformity, making it suitable for coating surfaces with openings with high aspect ratios. However, ALD has a relatively slow deposition rate, so it is sometimes preferable to combine it with other deposition methods, such as CVD, which have faster deposition rates.

[0230] Furthermore, when using CVD, films of arbitrary compositions can be deposited depending on the source gas flow ratio. For example, by varying the source gas flow ratio while deposition is performed, films with continuously varying compositions can be deposited. When deposition is performed while varying the source gas flow ratio, the time required for transfer or pressure adjustment is eliminated, thus shortening the deposition time compared to deposition using multiple deposition chambers. Consequently, the productivity of semiconductor devices can sometimes be improved.

[0231] When using ALD, films of any composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, films of any composition can be deposited by controlling the number of cycles for each precursor. Furthermore, similar to CVD, films with continuously varying compositions can be deposited.

[0232] First, a substrate (not shown) is prepared, and an insulating layer 11 ( Figure 13A As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The insulating layer 11 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. If the surface on which the insulating layer 11 is formed is uneven, it is preferable to perform a planarization treatment after depositing the insulating layer 11 to make the top surface of the insulating layer 11 flat.

[0233] Next, a conductive film that will become the conductive layer 31 is formed on the insulating layer 11. Next, a resist mask is formed on the conductive film by, for example, photolithography, and the areas of the conductive film not covered by the resist mask are removed, and then the resist mask is removed. Thus, the conductive layer 31 can be formed. Next, an insulating film that will become the insulating layer 44 is deposited, and the areas overlapping with the conductive layer 31 are removed, thereby forming the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 ( Figure 13A When processing the insulating film to be the insulating layer 44, it is preferable to use a CMP method. For example, by processing the insulating film until the top surface of the conductive layer 31 is exposed, a Figure 13A Insulation layer 44 is shown.

[0234] In addition, when forming the insulating layer 44 and the conductive layer 31, the following process can also be used: first, an insulating film that will become the insulating layer 44 is formed, then an opening is formed in the insulating film, and a conductive film is formed in a manner to fill the opening, and polishing (flattening) using the CMP method is performed until the top surface of the insulating film is exposed.

[0235] By performing a planarization process so that the top surface of the insulating layer 44 is aligned with the top surface of the conductive layer 31, the top surface of the insulating layer 41 formed subsequently can be flattened. Alternatively, the insulating layer 44 may not be provided, and the insulating layer 41 may be provided so as to cover the conductive layer 31. In this case, the top surface of the insulating layer 41 is preferably planarized by a CMP process.

[0236] Next, insulating layers 41a, 41b, and 41c (hereinafter, these may be collectively referred to as insulating layers 41) are formed on the conductive layer 31 and the insulating layer 44. Figure 13B ) When forming the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c, sputtering, CVD, MBE, PLD, ALD, or the like may be used.

[0237] Here, the thickness of the insulating layer 41 affects the channel length of the transistor, and therefore it is important to avoid unevenness in the thickness of the insulating layer 41 .

[0238] Furthermore, by depositing the insulating layer 41b using a sputtering method in an oxygen-containing atmosphere, it is possible to form an insulating layer 41b containing a large amount of oxygen. Furthermore, by utilizing a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 41b can be reduced. By depositing the insulating layer 41b in this manner, oxygen is supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0239] Next, a conductive layer 32 and an insulating layer 45 are formed on the insulating layer 41 ( Figure 13C The conductive layer 32 and the insulating layer 45 can be formed by the same methods as those of the conductive layer 31 and the insulating layer 44, respectively.

[0240] Next, an insulating layer 42 ( Figure 13D ). The insulating layer 42 can be formed by, for example, the same method as that of the insulating layer 41b.

[0241] Next, by processing a portion of the insulating layer 42, an opening 20b is formed that reaches the conductive layer 32. Then, by processing a portion of the conductive layer 32 and a portion of the insulating layer 41, an opening 20a ( 20b ) having a region overlapping with the opening 20b and reaching the conductive layer 31 is formed. Figure 14A As described above, the opening 20 a and the opening 20 b can be regarded as one opening 20 .

[0242] For example, a resist mask is first formed on insulating layer 42 using photolithography, and the areas of insulating layer 42 not covered by the resist mask are removed by etching. The resist mask is then removed. Thus, opening 20b is formed in insulating layer 42. Next, a resist mask is formed on insulating layer 42 and conductive layer 32 using photolithography, and the areas of conductive layer 32 and insulating layer 41 not covered by the resist mask are removed by etching. The resist mask is then removed. Thus, opening 20a is formed in conductive layer 32 and insulating layer 41. As described above, opening 20 is formed in insulating layer 41, conductive layer 32, and insulating layer 42. Furthermore, opening 20 is preferably formed so that the diameter of opening 20b is larger than the diameter of opening 20a.

[0243] Here, the opening 20a can also be formed by the same process as the opening 20b. Specifically, the opening 20a can also be formed under the same etching conditions as the opening 20b. Even in the above case, for example, by retreating the resist mask when forming the opening 20a, the diameter of the opening 20b can be made larger than the diameter of the opening 20a. The insulating layer 41 can be processed using the conductive layer 32 as a hard mask, and the insulating layer 42 can be processed according to the resist pattern. Therefore, even in the case where the resist mask retreats when forming the opening 20a and the opening 20a is formed by the same process as the opening 20b, the diameter of the opening 20b can be made larger than the diameter of the opening 20a.

[0244] Alternatively, opening 20b may be formed in insulating layer 42 so as to reach not only conductive layer 32 but also insulating layer 45. In this case, etching insulating layer 42 under conditions where the etching rate of insulating layer 42 is faster than the etching rate of insulating layer 45 can suppress etching of insulating layer 45, which is preferable.

[0245] The sidewalls of the opening 20 are preferably perpendicular to the top surface of the conductive layer 31. This structure allows for the manufacture of a transistor with a small footprint. Alternatively, the sidewalls of the opening 20 may have a tapered shape. This tapered shape improves the coverage of the film formed within the opening 20.

[0246] The maximum width of the opening 20a (the maximum diameter when the opening 20a is circular when viewed from a plane) is preferably as fine as possible. For example, the maximum width of the opening 20a is preferably less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, or less than 20 nm and greater than 5 nm. In this way, in order to form the fine opening 20a, it is preferred to use photolithography using short-wavelength light such as EUV light or an electron beam. Note that the maximum width of the opening 20b can be greater than the maximum width of the opening 20a, but like the opening 20a, the opening 20b is also preferably formed using photolithography using short-wavelength light such as EUV light or an electron beam.

[0247] Because opening 20 has a large aspect ratio, it is preferably formed by anisotropic etching. Dry etching is particularly preferred because it is suitable for micromachining. Furthermore, the etching conditions for insulating layer 42, conductive layer 32, insulating layer 41c, insulating layer 41b, and insulating layer 41a during this processing may differ from one another. Furthermore, the angle of the sidewalls of opening 20b may differ from the angle of the sidewalls of opening 20a. Furthermore, the angle of the sidewalls of opening 20a in conductive layer 32, insulating layer 41c, insulating layer 41b, and insulating layer 41a may also differ from one another.

[0248] When etching insulating layer 42, a portion of the top of conductive layer 32 may be etched, thinning conductive layer 32 at the bottom of opening 20b. Also, when etching insulating layer 41, a portion of the top of conductive layer 31 may be etched, thinning conductive layer 31 at the bottom of opening 20a. Alternatively, after forming opening 20b and before forming opening 20a, a portion of the top of conductive layer 32 may be etched to thin conductive layer 32. Furthermore, after forming opening 20a, a portion of the top of conductive layer 31 may be etched to thin conductive layer 31.

[0249] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or inert gas or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be set to about 20%. In addition, the heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or inert gas, heat treatment may be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas in order to compensate for the oxygen that has been released. By performing the above-mentioned heat treatment, impurities such as water contained in the insulating layer 41 may be reduced, for example, before depositing the oxide semiconductor film that will become the semiconductor layer.

[0250] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment can be set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment can minimize moisture absorption by the insulating layer 41, for example.

[0251] Next, a semiconductor film 21f is formed so as to have a region located inside the opening 20 and to cover the conductive layer 31, the insulating layer 41, the conductive layer 32, and the insulating layer 42. Figure 14B). The semiconductor film 21f is a semiconductor film that will later become the semiconductor layer 21. As the semiconductor film 21f, an oxide semiconductor film can be used. When forming the semiconductor film 21f, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used. Here, the semiconductor film 21f is preferably formed in a manner that contacts the bottom and sidewalls of the opening 20 with a large aspect ratio. Therefore, when forming the semiconductor film 21f, it is preferred to use a deposition method with good coverage, and more preferably to use a CVD method or an ALD method. For example, as the semiconductor film 21f, In-Ga-Zn oxide can be deposited using the ALD method. In addition, when the opening 20 has a tapered shape, the semiconductor film 21f can be formed using a sputtering method.

[0252] Furthermore, during or after the deposition of the semiconductor film 21f, it is preferable to perform a treatment such as microwave treatment in an oxygen-containing atmosphere to reduce the impurity concentration in the semiconductor film 21f. Note that examples of impurities include hydrogen and carbon. Microwave treatment can also improve the crystallinity of the semiconductor film 21f. Microwave treatment, for example, refers to treatment using an apparatus that includes a power source for generating high-density plasma using microwaves.

[0253] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high frequencies such as RF, and the oxygen plasma can be applied to the semiconductor film 21f, which can use an oxide semiconductor. The oxygen that acts on the semiconductor film 21f can be in various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also known as O radicals, which are atoms, molecules, or ions with unpaired electrons). The oxygen that acts on the semiconductor film 21f can be in any one or more of the above forms, with oxygen radicals being particularly preferred.

[0254] Furthermore, heating the substrate during microwave treatment in the aforementioned oxygen-containing atmosphere is preferred because it can further reduce the impurity concentration in the semiconductor film 21f. The substrate can be heated at a temperature of 100°C to 650°C, preferably 200°C to 600°C, and more preferably 300°C to 450°C.

[0255] By heating the substrate during microwave treatment in the oxygen-containing atmosphere, the carbon concentration in the semiconductor film 21f obtained by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0256] Note that while the above example illustrates a structure in which the semiconductor film 21f is microwave-treated in an atmosphere containing oxygen, the present invention is not limited thereto. For example, an insulating film located near the semiconductor film 21f, more specifically a silicon oxide film, may also be microwave-treated in an atmosphere containing oxygen. This allows hydrogen contained in the silicon oxide film to be released to the outside as H2O. By releasing hydrogen from the silicon oxide film located near the semiconductor film 21f, a highly reliable semiconductor device can be realized.

[0257] In addition, when the semiconductor film 21f has a stacked structure, the deposition methods of each layer may be the same or different. For example, when the semiconductor film 21f has a two-layer stacked structure, the lower layer of the semiconductor film 21f may be deposited by sputtering and the upper layer of the semiconductor film 21f may be deposited by ALD. The oxide semiconductor film deposited by sputtering tends to have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower layer of the semiconductor film 21f, the crystallinity of the upper layer of the semiconductor film 21f can be improved. In addition, even if pinholes or breaks are formed in the lower layer of the semiconductor film 21f deposited by sputtering, the upper layer of the semiconductor film 21f deposited by ALD with good coverage can be used to fill the area overlapping with the pinholes or breaks.

[0258] Here, the semiconductor film 21f is preferably formed in a manner having an area in contact with the top surface of the conductive layer 31 in the opening portion 20a, the side surface of the insulating layer 41 in the opening portion 20a, the side surface of the conductive layer 32 in the opening portion 20a, the top surface of the conductive layer 32 in the opening portion 20b, and the side surface of the insulating layer 42 in the opening portion 20b.

[0259] After the semiconductor film 21f is deposited, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the semiconductor film 21f does not undergo polycrystallization, and can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen content can be set to about 20%. In addition, heat treatment can also be performed under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher in order to compensate for the oxygen that has been released.

[0260] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment can be set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, for example, it is possible to minimize moisture absorption by the semiconductor film 21f.

[0261] Here, the heat treatment is preferably performed while the semiconductor film 21f is in contact with the insulating layer 41b containing a large amount of oxygen. This allows oxygen to be supplied from the insulating layer 41b to the channel formation region of the semiconductor film 21f, thereby reducing oxygen vacancies.

[0262] Note that although the example in which the heat treatment is performed after the semiconductor film 21f is deposited is shown above, the heat treatment may be performed in a later step.

[0263] Next, an insulating film 22f ( Figure 14B The insulating film 22f is an insulating film that will later become the insulating layer 22. When forming the insulating film 22f, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used.

[0264] The insulating film 22f is preferably provided with the most uniform thickness possible on the side surfaces of the semiconductor film 21f in the opening 20a. Therefore, the insulating film 22f is preferably formed using the ALD method, which is a deposition method with excellent coverage. Furthermore, if the sidewalls of the openings 20a and 20b have a tapered shape, the insulating layer 22 can be deposited using a deposition method such as sputtering, which has lower coverage than the ALD method.

[0265] Next, a conductive film 23f ( 23f ) is formed on the insulating film 22f so as to have a region located inside the opening 20. Figure 14B The conductive film 23f is a conductive film that will later become the conductive layer 23. The conductive film 23f is provided so that a part thereof is embedded in the opening 20.

[0266] The conductive film 23f is preferably deposited by a deposition method with high coverage or embedding properties, more preferably CVD or ALD. If the sidewalls of the opening 20 have a tapered shape, the conductive film can be deposited by sputtering.

[0267] Next, the semiconductor film 21f, the insulating film 22f, and the conductive film 23f are planarized by, for example, CMP to expose the top surface of the insulating layer 42. Thus, the semiconductor layer 21 having a region in contact with the conductive layer 31 and a region in contact with the conductive layer 32, the insulating layer 22 on the semiconductor layer 21, and the conductive layer 23 on the insulating layer 22 are formed inside the opening 20. Figure 15A Here, the conductive layer 23 is formed so as to fill the opening 20. Alternatively, for example, the conductive layer 23, the insulating layer 22, and the semiconductor layer 21 may be formed by processing the top of the conductive film 23f, the top of the insulating film 22f, and the top of the semiconductor film 21f using an etching method such as dry etching until the top surface of the insulating layer 42 is exposed. As described above, the heights of the top surface of the insulating layer 42, the topmost surface of the semiconductor layer 21, the topmost surface of the insulating layer 22, and the top surface of the conductive layer 23 can be made uniform or substantially uniform.

[0268] Next, an insulating layer 46 is formed on the insulating layer 42, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23. Then, an insulating layer 49 ( Figure 15B ) When forming the insulating layer 46 and the insulating layer 49, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used.

[0269] Next, the insulating layer 49 is partially processed to form the opening 29 that reaches the insulating layer 46. Then, the insulating layer 46 is partially processed to form the opening 26 ( Figure 16A ).

[0270] For example, a resist mask is first formed on insulating layer 49 using photolithography, and the areas of insulating layer 49 not covered by the resist mask are removed by etching. The resist mask is then removed. Thus, opening 29 is formed in insulating layer 49. Next, a resist mask is formed on insulating layer 49 and insulating layer 46 using photolithography, and the areas of insulating layer 49 and insulating layer 46 not covered by the resist mask are removed by etching. The resist mask is then removed. Thus, opening 26 is formed in insulating layer 46.

[0271] Here, when forming the opening portion 29, the insulating layer 49 is etched under the condition that the etching rate of the insulating layer 49 is faster than the etching rate of the insulating layer 46, thereby suppressing the insulating layer 46 from being unintentionally etched. As a result, for example, the top surface of the semiconductor layer 21 can be prevented from being exposed. In addition, the insulating layer used as an etching stop layer when forming the opening portion 29 in the insulating layer 49 can also be formed between the insulating layer 46 and the insulating layer 49. In this case, it is not necessary to etch the insulating layer 49 under the condition that the etching rate of the insulating layer 49 is faster than the etching rate of the insulating layer 46 when forming the opening portion 29, so the range of selection of etching conditions can be expanded. Note that, as described above, the insulating layer used as an etching stop layer can also be included in the insulating layer 46, for example. In this case, the uppermost part of the insulating layer 46 can be the insulating layer used as the etching stop layer.

[0272] Here, when the diameter of opening 20b is larger than that of opening 20a, the area of ​​the top surface of conductive layer 23 can be increased while suppressing an increase in the area occupied by transistor 10. This prevents, for example, opening 26 from reaching semiconductor layer 21 and causing conductive layer 33, which is formed in a subsequent step, to come into contact with semiconductor layer 21. As described above, a method for manufacturing a semiconductor device including miniaturized transistors with high yield can be achieved.

[0273] Next, a conductive film to become conductive layer 33 is formed so as to include a region located inside opening 26 and a region located inside opening 29 and so as to cover conductive layer 23, insulating layer 46, and insulating layer 49. This conductive film can be formed so as to include a region in contact with the top surface of conductive layer 23 inside opening 26.

[0274] Next, the conductive film is planarized by, for example, CMP to expose the top surface of the insulating layer 49. Thus, the conductive layer 33 ( Figure 16B). The conductive layer 33 is formed in a manner having a region in contact with the conductive layer 23 inside the opening 26. In addition, the conductive layer 33 is formed in a manner having a region located on the insulating layer 46 and in a manner having a region overlapping with the insulating layer 42 via the insulating layer 46, a region overlapping with the semiconductor layer 21, a region overlapping with the insulating layer 22, and a region overlapping with the conductive layer 23. Specifically, the conductive layer 33 is formed in a manner having a region overlapping with the top surface of the insulating layer 42 via the insulating layer 46, a region overlapping with the topmost surface of the semiconductor layer 21, a region overlapping with the topmost surface of the insulating layer 22, and a region overlapping with the top surface of the conductive layer 23. In addition, for example, the conductive layer 33 can also be formed by processing the top of the conductive film to be the conductive layer 33 using an etching method such as a dry etching method until the top surface of the insulating layer 49 is exposed. As described above, the height of the top surface of the conductive layer 33 can be made consistent or approximately consistent with the height of the top surface of the insulating layer 49.

[0275] Through the above process, it is possible to produce Figure 2B and Figure 2C The transistor 10 is shown.

[0276] [Manufacturing method example 2]

[0277] Next, an example of a method for manufacturing a semiconductor device which is partially different from the above-mentioned manufacturing method example 1 will be described. More specifically, Figure 3A and Figure 3B FIG. 1 is an example of a method for manufacturing the transistor 10. Note that descriptions of portions overlapping with those of the above-described manufacturing method example 1 are omitted as appropriate.

[0278] First, the conductive layer 32 and the insulating layer 45 are formed in the same manner as in the manufacturing method example 1. Next, the insulating layer 43 ( Figure 17A The insulating layer 43 can be formed by, for example, the same method as that of the insulating layer 46 .

[0279] Next, an insulating layer 42 ( Figure 17B The formation of the insulating layer 42 may refer to the manufacturing method example 1 described above.

[0280] Next, by processing a portion of the insulating layer 42, an opening 20b is formed that reaches the insulating layer 43. Then, by processing a portion of the insulating layer 43, a portion of the conductive layer 32, and a portion of the insulating layer 41, an opening 20a ( Figure 18A The formation of the opening 20b and the opening 20a can refer to the above-mentioned manufacturing method example 1.

[0281] Here, when forming opening 20b, insulating layer 42 is etched under conditions where the etching rate of insulating layer 42 is faster than the etching rate of insulating layer 43, thereby preventing unintended etching of insulating layer 43. This can, for example, prevent the thickness of insulating layer 43 from being reduced, thereby preventing the distance between the top surface of conductive layer 32 and conductive layer 23, which will be formed later, from being reduced. Consequently, an increase in parasitic capacitance in the region where the top surface of conductive layer 32 overlaps conductive layer 23 can be prevented. Furthermore, an insulating layer serving as an etch stop layer when forming opening 20b in insulating layer 42 can also be formed between insulating layer 43 and insulating layer 42. In this case, it is not necessary to etch insulating layer 42 under conditions where the etching rate of insulating layer 42 is faster than the etching rate of insulating layer 43 when forming opening 20b, thereby expanding the range of etching conditions. Note that, as described above, the insulating layer serving as an etch stop layer can be included in insulating layer 43, for example. In this case, the uppermost portion of insulating layer 43 can be the insulating layer serving as the etch stop layer.

[0282] Next, a semiconductor film 21f is formed so as to have a region located inside the opening 20 and to cover the conductive layer 31, the insulating layer 41, the conductive layer 32, the insulating layer 43, and the insulating layer 42. Figure 18B The formation of the semiconductor film 21f can refer to the above-mentioned manufacturing method example 1. Here, the semiconductor film 21f is preferably formed so as to have a region in contact with the top surface of the conductive layer 31 in the opening 20a, the side surface of the insulating layer 41 in the opening 20a, the side surface of the conductive layer 32 in the opening 20a, the side surface of the insulating layer 43 in the opening 20a, the top surface of the insulating layer 43 in the opening 20b, and the side surface of the insulating layer 42 in the opening 20b.

[0283] Next, an insulating film 22f is formed on the semiconductor film 21f so as to have a region located inside the opening 20. Then, a conductive film 23f ( Figure 18B The formation of the insulating film 22f and the conductive film 23f can refer to the above-mentioned manufacturing method example 1.

[0284] The following steps can refer to the manufacturing method example 1. Through the above steps, Figure 3A and Figure 3B The transistor 10 is shown.

[0285] [Manufacturing method example 3]

[0286] Next, an example of a method for manufacturing a semiconductor device which is partially different from the above-mentioned manufacturing method example 1 will be described. More specifically, Figures 6A to 6CFIG. 1 is an example of a method for manufacturing the transistor 10. Note that descriptions of portions overlapping with those of the above-described manufacturing method example 1 are omitted as appropriate.

[0287] First, similarly to the manufacturing method example 1, a semiconductor film 21f is formed. Next, a resist mask is formed on the semiconductor film 21f by, for example, photolithography, and portions of the semiconductor film 21f not covered by the resist mask are removed by etching, and then the resist mask is removed. Thus, a semiconductor layer 21 ( Figure 19A ).

[0288] Next, the insulating layer 22 is formed so as to cover the semiconductor layer 21 and the insulating layer 42 ( Figure 19B When forming the insulating layer 22, the description on the formation of the insulating film 22f in the above-mentioned manufacturing method example 1 can be referred to.

[0289] Next, a conductive film to be the conductive layer 23 is formed on the insulating layer 22. When forming the conductive film to be the conductive layer 23, the description of the formation of the conductive film 23f in the above-mentioned manufacturing method example 1 can be referred to.

[0290] Next, a resist mask is formed on the conductive film to be the conductive layer 23 by, for example, photolithography, and portions of the conductive film 23f not covered by the resist mask are removed by etching, and then the resist mask is removed. Thus, the conductive layer 23 ( Figure 19B ).

[0291] Through the above process, it is possible to produce Figures 6A to 6C The transistor 10 is shown.

[0292] The above is the description of the manufacturing method example.

[0293] [Application Examples]

[0294] Hereinafter, a structural example of a memory device according to one embodiment of the present invention using transistors and capacitors will be described.

[0295] Figure 20 The following illustrates an example circuit configuration of a memory cell 30 included in a memory device according to one embodiment of the present invention. Memory cell 30 is composed of one transistor Tr and one capacitor C, and can therefore be referred to as 1Tr1C. In transistor Tr, the gate is electrically connected to wiring WL, one of the source and drain is electrically connected to wiring BL, and the other of the source and drain is electrically connected to one electrode of capacitor C. The other electrode of capacitor C is connected to wiring PL.

[0296] Memory cell 30 stores data by holding the data potential input from wiring BL via transistor Tr in capacitor C. Furthermore, data can be retained by turning transistor Tr off. Furthermore, by turning transistor Tr on, a potential corresponding to the retained data can be output to wiring BL to read the data. Wiring WL is supplied with a signal that controls the conduction and non-conduction of transistor Tr. Furthermore, wiring PL is supplied with a predetermined potential (e.g., a fixed potential).

[0297] Figure 21A1 An example of a planar structure of a storage device according to one embodiment of the present invention is shown. Figure 21B and Figure 21C Shown separately Figure 21A1 The cross-sectional structure example of the cut-off line A1-A2 and the cut-off line B1-B2 in FIG. Specifically, Figure 21A1 、 Figure 21B and Figure 21C Show Figure 20 An example of the structure of the storage unit 30 is shown.

[0298] like Figure 21B and Figure 21C As shown, the memory cell 30 has a structure in which a transistor 10 is stacked on a capacitor 50. The transistor 10 corresponds to the transistor Tr, and the capacitor 50 corresponds to the capacitor C. Figure 21A2 The summary shows Figure 21A1 A plan view of capacitor 50 in FIG.

[0299] Since the structure of transistor 10 can be referred to above, its description is omitted. Capacitor 50 includes conductive layer 51, conductive layer 52, and insulating layer 53 interposed therebetween. Capacitor 50 is a so-called MIM (Metal-Insulator-Metal) capacitor.

[0300] Conductive layer 34 is provided on insulating layer 11, and insulating layer 47 is provided on conductive layer 34. Insulating layer 47 is provided with an opening 54a that reaches conductive layer 34. Conductive layer 51 is provided so that a region within opening 54a contacts the side surfaces of insulating layer 47 and the top surface of conductive layer 34. Furthermore, insulating layer 53 is provided so as to cover insulating layer 47 and conductive layer 51. Insulating layer 48 is provided on insulating layer 53, and insulating layer 48 is provided with an opening 54b that has a region overlapping with opening 54a and reaches insulating layer 53. Conductive layer 52 is provided so as to be embedded in opening 54b.

[0301] The top surfaces of the conductive layer 52 and the insulating layer 48 are flattened so that the top surfaces have the same or substantially the same height. The insulating layer 44 and the conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48. The conductive layer 31 is provided so as to have a region in contact with the top surface of the conductive layer 52.

[0302] exist Figure 21B and Figure 21C In the embodiment, the conductive layer 32 corresponds to Figure 20 The wiring BL shown, the conductive layer 33 corresponds to Figure 20 The wiring WL shown, the conductive layer 34 corresponds to Figure 20 The wiring PL shown.

[0303] Conductive materials with low resistance can be used for the conductive layers 34, 51, and 52. For example, the materials used for the conductive layer 23 described above can be used.

[0304] The insulating layer 53 is used as the dielectric layer of the capacitor 50. Therefore, the thinner the thickness and the higher the relative dielectric constant, the greater the capacity of the capacitor 50 can be. The insulating layer 53 is preferably made of a material with a high relative dielectric constant (high-k). For example, the insulating layer 53 is preferably used by stacking layers containing high-k materials. For example, the insulating layer 53 preferably has a stacked structure of a high-k material and a material with a dielectric strength greater than that of the high-k material. For example, as the insulating layer 53, an insulating film (also called ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film (also called ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film (also called ZAZA) in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength of the insulating layer 53 is improved, and electrostatic damage to the capacitor 50 can be suppressed.

[0305] In addition, a material exhibiting ferroelectricity may be used as the insulating layer 53. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0) and the like.

[0306] Figure 22A 、 Figure 22B and Figure 22C Show not set Figure 21A1 、 Figure 21B and Figure 21C The conductive layer 31 , the insulating layer 48 , and the insulating layer 44 shown, and the insulating layer 41 are examples of a single layer. Figure 22B and Figure 22C The example in which the opening 20a reaches the conductive layer 52 and the bottom surface of the semiconductor layer 21 is in contact with the conductive layer 52 is shown. Figure 22Band Figure 22C FIG. 4 shows an example in which the insulating layer 41 covers a portion of the top surface of the conductive layer 52 and the side surface outside the opening 54. Figure 22B and Figure 22C In the embodiment, the insulating layer 41 may have a region in contact with the top surface of the conductive layer 52 and a region in contact with the side surface of the conductive layer 52. Figure 22B and Figure 22C In the Figure 21B and Figure 21C The opening portion 54a in the figure is referred to as the opening portion 54.

[0307] exist Figures 22A to 22C In the example shown, a structure in which the opening 20 reaches the insulating layer 53 and the semiconductor layer 21 covers the top surface of the conductive layer 52 and the side surfaces outside the opening 54 may be adopted. In this case, a structure in which the insulating layer 41 does not contact the conductive layer 52 may also be adopted. Figure 22B and Figure 22C The example in which the insulating layer 41 has a single-layer structure is shown, but the insulating layer 41 may also have a stacked structure of two or more layers. Figure 21B and Figure 21C The three-layer stacked structure shown in FIG.

[0308] exist Figures 22A to 22C In the example shown, the conductive layer 52 is used as one of the source electrode and the drain electrode of the transistor 10. In this case, the conductive layer 52 is preferably made of the same material as that used for the Figure 21A1 、 Figure 21B and Figure 21C The material of the conductive layer 31 shown is the same material.

[0309] Figure 23A and Figure 23B An example of a memory device is shown in which two memory cells 30 are connected to a common wiring. Figure 23A This is an example of a planar structure of a storage device. Figure 23B yes Figure 23A An example of a cross-sectional structure along the cutting line A3-A4 in FIG.

[0310] Figure 20 The conductive layers 33 shown functioning as the wirings WL are provided in the two memory cells 30 , respectively. Figure 20 The conductive layer 32 shown as the wiring BL is provided in common in the two memory cells 30 .

[0311] also, Figure 20 Conductive layer 32 serving as wiring BL is electrically connected to conductive layers 61 and 62 serving as plugs (also called connection electrodes) embedded in the interlayer insulating layers. Conductive layer 61 may also be electrically connected to a sense amplifier (not shown) provided below insulating layer 11.

[0312] The insulating layer 65 serves as a barrier layer and has a function of preventing impurities such as water and hydrogen from diffusing from the outside into the memory device.

[0313] In addition, by arranging the memory cells 30 in a three-dimensional matrix, a memory cell array can be formed. As an example of a memory cell array, Figure 24A An example of a planar structure of a storage device is shown in which four × two × four storage cells 30 are arranged in the X direction, the Y direction, and the Z direction. Figure 24B Show Figure 24A An example of a cross-sectional structure along the cutting line A3-A4 in FIG.

[0314] exist Figure 24A and Figure 24B In the illustrated example, a group of four storage cells 30 is referred to as a memory cell 60 . Figure 24A Eight memory cells 60 are shown (memory cell 60 [1, 1] to memory cell 60 [2, 4]). In addition, Figure 24B Four memory cells 60 (memory cell 60 [1, 1] to memory cell 60 [1, 4]) are shown. In memory cell 60 [a, b] (a and b are both positive integers), a represents the address in the Y direction, and b represents the address in the Z direction.

[0315] In memory cell 60, every two memory cells 30 are arranged symmetrically around conductive layer 61 or conductive layer 62. Conductive layer 62 electrically connects the conductive layers 32 of each memory cell 60 stacked in the Z direction. By stacking multiple memory cells 60 in this manner, the storage capacity per unit area can be increased, thereby enabling a miniaturized or highly integrated memory device.

[0316] Figure 25A An example of a planar structure of a memory device in which a connection portion is arranged at an end portion of a memory cell is shown. Figure 25B Show Figure 25A Example of the cross-sectional structure of the cut line A5-A6 in FIG. Figure 25A and Figure 25B , as an example of a memory cell array, an example of a memory device having three × three × four memory cells 30 is shown. The first to fourth layers including the memory cells 30 are denoted as layers 70[1] to 70[4], respectively.

[0317] A conductive layer 63 is provided on the outside of the memory cell. The conductive layer 63 can also be electrically connected to the conductive layer 35 of the layer 70 above the layer 70 including the conductive layer 63. For example, the conductive layer 63 provided on the layer 70[1] is electrically connected to the conductive layer 35 provided on the layer 70[2]. In addition, the conductive layer 63 can be electrically connected to the conductive layer 35 of the layer 70 including the conductive layer 63, and can also be electrically connected to the conductive layer 35 of the layer 70 below the layer 70 including the conductive layer 63. Note that Figure 25B In the example shown, conductive layer 35 is provided on the same layer as conductive layer 34, that is, conductive layer 35 is formed by the same process and includes the same material as conductive layer 34, but one embodiment of the present invention is not limited to this. For example, conductive layer 35 may be provided on the same layer as conductive layer 33, the same layer as conductive layer 52, or the same layer as conductive layer 31.

[0318] Figure 26 An example of a cross-sectional structure of a memory device is shown in which a layer including memory cells 30 is stacked on a layer provided with a driver circuit including a sense amplifier.

[0319] Figure 26 In the example shown, the capacitor 50 is provided above the transistor 90, and the transistor 10 is provided on the capacitor 50. The transistor 90 may be one of the transistors included in the sense amplifier.

[0320] By providing a sense amplifier with an area overlapping with the memory cell 30, the bit line can be shortened. This reduces the load on the bit line, improving the read sensitivity of the sense amplifier. Consequently, the storage capacitance of the memory cell 30 can be reduced.

[0321] Transistor 90 is provided on substrate 91 and includes a conductive layer 94 serving as a gate electrode, an insulating layer 93 serving as a gate insulating layer, a semiconductor region 92 formed as a portion of substrate 91, a low-resistance region 95 a serving as one of a source region and a drain region, and a low-resistance region 95 b serving as the other of the source region and the drain region. Transistor 90 may be a p-channel type or an n-channel type.

[0322] Here, in Figure 26 In the transistor 90 shown, a semiconductor region 92 (a portion of a substrate 91) forming a channel has a convex shape. This transistor 90 utilizes the convex portion of the semiconductor substrate and is therefore also called a FIN-type transistor.

[0323] exist Figure 26In the illustrated memory device, an insulating layer 520 is provided on a substrate 91 to cover the convex-shaped region. An opening is provided in the insulating layer 520 to reach the semiconductor region 92, and an insulating layer 93 is provided along the top surface of the semiconductor region 92 and the side surfaces of the insulating layer 520 within the opening. A conductive layer 94 is provided on the insulating layer 93 to fill the opening. Furthermore, the height of the top surface of the insulating layer 520, the height of the topmost surface of the insulating layer 93, and the height of the top surface of the conductive layer 94 can be made equal or substantially equal.

[0324] exist Figure 26 In the illustrated example, insulating layer 522, insulating layer 524, and insulating layer 526 are sequentially stacked on insulating layer 520. Conductive layer 528, which is electrically connected to low-resistance region 95a or low-resistance region 95b, is embedded in insulating layer 520 and insulating layer 522. Conductive layer 530, which is electrically connected to conductive layer 528, is embedded in insulating layer 524 and insulating layer 526.

[0325] A wiring layer may also be provided on the insulating layer 526 and the conductive layer 530. Figure 26 In the illustrated example, an insulating layer 550, an insulating layer 582, and an insulating layer 584 are sequentially stacked on the insulating layer 526 and the conductive layer 530. A conductive layer 586 electrically connected to the conductive layer 530 is embedded in the insulating layer 550, the insulating layer 582, and the insulating layer 584.

[0326] The insulating layer 520, the insulating layer 522, the insulating layer 524, the insulating layer 526, the insulating layer 550, the insulating layer 582, and the insulating layer 584 function as interlayer insulating layers, and the conductive layer 528, the conductive layer 530, and the conductive layer 586 function as plugs or wirings.

[0327] Insulating layer 11 is provided over insulating layer 584 and conductive layer 586. Conductive layer 12, which is electrically connected to conductive layer 586, is embedded in insulating layer 11. Insulating layer 55 is provided over insulating layer 11. Insulating layer 55 serves as an interlayer insulating layer. Conductive layer 34, which is electrically connected to conductive layer 51 included in capacitor 50, and conductive layer 36, which is electrically connected to conductive layer 12, are embedded in insulating layer 55.

[0328] Insulating layer 47, insulating layer 53, and insulating layer 48 are sequentially stacked on insulating layer 55, conductive layer 34, and conductive layer 36. Conductive layer 37 electrically connected to conductive layer 36 is embedded in insulating layer 47, insulating layer 53, and insulating layer 48.

[0329] An insulating layer 44 is provided on the insulating layer 48. In addition to the conductive layer 31 included in the transistor 10, the insulating layer 44 embeds a conductive layer 38 electrically connected to the conductive layer 37.

[0330] Insulating layer 41 is stacked in this order on insulating layer 44, conductive layer 31, and conductive layer 38. Conductive layer 39, which is electrically connected to conductive layer 38, is embedded in insulating layer 41. Conductive layer 39 is provided on insulating layer 41 and conductive layer 39, and conductive layer 39 is electrically connected to conductive layer 32.

[0331] As described above, the low resistance region 95 a or the low resistance region 95 b and the conductive layer 32 are electrically connected through the conductive layers 528 , 530 , 586 , 12 , 36 , 37 , 38 , and 39 . Figure 26 An example is shown in which the low-resistance region 95 a is electrically connected to the conductive layer 32 .

[0332] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0333] (Implementation Method 2)

[0334] In this embodiment, referring to Figures 27 to 30 A memory device according to one embodiment of the present invention will be described. In this embodiment, a structural example of a memory device in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier will be described.

[0335] <Configuration Example of Storage Device>

[0336] Figure 27 4 is a block diagram illustrating a configuration example of a storage device 480 according to one embodiment of the present invention. Figure 27 The illustrated memory device 480 includes layer 420 and stacked layer 470 .

[0337] Layer 420 is a layer including Si transistors. In stacked layer 470, element layers 430[1] to 430[m] (m is an integer greater than or equal to 2) are stacked. Element layers 430[1] to 430[m] are layers including OS transistors. Layer 470, in which layers including OS transistors are stacked, can be stacked on layer 420.

[0338] Elements such as OS transistors and capacitors included in the element layers 430 [ 1 ] to 430 [ m ] constitute memory cells. Figure 27 An example is shown in which the element layers 430 [ 1 ] to 430 [ m ] include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer equal to or greater than 2).

[0339] exist Figure 27, the 1st row and 1st column storage cell 432 is represented as storage cell 432[1, 1], and the mth row and nth column storage cell 432 is represented as storage cell 432[m, n]. In addition, for example, in this embodiment, sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, for example, in this embodiment, the i-th row and j-th column storage cell 432 is represented as storage cell 432[i, j]. Note that, for example, in this embodiment, when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0340] Also, as an example, Figure 27 m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are shown. For example, in this embodiment, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n]. Note that the number of layers of the element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) may also be different.

[0341] The plurality of memory cells 432 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 432 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0342] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line to control the on / off state (conductive state or non-conductive state) of the access transistor used as a switch. Wiring PL is used as a constant potential line connected to the capacitor. In addition, wiring for transmitting the back gate potential can be provided separately.

[0343] The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the substrate surface on which the layer 420 is provided. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] with wiring arranged in a direction parallel to the substrate surface and wiring arranged in a direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cells and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit lines can be significantly reduced, power consumption and signal delay can be reduced. As a result, the power consumption and signal delay of the memory device 480 can be reduced. In addition, the memory device 480 can still operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. As a result, the memory device 480 can be miniaturized.

[0344] Layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. Peripheral circuit 422 includes a driver circuit 440, a control circuit 473 (control circuit), and a voltage generation circuit 474. Note that each circuit included in layer 420 includes Si transistors.

[0345] In storage device 480, various circuits, signals, and voltages can be appropriately selected as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, while signal RDA is an external output signal. Signal CLK is a clock signal.

[0346] In addition, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can also be generated in control circuit 473.

[0347] The control circuit 473 is a logic circuit that controls the overall operation of the memory device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates control signals for the driver circuit 440 to implement the aforementioned operating mode.

[0348] Voltage generating circuit 474 generates a negative voltage. Signal WAKE controls the input of signal CLK to voltage generating circuit 474. For example, when signal WAKE is at an H level, signal CLK is input to voltage generating circuit 474, causing voltage generating circuit 474 to generate a negative voltage.

[0349] The driver circuit 440 is a circuit for writing and reading data from the memory cell 432. In addition to a row decoder 442 (Row Decoder), a column decoder 444 (Column Decoder), a row driver 443 (Row Driver), a column driver 445 (Column Driver), an input circuit 447 (Input Cir.), and an output circuit 448 (Output Cir.), the driver circuit 440 also includes the aforementioned sense amplifier 446.

[0350] The row decoder 442 and column decoder 444 decode the signal ADDR. The row decoder 442 specifies the row to be accessed, while the column decoder 444 specifies the column to be accessed. The row driver 443 selects the wiring WL specified by the row decoder 442. The column driver 445 writes data to the memory cell 432, reads data from the memory cell 432, and stores the read data.

[0351] Input circuit 447 holds signal WDA. Data held in input circuit 447 is output to column driver 445. The output data from input circuit 447 is data (Din) written to memory cell 432. Data (Dout) read from memory cell 432 by column driver 445 is output to output circuit 448. Output circuit 448 holds Dout. Furthermore, output circuit 448 outputs Dout to the outside of memory device 480. Data output from output circuit 448 is signal RDA.

[0352] PSW471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply voltage of the memory device 480 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The on / off of PSW471 is controlled by the signal PON1, and the on / off of PSW472 is controlled by the signal PON2. Figure 27 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but it may be multiple. In this case, a power switch may be provided for each power domain.

[0353] Element layers 430 [ 1 ] to 430 [ m ] may be stacked on layer 420 . Figure 28A 4 is a perspective view of a memory device 480 showing a state in which five (m=5) element layers 430 [ 1 ] to 430 [ 5 ] are stacked on a layer 420 .

[0354] exist Figure 28A In the embodiment, the element layer 430 provided in the first layer is referred to as element layer 430[1], the element layer 430 provided in the second layer is referred to as element layer 430[2], and the element layer 430 provided in the fifth layer is referred to as element layer 430[5]. Figure 28A The diagram shows wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y and Z directions (directions perpendicular to the substrate surface on which the driver circuit is provided). Wiring BLB is an inverted bit line. Note that for easier understanding of the drawing, some of the wirings WL and PL included in each element layer 430 are omitted.

[0355] Figure 28B It is an explanation Figure 28A The diagram shows an example of a structure of a memory cell 432 included in a sense amplifier 446 connected to a wiring BL and a wiring BLB, and element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. A structure in which multiple memory cells (memory cells 432) are electrically connected to a single wiring BL and a wiring BLB is also referred to as a "memory string."

[0356] Figure 28B An example of a circuit structure of a memory cell 432 connected to a wiring BLB is shown. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. As the memory cell 432, for example, the memory cell 30 shown in the above embodiment can be used. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438. In addition, as the transistor included in the sense amplifier 446, a transistor 90 (see Figure 26 ).

[0357] In the memory cell 432, one of the source and drain of the transistor 437 is connected to the wiring BL. The other of the source and drain of the transistor 437 is connected to one electrode of the capacitor 438. The other electrode of the capacitor 438 is connected to the wiring PL. The gate of the transistor 437 is connected to the wiring WL.

[0358] The wiring PL is a wiring that supplies a constant potential for maintaining the potential of the capacitor 438. By connecting a plurality of wirings PL and using them as one wiring, the number of wirings can be reduced.

[0359] In one embodiment of the present invention, OS transistors are stacked and arranged, and bit line wiring is arranged perpendicular to the substrate surface on which layer 420 is provided. Furthermore, transistor 437 and capacitor 438 included in memory cell 432 are arranged perpendicular to the substrate surface on which layer 420 is provided. By arranging each element and wiring perpendicular to the substrate surface, the wiring length between element layers can be shortened, and the element density per unit area can be increased. This allows for a memory device that excels in reducing storage capacity and power consumption.

[0360] [Configuration Example of Memory Cell 432 and Sense Amplifier 446]

[0361] Figure 29A and Figure 29B 1 is a circuit diagram corresponding to the above-mentioned storage unit 432 and a circuit block diagram corresponding to the circuit diagram. Figure 29A and Figure 29B As shown, sometimes the storage unit 432 is represented as a block in the drawings and the like. Figure 29A and Figure 29B The same representation can be applied even when the wiring BL shown is replaced with the wiring BLB.

[0362] in addition, Figure 29C and Figure 29D 4 is a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. Sense amplifier 446 shows a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. In addition to wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB for outputting a read signal are also shown.

[0363] like Figure 29C As shown, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conductive states of the wiring pair SA_OUT and SA_OUTB and the wiring pair BL and BLB in response to the signal CSEL.

[0364] like Figure 29C As shown, the precharge circuit 483 includes an n-channel transistor 483_1, a transistor 483_2, and a transistor 483_3. The precharge circuit 483 performs precharging so that the potentials of the wirings BL and BLB reach an intermediate potential VPRE corresponding to the potential VDD / 2 according to the signal EQ.

[0365] like Figure 29C As shown, precharge circuit 484 includes p-channel transistors 484_1, 484_2, and 484_3. Precharge circuit 484 performs precharging so that the potentials of wirings BL and BLB reach an intermediate potential VPRE corresponding to potential VDD / 2 in response to signal EQB.

[0366] like Figure 29C As shown, amplifier circuit 485 is composed of p-channel transistors 485_1 and 485_2, and n-channel transistors 485_3 and 485_4, connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is a wiring that has the function of supplying VDD or VSS. Transistors 485_1 to 485_4 are transistors that form an inverter loop.

[0367] also, Figure 29D For example, the corresponding Figure 29C The circuit block diagram of the sense amplifier 446 is shown in FIG. Figure 29D As shown, the sense amplifier 446 is sometimes represented as a block in the drawings and the like.

[0368] Figure 30 yes Figure 27 A block diagram of the storage device 480 is shown. Figure 30 Use Figure 29B and Figure 29D The circuit blocks described in .

[0369] like Figure 30 As shown, layer 470 having element layer 430[m] includes memory cell 432. As an example, Figure 30 The memory cell 432 shown is connected to a pair of wiring BL[1] and wiring BLB[1] or wiring BL[2] and wiring BLB[2]. The memory cell 432 connected to the wiring BL is a memory cell that performs data writing or reading.

[0370] The wiring BL[1] and the wiring BLB[1] are connected to the read amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to the read amplifier 446[2]. The read amplifier 446[1] and the read amplifier 446[2] can be connected according to Figure 29D The data is read out using the various signals described in [1].

[0371] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0372] (Implementation 3)

[0373] In this embodiment, a structural example of a display device using a transistor that is one embodiment of the present invention is described.

[0374] Because the transistor of one embodiment of the present invention can be formed extremely finely, a display device using the transistor of one embodiment of the present invention can be an extremely high-definition display device. For example, the display device of one embodiment of the present invention can be used in the display portion of information terminal devices (wearable devices) such as watches and bracelets, and in the display portion of wearable devices (HMDs) such as head-mounted displays (HMDs) for VR devices and glasses-type AR devices.

[0375] [Display module]

[0376] Figure 31A 2 is a perspective view of a display module 280. The display module 280 includes a display device 200A and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 200A, and may also be the display device 200B or the display device 200C described later.

[0377] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display portion 281. The display portion 281 is a region for displaying an image.

[0378] Figure 31B A perspective schematic diagram shows the structure of one side of a substrate 291. A circuit portion 282, a pixel circuit portion 283 on circuit portion 282, and a pixel portion 284 on pixel circuit portion 283 are stacked on substrate 291. Furthermore, a terminal portion 285 for connecting to an FPC 290 is provided in an area of ​​substrate 291 that does not overlap with pixel portion 284. Terminal portion 285 and circuit portion 282 are electrically connected via a wiring portion 286 composed of a plurality of wiring lines.

[0379] The pixel portion 284 includes a plurality of pixels 284 a arranged periodically. Figure 31B An enlarged view of one pixel 284a is shown on the right side of FIG. The pixel 284a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0380] The pixel circuit portion 283 includes a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a controls the light emission of three light-emitting elements included in one pixel 284a. One pixel circuit 283a may include three circuits for controlling the light emission of one light-emitting element. For example, the pixel circuit 283a may have a structure including at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. Thus, an active matrix display device can be realized.

[0381] The circuit portion 282 includes circuits for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit. Furthermore, the transistors provided in the circuit portion 282 may also constitute part of the pixel circuit 283a. In other words, the pixel circuit 283a may be constituted by the transistors included in the pixel circuit portion 283 and the transistors included in the circuit portion 282.

[0382] The FPC 290 is used as wiring for supplying video signals, power supply potential, and the like from the outside to the circuit portion 282. Alternatively, an IC may be mounted on the FPC 290.

[0383] The display module 280 can adopt a structure in which one or both of the pixel circuit unit 283 and the circuit unit 282 are overlapped on the lower side of the pixel unit 284, so that the display unit 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display unit 281 can be greater than 40% and less than 100%, preferably greater than 50% and less than 95%, and more preferably greater than 60% and less than 95%. In addition, the pixels 284a can be arranged at an extremely high density, thereby making the display unit 281 have an extremely high definition. For example, the display unit 281 preferably configures the pixels 284a with a definition of greater than 2000ppi, more preferably greater than 3000ppi, further preferably greater than 5000ppi, and even more preferably greater than 6000ppi and less than 20,000ppi or less than 30,000ppi.

[0384] This display module 280 is very clear and is therefore suitable for use in VR devices such as head-mounted displays or glasses-type AR devices. For example, because the display module 280 has a display portion 281 with extremely high clarity, in a structure where the display portion of the display module 280 is viewed through a lens, even if the user uses the lens to magnify the display portion, the pixels cannot be seen, thereby achieving a highly immersive display. In addition, the display module 280 can also be applied to electronic devices with relatively small display portions. For example, it is suitable for use in the display portion of wearable electronic devices such as watch-type devices.

[0385] [Display device 200A]

[0386] Figure 32 The display device 200A shown includes a substrate 331 , a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 240 , and a transistor 10 .

[0387] Substrate 331 is equivalent to Figure 31A The structure of the transistor 10 can refer to that of Embodiment Mode 1, and thus description thereof will be omitted.

[0388] An insulating layer 332 is provided over the substrate 331, and the transistor 10 is provided over the insulating layer 332. The insulating layer 332 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the substrate 331 into the transistor 10 and prevents oxygen from escaping from the semiconductor layer 21 toward the insulating layer 332. For example, a film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, into which hydrogen and oxygen are less likely to diffuse than a silicon oxide film, can be used as the insulating layer 332.

[0389] Insulating layer 42, insulating layer 46, insulating layer 49, and insulating layer 266 serve as interlayer insulating layers. A barrier layer may be provided between insulating layer 266 and insulating layer 49 to prevent impurities such as water or hydrogen from diffusing from insulating layer 266 into transistor 10. The barrier layer can be an insulating film similar to that used for insulating layer 332.

[0390] Plug 274, electrically connected to one of the conductive layers 32, is embedded in insulating layer 266, insulating layer 49, insulating layer 46, and insulating layer 42. Plug 274 preferably includes a conductive layer 274a that covers the side surfaces of the openings in insulating layers 266, 49, 46, and 42 and a portion of the top surface of conductive layer 32, and a conductive layer 274b located inside conductive layer 274a and filling the openings. A conductive material that is not easily diffused by hydrogen and oxygen is preferably used for conductive layer 274a.

[0391] Furthermore, capacitor 240 is provided on insulating layer 266. Capacitor 240 includes conductive layer 241, conductive layer 245, and insulating layer 243 located therebetween. Conductive layer 241 serves as one electrode of capacitor 240, conductive layer 245 serves as the other electrode of capacitor 240, and insulating layer 243 serves as a dielectric of capacitor 240.

[0392] Conductive layer 241 is provided on plug 274 and insulating layer 266 and embedded in insulating layer 254. Conductive layer 241 is electrically connected to conductive layer 32 of transistor 10 via plug 274. Insulating layer 243 is provided to cover conductive layer 241. Conductive layer 245 is provided in a region overlapping conductive layer 241 with insulating layer 243 interposed therebetween.

[0393] The capacitor 240 is covered with an insulating layer 255 a , an insulating layer 255 b is provided on the insulating layer 255 a , and an insulating layer 255 c is provided on the insulating layer 255 b .

[0394] Inorganic insulating films can be used as appropriate for the insulating layers 255a, 255b, and 255c. For example, preferably, silicon oxide films are used for the insulating layers 255a and 255c, and a silicon nitride film is used for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. Although this embodiment shows an example in which a recess is formed by etching a portion of the insulating layer 255c, the recess need not be formed in the insulating layer 255c.

[0395] The light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B are provided on the insulating layer 255c. The light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B will be described in detail in Embodiment 3.

[0396] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in the light-emitting elements 110R, 110G, and 110B.

[0397] Organic layer 112R included in light-emitting element 110R contains a light-emitting organic compound that emits at least red light. Organic layer 112G included in light-emitting element 110G contains a light-emitting organic compound that emits at least green light. Organic layer 112B included in light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layer 112R, organic layer 112G, and organic layer 112B may each be referred to as an EL layer and include at least a layer containing a light-emitting organic compound (light-emitting layer).

[0398] Display device 200A employs separate light-emitting devices for each color, minimizing chromaticity variation between low-brightness and high-brightness light. Furthermore, organic layers 112R, 112G, and 112B are separated from one another, minimizing crosstalk between adjacent sub-pixels even in high-definition displays. This enables the realization of a high-definition, high-quality display device.

[0399] An insulating layer 125 , a resin layer 126 , and a layer 128 are provided in a region between adjacent light emitting elements.

[0400] The pixel electrodes 111R, 111G, and 111B of the light-emitting elements are electrically connected to the conductive layer 32 of the transistor 10 via the plugs 256 embedded in the insulating layers 255a, 255b, and 255c, the conductive layer 241 embedded in the insulating layer 254, and the plugs 274. The height of the top surface of the insulating layer 255c is equal to or substantially equal to the height of the top surface of the plugs 256. Various conductive materials can be used as the plugs.

[0401] Furthermore, a protective layer 121 is provided on the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B. A substrate 170 is bonded to the protective layer 121 via an adhesive layer 171 .

[0402] No insulating layer covering the top end of the pixel electrodes 111 is provided between two adjacent pixel electrodes 111. Therefore, the interval between adjacent light-emitting elements can be made very small, thereby achieving a high-definition or high-resolution display device.

[0403] [Display device 200B]

[0404] Hereinafter, a display device having a partially different structure from the above example will be described. Note that the same parts as above will be referred to the above description, and the description may be omitted.

[0405] Figure 33 The display device 200B shown shows an example in which a transistor 10A, which is a planar transistor in which a semiconductor layer is formed on a plane, and a transistor 10, which is a vertical channel transistor, are stacked.

[0406] The transistor 10A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0407] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the substrate 331 to the transistor 10 and prevents oxygen from escaping from the semiconductor layer 351 toward the insulating layer 352. For example, a film into which hydrogen and oxygen are less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used as the insulating layer 352.

[0408] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided over the insulating layer 352 to cover the conductive layer 357. The conductive layer 357 serves as a first gate electrode of the transistor 10A, and a portion of the insulating layer 356 serves as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least the region of the insulating layer 356 that contacts the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0409] The semiconductor layer 351 is provided on the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 are in contact with the semiconductor layer 351 and function as a source electrode and a drain electrode.

[0410] Insulating layer 358 and insulating layer 350 are provided to cover the top and side surfaces of the pair of conductive layers 355 and the side surfaces of semiconductor layer 351. Insulating layer 358 serves as a barrier layer that prevents impurities such as water and hydrogen from diffusing into semiconductor layer 351 and oxygen from escaping from semiconductor layer 351. As insulating layer 358, the same insulating film as that of insulating layer 352 can be used.

[0411] Insulating layer 358 and insulating layer 350 have openings that reach semiconductor layer 351. Embedded within these openings are insulating layer 353, which contacts the top surface of semiconductor layer 351, and conductive layer 354. Conductive layer 354 functions as a second gate electrode, and insulating layer 353 functions as a second gate insulating layer.

[0412] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are uniform or substantially uniform, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer to prevent impurities such as water and hydrogen from diffusing into the transistor 10. The insulating layer 359 can be the same insulating film as the insulating layer 352 described above.

[0413] Transistor 10 employs a structure in which two gates sandwich a semiconductor layer forming a channel. Alternatively, the two gates may be connected and the transistor may be driven by supplying the same signal to both gates. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving the other.

[0414] Insulating layer 361 is provided on insulating layer 359, and plug 374 is embedded in insulating layer 361, insulating layer 359, insulating layer 350, and insulating layer 358. Plug 374 preferably includes a conductive layer 374a that covers the side surfaces of the openings in insulating layers 361, 359, 350, and 358 and a portion of the top surface of conductive layer 355, and a conductive layer 374b located inside conductive layer 374a and filling the openings. Conductive layer 374a can be made of the same material as that used for conductive layer 274a, and conductive layer 374b can be made of the same material as that used for conductive layer 274b.

[0415] A conductive layer 371 is provided over the plug 374 and the insulating layer 361. The conductive layer 371 is electrically connected to the conductive layer 355 of the transistor 10A via the plug 374. Furthermore, an insulating layer 362 is provided over the insulating layer 361 to cover the conductive layer 371. Furthermore, an insulating layer 332 is provided over the insulating layer 362.

[0416] [Display device 200C]

[0417] Figure 34 The display device 200C shown includes a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 10 which is a vertical channel transistor.

[0418] Transistor 310 is a transistor having a channel formation region in substrate 301. As substrate 301, a semiconductor substrate such as a single crystal silicon substrate can be used, for example. Transistor 310 includes a portion of substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. Conductive layer 311 serves as a gate electrode. Insulating layer 313 is located between substrate 301 and conductive layer 311 and serves as a gate insulating layer. Low-resistance region 312 is a region in substrate 301 doped with impurities and serves as either a source or a drain. Insulating layer 314 covers the side surfaces of conductive layer 311.

[0419] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0420] An insulating layer 261 is provided to cover the transistor 310, and a plug 271 is embedded in the insulating layer 261. A conductive layer 251 is provided on the plug 271 and the insulating layer 261. The conductive layer 251 is electrically connected to the low-resistance region 312 of the transistor 310 via the plug 271. Furthermore, an insulating layer 262 is provided on the insulating layer 261 to cover the conductive layer 251. Furthermore, the conductive layer 252 is provided on the insulating layer 262, the insulating layer 263 is provided on the conductive layer 252, and the insulating layer 332 is provided on the insulating layer 263.

[0421] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0422] (Implementation 4)

[0423] This embodiment describes a structural example of a display device that can be used in a display device manufactured using a transistor of one embodiment of the present invention. The display device described below can be used in the pixel portion 284 of Embodiment 3, for example.

[0424] One embodiment of the present invention is a display device including a light-emitting element. The display device includes at least two or more pixels emitting different colors. Each pixel includes a light-emitting element. Each light-emitting element includes a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). The two or more light-emitting elements emitting different colors each include an EL layer containing a different material. For example, a full-color display device can be realized by including three light-emitting elements that emit red (R), green (G), or blue (B) light, respectively.

[0425] When manufacturing a display device that includes multiple light-emitting elements emitting different colors, it is necessary to form at least the layer containing the light-emitting material (the light-emitting layer) into an island shape. A known method is to form island-shaped organic films using a metal mask or other shadow mask when forming a portion or all of the EL layer. However, this method suffers from various factors, such as the accuracy of the metal mask, misalignment between the metal mask and the substrate, metal mask deflection, and vapor scattering that causes the deposited film to expand. This can cause the shape and position of the island-shaped organic films to deviate from the designed shape and position, making it difficult to achieve high-definition and high-aperture display devices. Furthermore, during vapor deposition, the layer outline may be blurred, resulting in a reduced film thickness at the ends. In other words, the film thickness of the island-shaped light-emitting layer may vary depending on the location. Furthermore, when manufacturing large, high-resolution or high-definition display devices, there is a concern that the manufacturing yield may decrease due to low dimensional accuracy of the metal mask and deformation caused by heat, etc. Therefore, efforts have been made to artificially improve resolution (also known as pixel density) by adopting special pixel arrangements such as the Pentile arrangement.

[0426] Note that in this specification, "island-shaped" refers to a state in which two or more layers formed from the same material in the same process are physically separated. For example, an island-shaped light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0427] In one embodiment of the present invention, the EL layer is processed into a fine pattern using photolithography, without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a high aperture ratio, which was previously difficult to achieve. Furthermore, since the EL layer can be manufactured separately, a high-quality display device with extremely clear and high contrast can be realized. Furthermore, for example, the EL layer can be processed into a fine pattern using both a metal mask and photolithography.

[0428] In addition, part or all of the EL layer can be physically separated. As a result, leakage current between light-emitting elements through the layer commonly used by adjacent light-emitting elements (also called a common layer) can be suppressed. Therefore, crosstalk caused by unintentional light emission can be suppressed, thereby realizing a display device with very high contrast. In particular, a display device with high current efficiency at low brightness can be realized.

[0429] One embodiment of the present invention can also realize a display device that combines a white light-emitting element and a color filter. In this case, light-emitting elements of the same structure can be used for each light-emitting element in a pixel (sub-pixel) that emits light of different colors, and all layers in each light-emitting element can be used as a common layer. Furthermore, it is also possible to cut off part or all of each EL layer by using photolithography. Thus, the leakage current through the common layer can be suppressed and a display device with high contrast can be realized. In particular, in an element having a series structure in which a plurality of light-emitting layers are stacked with an intermediate layer having high conductivity, the leakage current through the intermediate layer can be effectively prevented, so a display device with high brightness, high definition and high contrast can be realized.

[0430] When processing the EL layer using photolithography, degradation may occur due to partial exposure of the light-emitting layer. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. This insulating layer may also cover a portion of the top surface of the island-shaped EL layer. This insulating layer is preferably made of a material that has barrier properties to water and oxygen. For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This can suppress degradation of the EL layer and achieve a highly reliable display device.

[0431] In addition, there is an area (recess) between two adjacent light-emitting elements where the EL layer of each light-emitting element is not provided. When a common electrode or a common electrode and a common layer are formed in a manner covering this recess, the common electrode may be disconnected (also called disconnected) due to a step at the end of the EL layer, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to adopt a structure (also called LFP: Local Filling Planarization) in which a resin layer used as a planarizing film is used to fill the local step between two adjacent light-emitting elements. This resin layer is used as a planarizing film. As a result, disconnection of the common layer or common electrode can be suppressed, and a highly reliable display device can be realized.

[0432] Hereinafter, a more specific structural example of a display device according to one embodiment of the present invention will be described with reference to the drawings.

[0433] [Structure example 1]

[0434] Figure 35A FIG1 is a plan view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a plurality of red light-emitting elements 110R, a plurality of green light-emitting elements 110G, and a plurality of blue light-emitting elements 110B on a substrate 101. Figure 35A In order to distinguish the light-emitting elements, the symbols R, G or B are attached to the light-emitting area of ​​each light-emitting element.

[0435] The light emitting elements 110R, the light emitting elements 110G, and the light emitting elements 110B are arranged in a matrix. Figure 35A This figure shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of light-emitting elements is not limited to this. Other arrangements such as S-stripe arrangement, Delta arrangement, Bayer arrangement, or zigzag arrangement can also be used. Pentile arrangement or Diamond arrangement can also be used.

[0436] As the light-emitting elements 110R, 110G, and 110B, an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) is preferably used. As the light-emitting substance contained in the EL element, examples include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). As the light-emitting substance contained in the EL element, in addition to organic compounds, inorganic compounds (for example, quantum dot materials) can also be used.

[0437] In addition, Figure 35A A connection electrode 111C electrically connected to the common electrode 113 is shown. The connection electrode 111C is supplied with the potential (for example, an anode potential or a cathode potential) supplied to the common electrode 113. The connection electrode 111C is provided, for example, outside the display area in which the light-emitting elements 110R are arranged.

[0438] The connection electrode 111C can be provided along the outer periphery of the display area. For example, it can be provided along one side of the outer periphery of the display area, or can be provided across two or more sides of the outer periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangular), L-shaped, "冂"-shaped (bracket-shaped), or quadrangular, etc.

[0439] Figure 35B , Figure 35C ​​​​​​​​​​​​Organic layer 112R included in light-emitting element 110R contains a light-emitting organic compound that emits at least red light. Organic layer 112G included in light-emitting element 110G contains a light-emitting organic compound that emits at least green light. Organic layer 112B included in light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layer 112R, organic layer 112G, and organic layer 112B may each be referred to as an EL layer and include at least a layer containing a light-emitting organic compound (light-emitting layer).

[0442] Hereinafter, when describing common features among light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, they may be referred to as light-emitting element 110. Similarly, when describing common features among components identified by letters, such as organic layer 112R, organic layer 112G, and organic layer 112B, the letters may be omitted.

[0443] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 may include a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 may include an electron injection layer.

[0444] The pixel electrode 111R, the pixel electrode 111G and the pixel electrode 111B are all provided in each light-emitting element. In addition, the common electrode 113 and the common layer 114 are provided as a layer commonly used by each light-emitting element. A conductive film that is translucent to visible light is used as one of the pixel electrodes and the common electrode 113, and a reflective conductive film is used as the other. By making each pixel electrode translucent and the common electrode 113 reflective, a bottom-emission type (bottom-emission structure) display device can be realized. Conversely, by making each pixel electrode reflective and the common electrode 113 translucent, a top-emission type (top-emission structure) display device can be realized. In addition, by making both the pixel electrode and the common electrode 113 translucent, a double-sided emission type (double-sided emission structure) display device can also be realized.

[0445] A protective layer 121 is provided on the common electrode 113 so as to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above to each light emitting element.

[0446] The end of the pixel electrode 111 preferably has a tapered shape. When the end of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the end of the pixel electrode 111 may also have a tapered shape. By making the side of the pixel electrode 111 have a tapered shape, the coverage of the organic layer 112 provided across the end of the pixel electrode 111 can be improved. In addition, by making the side of the pixel electrode 111 have a tapered shape, foreign matter (for example, dust or particles) can be easily removed during the manufacturing process through washing, etc., which is preferable.

[0447] Note that in this specification, a tapered shape refers to a shape in which at least a portion of a side surface of a component is inclined relative to the substrate surface. For example, a region where the angle between the inclined side surface and the substrate surface (also referred to as a taper angle) is less than 90° is preferably present.

[0448] The organic layer 112 is processed into an island shape using photolithography. As a result, the organic layer 112 has a shape at its ends where the angle between the top surface and the side surfaces is close to 90 degrees. On the other hand, the thickness of an organic film formed using, for example, a Fine Metal Mask (FMM) tends to decrease toward the ends. For example, the top surface is sloped within a range of 1 μm to 10 μm from the end, making it difficult to distinguish between the top surface and the side surfaces.

[0449] An insulating layer 125 , a resin layer 126 , and a layer 128 are provided between two adjacent light emitting elements.

[0450] Between two adjacent light-emitting elements, the side surfaces of each organic layer 112 face each other via a resin layer 126. The resin layer 126 is positioned between the two adjacent light-emitting elements and is provided to fill the ends of each organic layer 112 and the area between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and the common layer 114 and the common electrode 113 are provided to cover the top surface of the resin layer 126.

[0451] Resin layer 126 serves as a planarization film, filling the step between adjacent light-emitting elements. This prevents common electrode 113 from being disconnected (also called disconnected) from organic layer 112 due to the step at the end of organic layer 112, which could result in insulation of common electrode 113 on organic layer 112. Resin layer 126 is also referred to as an LFP (Local Filling Planarization) layer.

[0452] An insulating layer composed of an organic material can be suitably used as the resin layer 126. For example, acrylic resins, polyimide resins, epoxy resins, imide resins, polyamide resins, polyimideamide resins, silicone resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resins can be used as the resin layer 126.

[0453] Alternatively, a photosensitive resin may be used as the resin layer 126. A photoresist may be used as the photosensitive resin. A positive-type material or a negative-type material may be used as the photosensitive resin.

[0454] Resin layer 126 may also contain a material that absorbs visible light. For example, resin layer 126 itself may be composed of a material that absorbs visible light, or resin layer 126 may contain a pigment that absorbs visible light. Examples of resin layer 126 include resins that function as color filters that transmit red, blue, or green light and absorb other light, or resins that contain carbon black as a pigment and function as a black matrix.

[0455] The insulating layer 125 is provided so as to have a region in contact with the side surface of the organic layer 112. The insulating layer 125 also covers the upper end portion of the organic layer 112. A portion of the insulating layer 125 is in contact with the top surface of the substrate 101.

[0456] Insulating layer 125 is located between resin layer 126 and organic layer 112 and serves as a protective film to prevent resin layer 126 from contacting organic layer 112. When organic layer 112 and resin layer 126 come into contact, there is a risk that organic layer 112 may be dissolved, for example, by an organic solvent used to form resin layer 126. Therefore, providing insulating layer 125 between organic layer 112 and resin layer 126 protects the side surfaces of organic layer 112.

[0457] The insulating layer 125 may be an insulating layer containing an inorganic material. As the insulating layer 125, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film may be used. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of nitride oxide insulating films include silicon oxynitride films and aluminum oxynitride films. In particular, by using a metal oxide film such as an aluminum oxide film or a hafnium oxide film, or an inorganic insulating film such as a silicon oxide film, formed by an ALD method, for the insulating layer 125 , the insulating layer 125 can have fewer pinholes and an excellent function of protecting the EL layer.

[0458] In this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, while "oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0459] The insulating layer 125 can be formed by sputtering, CVD, PLD, ALD, or the like. The insulating layer 125 is preferably formed by ALD, which has good coverage.

[0460] Alternatively, a reflective film (e.g., a metal film containing one or more metals selected from silver, palladium, copper, titanium, and aluminum) may be provided between the insulating layer 125 and the resin layer 126 to reflect light emitted by the light-emitting layer. This can further improve light extraction efficiency.

[0461] Layer 128 is the remaining portion of a protective layer (also referred to as a mask layer or sacrificial layer) used to protect organic layer 112 during etching of organic layer 112. Layer 128 can use the same material as that used for insulating layer 125. In particular, layer 128 and insulating layer 125 are preferably made of the same material, thereby enabling, for example, the use of the same processing equipment.

[0462] In particular, among metal oxide films such as aluminum oxide films and hafnium oxide films, or inorganic insulating films such as silicon oxide films formed by the ALD method, films with relatively few pinholes have an excellent function of protecting the EL layer and are therefore preferably used for the insulating layer 125 and the layer 128 .

[0463] The protective layer 121 can have, for example, a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, a semiconductor material or conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide can be used as the protective layer 121.

[0464] As the protective layer 121, a laminated film of an inorganic insulating film and an organic insulating film can also be used. For example, it is preferred to sandwich an organic insulating film between a pair of inorganic insulating films. In addition, the organic insulating film is preferably used as a planarizing film. Therefore, the top surface of the organic insulating film can be made flat, so the coverage of the inorganic insulating film thereon is improved, thereby improving the barrier property. In addition, the top surface of the protective layer 121 becomes flat, so when a structure (for example, a color filter, an electrode or a lens array of a touch sensor, etc.) is provided above the protective layer 121, the influence of the concave and convex shape caused by the lower structure can be reduced, so it is preferred.

[0465] Figure 35C The figure shows a connection portion 140 that electrically connects the connection electrode 111C to the common electrode 113. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected in this opening.

[0466] Notice, Figure 35C Although the connection portion 140 electrically connecting the connection electrode 111C and the common electrode 113 is shown, the common electrode 113 may also be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used as the common layer 114, the resistivity of the material used for the common layer 114 is sufficiently low and the film thickness is also thin, so in many cases, there is no problem with the common layer 114 being located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same shadow mask, thereby reducing manufacturing costs.

[0467] [Structure Example 2]

[0468] Hereinafter, a display device having a partially different structure from that of the above-described Structure Example 1 will be described. Note that regarding the same parts as those of the above-described Structure Example 1, the above-described Structure Example 1 may be referred to and the description thereof may be omitted.

[0469] Figure 36A The display device 100a is shown in cross section. The main differences between the display device 100a and the display device 100 are: the structure of the light emitting element; and the fact that the former includes a coloring layer.

[0470] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may include two or more light-emitting materials whose luminescent colors are complementary to each other. For example, the organic layer 112W may include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Alternatively, the organic layer 112W may include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0471] Each organic layer 112W is separated between two adjacent light-emitting elements 110W. This prevents leakage current from flowing between adjacent light-emitting elements 110W through the organic layer 112W, thereby suppressing crosstalk caused by this leakage current. Consequently, a display device with high contrast and color reproducibility can be achieved.

[0472] An insulating layer 122 serving as a planarization film is provided over the protective layer 121 , and the colored layer 116R, the colored layer 116G, and the colored layer 116B are provided over the insulating layer 122 .

[0473] An organic resin film or an inorganic insulating film with a flattened top surface can be used as insulating layer 122. Since insulating layer 122 serves as the surface on which colored layers 116R, 116G, and 116B are formed, a flat top surface of insulating layer 122 can make the thickness of colored layers 116R, 116G, and 116B uniform, thereby improving the color purity of light extracted from each light-emitting element. Note that if the thickness of colored layers 116R, 116G, and 116B is non-uniform, the amount of light absorbed varies depending on the region within colored layers 116R, 116G, and 116B, potentially reducing color purity.

[0474] [Structure Example 3]

[0475] Figure 36B A cross section of the display device 100 b is shown.

[0476] The light-emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layers 115R, 115G, and 115B are all light-transmitting and function as optical adjustment layers.

[0477] A microcavity resonator (microcavity) structure can be achieved by using a film that reflects visible light as pixel electrode 111 and a film that is both reflective and transmissive to visible light as common electrode 113. In this case, by adjusting the thicknesses of conductive layers 115R, 115G, and 115B to achieve an optimal optical path length, even when using an organic layer 112 that emits white light, it is possible to extract light of different wavelengths from each of light-emitting elements 110R, 110G, and 110B, thereby enhancing the intensity of light.

[0478] Furthermore, by providing the colored layers 116R, 116G, and 116B on the optical paths of the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, respectively, light with high color purity can be extracted.

[0479] Insulating layer 123 is provided to cover the ends of pixel electrode 111 and conductive layer 115. The ends of insulating layer 123 are preferably tapered. Providing insulating layer 123 improves coverage of organic layer 112W, common electrode 113, and protective layer 121 formed thereon.

[0480] The organic layer 112W and the common electrode 113 are respectively provided as a continuous film in each light emitting element. By adopting this structure, the manufacturing process of the display device can be greatly simplified, so it is preferred.

[0481] Here, the end of the pixel electrode 111 preferably has a substantially vertical shape. This allows a steeply inclined region to be formed on the surface of the insulating layer 123, and a thin region to be formed in a portion of the organic layer 112W covering this region, or allows a portion of the organic layer 112W to be separated. This eliminates the need for photolithographic processing of the organic layer 112W, for example, and suppresses leakage current between adjacent light-emitting elements through the organic layer 112W.

[0482] The above describes the structural examples of the display device.

[0483] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0484] (Implementation 5)

[0485] In this embodiment, an electronic device according to one embodiment of the present invention is described with reference to FIG. 37 to FIG. 39 .

[0486] The electronic device of this embodiment includes a display panel (display device) using a transistor according to one embodiment of the present invention in its display portion. The display device according to one embodiment of the present invention can easily achieve high definition and high resolution, and can also achieve high display quality. Therefore, it can be used in the display portions of various electronic devices.

[0487] Examples of electronic devices include televisions, desktop or notebook personal computers, displays for computers, digital signage, large-scale game consoles such as pinball machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0488] In particular, because the display panel of one embodiment of the present invention can improve clarity, it can be suitably used in electronic devices with smaller display units. Examples of such electronic devices include watch-type and bracelet-type information terminals (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, and glasses-type AR and MR devices.

[0489] The display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (pixel number is 1280×720), FHD (pixel number is 1920×1080), WQHD (pixel number is 2560×1440), WQXGA (pixel number is 2560×1600), 4K (pixel number is 3840×2160), 8K (pixel number is 7680×4320), etc. In particular, it is preferably set to a resolution of 4K, 8K or above. In addition, the pixel density (clarity) in the display panel of one embodiment of the present invention is preferably 100ppi or more, preferably 300ppi or more, more preferably 500ppi or more, further preferably 1000ppi or more, further preferably 2000ppi or more, further preferably 3000ppi or more, further preferably 5000ppi or more, further preferably 7000ppi or more. By using a display panel with either or both high resolution and high definition, the sense of realism and depth can be further enhanced. Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can accommodate various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0490] The electronic device of this embodiment may also include a sensor (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, tilt, vibration, smell or infrared).

[0491] The electronic device of this embodiment can have various functions. For example, it can have the following functions: the function of displaying various information (static images, dynamic images, text images, etc.) on the display unit; the function of using a touch panel; the function of displaying a calendar, date, or time; the function of executing various software (programs); the function of conducting wireless communications; the function of reading programs or data stored in a storage medium; etc.

[0492] use Figures 37A to 37D This section describes an example of a wearable device that can be worn on the head. These wearable devices can display either AR content or VR content, or both. Furthermore, these wearable devices can also display SR or MR content in addition to AR and VR. When an electronic device displays at least one of AR, VR, SR, and MR content, it can enhance the user's sense of immersion.

[0493] Figure 37A The electronic device 700A shown and Figure 37B The electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), a camera unit (not shown), a pair of optical components 753, a frame 757 and a pair of nose pads 758.

[0494] The display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high definition can be realized.

[0495] Both electronic devices 700A and 700B can project the image displayed by display panel 751 onto display area 756 in optical member 753. Because optical member 753 is light-transmissive, the user can see the image displayed in the display area superimposed on the image transmitted through optical member 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0496] The electronic devices 700A and 700B may also be provided with a camera capable of photographing the front as an imaging unit. In addition, by providing an acceleration sensor such as a gyro sensor on the electronic devices 700A and 700B, the user's head direction can be detected and an image corresponding to that direction can be displayed on the display area 756.

[0497] The communication unit includes a wireless communication device through which, for example, a video signal can be supplied. Alternatively, the communication unit may include a connector to which a cable for supplying the video signal and the power supply potential can be connected, instead of or in addition to the wireless communication device.

[0498] Furthermore, electronic devices 700A and 700B are provided with batteries, and can be charged wirelessly or by wire, or both.

[0499] The frame 721 may also be provided with a touch sensor module. The touch sensor module has the function of detecting whether the outer surface of the frame 721 is touched. The touch sensor module can detect user tapping or sliding operations and perform various operations. For example, a tapping operation can temporarily pause or replay a dynamic image, while a sliding operation can fast forward or rewind the image. In addition, by providing a touch sensor module on each of the two frames 721, the operating range can be expanded.

[0500] A variety of touch sensors can be used in the touch sensor module. For example, various touch sensors can be used, such as capacitance, resistive film, infrared, electromagnetic induction, surface acoustic wave, or optical. Capacitive or optical sensors are particularly preferred for use in the touch sensor module.

[0501] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as a light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can use either an inorganic semiconductor or an organic semiconductor, or both.

[0502] Figure 37C The electronic device 800A shown and Figure 37D Each of the electronic devices 800B shown includes a pair of display portions 820 , a housing 821 , a communication portion 822 , a pair of mounting portions 823 , a control portion 824 , a pair of imaging portions 825 , and a pair of lenses 832 .

[0503] The display unit 820 can employ a display panel according to one embodiment of the present invention. This allows for an electronic device capable of displaying extremely high definition, thereby providing a user with a high sense of immersion.

[0504] The display unit 820 is provided at a position inside the housing 821 that can be viewed through the lens 832. In addition, by displaying different images on each of the pair of display units 820, three-dimensional display utilizing parallax can be performed.

[0505] Both electronic device 800A and electronic device 800B can be referred to as VR-compatible electronic devices. A user wearing electronic device 800A or electronic device 800B can view an image displayed on display unit 820 through lens 832 .

[0506] Electronic devices 800A and 800B preferably have a mechanism that allows the left and right positions of lens 832 and display unit 820 to be adjusted so that lens 832 and display unit 820 are positioned optimally according to the position of the user's eyes. Furthermore, they preferably have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.

[0507] The user can use the mounting portion 823 to mount the electronic device 800A or the electronic device 800B on the head. Figure 37C In the embodiment, the mounting portion 823 is shaped like the temples of glasses (e.g., also referred to as temples), but is not limited thereto. As long as the user can fit the mounting portion 823, for example, the mounting portion 823 may have a helmet-type or belt-type shape.

[0508] The camera unit 825 has a function of acquiring external information. The data acquired by the camera unit 825 can be output to the display unit 820. An image sensor can be used in the camera unit 825. Alternatively, multiple cameras can be provided to support various viewing angles such as telephoto and wide-angle.

[0509] Note that while this example includes the imaging unit 825, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of a detection unit. As a detection unit, for example, an image sensor or a distance image sensor such as a LiDAR (Light Detection and Ranging) can be used. By using images acquired by the camera and images acquired by the distance image sensor, more information can be obtained, enabling more precise gesture manipulation.

[0510] Electronic device 800A may also include a vibration mechanism for use as bone conduction headphones. For example, one or more of the display unit 820, housing 821, and mounting unit 823 may include this vibration mechanism. This eliminates the need for separate headphones, earphones, or speakers; simply attaching electronic device 800A allows for the enjoyment of video and audio.

[0511] Electronic devices 800A and 800B may both include input terminals. For example, cables for supplying video signals from a video output device or the like and power for charging batteries provided in the electronic devices may be connected to the input terminals.

[0512] The electronic device of one embodiment of the present invention may also have a function of wirelessly communicating with the earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (such as sound data) from the electronic device through the wireless communication function. For example, Figure 37A The electronic device 700A shown has a function of transmitting information to the headset 750 through a wireless communication function. In addition, for example Figure 37C The electronic device 800A shown has a function of transmitting information to the headset 750 through a wireless communication function.

[0513] Furthermore, the electronic device may include an earphone unit. Figure 37B The electronic device 700B shown includes an earphone unit 727. For example, a wired connection between the earphone unit 727 and the control unit may be employed. A portion of the wire connecting the earphone unit 727 and the control unit may also be disposed within the housing 721 or the mounting portion 723.

[0514] same, Figure 37D The electronic device 800B shown includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected by wire can be employed. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed within the housing 821 or the mounting portion 823. Alternatively, the earphone unit 827 and the mounting portion 823 can include magnets. This allows the earphone unit 827 to be secured to the mounting portion 823 by magnetic force, making storage easier and therefore preferred.

[0515] The electronic device may also include a sound output terminal that can be connected to earphones or headphones. Furthermore, the electronic device may include one or both of a sound input terminal and a sound input mechanism. For example, a microphone or other sound receiving device may be used as the sound input mechanism. By incorporating a sound input mechanism into the electronic device, the electronic device can be given the functionality of a so-called headset.

[0516] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type (electronic devices 700A and 700B, etc.) and goggles-type (electronic devices 800A and 800B, etc.) are preferable.

[0517] Figure 38A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0518] Electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Display portion 6502 has a touch panel function. Control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for display portion 6502 and control device 6509. Using a semiconductor device according to one embodiment of the present invention in control device 6509 is preferred because it can reduce power consumption.

[0519] The display portion 6502 can use the display panel of one embodiment of the present invention.

[0520] Figure 38B 65 is a cross-section including the end portion of the housing 6501 on the microphone 6506 side.

[0521] A light-transmitting protective member 6510 is provided on the display surface side of the frame 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in the space surrounded by the frame 6501 and the protective member 6510.

[0522] The display panel 6511 , the optical member 6512 , and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0523] In a region outside the display portion 6502, a portion of the display panel 6511 is folded, and an FPC 6515 is connected to the folded region. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on a printed circuit board 6517.

[0524] The display panel 6511 can use a flexible display according to one embodiment of the present invention. This allows for an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while reducing the thickness of the electronic device. Furthermore, by folding a portion of the display panel 6511 to provide a connection to the FPC 6515 on the back side of the pixel unit, an electronic device with a narrow frame can be realized.

[0525] Figure 38C An example of a television set is shown. In a television set 7100, a display portion 7000 is incorporated into a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0526] The operation can be performed by using the operation switch provided by the frame 7101 and the remote control unit 7111 provided separately. Figure 38C Alternatively, the display unit 7000 may be provided with a touch sensor, and the television unit 7100 may be operated by touching the display unit 7000 with a finger or the like. Furthermore, the remote control unit 7111 may be provided with a display unit that displays data output from the remote control unit 7111. Using the operation keys or touch panel provided on the remote control unit 7111, the channel and volume can be controlled, and the image displayed on the display unit 7000 can be manipulated.

[0527] The television set 7100 also includes a receiver and a modem. The receiver can receive standard television broadcasts. Furthermore, the modem can be connected to a wired or wireless communication network to enable one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers) information communication.

[0528] Figure 38D An example of a notebook personal computer is shown. Notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and a control device 7216. Display unit 7000 is incorporated into housing 7211. Control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for display unit 7000 and control device 7216. Using a semiconductor device according to one embodiment of the present invention for control device 7216 is preferred because it can reduce power consumption.

[0529] Figure 38E and Figure 38F An example of digital signage is shown.

[0530] Figure 38E The digital signage 7300 shown includes a housing 7301, a display portion 7000, a speaker 7303, etc. In addition, it may include an LED light, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0531] Figure 38F The digital signage 7400 is shown installed on a cylindrical pillar 7401. The digital signage 7400 includes a display unit 7000 installed along the curved surface of the pillar 7401.

[0532] The larger the display unit 7000 is, the more information it can provide at one time. The larger the display unit 7000 is, the easier it is to attract people's attention, for example, it can improve the effectiveness of advertising.

[0533] The use of a touch panel in the display unit 7000 is preferred because it allows not only still images or moving images to be displayed on the display unit 7000 but also intuitive operation by the user. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0534] like Figure 38E and 38F As shown, digital signage 7300 or digital signage 7400 can preferably be linked to information terminal device 7311 or information terminal device 7411, such as a smartphone, carried by the user via wireless communication. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. In addition, the display of display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0535] Furthermore, the game can be played on the digital signage 7300 or 7400 using the screen of the information terminal device 7311 or 7411 as an operation unit (controller). This allows an unspecified number of users to participate in the game and enjoy the game at the same time.

[0536] exist Figures 38C to 38F In the embodiment of the present invention, the display panel can be used for the display portion 7000 .

[0537] Figures 39A to 39G The electronic device shown includes a frame 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0538] Figures 39A to 39GThe electronic device shown has various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of performing wireless communication; a function of reading out programs or data stored in a storage medium and processing them; etc. Note that the functions of an electronic device are not limited to the functions described above, but may have various functions. An electronic device may include multiple display units. In addition, for example, a camera may be provided in an electronic device so that it has the following functions: a function of capturing static images or dynamic images and storing the captured images in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the captured images on a display unit; etc.

[0539] Below, we will explain in detail Figures 39A to 39G Electronic devices shown.

[0540] Figure 39A : is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smartphone, for example. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc. can also be provided in the portable information terminal 9101. In addition, as the portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 39A 9050 is shown as an example. Information 9051, indicated by a dotted rectangle, can also be displayed on another surface of display portion 9001. Examples of information 9051 include information notifying of the receipt of an email, social media, or phone call; the title of the email or social media; the name of the sender of the email or social media; the date; the time; the remaining battery level; and the radio frequency strength. Alternatively, icon 9050 can be displayed in the location where information 9051 is displayed.

[0541] Figure 39B This is a perspective view of a portable information terminal 9102. Portable information terminal 9102 has the function of displaying information on three or more surfaces of display unit 9001. Here, an example is shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when portable information terminal 9102 is placed in a jacket pocket, the user can check information 9053 displayed in a position visible from above portable information terminal 9102. This allows the user to check this display without removing portable information terminal 9102 from their pocket, allowing them to decide whether to answer a call.

[0542] Figure 39CThis is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can run various application software, such as mobile phone use, reading and editing emails and articles, playing music, network communications, and computer games. The tablet terminal 9103 includes a display portion 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of a housing 9000. It also includes operation keys 9005 serving as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0543] Figure 39D is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display portion 9001 is curved, and a display can be displayed along the curved display surface. Furthermore, the portable information terminal 9200 can communicate with a headset capable of wireless communication, for example, to enable hands-free calls. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data to other information terminals or be charged. Charging can also be performed by wireless power supply.

[0544] Figures 39E to 39G 1 is a perspective view showing a foldable portable information terminal 9201. Figure 39E This is a perspective view of the portable information terminal 9201 in an unfolded state. Figure 39G This is a three-dimensional diagram of the folded state. Figure 39F It is from Figure 39E Status and Figure 39G A perspective view of a state midway between transitioning from one state to another. The portable information terminal 9201 offers excellent portability when folded, while its large, seamless display area in the unfolded state provides enhanced viewing convenience. The display portion 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display portion 9001 can be bent, for example, within a range of a curvature radius of 0.1 mm to 150 mm.

[0545] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0546] (Implementation 6)

[0547] This embodiment describes an example application of a semiconductor device according to one embodiment of the present invention. For example, a semiconductor device according to one embodiment of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using a semiconductor device according to one embodiment of the present invention are very effective in achieving high performance, such as low power consumption.

[0548] For example, an electronic component using the semiconductor device of one embodiment of the present invention can be used in the electronic device described in Embodiment 5.

[0549] [Electronic components]

[0550] Figure 40A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Figure 40A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Figure 40A 700 is partially omitted to illustrate its interior. Electronic component 700 includes lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, which are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. By combining multiple electronic components and electrically connecting them on printed circuit board 702, a circuit board 704 is completed.

[0551] In addition, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driver circuit layer 715 and the memory layer 716 are stacked can be a monolithic stacked structure. In a monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driver circuit layer 715 and the memory layer 716 are stacked in a monolithic manner, a so-called on-chip memory structure can be realized, for example, in which a memory is directly formed on a processor. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0552] Furthermore, the use of an on-chip memory structure allows for smaller interconnect wiring, compared to technologies using through-hole electrodes such as TSVs, thereby increasing the number of pins. This increase in pins allows for parallel operation, thereby increasing the memory bandwidth.

[0553] In addition, it is preferable to use OS transistors to form multiple memory cell arrays in the memory layer 716, and stack the multiple memory cell arrays in a monolithic manner. By making the multiple memory cell arrays have a monolithic stacking structure, one or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is more difficult to achieve a monolithic stacking structure compared to OS transistors. Therefore, in a structure stacked in a monolithic manner, OS transistors are superior to Si transistors.

[0554] In addition, the semiconductor device 710 may be referred to as a bare die. In this specification, etc., a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular pieces. Examples of semiconductor materials that can be used for bare chips include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon chip.

[0555] then, Figure 40B A perspective view of an electronic component 730 is shown. Electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board). A semiconductor device 735 and a plurality of semiconductor devices 710 are provided on interposer 731.

[0556] Electronic component 730 illustrates an example of using semiconductor device 710 as a high bandwidth memory (HBM). Alternatively, semiconductor device 735 can be used in integrated circuits such as a CPU (CPU), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0557] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, and the interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0558] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon interposer is used, TSV can also be used as a through electrode.

[0559] To achieve a wide memory bandwidth in HBM, numerous wiring connections are required. Therefore, the interposer on which HBM is mounted must be able to form fine wiring at a high density. Therefore, a silicon interposer is preferred for HBM mounting.

[0560] Furthermore, in SiPs and MCMs using silicon interposers, reliability degradation due to differences in thermal expansion coefficients between the integrated circuit and the interposer is less likely to occur. Furthermore, due to the high surface flatness of the silicon interposer, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly suitable for 2.5D packaging (2.5D assembly), in which multiple integrated circuits are arranged horizontally on the interposer.

[0561] On the other hand, when using silicon interposers and TSVs to electrically connect multiple integrated circuits with different terminal pitches, space is required, such as the width of the terminal pitch. Therefore, when reducing the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it is sometimes difficult to provide the large amount of wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can be used.

[0562] Alternatively, a heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 uniform.

[0563] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Figure 40BThe example of electrodes 733 formed using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 can be formed using conductive pins. Arranging conductive pins in a matrix on the bottom of the package substrate 732 enables PGA (Pin Grid Array) mounting.

[0564] The electronic component 730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded Package), and QFN (Quad Flat Non-leaded Package).

[0565] [Mainframe computer]

[0566] then, Figure 41A 1 is a perspective view of a mainframe computer 5600. In the mainframe computer 5600, a plurality of rack-mount computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0567] Figure 41B A perspective view shows an example of a computer 5620. Computer 5620 includes a motherboard 5630. Motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into slots 5631. Personal computer card 5621 also includes connection terminals 5623, 5624, and 5625, which are connected to motherboard 5630.

[0568] Figure 41C An example of a personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, a GPU, and a storage device. The personal computer card 5621 includes a board 5622, and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Figure 41C Components other than the electronic component 5626, the electronic component 5627, and the electronic component 5628 are shown.

[0569] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. An example of the standard of the connection terminal 5629 is PCIe.

[0570] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the PC card 5621 and inputting signals. Furthermore, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when video signals are output from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0571] The electronic component 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) included in the board 5622 , the electronic component 5626 and the board 5622 can be electrically connected.

[0572] Electronic components 5627 and 5628 include multiple terminals, and can be mounted by, for example, soldering these terminals to wiring included in board 5622 using reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 5627 can be electronic component 730. For example, electronic component 5628 can be a storage device. For example, electronic component 700 can be electronic component 5628.

[0573] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0574] [Space Equipment]

[0575] The semiconductor device according to one embodiment of the present invention can be applied to space equipment.

[0576] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor due to exposure to radiation vary little. In other words, the OS transistor has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space. Specifically, an OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron radiation. Note that outer space, for example, refers to an altitude of 100 km or more, but the outer space shown in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0577] exist Figure 42A , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Figure 42A An example of a planet 6804 in outer space is shown.

[0578] In addition, although Figure 42A Although not shown, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the battery management system or the battery control circuit, power consumption is low and high reliability is achieved even in outer space, which is preferable.

[0579] Furthermore, outer space is an environment with a radiation dose over 100 times greater than that on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and muon rays.

[0580] When sunlight hits the solar panels 6802, they generate the electricity necessary to operate the satellite 6800. However, if sunlight does not reach the solar panels, or if the amount of sunlight hitting the solar panels is low, the amount of electricity generated decreases. Consequently, there is a possibility that the required electricity for satellite 6800 will not be generated. To enable satellite 6800 to operate even when the generated electricity is low, satellite 6800 is preferably equipped with a secondary battery 6805. Solar panels are sometimes referred to as solar cell modules.

[0581] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver receiving the signal can be measured. Thus, satellite 6800 can form a satellite positioning system.

[0582] Furthermore, control device 6807 has the function of controlling artificial satellite 6800. Control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Furthermore, a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used as control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to exposure to radiation. Therefore, OS transistors are highly reliable and can be suitably used even in environments where radiation is likely to enter.

[0583] Additionally, artificial satellite 6800 may include sensors. For example, by including a visible light sensor, artificial satellite 6800 may be capable of detecting sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, artificial satellite 6800 may be capable of detecting thermal infrared radiation emitted from the Earth's surface. Thus, artificial satellite 6800 may be used, for example, as an Earth observation satellite.

[0584] Note that in this embodiment, an artificial satellite is described as an example of space equipment, but the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0585] As described above, OS transistors have superior effects compared to Si transistors, such as achieving a wider memory bandwidth and having high radiation resistance.

[0586] [Data Center]

[0587] For example, a semiconductor device according to one embodiment of the present invention can be applied to storage systems used in data centers. Data centers are required to manage data over the long term, ensuring data immutability. This long-term data management requires large-scale facilities, such as storage and servers to store large amounts of data, ensuring a stable power supply to maintain data, and ensuring the cooling equipment required for data storage.

[0588] By using a semiconductor device according to one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required to retain data and miniaturize the semiconductor device that retains data. Consequently, it is possible to miniaturize the storage system, the power supply required to retain data, and the cooling equipment required. This can save space in the data center.

[0589] Furthermore, the semiconductor device according to one embodiment of the present invention consumes low power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, the use of the semiconductor device according to one embodiment of the present invention enables the realization of a data center that can operate stably even in high-temperature environments. Consequently, the reliability of the data center can be improved.

[0590] Figure 42B A storage system that may be used in a data center is shown. Figure 42B The storage system 6000 shown includes a plurality of servers 6001sb as hosts 6001 and a plurality of storage devices 6003md as storage 6003. The hosts 6001 and storage 6003 are connected via a storage area network 6004 and a storage control circuit 6002.

[0591] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0592] In the storage 6003, the use of flash memory shortens the data access speed, that is, shortens the time required to store and output data. However, this time is much longer than the time required by DRAM, which can be used as a cache memory in the storage. In order to solve the problem of the long access speed of the storage 6003, a cache memory is generally provided in the storage to shorten the time required to store and output data.

[0593] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003 and then output to the host 6001 or the storage 6003.

[0594] When OS transistors are used as transistors for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0595] Note that by using a semiconductor device according to one embodiment of the present invention in any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, it is currently believed that as energy requirements increase with the performance and integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can also reduce greenhouse gas emissions such as carbon dioxide (CO2). In addition, the semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure to combat global warming.

[0596] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0597] [Explanation of symbols]

[0598] 10A: Transistor, 10: Transistor, 11: Insulating layer, 12: Conductive layer, 20a: Opening, 20b: Opening, 20: Opening, 21f: Semiconductor film, 21i: Channel formation region, 21n: Low resistance region, 21: Semiconductor layer, 22f: Insulating film, 22: Insulating layer, 23f: Conductive film, 23: Conductive layer, 26: Opening, 27: Conductive layer, 28: Insulating layer, 29: Opening, 30: Memory cell, 31: Conductive layer, 32: Conductive layer, 33: Conductive layer, 34: Conductive layer, 35: Conductive layer, 36: Conductive layer, 37: Conductive layer, 38: Conductive layer, 39: Conductive layer, 41a: Insulating layer, 41b: Insulating layer, 41c: Insulating layer, 41: Layer, 42: Insulating layer, 43: Insulating layer, 44: Insulating layer, 45: Insulating layer, 46: Insulating layer, 47: Insulating layer, 48: Insulating layer, 49: Insulating layer, 50: Capacitor, 51: Conductive layer, 52: Conductive layer, 53: Insulating layer, 54a: Opening, 54b: Opening, 54: Opening, 55: Insulating layer, 60: Memory cell, 61: Conductive layer, 62: Conductive layer, 63: Conductive layer, 65: Insulating layer, 70: Layer, 90: Transistor, 91: Substrate, 92: Semiconductor region, 93: Insulating layer, 94: Conductive layer, 95a: Low resistance region, 95b: Low resistance region, 100a: Display device, 100b: Display device, 100: Display device, 101: Substrate , 110: light-emitting element, 111: pixel electrode, 112: organic layer, 113: common electrode, 114: common layer, 115: conductive layer, 116B: coloring layer, 116G: coloring layer, 116R: coloring layer, 121: protective layer, 122: insulating layer, 123: insulating layer, 125: insulating layer, 126: resin layer, 128: layer, 140: connecting portion, 170: substrate, 171: adhesive layer, 200A: display device, 200B: display device, 200C: display device, 240: capacitor, 241: conductive layer, 243: insulating layer, 245: conductive layer, 251: conductive layer, 252: conductive layer, 254: insulating layer, 255a: insulating layer, 255b: Insulating layer, 255c: Insulating layer, 256: Plug, 261: Insulating layer, 262: Insulating layer, 263: Insulating layer, 266: Insulating layer, 271: Plug, 274a: Conductive layer, 274b: Conductive layer, 274: Plug, 280: Display module, 281: Display unit, 282: Circuit unit, 283a: Pixel circuit, 283: Pixel circuit unit, 284a: Pixel, 284: Pixel unit, 285: Terminal unit, 286: Wiring unit, 290: FPC, 291: Substrate, 292: Substrate, 301: Substrate, 310: Transistor, 311: Conductive layer, 312: Low resistance region, 313: Insulating layer, 314: Insulating layer, 315: Element isolation layer, 331: Substrate,332: Insulating layer, 350: Insulating layer, 351: Semiconductor layer, 352: Insulating layer, 353: Insulating layer, 354: Conductive layer, 355: Conductive layer, 356: Insulating layer, 357: Conductive layer, 358: Insulating layer, 359: Insulating layer, 361: Insulating layer, 362: Insulating layer, 371: Conductive layer, 374a: Conductive layer, 374b: Conductive layer, 374: Plug, 420: Layer, 422: Peripheral circuit, 430: Element layer, 432: Memory cell, 437: Transistor, 438: Capacitor, 440: Driver circuit, 442: Row decoder, 443: Row driver, 444: Column decoder, 445: Column driver, 446: Sense amplifier, 447: Input circuit 448: Output circuit, 470: Layer, 471: PSW, 472: PSW, 473: Control circuit, 474: Voltage generation circuit, 480: Storage device, 482_1: Transistor, 482_2: Transistor, 482: Switch circuit, 483_1: Transistor, 483_2: Transistor, 483_3: Transistor, 483: Precharge circuit, 484_1: Transistor, 484_2: Transistor, 484_3: Transistor, 484: Precharge circuit, 485_1: Transistor, 485_2: Transistor, 485_3: Transistor, 485_4: Transistor, 485: Amplifier circuit, 520: Insulation layer, 522: Insulation layer, 524: Insulation layer, 526: Insulating layer, 528: Conductive layer, 530: Conductive layer, 550: Insulating layer, 582: Insulating layer, 584: Insulating layer, 586: Conductive layer, 700A: Electronic device, 700B: Electronic device, 700: Electronic component, 702: Printed circuit board, 704: Circuit board, 710: Semiconductor device, 711: Mold, 712: Connecting pad, 713: Electrode pad, 714: Lead, 715: Driving circuit layer, 716: Storage layer, 721: Frame, 723: Mounting portion, 727: Headphone portion, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 750: Headphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display unit, 821: Frame, 822: Communication unit, 823: Mounting unit, 824: Control unit, 825: Camera unit, 827: Headphone unit, 832: Lens, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: Personal computer card, 5622: Board, 5623: Connecting terminal, 5624: Connecting terminal, 5625: Connecting terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connecting terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system,6001sb: Server, 6001: Host, 6002: Storage control circuit, 6003md: Storage device, 6003: Storage, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 6800: Satellite, 6801: Main body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Display unit, 7100: Television set, 7101: Frame, 7103: Bracket, 71 11: Remote control unit, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control device, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal device, 7400: Digital signage, 7401: Pillar, 7411: Information terminal device, 9000: Housing, 9001: Display unit, 900 2: Camera, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

1. A semiconductor device, comprising: a transistor; a first insulating layer; a second insulating layer; a third insulating layer; and a wiring, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a fourth insulating layer, the first insulating layer is disposed on the first conductive layer, the second conductive layer is disposed on the first insulating layer, the second insulating layer is disposed on the second conductive layer, the first insulating layer, the second conductive layer, and the second insulating layer include a first opening reaching the first conductive layer, the semiconductor layer is located inside the first opening and has a region in contact with the first conductive layer and a region in contact with the second conductive layer, the fourth insulating layer is disposed between the semiconductor layer inside the first opening and the third conductive layer, the third conductive layer is disposed so as to fill the first opening, the third insulating layer is disposed on the second insulating layer, the semiconductor layer, the fourth insulating layer, and the third conductive layer and includes a second opening reaching the third conductive layer, and the wiring has a region in contact with the third conductive layer inside the second opening and has a region overlapping with the semiconductor layer with the third insulating layer interposed therebetween.

2. A semiconductor device, comprising: a transistor; a first insulating layer; a second insulating layer; a third insulating layer; and a wiring, wherein the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a fourth insulating layer, the first insulating layer is disposed on the first conductive layer, the second conductive layer is disposed on the first insulating layer, the first insulating layer and the second conductive layer include a first opening reaching the first conductive layer, the second insulating layer is disposed on the second conductive layer, the second insulating layer includes a second opening reaching the second conductive layer and having a region overlapping with the first opening, the semiconductor layer is located inside the first opening and inside the second opening and has a region in contact with the first conductive layer and a region in contact with the second conductive layer, the fourth insulating layer is disposed between the semiconductor layer inside the first opening and inside the second opening and the third conductive layer, the third conductive layer is disposed so as to fill the first opening and the second opening, the third insulating layer is disposed on the second insulating layer, the semiconductor layer, the fourth insulating layer, and the third conductive layer and includes a third opening reaching the third conductive layer, and the wiring has a region in contact with the third conductive layer inside the third opening and has a region overlapping with the semiconductor layer with the third insulating layer interposed therebetween.

3. The semiconductor device according to claim 2, wherein the semiconductor layer has a region in contact with the top surface of the second conductive layer.

4. The semiconductor device according to any one of claims 1 to 3, The height of the top surface of the second insulating layer, the height of the top surface of the semiconductor layer, the height of the top surface of the fourth insulating layer, and the height of the top surface of the third conductive layer are the same as or substantially the same as each other.

5. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer contains a metal oxide.

6. The semiconductor device according to claim 5, wherein the metal oxide contains two or three selected from In, element M, and Zn, and the element M is one or more selected from Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.

7. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first insulating layer; Forming a first conductive layer on the first insulating layer; Forming a second insulating layer on the first conductive layer; Forming a first opening in the second insulating layer, the first conductive layer, and the first insulating layer; Forming a semiconductor layer having a region in contact with the first conductive layer inside the first opening, a third insulating layer on the semiconductor layer, and a second conductive layer on the third insulating layer; Forming a fourth insulating layer on the second insulating layer, the semiconductor layer, the third insulating layer, and the second conductive layer; Forming a second opening in the fourth insulating layer reaching the second conductive layer; and Forming a wiring in such a manner as to have a region in contact with the second conductive layer inside the second opening and a region overlapping the semiconductor layer with the fourth insulating layer interposed therebetween.

8. The method for manufacturing a semiconductor device according to claim 7, wherein after forming the first opening, a semiconductor film, an insulating film on the semiconductor film, and a conductive film on the insulating film are formed in such a manner as to have a region located inside the first opening and a region overlapping the second insulating layer, and the top surface of the second insulating layer is exposed by performing a planarization process on the conductive film, the insulating film, and the semiconductor film to form the semiconductor layer, the third insulating layer, and the second conductive layer.

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