Gate drive circuit and display device

Abstract

The application discloses a gate driving circuit and a display device. The gate driving circuit comprises a plurality of driving units connected in cascade, each of the driving units comprising: an input module connected to a first node, configured to adjust a voltage of the first node according to an input signal; an output module connected to the first node, configured to provide a current-stage driving signal according to a first clock signal and the voltage of the first node; a control module connected between the first node and a second node, configured to adjust a voltage of the second node according to the voltage of the first node; a stabilizing module configured to maintain the first node and the current-stage driving signal at a gate cut-off voltage when the second node is at an effective level; and a compensation module connected to the second node, configured to maintain the effective level of the second node according to an effective control signal, wherein the control signal represents an operating temperature of the gate driving circuit. On the basis of ensuring display quality, the gate driving circuit provided by the application has a larger operating temperature range.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] With the rapid development of display technology, display devices are widely used in various electronic devices, ranging from everyday mobile phones and tablets to professional industrial control equipment and automotive display systems.

[0003] The diverse operating environments place higher demands on the applicable temperature range of display devices. In particular, the gate drive circuit inside the display device is extremely susceptible to high temperatures. At high temperatures, the capacitive and inductive coupling effects within the circuit are aggravated, interfering with the scanning signal provided by the gate drive circuit to the display panel, which in turn leads to horizontal lines on the display and seriously affects the display quality and reliability of the display device. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a gate driving circuit and display device that can effectively improve the applicable temperature range while ensuring display quality.

[0005] According to one aspect of this application, a gate driving circuit is provided, comprising a plurality of cascaded driving units, wherein each driving unit comprises: an input module connected to a first node, configured to adjust the voltage of the first node according to an input signal; an output module connected to the first node, configured to provide a driving signal for this stage according to a first clock signal and the voltage of the first node; a control module connected between the first node and a second node, configured to adjust the voltage of the second node according to the voltage of the first node; a stabilization module, configured to maintain the first node and the driving signal for this stage at a gate cutoff voltage when the second node is at an active level; and a compensation module connected to the second node, configured to maintain an active level of the second node according to an active control signal, wherein the control signal characterizes the operating temperature of the gate driving circuit.

[0006] Optionally, the gate drive circuit further includes a control signal generation unit, used to provide the control signal according to the gate cutoff voltage or the gate turn-on voltage.

[0007] Optionally, the compensation module includes: a ninth transistor, a first terminal connected to a third power supply terminal, a second terminal connected to the second node, and a control terminal receiving a first control signal. The control signal generation unit obtains the first control signal based on the gate cutoff voltage when the operating temperature is less than a first preset temperature, and obtains the first control signal based on the gate turn-on voltage when the operating temperature is greater than or equal to the first preset temperature.

[0008] Optionally, the compensation module further includes: a tenth transistor, with a first terminal connected to the second node, a control terminal connected to the second terminal and receiving a second control signal; the control signal generation unit obtains the second control signal based on the gate cutoff voltage when the operating temperature is less than the second preset temperature, and obtains the second control signal based on the gate turn-on voltage when the operating temperature is greater than or equal to the second preset temperature.

[0009] Optionally, the first preset temperature is lower than the second preset temperature.

[0010] Optionally, the input module includes: a first transistor, with a first terminal connected to a first power supply terminal and a second terminal connected to the first node, and a control terminal receiving a preceding stage drive signal; and a second transistor, with a first terminal connected to the first node, a control terminal receiving a subsequent stage drive signal, and a second terminal connected to a second power supply terminal; the output module includes: a third transistor, with a control terminal connected to the first node, a first terminal receiving the first clock signal, and a second terminal providing the current stage drive signal; and a capacitor connected between the control terminal and the second terminal of the third transistor.

[0011] Optionally, the control module includes: a fourth transistor, with its control terminal and a first terminal connected to a third power supply terminal, and a second terminal connected to the second node; and a fifth transistor, with its control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the second power supply terminal; the stabilization module includes: a sixth transistor, with its control terminal connected to the second node, a first terminal connected to the first node, and a second terminal connected to the second power supply terminal; and a seventh transistor, with its control terminal connected to the second node, a first terminal connected to the output terminal of the output module, and a second terminal connected to the second power supply terminal.

[0012] Optionally, the gate drive circuit further includes: an eighth transistor, whose control terminal receives a second clock signal, whose first terminal is connected to the output terminal of the output module, and whose second terminal is connected to the second power supply terminal.

[0013] According to another aspect of this application, a display device is provided, comprising: a gate driving circuit as described in any of the preceding claims; and a power management circuit for providing the gate cutoff voltage, the gate turn-on voltage, and a first supply voltage according to the input voltage of the display device.

[0014] Optionally, the display device further includes a temperature detection circuit for acquiring the operating temperature of the gate driving circuit.

[0015] According to the gate driving circuit and display device provided in this application, compensation is provided to the second node through the compensation module at high temperatures to stabilize the potential of the second node and prevent the scanning signal provided by the gate driving circuit from changing due to the potential fluctuation of the second node. Therefore, the gate driving circuit provided in this application can provide a stable scanning signal even at high temperatures, solving the problem of horizontal lines in the display at high temperatures, improving display quality, and enabling the display device to have a wider operating temperature range.

[0016] Furthermore, by multiplexing the gate cutoff voltage and gate turn-on voltage to provide control signals to the compensation module, the second node is not affected at low temperatures, while compensation can be performed on the second node at high temperatures, thus enhancing the temperature adaptability of the gate drive circuit. Simultaneously, due to signal multiplexing, control of the compensation module can be achieved without the need for additional level shifting circuitry, saving production costs and circuit layout area. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 This application shows a schematic structural diagram of a display device according to an embodiment of the present application;

[0019] Figure 2 This diagram illustrates a schematic structure of a single driving unit in the gate driving circuit of an embodiment of this application.

[0020] Figure 3 This diagram illustrates a schematic structural diagram of the control signal generation unit in the gate drive circuit of an embodiment of this application.

[0021] Figure 4 A schematic circuit diagram of a single drive unit is shown in some embodiments of this application;

[0022] Figure 5 Show Figure 4 A schematic diagram of the working waveforms of the drive circuit.

[0023] Figure 6 Show Figure 4 A schematic waveform diagram of the first control signal;

[0024] Figure 7 Schematic circuit diagrams of a single drive unit are shown in some embodiments of this application;

[0025] Figure 8 Show Figure 7 A schematic waveform diagram of the first and second control signals. Detailed Implementation

[0026] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0027] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0028] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0029] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0030] This application provides a display device, taking a liquid crystal display panel as an example. Figure 1 A schematic structural block diagram of a display device according to an embodiment of this application is shown. Figure 1 As shown, the display device 1 includes a display panel, a gate driving circuit 100, a source driving circuit 200, a timing control circuit 300, and a power management circuit 400.

[0031] The display panel includes pixel units arranged in an array for displaying images. Each pixel unit includes a thin-film transistor T and a pixel capacitor (not shown) formed between a pixel electrode and a common electrode. Each pixel unit is connected to a source drive circuit 200 via a corresponding data line S to receive data signals, and to a gate drive circuit 100 via a corresponding scan line G to receive scan signals. When the thin-film transistor T is turned on by the scan signal, the display is performed according to the data signal. Figure 1 In the example, the display panel includes i×j pixel units, and correspondingly, data lines S1~Sj and scan lines G1~Gi are shown, where i and j are positive integers.

[0032] The timing control circuit 300 provides display data Data and source control signal Cd to the source drive circuit 200 based on the received image data IMG and timing control signal Cont, and provides gate control signal Cg to the gate drive circuit 100. The timing control signal Cont should be understood as a type of signal, such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK.

[0033] The source drive circuit 200 converts the display data Data into corresponding data signals according to the source control signal Cd and provides them to the corresponding pixel units via each data line S.

[0034] The power management circuit 400 provides a gate turn-on voltage VGH, a gate turn-off voltage VGL, and a first voltage AVDD based on the power supply voltage of the display device 1. The gate turn-on voltage VGH is the voltage that enables the thin-film transistor T to turn on, the gate turn-off voltage VGL is the voltage that enables the thin-film transistor T to turn off, and the first voltage AVDD can be a positive voltage between VGH and VGL, for example, VGH is 18V, VGL is -7V, and AVDD is 5.5V.

[0035] Furthermore, such as Figure 1 As shown, the gate drive circuit 100 of this embodiment includes a plurality of cascaded drive units 110. Figure 1In this example, 110-1 to 110-n are used. Each driving unit 110 converts the gate enable voltage VGH, gate cutoff voltage VGL, and first voltage AVDD into a scan signal according to the corresponding gate control signal Cg, and provides it to the corresponding pixel unit via the scan line G connected to the driving unit 110. When the driving unit 110 provides the gate enable voltage VGH via the scan line G, the thin-film transistor T connected to the scan line G is turned on, thereby enabling the corresponding pixel unit to display according to the data signal provided by the source driving circuit 200; when the driving unit 110 provides the gate cutoff voltage VGL via the scan line G, the thin-film transistor T connected to the scan line G is turned off.

[0036] It should be noted that the source control signal Cd, the gate control signal Cg, and the gate control signal Vgc should also be understood as a collective term for a class of signals rather than a single signal. For example, the gate control signal Cg usually includes at least one gate start pulse signal and multiple clock signals.

[0037] Accordingly, such as Figure 1 As shown, the gate drive circuit 100 further includes a control signal generation unit 120 for providing a control signal TC to the compensation module. In a preferred embodiment, the control signal generation unit 120 includes, for example, a temperature control switch, thereby selecting either the gate cutoff voltage VGL or the gate turn-on voltage VGH to provide the aforementioned control signal based on the operating temperature of the gate drive circuit 100, which helps to save costs.

[0038] Figure 2 This diagram illustrates a schematic structure of a single driving unit in the gate driving circuit of an embodiment of this application. Figure 2 As shown, the gate driving circuit 100 of this application embodiment includes a plurality of cascaded driving units 110. Each stage driving unit 110 can be connected to a row of pixel units on the display panel through a corresponding scan line G, thereby applying the scan signal, that is, the driving signal output by the stage driving unit 110, to these pixel units to control the turning on or off of the thin film transistor T.

[0039] In this embodiment, the driving unit 110 includes a driving circuit and a compensation module 115.

[0040] The driver circuit provides the drive signal Gn for this stage. (Reference) Figure 2 The driving circuit may include an input module 111, an output module 112, a control module 113, and a stabilization module 114. In some embodiments, the driving circuit may further include a reset module 116. More specifically, refer to... Figure 2Input module 111 is connected to the first node Q and is used to adjust the voltage of the first node Q according to the input signal. Output module 112 is connected to the first node Q and is used to provide the current stage drive signal Gn according to the first clock signal and the voltage of the first node Q. Control module 113 is connected between the first node Q and the second node QB and is used to adjust the voltage of the second node QB according to the voltage of the first node Q. Stabilization module 114 is connected to the second node QB and the output terminal of output module 112 and is used to maintain the first node Q and the current stage drive signal Gn at the gate cutoff voltage VGL when the second node QB is at an active level. Reset module 116 is connected to the output terminal of output module 112 and is used to reset the current stage drive signal Gn according to the active second clock signal.

[0041] The compensation module 115 is connected to the drive circuit, specifically to the second node QB, and is used to maintain the effective level of the second node according to the effective control signal TC. The control signal TC represents the operating temperature of the gate drive circuit 100. More specifically, the control signal TC has an effective level when the operating temperature is greater than or equal to a preset temperature.

[0042] Figure 3 This diagram illustrates a schematic structural diagram of the control signal generation unit in the gate drive circuit of an embodiment of this application; as shown... Figure 3 As shown, the gate drive circuit 100 further includes a control signal generation unit 120. The control signal generation unit 120 is used to provide a control signal TC according to the operating temperature of the gate drive circuit 100. In some embodiments, such as... Figure 3 As shown, the control signal generation unit 120 may include a temperature control switch, and the conduction of the temperature control switch is controlled by the operating temperature T, thereby multiplexing the gate turn-on voltage VGH or the gate turn-off voltage VGL into a control signal TC.

[0043] It should be noted that, in the embodiments of this application, the driving circuit can be implemented with reference to any related technology. To facilitate understanding of the driving unit provided in this application, an 8T1C driving circuit is used as an example below, that is, a driving circuit comprising 8 transistors and 1 capacitor is used as an example to describe the driving unit 110 provided in this application in detail. These transistors are, for example, thin-film transistors, each including a first terminal, a second terminal, and a control terminal. Each thin-film transistor is turned on or off according to the voltage of the control terminal, and when turned on, current flows from the terminal with the higher potential to the terminal with the lower potential.

[0044] Figure 4 Schematic circuit diagrams of a single drive unit are shown in some embodiments of this application. Reference Figure 4In some embodiments of the driving unit 110a, for the nth stage driving unit, the input module 111 is connected to the first node Q and is used to adjust the voltage of the first node Q according to the input signal. In the example, the input module 111 includes a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 is connected to a first power supply terminal, the second terminal is connected to the first node Q, and the control terminal receives the preceding stage driving signal, such as the driving signal Gn-4 provided for a driving unit four stages ahead. The first terminal of the second transistor T2 is connected to the first node Q, the second terminal is connected to a second power supply terminal, and the control terminal receives the following stage driving signal, such as the driving signal Gn+4 provided for a driving unit four stages behind.

[0045] In such Figure 4 In the example shown, the first power supply terminal provides the gate turn-on voltage VGH, and the second power supply terminal provides the gate turn-off voltage VGL. That is, in the example shown... Figure 4 In the example, the input signals may include the gate turn-on voltage VGH, the gate turn-off voltage VGL, the pre-stage drive signal Gn-4, and the post-stage drive signal Gn+4.

[0046] Output module 112 is connected to the first node Q and is used to provide a driving signal Gn based on the first clock signal CLK2 and the voltage of the first node Q. In this example, output module 112 includes a third transistor T3 and a capacitor C. The first terminal of the third transistor T3 receives the first clock signal CLK2, the second terminal provides the driving signal Gn, and the control terminal is connected to the first node Q. The capacitor C is connected between the control terminal and the second terminal of the third transistor T3. In some embodiments, the capacitor C is a parasitic capacitance between the control terminal and the second terminal of the third transistor. However, it should be understood that in other embodiments, in order to improve the coupling effect of the capacitor and thus improve the pull-up effect on the voltage of the first node Q, an independent capacitor is also provided between the control terminal and the second terminal of the third transistor T3, and the capacitor C is the sum of the parasitic capacitance between the control terminal and the second terminal of the third transistor and the independent capacitance. The first clock signal CLK2 may be a clock signal that differs from the basic clock signal by two clock cycles.

[0047] Control module 113 is connected between the first node Q and the second node QB, and is used to adjust the voltage of the second node QB according to the voltage of the first node Q. In this example, control module 113 includes a fourth transistor T4 and a fifth transistor T5. The control terminal of the fourth transistor T4 is connected to the first terminal and to the third power supply terminal, and the second terminal is connected to the second node QB. The control terminal of the fifth transistor T5 is connected to the first node Q, the first terminal is connected to the second node QB, and the second terminal is connected to the second power supply terminal.

[0048] In such Figure 4 In the example shown, the third power supply terminal can be the one that provides the first voltage AVDD.

[0049] The stabilization module 114 is used to maintain the first node Q and the current stage drive signal Gn at the gate cutoff voltage VGL when the second node QB is at an effective potential. In this example, the stabilization module 114 includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the sixth transistor T6 is connected to the second node QB, its first terminal is connected to the first node Q, and its second terminal is connected to the second power supply terminal. The control terminal of the seventh transistor T7 is connected to the second node QB, its first terminal is connected to the second terminal of the third transistor T3, which is also the output terminal of the output module 112, and its second terminal is connected to the second power supply terminal.

[0050] Reset module 116 is used to reset the current stage drive signal Gn to the gate cutoff voltage VGL based on a valid second clock signal CLK4. In this example, reset module 116 includes an eighth transistor T8. The control terminal of the eighth transistor T8 receives the second clock signal CLK4, its first terminal is connected to the second terminal of the third transistor T3, and its second terminal is connected to the second power supply terminal. The second clock signal can be a clock signal that differs from the reference clock signal by four clock cycles. More specifically, the second clock signal CLK4 is the inverted signal of the first clock signal CLK2.

[0051] Taking the first transistor T1 to the eighth transistor T8 as an example, all of which are N-type transistors, the effective level of the second node QB is high. Figure 5 Show Figure 4 A schematic waveform diagram of the driving circuit. (Reference) Figure 5 The working process of the drive circuit in each stage of the drive unit is divided into a pre-charging stage, a pull-up stage, a pull-down stage, and a stabilization stage.

[0052] Pre-charge phase: In this embodiment, the pre-stage drive signal Gn-4 is used as the pre-charge signal. The level of the pre-stage drive signal Gn-4, output from a drive unit four stages ahead, changes from low to high, turning on the first transistor T1. The first node Q is pre-charged through the turned-on first transistor T1. As the voltage of the first node Q increases, the third transistor T3 and the fifth transistor T5 are gradually turned on. Furthermore, as the fifth transistor T5 is turned on, the voltage of the second node QB is pulled down to the gate cutoff voltage VGL. Therefore, the sixth transistor T6 and the seventh transistor T7 are gradually turned off.

[0053] Pull-up Phase: After the pre-charge phase, the first node Q has been pre-charged, and the third transistor T3 is turned on. When the first clock signal CLK2 goes high, the gate drive signal Gn output by this drive unit is pulled high by the first clock signal CLK2 through the turned-on third transistor T3. Due to the bootstrap effect of capacitor C, the voltage of the first node Q is further pulled up, making the third transistor T3 more fully turned on. At the same time, the second clock signal CLK4 controls the eighth transistor T8 to turn off.

[0054] Pull-down phase: In this application, the subsequent drive signal Gn+4 is used as the pull-down signal. When the subsequent drive signal Gn+4 changes from low to high, the second transistor T2 turns on, the potential of the first node Q is pulled low, and the third transistor T3 gradually turns off. When the level of the first clock signal CLK2 changes from high to low, the level of the second clock signal CLK4 changes from low to high, the eighth transistor T8 turns on, and the current stage drive signal Gn is pulled low to the voltage of the second power supply terminal, i.e., the gate cutoff voltage VGL, through the turned-on eighth transistor T8.

[0055] Stabilization Phase: During the pull-down phase, the voltage of the first node Q is pulled low, and the fifth transistor T5 is turned off. The turned-on fourth transistor T4 gradually pulls the potential of the second node QB to an effective level, thereby gradually turning on the sixth transistor T6 and the seventh transistor T7, and stabilizing the first node Q and the current stage drive signal Gn at the voltage of the second power supply terminal, i.e., the gate cutoff voltage VGL, thus obtaining the ideal waveform of the current stage drive signal. It should be noted that compared to the fourth transistor T4, the fifth transistor T5 should have a larger size to provide stronger current drive capability, so that the voltage of the second node QB can be pulled down by the turned-on fifth transistor T5.

[0056] At high temperatures, the coupling effect of the second node QB intensifies, causing voltage fluctuations in the second node QB. The stabilization module 114 fails to maintain stability, resulting in fluctuations in the first node Q and the driving signal Gn. Such fluctuations can cause the corresponding pixel units to turn on incorrectly, resulting in horizontal stripes on the display.

[0057] In some embodiments, to avoid displaying horizontal stripes, it is necessary to increase the voltage at the first power supply terminal. If a gate turn-on voltage VGH higher than the first voltage AVDD is directly supplied to the first power supply terminal, the potential of the second node QB will be high, and at low temperatures, the second node QB will not be easily pulled low. If other voltages higher than the first voltage AVDD are supplied to the first power supply terminal, additional level shifting circuitry is required, resulting in higher production costs.

[0058] In the embodiments of this application, a compensation module connected to the second node QB is provided to maintain the effective level of the second node QB according to the effective control signal TC.

[0059] Furthermore, in Figure 4 In the embodiment shown, the compensation module 115a is used to provide compensation to the second node QB according to the effective control signal TC when the operating temperature is greater than or equal to the first preset temperature, so as to stabilize the voltage of the second node QB, thereby improving the display effect at high temperature and facilitating the expansion of the operating temperature range of the display device.

[0060] In such Figure 4 In the illustrated embodiment, the compensation module 115a includes a ninth transistor T9. Correspondingly, the control signal TC includes a first control signal TC1. The first terminal of the ninth transistor T9 is connected to the third power supply terminal, the second terminal is connected to the second node QB, and the control terminal receives the first control signal TC1.

[0061] Figure 6 A schematic waveform diagram of the first control signal TC1 is shown. Combined with... Figure 3 , Figure 4 and Figure 6 The control signal TC includes a first control signal TC1. When the operating temperature is lower than the first preset temperature T1, the control signal generation unit 120 multiplexes the gate cutoff voltage VGL as the first control signal TC1. At this time, the ninth transistor T9 is turned off and does not affect the second node QB. When the operating temperature is greater than or equal to the first preset temperature T1, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1. At this time, the ninth transistor T9 is turned on to stabilize the voltage of the second node QB, thereby avoiding the fluctuation of the first node Q and the current stage driving signal Gn caused by the potential fluctuation of the second node QB, and thus avoiding the display horizontal lines caused by the fluctuation of the first node Q and the current stage driving signal Gn. Therefore, the gate driving circuit provided in this application can provide a stable scanning signal even at high temperatures, solve the display horizontal line problem at high temperatures, improve display quality, and enable the display device to have a wider operating temperature range.

[0062] Furthermore, Figure 7 Schematic circuit diagrams of a single drive unit are shown in some further embodiments of this application. For example... Figure 7 As shown, in some other embodiments of the drive unit 110b, an 8T1C structure is also used as an example of the drive circuit. Accordingly, the connection methods of the first transistor T1 and the second transistor T2 in the input module 111, the third transistor T3 and capacitor C in the output module 112, the fourth transistor T4 and the fifth transistor T5 in the control module 113, the sixth transistor T6 and the seventh transistor T7 in the stabilization module 114, and the eighth transistor T8 in the reset module 116, as well as the signals of the input drive circuit or the output drive circuit, are all related to... Figure 4 The embodiments shown are the same, and will not be described again here.

[0063] and Figure 4 The difference between the illustrated embodiment and the one shown is that, in Figure 7 In the illustrated embodiment, the compensation module 115b includes not only the ninth transistor T9 but also the tenth transistor T10. Correspondingly, the control signal TC includes a first control signal TC1 and a second control signal TC2. The ninth transistor T9 also has a control terminal that receives the first control signal TC1, a first terminal connected to the third power supply terminal to receive the first voltage AVDD, and a second terminal connected to the second node QB. The tenth transistor T10 has a first terminal connected to the second node QB, and its control terminal connected to and receiving the second control signal TC2.

[0064] Figure 8 It shows in Figure 7 The illustrated embodiment shows schematic waveforms of the first control signal TC1 and the second control signal TC2. (Combined with...) Figure 3 , Figure 7 and Figure 8 The control signal TC includes a first control signal TC1 and a second control signal TC2. When the operating temperature is lower than the first preset temperature T1, the control signal generation unit 120 multiplexes the gate cutoff voltage VGL as the first control signal TC1 and the second control signal TC2. At this time, both the ninth transistor T9 and the tenth transistor T10 are turned off, and they do not affect the second node QB. When the operating temperature is greater than or equal to the first preset temperature T1, but less than the second preset temperature T2, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1 and the gate cutoff voltage VGL as the second control signal TC2. At this time, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off, with the ninth transistor T9 stabilizing the voltage of the second node QB. When the operating temperature is greater than or equal to the second preset temperature T2, the control signal generation unit 120 multiplexes the gate turn-on voltage VGH as the first control signal TC1 and the second control signal TC2. At this time, both the ninth transistor T9 and the tenth transistor T10 are turned on, thus enhancing the ability to maintain the potential of the second node QB. Even when the potential of the first voltage AVDD is limited, it can improve the ability to suppress potential fluctuations of the first node Q and the current stage drive signal Gn, which is more conducive to improving the working stability of the drive unit and the gate drive circuit.

[0065] The first preset temperature T1 is less than the second preset temperature T2. For example, the first preset temperature can be 50°C and the second preset temperature can be 85°C. That is, when the operating temperature is less than 50°C, no compensation is required for the second node QB; when the operating temperature is between 50°C and 85°C, the ninth transistor T9 provides compensation to the second node QB; when the operating temperature is greater than or equal to 85°C, the ninth transistor T9 and the tenth transistor T10 jointly provide compensation for the second node QB.

[0066] Furthermore, a temperature detection circuit is usually provided in the display device to obtain the operating temperature of the gate drive circuit 100. The control signal generation unit 120 mentioned above is connected to the temperature detection circuit to obtain the operating temperature. It has a simple structure and low cost.

[0067] According to the gate driving circuit and display device provided in this application, compensation is provided to the second node through the compensation module at high temperatures to stabilize the potential of the second node and prevent the scanning signal provided by the gate driving circuit from changing due to the potential fluctuation of the second node. Therefore, the gate driving circuit provided in this application can provide a stable scanning signal even at high temperatures, solving the problem of horizontal lines in the display at high temperatures, improving display quality, and enabling the display device to have a wider operating temperature range.

[0068] Furthermore, by multiplexing the gate cutoff voltage and gate turn-on voltage to provide control signals to the compensation module, the second node is not affected at low temperatures, while compensation can be performed on the second node at high temperatures, thus enhancing the temperature adaptability of the gate drive circuit. Simultaneously, due to signal multiplexing, control of the compensation module can be achieved without the need for additional level shifting circuitry, saving production costs and circuit layout area.

[0069] As described above, these embodiments of the present application do not exhaustively describe all details, nor do they limit the present application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it.

Claims

1. A gate driving circuit, comprising a plurality of cascaded driving units, wherein, Each of the drive units includes: An input module, connected to the first node, is used to adjust the voltage of the first node according to the input signal; The output module, connected to the first node, is used to provide a driving signal that follows the first clock signal when the voltage of the first node is at a first level. A control module is connected between the first node and the second node, and is used to adjust the voltage of the second node according to the voltage of the first node. When the voltage of the first node is at the second level, the second node is at the active level. A stabilization module is configured to maintain the first node and the current stage drive signal at the gate cutoff voltage when the second node is at an active level; and A compensation module, connected to the second node, is used to maintain the effective voltage level of the second node when the voltage of the first node is at a second level, based on a valid control signal. The control signal represents the operating temperature of the gate drive circuit.

2. The gate driving circuit according to claim 1, wherein, The gate driving circuit further includes: A control signal generation unit is used to provide the control signal according to the gate cutoff voltage or the gate turn-on voltage.

3. The gate driving circuit according to claim 2, wherein, The compensation module includes: The ninth transistor has its first terminal connected to the third power supply terminal, its second terminal connected to the second node, and its control terminal receiving the first control signal. The control signal generation unit obtains the first control signal based on the gate cutoff voltage when the operating temperature is lower than the first preset temperature, and obtains the first control signal based on the gate turn-on voltage when the operating temperature is greater than or equal to the first preset temperature.

4. The gate driving circuit according to claim 3, wherein, The compensation module also includes: The tenth transistor has its first terminal connected to the second node, and its control terminal connected to its second terminal to receive the second control signal. The control signal generation unit obtains the second control signal based on the gate cutoff voltage when the operating temperature is lower than the second preset temperature, and obtains the second control signal based on the gate turn-on voltage when the operating temperature is greater than or equal to the second preset temperature.

5. The gate driving circuit according to claim 4, wherein, The first preset temperature is lower than the second preset temperature.

6. The gate driving circuit according to claim 1, wherein, The input module includes: A first transistor, with its first terminal connected to a first power supply terminal and its second terminal connected to the first node, and its control terminal receiving a drive signal from the preceding stage; and The second transistor has its first terminal connected to the first node, its control terminal receiving drive signals from subsequent stages, and its second terminal connected to the second power supply terminal. The output module includes: The third transistor has a control terminal connected to the first node, a first terminal receiving the first clock signal, and a second terminal providing the drive signal for this stage; and A capacitor is connected between the control terminal and the second terminal of the third transistor.

7. The gate drive circuit according to claim 1, wherein, The control module includes: The fourth transistor has its control terminal and first terminal connected to the third power supply terminal, and its second terminal connected to the second node; and The fifth transistor has its control terminal connected to the first node, its first terminal connected to the second node, and its second terminal connected to the second power supply terminal. The stabilization module includes: The sixth transistor has its control terminal connected to the second node, its first terminal connected to the first node, and its second terminal connected to the second power supply terminal; and The seventh transistor has its control terminal connected to the second node, its first terminal connected to the output terminal of the output module, and its second terminal connected to the second power supply terminal.

8. The gate driving circuit according to claim 1, wherein, The gate driving circuit further includes: The eighth transistor has a control terminal that receives a second clock signal, a first terminal that is connected to the output terminal of the output module, and a second terminal that is connected to the second power supply terminal.

9. A display device, wherein, include: The gate drive circuit as described in any one of claims 1-8; as well as A power management circuit is used to provide the gate cutoff voltage, the gate turn-on voltage, and the first power supply voltage according to the input voltage of the display device.

10. The display device according to claim 9, wherein, The display device further includes: A temperature detection circuit is used to obtain the operating temperature of the gate drive circuit.

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