Hardware module for modular multiplication calculation

Abstract

The embodiment of the invention provides a hardware module for modular multiplication calculation. The hardware module comprises a partial product generator used for receiving a current quantization bit input by a second multiplier in a minimum radix-4 redundancy mr4 form in a current clock period and outputting a first bit string which is a binary representation of a partial product obtained by multiplying the current quantization bit by a first multiplier in a binary form; the hybrid redundancy modular reduction array comprises a plurality of minimum redundancy hybrid radix-4 adders mrHY4A and a group of registers; the plurality of mrHY4A are used for outputting the intermediate sum data of the current clock period according to a first bit string, the intermediate sum data in the form of mr4 obtained from the last clock period obtained from one group of registers, and the target product in the form of binary related to modulus, and caching the intermediate sum data into one group of registers; the intermediate sum data of the last clock period is used as a modular multiplication result of the first multiplier, the second multiplier and the scaling factor under the modulus.

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