A high-reliability trench-gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides a high-reliability trench-gate silicon carbide VDMOS and a preparation method thereof. The method comprises: depositing metal to form a drain metal layer, performing epitaxial growth to form a drift layer; forming a barrier layer, etching, and ion implanting to form a P-type source region, a P-type well region, and an N-type source region; reforming the barrier layer, etching, and depositing to form a first insulating layer; reforming the barrier layer, etching, and depositing to form a suspended gate; reforming the barrier layer, etching, and oxidizing to form a second insulating layer; reforming the barrier layer, etching, and depositing metal to form a first metal layer; reforming the barrier layer, etching, and depositing to form a third insulating layer and a fourth insulating layer; reforming the barrier layer, etching, and depositing metal to form a second metal layer and a source metal layer, and removing the barrier layer to complete the preparation; by splitting the conductive channel of the device, the device can be ensured to be turned off, and a large current freewheeling of the body diode can be provided, thereby improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] The natural wide bandgap characteristics of silicon carbide VDMOS can effectively meet the requirements of high total dose radiation resistance, but due to its gate oxide quality issues, its radiation resistance to single particles is weak, and its application in commercial aerospace, deep space exploration and other fields is limited. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly reliable trench gate silicon carbide VDMOS and a preparation method. By splitting the conductive channel of the device, when a single-particle gate breakdown problem occurs in a single direction of the device, the device will not be turned on for a long time. The device can be ensured to be turned off, and a large current is provided for the body diode to continue to flow, thereby improving the reliability of the device.

[0004] In a first aspect, the present invention provides a method for preparing a high-reliability trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type source region;

[0007] Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region;

[0008] Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0009] Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the P-type well region to form a groove, and deposit to form a first insulating layer;

[0010] Step 6: removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a floating gate;

[0011] Step 7: removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and oxidizing to form a second insulating layer, wherein the second insulating layer has a first groove;

[0012] Step 8: removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a first metal layer;

[0013] Step 9: remove the barrier layer in step 8, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer and the second insulating layer to the upper side of the P-type well region, and deposit to form a third insulating layer;

[0014] Step 10: removing the barrier layer of step 9, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a fourth insulating layer, wherein the insulating dielectric layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, and a trench is provided in the insulating dielectric layer;

[0015] Step 11: removing the barrier layer of step 10, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the fourth insulating layer, depositing metal to form a second metal layer, where the gate metal layer includes the first metal layer and the second metal layer;

[0016] Step 12: remove the barrier layer of step 11, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to the upper side of the P-type source region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0017] In a second aspect, the present invention provides a high-reliability trench gate silicon carbide VDMOS, which is prepared by the method for preparing a high-reliability trench gate silicon carbide VDMOS according to the first aspect.

[0018] The advantages of the present invention are:

[0019] First, the present invention divides the conductive channel of the device into two directions, horizontal and vertical. When a single particle breaks down the dielectric of the device gate insulation horizontally or vertically, the device will no longer conduct, but the device's voltage resistance can still be maintained, without affecting the working state of the system, thereby improving system stability.

[0020] Second, the gate metal layer of the present invention can be controlled to form a horizontal conductive channel and a vertical conductive channel, so that the gate metal layer can control the two conductive channels of the device;

[0021] 3. The present invention constructs a floating gate, which has two functions: one is to shield the gate from the drain capacitance and improve the switching speed of the device; the other is to form protection for the longitudinal gate structure of the device, which provides effective buffering in the event of single-particle damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This is a schematic diagram of a high-reliability trench-gate silicon carbide VDMOS according to the present invention.

[0024] Figure 2This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0025] Figure 3 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0026] Figure 4 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0027] Figure 5 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0028] Figure 6 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0029] Figure 7 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0030] Figure 8 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0031] Figure 9 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0032] Figure 10 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0033] Figure 11 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0034] Figure 12 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 one.

[0035] Figure 13 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 two.

[0036] Figure 14 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 three.

[0037] Figure 15 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 Four.

[0038] Figure 16 This is a cross-sectional view of the process of a high-reliability trench gate silicon carbide VDMOS of the present invention Figure 10 five. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0042] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0043] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] like Figures 1 to 16 As shown, the embodiment of the present application provides a method for preparing a high-reliability trench gate silicon carbide VDMOS, comprising the following steps:

[0045] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8, and epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0046] Step 2: forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and implanting ions to form a P-type source region 3;

[0047] Step 3: remove the barrier layer in step 2, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and implant ions to form a P-type well region 4;

[0048] Step 4: remove the barrier layer in step 3, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and implant ions to form an N-type source region 41;

[0049] Step 5: remove the barrier layer of step 4, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the drift layer 2 and the P-type well region 4 to form a groove 21, and deposit to form a first insulating layer 53;

[0050] Step 6: remove the barrier layer in step 5, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, deposit metal, and form a floating gate 51;

[0051] Step 7: remove the barrier layer in step 6, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and oxidize to form a second insulating layer 54, wherein the second insulating layer 54 has a first groove 541;

[0052] Step 8: remove the barrier layer of step 7, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and deposit metal to form a first metal layer 61;

[0053] Step 9: remove the barrier layer in step 8, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the drift layer 2 and the second insulating layer 54 to the upper side of the P-type well region 4, and deposit to form a third insulating layer 55;

[0054] Step 10: remove the barrier layer of step 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and deposit to form a fourth insulating layer 56. The insulating dielectric layer 5 includes a first insulating layer 53, a second insulating layer 54, a third insulating layer 55, and a fourth insulating layer 56. A trench 52 is provided in the insulating dielectric layer 5.

[0055] Step 11: remove the barrier layer of step 10, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the fourth insulating layer 56, deposit metal to form a second metal layer 62, and the gate metal layer 6 includes a first metal layer 61 and a second metal layer 62;

[0056] Step 12: remove the barrier layer of step 11, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, etch the drift layer 2 to the upper side of the P-type source region 3, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.

[0057] In this embodiment, preferably, the groove 52 is in an inverted convex shape, and the gate metal layer 6 matches the groove 52 .

[0058] In this embodiment, preferably, the upper side surface of the floating gate 51 is lower than the upper side surface of the drift layer 2 .

[0059] In this embodiment, preferably, the thickness of the P-type well region 4 is equal to the sum of the thickness of the N-type source region 41 and the thickness of the P-type source region 3 .

[0060] In this embodiment, preferably, the doping concentration of the P-type source region 3 is greater than the doping concentration of the P-type well region 4 .

[0061] In this embodiment, preferably, the doping concentration of the N-type source region 41 is greater than the doping concentration of the P-type well region 4 .

[0062] like Figure 1 As shown, the trench gate silicon carbide VDMOS obtained by the above manufacturing method includes:

[0063] Silicon carbide substrate 1;

[0064] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a groove 21 is provided on the drift layer 2;

[0065] A P-type source region 3, wherein the lower side of the P-type source region 3 is connected to the upper side of the drift layer 2;

[0066] A P-type well region 4, wherein the lower side of the P-type well region 4 is connected to the upper side of the drift layer 2, and the outer side of the P-type well region 4 is connected to the inner side of the P-type source region 3; an N-type source region 41 is provided on the P-type well region 4;

[0067] an insulating dielectric layer 5, wherein the lower portion of the insulating dielectric layer 5 is disposed in the groove 21 and connected to the P-type well region 4 and the N-type source region 41; a floating gate 51 and a trench 52 are disposed in the insulating dielectric layer 5; the floating gate 51 is located below the trench 52;

[0068] a gate metal layer 6 disposed in the trench 52;

[0069] a source metal layer 7 , the source metal layer 7 being connected to the N-type source region 41 and the P-type source region 3 ;

[0070] and a drain metal layer 8 connected to the lower side of the silicon carbide substrate 1 .

[0071] Another embodiment of the present invention includes a drain metal layer 8, an N-type silicon carbide substrate 1, an N-type drift layer 2, an insulating dielectric layer 5, a floating gate 51, a P-type well region 4, a P-type source region 3, an N-type source region 41, a gate metal layer 6, and a source metal layer 7; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 6-10e16cm -3 , the doping concentration of the P-type well region 4 is 6-10e16cm -3 , the doping concentration of the P-type source region 3 is 1-5e19cm -3 The insulating dielectric layer 5 may be made of silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm -3 ;

[0072] The concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device. The doping concentration of the P-type well region 4 is to achieve the withstand voltage of the device pn junction structure when the device drain is subjected to a high voltage. The doping concentration of the P-type source region 3 is to reduce the contact resistance between the P-type source region 3 and the source metal layer 7, thereby reducing the conduction loss of the parasitic body diode of the device.

[0073] The thickness of the N-type silicon carbide substrate 1 of the device is 1μm, and the thickness of the N-type drift layer 2 is 50-100μm. It is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The maximum thickness of the insulating dielectric layer 5 is 1.5μm. The thickness of the insulating dielectric at the bottom of the floating gate 51 is 100-200nm. 100nm can achieve improved resistance to single particles. In order to reduce the difficulty of the manufacturing process, the thickness of the floating gate 51 is 200nm. The thickness of the insulating dielectric between the floating gate 51 and the device gate metal layer 6 is 100-200nm. The width of the insulating dielectric from the device gate metal layer 6 to the P-type well region 4 on its left and right sides is 50nm. This is for To ensure gate control capability, the thickness of the insulating dielectric above the N-type source region 41 and the P-type well region 4 is 50nm, and the thickness of the gate metal layer 6 located above the P-type well region 4 is 350nm. This is to ensure the gate control capability of the device and ensure the formation of a lateral conductive channel. The maximum thickness of the P-type well region 4 is 600nm, the thickness of the N-type source region 41 is 300nm, and the maximum thickness of the gate metal layer 6 is 900nm. The lower side of the gate metal layer 6 is 100nm higher than the lower side of the P-type well region 4. This is to avoid the gate insulation dielectric reliability problem caused by the electric field concentration of the gate metal layer 6 at the corner of the insulating dielectric. The thickness of the source metal layer 7 is 700nm, and the thickness of the P-type source region 3 is 300nm.

[0074] The width of the floating gate 51 is 1 μm, the width of the lower portion of the gate metal layer 6 is 1.4 μm, and the width of the upper portion is 2.4 μm. The maximum width of the P-type well region 4 is 800 nm, and the width of the N-type source region 41 is 400 nm. This is to ensure that the gate metal layer 6 covers the lateral conductive channel portion and ensures gate control capability. The width of the P-type source region 3 is 1 μm. This is to ensure that the device can achieve freewheeling when it is not working, ensure the derating operation of the power system, and improve reliability. The width of the insulating medium between the gate metal layer 6 and the source metal layer 7 is 300 nm. This is to ensure the isolation between the gate metal and the source metal.

[0075] The present invention divides the conductive channel of the device into two directions, horizontal and vertical. When a single particle breaks down the dielectric of the device gate in the horizontal or vertical direction, the device will no longer conduct, but the device's voltage resistance can still be maintained, which will not affect the working state of the system and improve the system stability.

[0076] The gate metal layer 6 of the present invention can control the formation of a horizontal conductive channel and a vertical conductive channel, so that the gate metal layer 6 can control the two conductive channels of the device;

[0077] The present invention constructs a floating gate 51, which has two functions: one is to shield the gate from the drain capacitance and improve the switching speed of the device; the other is to form protection for the longitudinal gate structure of the device and provide effective buffering in the event of single particle damage.

[0078] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-reliability trench-gate silicon carbide VDMOS, characterized by: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type source region; Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type well region; Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region; Step 5: remove the barrier layer of step 4, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer and the P-type well region to form a groove, and deposit to form a first insulating layer; Step 6: removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a floating gate; Step 7: removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and oxidizing to form a second insulating layer, wherein the second insulating layer has a first groove; Step 8: removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a first metal layer; Step 9: remove the barrier layer in step 8, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer and the second insulating layer to the upper side of the P-type well region, and deposit to form a third insulating layer; Step 10: removing the barrier layer of step 9, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a fourth insulating layer, wherein the insulating dielectric layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, and a trench is provided in the insulating dielectric layer, wherein the trench is in the shape of an inverted convex character; Step 11: removing the barrier layer of step 10, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the fourth insulating layer, depositing metal to form a second metal layer, wherein the gate metal layer includes the first metal layer and the second metal layer, and the gate metal layer matches the trench; Step 12: remove the barrier layer of step 11, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to the upper side of the P-type source region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, wherein: An upper side surface of the floating gate is lower than an upper side surface of the drift layer.

3. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the P-type well region is equal to the sum of the thickness of the N-type source region and the thickness of the P-type source region.

4. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region.

5. The method for preparing a high-reliability trench gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the N-type source region is greater than the doping concentration of the P-type well region.

6. A high-reliability trench-gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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