Branch prediction processing method and device, electronic equipment and storage medium
By using two predictors in the processor core to jointly predict and verify branch instructions, the branch prediction error problem caused by limited branch table capacity of historical instruction is solved, and the accuracy of branch prediction and the performance of computer systems are improved.
Patent Information
- Application Number
- CN202510061392.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2025-06-10
AI Technical Summary
Due to the limited capacity of the historical instruction branch table, the information of all branch instructions cannot be saved, resulting in branch prediction errors, affecting the performance and efficiency of the computer system.
Two predictors (first predictor and second predictor) are used to jointly predict whether the target instruction in the processor core is a branch instruction, and the accuracy of the prediction result is verified through pre-decoding results, thereby improving the accuracy of branch prediction.
Through verification and correction of the second predictor, branch instructions and non-branch instructions can be accurately identified, branch prediction error rate can be reduced, and overall performance of the computer system can be improved.
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Figure CN120123002A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technologies, and in particular, to a branch prediction processing method, apparatus, electronic device, and storage medium. Background Art
[0002] Branch prediction technology is a key technology in the field of computer technologies. Branch prediction technology mainly predicts the jump direction and jump address of the currently running instruction through the branch source address and jump address of the branch instruction recorded in the historical instruction branch table, which can effectively improve the performance and efficiency of the computer system.
[0003] Due to the limited capacity of the historical instruction branch table, it is impossible to save the information of all branch instructions in the instruction execution history. If the currently running instruction is a branch instruction, but this branch instruction is not recorded in the historical instruction branch table, it will be predicted that the currently running instruction is not a branch instruction, resulting in a branch prediction error. Or, when the jump address of the branch instruction changes, the branch predictor will still predict that the jump address of this branch instruction is the old address recorded in the historical instruction branch table, resulting in a branch prediction error. Summary of the Invention
[0004] Embodiments of the present application provide a branch prediction processing method, apparatus, electronic device, and storage medium, which can improve the accuracy of branch prediction.
[0005] The technical solution of the embodiments of the present application is implemented as follows:
[0006] In a first aspect, embodiments of the present application provide a branch prediction processing method, which is applied to a processor core. The processor core includes an instruction fetch unit, and the instruction fetch unit at least includes a first predictor, a second predictor, and a pre-decoding unit. The branch prediction processing method includes:
[0007] The first predictor predicts a first target instruction to obtain first instruction information;
[0008] The pre-decoding unit pre-decodes the first target instruction to obtain a pre-decoding result;
[0009] The second predictor determines second instruction information based on the pre-decoding result; and determines whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
[0010] In some preferred embodiments, the second predictor determines second instruction information based on the pre-decoding result, including:
[0011] The second predictor determines whether the instruction code in the pre-decoding result belongs to the instruction code set corresponding to the preset branch instruction set to obtain a determination result;
[0012] The second predictor determines the second instruction information based on the determination result;
[0013] Based on the first instruction information and the second instruction information, it is determined whether the prediction result of the first predictor is correct.
[0014] In some preferred embodiments, the second predictor determining the second instruction information based on the determination result includes:
[0015] If the determination result is that the instruction code in the pre-decoded result belongs to the instruction code set, the second predictor determines that the second instruction information represents that the first target instruction is a branch instruction;
[0016] If the determination result is that the instruction code in the pre-decoded result does not belong to the instruction code set, the second predictor determines that the second instruction information represents that the first target instruction is not a branch instruction.
[0017] In some preferred embodiments, determining whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information includes:
[0018] If the second instruction information represents that the first target instruction is a branch instruction and the first instruction information represents that the first target instruction is not a branch instruction, it is determined that the prediction result of the first predictor is incorrect;
[0019] If the second instruction information represents that the first target instruction is not a branch instruction and the first instruction information represents that the first target instruction is a branch instruction, it is determined that the prediction result of the first predictor is incorrect.
[0020] In some preferred embodiments, if the second instruction information represents that the first target instruction is not a branch instruction and the first instruction information represents that the first target instruction is a branch instruction, the method further includes:
[0021] In some preferred embodiments, if the second instruction information represents that the first target instruction is not a branch instruction and the first instruction information represents that the first target instruction is a branch instruction, the method further includes: the second predictor corrects the value of the instruction program counter based on the jump address calculated by the execution component of the first target instruction.
[0022] The second predictor corrects the value of the instruction program counter based on the second instruction information.
[0023] In some preferred embodiments, determining whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information includes:
[0024] If both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, compare whether the first address information in the first instruction information is consistent with the second address information in the second instruction information;
[0025] When the first address information is inconsistent with the second address information, determine that the prediction result of the first predictor is incorrect.
[0026] In some preferred embodiments, after determining that the prediction result of the first predictor is incorrect, the method further includes:
[0027] Determine the address information of the next instruction of the first target instruction based on the second address information.
[0028] In some preferred embodiments, the method further includes at least one of the following:
[0029] Clear the instructions on the error path corresponding to the first target instruction in the pipeline;
[0030] Update the address information of the next instruction of the first target instruction in the historical instruction branch table.
[0031] In some preferred embodiments, the pre-decoding unit pre-decodes the first target instruction as follows:
[0032] The pre-decoding unit decodes the first target instruction into an instruction with the same format as the T32 instruction set.
[0033] In some preferred embodiments, before the pre-decoding unit pre-decodes the first target instruction, the method further includes:
[0034] The pre-decoding unit obtains the first target instruction from the secondary cache framework;
[0035] After obtaining the pre-decoding result, the method further includes:
[0036] Store the pre-decoded first target instruction in the instruction cache.
[0037] In a second aspect, an embodiment of the present application provides a branch prediction processing device, which is located in a processor core. The branch prediction processing device includes an instruction fetching unit, and the instruction fetching unit at least includes a first predictor, a second predictor, and a pre-decoding unit;
[0038] The first predictor is configured to predict a first target instruction to obtain first instruction information;
[0039] The pre-decoding unit is configured to perform pre-decoding on the first target instruction to obtain a pre-decoding result;
[0040] The second predictor is configured to obtain second instruction information based on the pre-decoding result; and determine whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
[0041] In a third aspect, an embodiment of the present application provides a processor core that can execute the above-mentioned branch prediction processing method.
[0042] In a fourth aspect, an embodiment of the present application provides a processor that can execute the above-mentioned branch prediction processing method.
[0043] The branch prediction processing method provided by the embodiment of the present application is applied to a processor core. The method includes: a first predictor predicts a first target instruction to obtain first instruction information. A pre-decoding unit performs pre-decoding on the first target instruction to obtain a pre-decoding result; a second predictor determines second instruction information based on the pre-decoding result; and determines whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information. In the embodiment of the present application, two predictors are used to predict whether the first target instruction is a branch instruction, improving the accuracy of branch prediction. Description of the Drawings
[0044] Figure 1 is a schematic processing flow diagram of the branch prediction processing method provided by the embodiment of the present application;
[0045] Figure 2 is a schematic diagram of a specific implementation process in which the second predictor provided by the embodiment of the present application determines second instruction information based on a pre-decoding result;
[0046] Figure 3 is another schematic processing flow diagram of the branch prediction processing method provided by the embodiment of the present application;
[0047] Figure 4 is a schematic overall flow diagram of the branch prediction processing method provided by the embodiment of the present application;
[0048] Figure 5 is a schematic composition structure diagram of the branch prediction processing device provided by the embodiment of the present application;
[0049] Figure 6 is a schematic structure diagram of an electronic device provided by the embodiment of the present application. Detailed Embodiments
[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe this application in detail in conjunction with the accompanying drawings. The described embodiments should not be regarded as limitations of this application. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.
[0051] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.
[0052] In the following description, the terms "first / second" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second" can be interchanged with a specific order or sequence when permitted, so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here.
[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0054] It should be understood that in various embodiments of this application, the magnitudes of the serial numbers of each implementation process do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic and should not constitute any limitation to the implementation process of the embodiments of this application.
[0055] Before further elaborating on the embodiments of this application, the nouns and terms involved in the embodiments of this application are described. The nouns and terms involved in the embodiments of this application are subject to the following explanations.
[0056] 1) Processor core: It is the most core part inside the processor and can also be called the processor kernel.
[0057] 2) Processor: It includes one or more processor cores, as well as other components or devices such as a memory.
[0058] 3) Pipeline: It is an implementation technology that overlaps the execution of multiple instructions. Each step in the pipeline completes a part of the instruction. Each step is called a pipeline stage or pipeline segment. The pipeline stages are connected in sequence to form a pipeline; instructions enter at one end of the pipeline and exit at the other end through these pipeline stages; each pipeline corresponds to a task.
[0059] 4) Instruction fetching refers to the process of the fetch unit retrieving instructions from the memory.
[0060] In the related art, a dynamic branch prediction method is usually adopted to predict whether an instruction is a branch instruction. Specifically, a historical instruction branch table records the branch source address and the jump address of the branch instruction in the instruction execution history; the dynamic branch predictor traverses the historical instruction branch table to determine whether the source address of the currently running instruction hits the branch source address in the historical instruction branch table. If it hits, it is considered that the currently running instruction is a branch instruction; the jump address of the currently running instruction is the target address stored in the hit entry of the historical instruction branch table. If it does not hit, it is considered that the currently running instruction is not a branch instruction. After the dynamic branch predictor predicts the address of the next instruction of the currently running instruction, the fetch unit fetches the next instruction from the low-level cache according to the address of the next instruction and stores it in the instruction cache. However, due to the limited capacity of the historical instruction branch table, which cannot store the information of all branch instructions, and the jump address of the branch instruction may change, etc., the branch instructions predicted based on the historical instruction branch table may be incorrect.
[0061] The branch prediction processing method provided by the embodiments of the present application can at least solve the above problems.
[0062] The branch prediction processing method provided by the embodiments of the present application is applied to a processor core, and the processor core includes a fetch unit, and the fetch unit at least includes a first predictor, a second predictor, and a pre-decoding unit; a schematic diagram of a processing flow of the branch prediction processing method provided by the embodiments of the present application is as Figure 1 shown, and at least includes the following steps:
[0063] Step S101, the first predictor predicts a first target instruction to obtain first instruction information.
[0064] In some embodiments, the first predictor predicts the first target instruction in a dynamic prediction manner to predict whether the first target instruction is a branch instruction; if the first target instruction is a branch instruction, the first predictor also predicts the address information of the next instruction of the first target instruction. Among them, the first predictor can be a TAGE predictor.
[0065] Specifically, the first predictor traverses the historical instruction branch table to determine whether the source address of the first target instruction hits the branch source address in the historical instruction branch table. If the source address of the first target instruction hits the branch source address in the historical instruction branch table, it is considered that the first target instruction is a branch instruction, and the jump address of the first target instruction is the target address stored in the hit entry of the historical instruction branch table. If the source address of the first target instruction does not hit the branch source address in the historical instruction branch table, it is considered that the currently running instruction is not a branch instruction.
[0066] In the embodiments of the present application, the first instruction information includes: whether the first target instruction is a branch instruction; in the case where the first target instruction is a branch instruction, the first target instruction information further includes the jump address of the first target instruction.
[0067] Step S102, the pre-decoding unit pre-decodes the first target instruction to obtain a pre-decoding result.
[0068] In some embodiments, the pre-decoding unit obtains the first target instruction from the secondary cache framework (L2 cache). Among them, the L2 cache can be set inside the processor core; the L2 cache can also be set outside the processor core, and the L2 cache is connected to the processor core.
[0069] In some embodiments, the pre-decoding unit decodes the first target instruction into an instruction with the same format as the T32 instruction set. The pre-decoding unit stores the pre-decoded first target instruction in the instruction buffer. Among them, the first target instruction may be an instruction of the A64 instruction set or an instruction of the A32 instruction set; by converting the first target instruction into the T32 instruction set format, there are only T32 format instructions in the subsequent decoding stage, which can simplify the decoding logic.
[0070] Step S103, the second predictor determines the second instruction information based on the pre-decoding result.
[0071] In some embodiments, the specific implementation process of the second predictor determining the second instruction information based on the pre-decoding result is as Figure 2 shown, and at least includes:
[0072] Step S103a, the second predictor determines whether the instruction code in the pre-decoding result belongs to the instruction code set corresponding to the preset branch instruction set, and obtains a determination result.
[0073] In some embodiments, the preset branch instruction set may be the branch instruction set in the ARM instruction set; the instruction code set may be the instruction code set corresponding to the ARM branch instruction set. If the instruction code in the pre-decoding result is the same as an instruction code in the instruction code set corresponding to the ARM branch instruction set, the determination result is that the instruction code in the pre-decoding result belongs to the instruction code set. If the instruction code in the pre-decoding result is not the same as any instruction code in the instruction code set corresponding to the ARM branch instruction set, the determination result is that the instruction code in the pre-decoding result does not belong to the instruction code set.
[0074] Step S103b, the second predictor determines the second instruction information based on the determination result.
[0075] In some embodiments, if the determination result is that the instruction code in the pre-decoded result belongs to the instruction code set, the second predictor determines that the second instruction information indicates that the first target instruction is a branch instruction.
[0076] In other embodiments, if the determination result is that the instruction code in the pre-decoded result does not belong to the instruction code set, the second predictor determines that the second instruction information indicates that the first target instruction is not a branch instruction.
[0077] In the embodiments of the present application, if the second instruction information indicates that the first target instruction is a branch instruction, the second instruction information further includes: second address information, and the second address information may be an offset carried by the instruction code in the pre-decoded result; the offset represents the offset of the jump address of the first target instruction relative to the source address of the first target instruction.
[0078] Step S104, the second predictor determines whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
[0079] In some embodiments, if the first instruction information is exactly the same as the second instruction information, the prediction result of the first predictor is correct; if the first instruction information is not exactly the same as the second instruction information, the prediction result of the first predictor is incorrect.
[0080] Both the first instruction information and the second instruction information include whether the first target instruction is a branch instruction; if the first target instruction is a branch instruction, the first instruction information further includes first address information, and the second instruction information further includes second address information; both the first address information and the second address information include the offset of the jump address of the first target instruction relative to the source address of the first target instruction.
[0081] In some embodiments, if both the first instruction information and the second instruction information indicate that the first target instruction is not a branch instruction, the prediction result of the first predictor is correct. If both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, and the offset of the jump address of the first target instruction included in the first instruction information relative to the source address of the first target instruction is the same as the offset of the jump address of the first target instruction included in the second instruction information, the prediction result of the first predictor is correct.
[0082] If the first instruction information indicates that the first target instruction is not a branch instruction and the second instruction information indicates that the first target instruction is a branch instruction, the prediction result of the first predictor is incorrect. If the first instruction information indicates that the first target instruction is a branch instruction and the second instruction information indicates that the first target instruction is not a branch instruction, the prediction result of the first predictor is incorrect.
[0083] If both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, and the offset of the jump address of the first target instruction included in the first instruction information relative to the source address of the first target instruction is different from the offset of the jump address of the first target instruction included in the second instruction information, then the prediction result of the first predictor is incorrect.
[0084] It should be noted that in the embodiments of the present application, the second predictor can predict whether the first target instruction is a branch instruction. The branch instruction can be a direct branch instruction or an indirect branch instruction. The second predictor can predict that the type of the branch instruction is a direct branch instruction or an indirect branch instruction. The second predictor can predict the jump address of the direct branch instruction, but the second predictor cannot predict the jump address of the indirect branch instruction.
[0085] In the embodiments of the present application, not only is the first predictor used to predict the first instruction information corresponding to the first target instruction, but also the second predictor is used to predict the second instruction information corresponding to the first target instruction; then, by comparing the first instruction information with the second instruction information, it is determined whether the prediction result of the first predictor is accurate. Compared with the prior art in which only a single branch prediction is performed on an instruction, the branch prediction processing method provided by the present application can improve the accuracy of branch prediction; the branch prediction processing method provided by the present application can also detect branch prediction errors in advance, perform prediction error recovery, and narrow the window period for recovering branch prediction errors. The performance of the processor is improved.
[0086] The branch prediction processing method provided by the embodiments of the present application is applied to a processor core. The processor core includes an instruction fetch unit, and the instruction fetch unit at least includes a first predictor, a second predictor, and a pre-decoding unit; another schematic diagram of the processing flow of the branch prediction processing method provided by the embodiments of the present application is shown as Figure 3 shown, and at least includes the following steps:
[0087] Step S201, the first predictor predicts the first target instruction to obtain first instruction information.
[0088] Step S202, the pre-decoding unit pre-decodes the first target instruction to obtain a pre-decoding result.
[0089] Step S203, the second predictor determines second instruction information based on the pre-decoding result.
[0090] Step S204, the second predictor determines whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
[0091] In the embodiments of the present application, the detailed processing procedures of steps S201 to S204 are the same as those of steps S101 to S104, and will not be elaborated here.
[0092] Step S205, the second predictor corrects the branch prediction result for the first target instruction based on the second instruction information.
[0093] In some embodiments, if the second instruction information indicates that the first target instruction is a non-branch instruction, and the first instruction information indicates that the first target instruction is a branch instruction, then it is determined that the first target instruction is a branch instruction, and the value of the instruction program counter (PC) is corrected to the value corresponding to the sequential next instruction of the first target instruction.
[0094] In other embodiments, if the second instruction information indicates that the first target instruction is a branch instruction, and the first instruction information indicates that the first target instruction is a non-branch instruction, then it is determined that the first target instruction is a branch instruction, and the jump address of the next instruction is determined based on the offset carried in the second address information in the second instruction information.
[0095] In still other embodiments, if both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, and this branch instruction is a direct branch instruction, but the first address information in the first instruction information is inconsistent with the second address information in the second instruction information, then the address information of the next instruction of the first target instruction is determined based on the second address information. Specifically, the offset in the second address information is added to the source address of the first target instruction to obtain the jump address of the first target instruction.
[0096] In the embodiments of the present application, when the branch prediction result of the first target instruction by the first predictor is incorrect, the branch prediction processing method may further include:
[0097] The second predictor clears the instructions on the error path corresponding to the first target instruction in the pipeline; the second predictor updates the address information of the next instruction of the first target instruction in the historical instruction branch table. Specifically, the second predictor updates the address information of the next instruction of the first target instruction in the historical instruction branch table based on the second address information.
[0098] In an embodiment of the present application, the second predictor identifies the first target instruction as a branch instruction through the instruction code. The branch instruction is a direct branch instruction. If the first predictor predicts that the first target instruction is a non-branch instruction, the second predictor can directly trigger er_flush and correct the instruction PC according to the second address information obtained by decoding the first target instruction by the pre-decoder unit. The second predictor can also send a notification to the first predictor to notify the first predictor that the branch prediction result for the first target instruction is incorrect, and pause the fetch unit pipeline.
[0099] In an embodiment of the present application, the second predictor identifies the first target instruction as a branch instruction through the instruction code. The branch instruction is an indirect branch instruction. If the first predictor predicts that the first target instruction is a non-branch instruction, the second predictor can directly trigger er_flush. The second predictor can also send a notification to the first predictor to notify the first predictor that the branch prediction result for the first target instruction is incorrect, pause the fetch unit pipeline. After the execution component of the first target instruction calculates the jump address of the indirect branch instruction, then correct the instruction pc and restart the IFU pipeline.
[0100] The overall flowchart of the branch prediction processing method provided by the embodiment of the present application is as Figure 4 shown: The position of the first target instruction can be found in the memory according to the program counter PC value. The first predictor obtains the first target instruction from the instruction cache and determines whether the first target instruction hits the historical instruction branch table. If the first target instruction hits the historical instruction branch table, the first predictor determines that the first target instruction is a branch instruction; if the first target instruction does not hit the historical instruction branch table, the first predictor determines that the first target instruction is not a branch instruction. If the first predictor determines that the first target instruction is a branch instruction, the first target instruction is passed to the Instruction Decoder Unit (IDU), and the IDU decodes the first target instruction. In a specific implementation, if the first predictor does not obtain the first target instruction from the instruction cache, the first target instruction is obtained from the L2 cache.
[0101] The pre-decoder unit obtains the first target instruction from the L2 cache, pre-decodes the first target instruction, and stores the pre-decoded first target instruction in the instruction cache.
[0102] The second predictor fetches the first target instruction from the instruction cache, matches the instruction code obtained by pre-decoding with the instruction codes corresponding to the branch instructions in the ARM architecture manual. If the instruction code obtained by pre-decoding is the same as one of the instruction codes corresponding to the branch instructions in the ARM architecture manual, the second predictor determines that the first target instruction is a branch instruction, and adds the offset obtained by pre-decoding to the source address of the first target instruction to obtain the jump address of the direct branch. If the second predictor identifies that the jump address predicted by the first predictor is incorrect, it generates er_flush and sends a notification to the first predictor to notify the first predictor to correct the prediction result. If the prediction result of the second predictor is different from the prediction result of the first predictor, the second predictor sends a notification to the first predictor to notify the first predictor to correct the prediction result.
[0103] The branch prediction processing method provided by the embodiments of the present application can accurately identify branch instructions or non-branch instructions, determine the jump address of branch instructions, correct the incorrect prediction results of the first predictor, reduce the misprediction rate of branch instructions, and improve the overall performance of the computer system.
[0104] The embodiments of the present application further provide a branch prediction processing device. The branch prediction processing device is located in the processor core. The schematic diagram of the composition structure of the branch prediction processing device is as Figure 5 shown. The branch prediction device at least includes an instruction fetching unit, and the instruction fetching unit at least includes a first predictor 501, a pre-decoding unit 502, and a second predictor 503;
[0105] The first predictor 501 is used to predict the first target instruction to obtain first instruction information;
[0106] The pre-decoding unit 502 is used to perform pre-decoding on the first target instruction to obtain a pre-decoding result;
[0107] The second predictor 503 is used to obtain second instruction information based on the pre-decoding result; and determine whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
[0108] In some embodiments, the second predictor 503 is used to determine whether the instruction code in the pre-decoding result belongs to the instruction code set corresponding to the preset branch instruction set to obtain a determination result; and determine the second instruction information based on the determination result.
[0109] In some embodiments, if the determination result is that the instruction code in the pre-decoded result belongs to the instruction code set, the second predictor 503 is used to determine that the second instruction information indicates that the first target instruction is a branch instruction; if the determination result is that the instruction code in the pre-decoded result does not belong to the instruction code set, the second predictor 503 is used to determine that the second instruction information indicates that the first target instruction is not a branch instruction.
[0110] In some embodiments, if the second instruction information indicates that the first target instruction is a branch instruction and the first instruction information indicates that the first target instruction is a non-branch instruction, the second predictor 503 is used to determine that the prediction result of the first predictor is incorrect; if the second instruction information indicates that the first target instruction is a non-branch instruction and the first instruction information indicates that the first target instruction is a branch instruction, the second predictor 503 is used to determine that the prediction result of the first predictor is incorrect.
[0111] In some embodiments, if the second instruction information indicates that the first target instruction is a non-branch instruction and the first instruction information indicates that the first target instruction is a branch instruction, the processing unit 504 is further used to correct the value of the instruction program counter based on the second instruction information.
[0112] In some embodiments, if both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, the second predictor 503 is used to compare whether the first address information in the first instruction information is consistent with the second address information in the second instruction information; when the first address information is inconsistent with the second address information, the second predictor 503 is used to determine that the prediction result of the first predictor is incorrect.
[0113] In some embodiments, the second predictor 503 is further used to determine the address information of the next instruction of the first target instruction based on the second address information.
[0114] In some embodiments, the second predictor 503 is further used to clear the instructions on the error path corresponding to the first target instruction in the pipeline; and / or is further used to update the address information of the next instruction of the first target instruction in the historical instruction branch table.
[0115] In some embodiments, the pre-decoding unit 502 is used to decode the first target instruction into an instruction in the same format as the T32 instruction set.
[0116] In some embodiments, the pre-decoding unit 502 is further used to obtain the first target instruction from the secondary cache framework and store the pre-decoded first target instruction in the instruction buffer.
[0117] An embodiment of the present application further provides a processor core, and the processor core can execute the branch prediction processing method provided by the embodiment of the present application.
[0118] An embodiment of the present application further provides a processor, and the processor can execute the branch prediction processing method provided by the embodiment of the present application.
[0119] An embodiment of the present application further provides an electronic device, Figure 6 which is a schematic structural diagram of the electronic device 400 provided by the embodiment of the present application. Figure 6 The illustrated electronic device 400 includes: at least one processor 410, a memory 450, and a bus 440; each component in the electronic device 400 is coupled together through the bus 440. It can be understood that the bus 440 is used to implement the connection and communication between these components. In addition to the data bus, the bus 440 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 6 all kinds of buses are labeled as the bus 440.
[0120] The processor 410 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or any conventional processor, etc.
[0121] In some embodiments, the memory 450 can store data to support various operations, and examples of these data include programs, modules, and data structures, or subsets or supersets thereof.
[0122] In some embodiments, the electronic device 400 may further include:
[0123] An operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;
[0124] A network communication module 452, for reaching other computing devices via one or more (wired or wireless) network interfaces 420 or user interfaces 430. Exemplary network interfaces 420 include: Bluetooth, Wireless Fidelity (WiFi), and Universal Serial Bus (USB), etc.
[0125] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and scope of the present application are all included within the protection scope of the present application.
Claims
1. A branch prediction processing method, characterized in that: Applied to a processor core, the processor core includes an instruction fetch unit, the instruction fetch unit includes at least a first predictor, a second predictor and a pre-decoding unit, the branch prediction processing method includes: The first predictor predicts the first target instruction to obtain first instruction information; The pre-decoding unit pre-decodes the first target instruction to obtain a pre-decoding result; The second predictor determines second instruction information based on the pre-decoding result; and determines whether the prediction result of the first predictor is correct based on the first instruction information and the second instruction information.
2. The method according to claim 1, characterized in that: The second predictor determines, based on the pre-decoding result, that the second instruction information includes: The second predictor determines whether the instruction code in the pre-decoding result belongs to the instruction code set corresponding to the preset branch instruction set, and obtains a determination result; The second predictor determines the second instruction information based on the determination result.
3. The method according to claim 2, characterized in that The second predictor determines, based on the judgment result, that the second instruction information includes: If the judgment result is that the instruction code in the pre-decoding result belongs to the instruction code set, the second predictor determines that the second instruction information represents that the first target instruction is a branch instruction; If the determination result is that the instruction code in the pre-decoding result does not belong to the instruction code set, the second predictor determines that the second instruction information indicates that the first target instruction is not a branch instruction.
4. The method according to claim 1, characterized in that: The determining, based on the first instruction information and the second instruction information, whether the prediction result of the first predictor is correct comprises: If the second instruction information indicates that the first target instruction is a branch instruction, and the first instruction information indicates that the first target instruction is a non-branch instruction, determining that the prediction result of the first predictor is incorrect; If the second instruction information indicates that the first target instruction is a non-branch instruction and the first instruction information indicates that the first target instruction is a branch instruction, it is determined that the prediction result of the first predictor is incorrect.
5. The method according to claim 4, characterized in that If the second instruction information indicates that the first target instruction is a non-branch instruction, and the first instruction information indicates that the first target instruction is a branch instruction, the method further includes: The second predictor corrects a value of an instruction program counter based on the second instruction information.
6. The method according to claim 4, characterized in that If the second instruction information indicates that the first target instruction is a non-branch instruction, and the first instruction information indicates that the first target instruction is a branch instruction, the method further includes: The second predictor corrects the value of an instruction program counter based on a jump address calculated by an execution unit of the first target instruction.
7. The method according to claim 1, characterized in that The determining, based on the first instruction information and the second instruction information, whether the prediction result of the first predictor is correct comprises: If both the first instruction information and the second instruction information indicate that the first target instruction is a branch instruction, comparing whether the first address information in the first instruction information is consistent with the second address information in the second instruction information; When the first address information is inconsistent with the second address information, it is determined that the prediction result of the first predictor is incorrect.
8. The method according to claim 7, characterized in that After determining whether the prediction result of the first predictor is correct, the method further includes: The address information of the next instruction of the first target instruction is determined based on the second address information.
9. The method according to claim 5, 6 or 8, characterized in that: The method further comprises at least one of the following: Clearing the instructions of the error path corresponding to the first target instruction in the pipeline; Update the address information of the next instruction of the first target instruction in the historical instruction branch table.
10. The method according to claim 1, characterized in that The pre-decoding unit pre-decoding the first target instruction includes: The pre-decoding unit decodes the first target instruction into an instruction having the same format as that of the T32 instruction set.
11. The method according to claim 1, characterized in that: Before the pre-decoding unit pre-decodes the first target instruction, the method further includes: The pre-decoding unit obtains the first target instruction from the secondary cache framework; After obtaining the pre-decoding result, the method further includes: The pre-decoding unit stores the pre-decoded first target instruction in an instruction buffer.
12. A branch prediction processing device, characterized in that: The branch prediction processing device is located in the processor core, and the branch prediction processing device includes an instruction fetch unit, and the instruction fetch unit at least includes a first predictor, a second predictor and a pre-decoding unit; The first predictor is used to predict the first target instruction to obtain first instruction information; The pre-decoding unit is used to pre-decode the first target instruction to obtain a pre-decoding result; The second predictor is used to obtain second instruction information based on the pre-decoding result; Based on the first instruction information and the second instruction information, it is determined whether the prediction result of the first predictor is correct.
13. A processor core, characterized in that: The processor core is capable of executing the branch prediction processing method according to any one of claims 1 to 11.
14. A processor, characterized in that: The processor is capable of executing the branch prediction processing method according to any one of claims 1 to 11.