Display panel

Abstract

Embodiments of the present application disclose a display panel, which comprises a first detection circuit configured to detect a data signal of a data line, the first detection circuit comprising a first to-be-connected group, the first to-be-connected group comprising a first connecting part and a second connecting part, the first connecting part and the second connecting part being arranged in different layers; and the first to-be-connected group being configured to insulate the first connecting part and the second connecting part when the first detection circuit is not enabled. According to the present application, when the first detection circuit is not enabled, the first connecting part and the second connecting part in the first to-be-connected group are insulated, the first detection circuit is in an open circuit state, and thus the line from the first to-be-connected group to the first detection pad in the first detection circuit is not connected in parallel to the data line, the risk of impedance difference between the data lines is reduced, and the influence on the light-on test is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] In related technologies, in order to reduce the number of driver chips, demultiplexing circuits are used to reduce the number of connected traces. Then, when detecting the potential of the data lines behind the demultiplexing circuit, an independent detection path is usually designed for detection, and the detection path is always connected to the data lines in the plane through vias.

[0003] In the process of researching and practicing the prior art, the inventors of this application discovered that since the detection circuit is always connected to the data line in the plane, it is equivalent to a resistor being connected in parallel to the data line, which causes the potential of the data line to be different from the potential of other data lines, thus affecting the test results of other related tests in the plane. Summary of the Invention

[0004] This application provides a display panel that can detect data line signals while reducing the impact on lamp testing.

[0005] This application provides a display panel, which includes:

[0006] A first detection circuit is configured to detect data signals of a data line. The first detection circuit includes a first group to be connected, which includes a first connection part and a second connection part. The first connection part and the second connection part are disposed in different layers.

[0007] When the first connection group is configured to be disconnected, the first connection portion and the second connection portion are insulated.

[0008] Optionally, in some embodiments of this application, the display panel includes a demultiplexing circuit, the demultiplexing circuit includes a plurality of demultiplexing units, each demultiplexing unit includes at least two thin-film transistors, the input terminals of the at least two thin-film transistors are connected to the same signal input line, and the output terminal of each thin-film transistor is connected to a data line; the first detection circuit includes a first trace, a second trace, and a first detection pad, the first trace is located on one side of the demultiplexing circuit, and the first detection pad is configured as a contact probe;

[0009] One end of the first trace is connected to the output terminal of the thin-film transistor, the other end of the first trace is connected to the first connection portion, one end of the second trace is connected to the second connection portion, and the other end of the second trace is connected to the first detection pad.

[0010] Optionally, in some embodiments of this application, the display panel includes a demultiplexing circuit, the demultiplexing circuit includes a plurality of demultiplexing units, each demultiplexing unit includes at least two thin-film transistors, the input terminals of the at least two thin-film transistors are connected to the same signal input line, and the output terminal of each thin-film transistor is connected to a data line; each data line and the output terminal of the thin-film transistor electrically connected thereto are connected through a lead wire, the first detection circuit includes a first trace, a second trace and a first detection pad, the first trace and the lead wire are disposed on different layers, one end of the second trace is connected to the first trace, the other end of the second trace is connected to the first detection pad, and the first detection pad is configured as a contact probe;

[0011] In the display panel viewed from above, the extension direction of the first trace intersects with the extension direction of the lead wire, and multiple leads wires overlap with the same portion of the first trace. The portion of the first trace that overlaps with the lead wire is reused as the first connection portion, and the portion of the lead wire that overlaps with the first trace is reused as the second connection portion.

[0012] Optionally, in some embodiments of this application, the data signal includes a first data signal, which is a signal transmitted from the output terminal of the thin-film transistor of the demultiplexing unit to the data line, and the first detection circuit is configured to detect the first data signal.

[0013] In the thickness direction of the display panel, the first connecting portion and the second connecting portion are at least partially overlapped, and the first connecting group is configured to connect the first connecting portion and the second connecting portion when the first detection circuit is enabled.

[0014] Optionally, in some embodiments of this application, the first connection group is configured such that when the first detection circuit is enabled, the first connection portion and the second connection portion are laser welded.

[0015] Optionally, in some embodiments of this application, the display panel further includes a common trace, the common trace having a first common portion shared with the second trace;

[0016] The common trace is configured to transmit a common voltage when the first detection circuit is not enabled.

[0017] Optionally, in some embodiments of this application, a first cutting position is provided on the common trace outside the first common part, and the common trace is configured to cut the common trace at the first cutting position when the first detection circuit is enabled, so that the first detection circuit forms a conductive path.

[0018] Optionally, in some embodiments of this application, the second trace includes a first sub-section and a second sub-section, the first sub-section and the second sub-section are disposed in different layers, the first sub-section and the second sub-section are connected by a first via, at least a portion of the second sub-section is the first common section, and the first cut position is disposed in the common trace on the side of the first via that is away from the first common section and adjacent to the first via.

[0019] Optionally, in some embodiments of this application, the display panel further includes a second detection circuit, the second detection circuit includes a second group to be connected, the second group to be connected includes a third connection part and a fourth connection part, the third connection part and the fourth connection part are disposed on different layers and at least partially overlap;

[0020] When the second group to be connected is configured to not enable the second detection circuit, the third connection portion and the fourth connection portion are insulated.

[0021] Optionally, in some embodiments of this application, the data signal includes a second data signal, the second data signal being a signal input to the signal input line, the second detection circuit being configured to detect the second data signal, and the second connection group being configured to connect the third connection portion and the fourth connection portion when the second detection circuit is enabled.

[0022] Optionally, in some embodiments of this application, the second detection circuit includes a third trace, a fourth trace, and a second detection pad, wherein the third trace is located on one side of the demultiplexing circuit, and the second detection pad is configured as a contact probe.

[0023] One end of the third trace is connected to the signal input line, and the other end of the third trace is connected to the third connection part. One end of the fourth trace is connected to the fourth connection part, and the other end of the fourth trace is connected to the second detection pad.

[0024] Optionally, in some embodiments of this application, the display panel further includes a test line and a third detection pad, the test line being configured to transmit the stage transmission signal of the last stage of the gate drive circuit to the third detection pad; the test line has a second common portion shared with the fourth trace;

[0025] The test line is configured to transmit the stage transmission signal of the last stage of the gate drive circuit when the second detection circuit is not enabled.

[0026] Optionally, in some embodiments of this application, the test line is provided with a second cutting position located outside the second common part, and the test line is configured to cut the test line at the second cutting position when the second detection circuit is enabled, so that the second detection circuit forms a conductive path.

[0027] Optionally, in some embodiments of this application, the fourth trace includes a third sub-section and a fourth sub-section, the third sub-section and the fourth sub-section are disposed in different layers, the third sub-section and the fourth sub-section are configured to be connected by a connection structure, at least a portion of the fourth sub-section is the second common section, and the second cut position is disposed on the side of the test line away from the second common section.

[0028] Optionally, in some embodiments of this application, the structure to be connected is located on one side of the test line, and the structure to be connected includes a fifth connecting part and a sixth connecting part disposed in different layers. The fifth connecting part and the sixth connecting part at least partially overlap. The fifth connecting part is connected to the third sub-part, one end of the fourth sub-part is connected to the sixth connecting part, and the other end of the fourth sub-part is connected to the second detection pad.

[0029] When the structure to be connected is configured such that the fifth connection portion and the sixth connection portion are insulated when the second detection circuit is not enabled.

[0030] Optionally, in some embodiments of this application, the structure to be connected is configured such that the fifth connection portion and the sixth connection portion are connected when the second detection circuit is enabled.

[0031] Optionally, in some embodiments of this application, the second detection pad and the third detection pad are the same detection pad.

[0032] Optionally, in some embodiments of this application, the display panel is configured for testing experiments.

[0033] The display panel of this application embodiment includes a first detection circuit, which is configured to detect data signals of a data line. The first detection circuit includes a first connection group, which includes a first connection portion and a second connection portion. The first connection portion and the second connection portion are disposed in different layers. The first connection group is configured such that the first connection portion and the second connection portion are insulated when the first detection circuit is not enabled.

[0034] Understandably, when the first detection circuit is not activated, the insulation between the first connection part and the second connection part in the first group to be connected is such that the first detection circuit is in an open circuit state. This prevents the line from the first group to be connected to the first detection pad in the first detection circuit from being connected in parallel with the data line, reducing the risk of impedance differences between the data lines and thus reducing the impact on the lamp test. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the insulation arrangement of the first connecting part and the second connecting part in the display panel provided in the embodiment of this application;

[0037] Figure 3 This is a schematic diagram of laser welding of the first connecting part and the second connecting part in the display panel provided in the embodiment of this application;

[0038] Figure 4 This is another structural schematic diagram of the display panel provided in the embodiments of this application;

[0039] Figure 5 This is a waveform diagram of the original data signal, the first data signal, and the second data signal in an embodiment of this application;

[0040] Figure 6 This is another structural schematic diagram of the display panel provided in the embodiments of this application;

[0041] Figure 7 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0042] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0043] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] It is understood that the display panel can be an electroluminescent panel, an electrophoretic panel, or a liquid crystal panel, etc. The following explanation uses a liquid crystal display panel as an example, but it is not limited to this.

[0045] Optionally, in some embodiments of this application, the display panel is configured for detection experiments. In this case, when the display panel detects in-plane data signals, the first detection circuit and the second detection circuit are switched from being in an inactive state to being in an active state.

[0046] Optionally, in some embodiments of this application, the display panel is configured to display a screen. It should be noted that when the display panel is configured as a component of a terminal product and displays a screen, the first and second detection circuits of the display panel are in an inactive state; or, when the display panel is configured as a component of a terminal product and displays a screen, the first and second detection circuits of the display panel are in an active state.

[0047] Please refer to Figure 1 This application provides a display panel 100, which includes a first detection circuit 10.

[0048] The first detection circuit 10 is configured to detect the data signal of the data line 101. The first detection circuit 10 includes a first connection group 11, which includes a first connection portion 111 and a second connection portion 112. The first connection portion 111 and the second connection portion 112 are disposed on different layers and at least partially overlap.

[0049] In this configuration, the first group to be connected 11 is set so that the first connection portion 111 and the second connection portion 112 are insulated when the first detection circuit 10 is not enabled. For example... Figure 2 As shown, an insulating layer y1 is provided between the first connecting part 111 and the second connecting part 112.

[0050] Understandably, when the first detection circuit 10 is not activated, the first connection portion 111 and the second connection portion 112 of the first group to be connected 11 are insulated, and the first detection circuit 10 is in an open circuit state. This ensures that the lines from the first group to be connected 11 to the first detection pad 123 in the first detection circuit 10 are not connected in parallel to the data line 101, reducing the risk of impedance differences between the data lines 101 and thus reducing the impact on the lighting test.

[0051] It should be noted that the lamp test is to test the display status of the display panel 100 when the display device of the display panel 100 is powered on, in order to verify the display performance of the display panel 100, such as brightness, contrast, color gamut, viewing angle and refresh rate.

[0052] Secondly, it should be noted that the first detection circuit 10 is activated after the lamp-lighting test.

[0053] Optionally, in some embodiments of this application, the first connecting portion 111 and the second connecting portion 112 are at least partially overlapped in the thickness direction of the display panel 100. When the first group to be connected 11 is configured such that the first connecting portion 111 and the second connecting portion 112 are laser-welded when the first detection circuit 10 is enabled, such as... Figure 3 As shown.

[0054] Understandably, when the first detection circuit 10 is activated, the connection between the first connecting part 111 and the second connecting part 112 forms a conductive path in the first detection circuit 10, facilitating the detection of the first data signal. Furthermore, the laser welding method used to connect the first connecting part 111 and the second connecting part 112 eliminates the need for large dimensions in this method, thus reducing the space requirements of the first connecting part 111 and the second connecting part 112.

[0055] Optionally, in some embodiments, the display panel 100 further includes a demultiplexing circuit 30, which includes a plurality of demultiplexing units 3a. Each demultiplexing unit 3a includes at least two thin-film transistors t1. The input terminals of the at least two thin-film transistors t1 are connected to the same signal input line 102, and the output terminal of each thin-film transistor t1 is connected to a data line 101.

[0056] Optionally, the data signal includes a first data signal and a second data signal. The first data signal is the signal output by the thin-film transistor t1 of the demultiplexing unit 3a, and the second data signal is the signal of the input signal input line 102. The second data signal is converted into the first data signal after passing through the thin-film transistor t1 of the demultiplexing unit 3a.

[0057] The first detection circuit 10 is configured to detect the first data signal transmitted from the output terminal of the thin-film transistor t1 of the demultiplexing unit 3a to the data line 101.

[0058] Optionally, the demultiplexing unit 3a may include two thin-film transistors t1, or three thin-film transistors t1, or four thin-film transistors t1, etc.

[0059] Optionally, in some embodiments, such as Figure 1 As shown, the control terminals of an odd number of thin-film transistors t1 are connected to the first control line k1, for example, the first, third, and fifth thin-film transistors t1 are connected to the first control line k1; the control terminals of an even number of thin-film transistors t1 are connected to the second control line k2, for example, the second, fourth, and sixth thin-film transistors t1 are connected to the second control line k2.

[0060] Optionally, in other embodiments, such as Figure 4As shown, the control terminals of the odd-array demultiplexing unit 3a can be connected to the first control line group, and the control terminals of the even-array demultiplexing unit 3a can be connected to the second control line group. In the demultiplexing unit 3a, the gate of each thin-film transistor t1 is connected to a corresponding control line. For example, the odd-array demultiplexing unit 3a includes three thin-film transistors t1, and the first control line group includes three control lines kz. In the odd-array demultiplexing unit 3a, the gate of the first thin-film transistor t1 is connected to the first control line kz, the gate of the second thin-film transistor t1 is connected to the second control line kz, and the gate of the third thin-film transistor t1 is connected to the third control line kz. The even-array demultiplexing unit 3a includes three thin-film transistors t1, and the second control line group includes three control lines kz. In the even-array demultiplexing unit 3a, the gate of the first thin-film transistor t1 is connected to the first control line kz, the gate of the second thin-film transistor t1 is connected to the second control line kz, and the gate of the third thin-film transistor t1 is connected to the third control line kz.

[0061] For example, the demultiplexing unit 3a of the odd-array includes two thin-film transistors t1, and the first control line group includes two control lines kz. In the demultiplexing unit 3a of the odd-array, the gate of the first thin-film transistor t1 is connected to the first control line kz, and the gate of the second thin-film transistor t1 is connected to the second control line kz. The demultiplexing unit 3a of the even-array includes two thin-film transistors t1, and the second control line group includes two control lines kz. In the demultiplexing unit 3a of the even-array, the gate of the first thin-film transistor t1 is connected to the first control line kz, and the gate of the second thin-film transistor t1 is connected to the second control line kz.

[0062] It is understood that the display panel 100 in this embodiment of the application uses a demultiplexing circuit 30, which can reduce the number of traces connecting the data lines 101. For example, one signal input line 102 can correspond to at least two data lines 101 through one demultiplexing unit 3a, so that the number of signal input lines 102 is reduced by at least 1 / 2.

[0063] Optionally, the thin-film transistor t1 can be either N-type or P-type. When t1 is N-type, its input terminal is the source and its output terminal is the drain. When t1 is P-type, its input terminal is the drain and its output terminal is the source. Figure 1 The illustration is based on an N-type thin-film transistor t1, but it is not limited to this example.

[0064] exist Figure 1 In the display panel 100, there are also scan lines 103 and pixel electrodes 104. The scan lines 103 are connected to the gate of a switching transistor t2, the data lines 101 are connected to the first end of the switching transistor t2, and the pixel electrodes 104 are connected to the second end of the switching transistor t2.

[0065] Please refer to Figure 1 and Figure 4 Optionally, in some embodiments of this application, the first detection circuit 10 includes a first trace 121, a second trace 122 and a first detection pad 123, the first trace 121 being located on one side of the demultiplexing circuit 30, and the first detection pad 123 being configured as a contact probe.

[0066] One end of the first trace 121 is connected to the output terminal of a thin-film transistor t1, and the other end of the first trace 121 is connected to the first connection part 111. One end of the second trace 122 is connected to the second connection part 112, and the other end of the second trace 122 is connected to the first detection pad 123.

[0067] Understandably, before the first detection circuit 10 is activated, the second trace 122 and the first detection pad 123 are not electrically connected to a data line 101. Therefore, since the first trace 121 is located on one side of the data line 101, the first trace 121 is close to the data line 101 it connects to, and the length of the first trace 121 is relatively short, the impedance difference between the data line 101 connected to the first detection circuit 10 and other data lines 101 can be reduced during the lighting test, thereby reducing the impact on the test results of the lighting test.

[0068] Optionally, the length of the first trace 121 is less than the length of the second trace 122. The length of the first trace 121 is less than or equal to 1 / 10 of the length of the second trace 122, such as 1 / 10, 1 / 11, 1 / 12, 1 / 13, 1 / 14 or 1 / 15, etc.

[0069] Optional, please refer to Figure 4 In some embodiments of this application, the display panel 100 further includes a common trace 105, which has a first common portion g1 shared with the second trace 122. A first cutting position q1 located outside the first common portion g1 is provided on the common trace 105.

[0070] The common trace 105 is configured to transmit a common voltage when the first detection circuit 10 is not enabled; when the first detection circuit 10 is enabled, the common trace 105 is cut off at the first cut position q1, so that the first detection circuit 10 forms a conductive path.

[0071] It is understandable that since the common trace 105 and the first detection circuit 10 share some traces, it is not necessary to design the common trace 105 and the first detection circuit 10 separately, so as to save the overall trace layout area.

[0072] When the first detection circuit 10 is not enabled, the common trace 105 transmits the common signal normally. When the first detection circuit 10 is to be enabled, the common trace 105 is cut at the first cut position q1, so that the first common part g1 is used to form a conductive path for the first detection circuit 10, while other parts of the common trace 105 are not connected to the first detection circuit 10, which can ensure the accuracy of the first detection circuit 10 in detecting the first data signal.

[0073] In addition, in some embodiments, a portion of the common trace 105 is used as part of the first detection circuit 10. Since the common trace 105 transmits a common signal, even if the first common portion g1 of the common trace 105 is cut off, its impact on the common signal on the surface is relatively small.

[0074] Optionally, in some embodiments of this application, the second trace 122 includes a first sub-section 12a and a second sub-section 12b, which are disposed on different layers and connected by a first via 12c. At least a portion of the second sub-section 12b is a first common portion g1. A first cut-off position q1 is disposed in the common trace 105 on the side of the first via 12c away from the first common portion g1 and adjacent to the first via 12c.

[0075] It is understandable that setting the first cutting position q1 on one side of the first via 12c allows the first via 12c to be used as a reference mark, making it easier to accurately cut the first cutting position q1.

[0076] Optionally, the first cutting position q1 of the common trace 105 can be cut using laser cutting. It should be understood that in the liquid crystal display panel, the first cutting position q1 is blocked by the opposing substrate, so other methods cannot be used for cutting.

[0077] Optionally, in some embodiments of this application, the display panel 100 further includes a second detection circuit 20, which is configured to detect a second data signal on the signal input line 102. The second detection circuit 20 includes a second connection group 21, which includes a third connection portion 211 and a fourth connection portion 212. The third connection portion 211 and the fourth connection portion 212 are disposed on different layers and at least partially overlap.

[0078] The second connection group 21 is configured such that when the second detection circuit 20 is not enabled, the third connection part 211 and the fourth connection part 212 are insulated, and when the second detection circuit 20 is enabled, the third connection part 211 and the fourth connection part 212 are laser welded.

[0079] It should be noted that by setting the first detection circuit 10 and the second detection circuit 20 to detect the second data signal of the thin-film transistor t1 of the demultiplexing circuit 30 and the first data signal output by the thin-film transistor t1 of the demultiplexing circuit 30 respectively, and based on the obtained first data signal and second data signal (e.g. Figure 5 As shown, the voltage loss of the data signal before and after the thin-film transistor t1 can be analyzed, and the electrical properties of the thin-film transistor t1 can be adjusted to improve the voltage loss value and increase the charging potential of the first data signal in the plane.

[0080] Secondly, after the thin-film transistor t1 is turned on, the signal input line 102 is electrically connected to the data line 101. Since the third connection portion 211 and the fourth connection portion 212 of the second connection group 21 are insulated when the second detection circuit 20 is not enabled, the second detection circuit 20 is in an open-circuit state. This prevents the lines from the second connection group 21 to the second detection pad 223 in the second detection circuit 20 from being connected in parallel to the signal input line 102, reducing the risk of impedance differences between the data lines 101 and thus reducing the impact on the lamp lighting test.

[0081] When the second detection circuit 20 is activated, the connection between the third connecting part 211 and the fourth connecting part 212 forms a conductive path in the second detection circuit 20, facilitating the detection of the second data signal. Furthermore, the third connecting part 211 and the fourth connecting part 212 are connected by laser welding. This method eliminates the need for the third connecting part 211 and the fourth connecting part 212 to have large dimensions, thus reducing their space requirements.

[0082] Optionally, in some embodiments of this application, the second detection circuit 20 includes a third trace 221, a fourth trace 222, and a second detection pad 223. The third trace 221 is located on one side of the demultiplexing circuit 30, and the second detection pad 223 is configured as a contact probe.

[0083] One end of the third trace 221 is connected to the signal input line 102, and the other end of the third trace 221 is connected to the third connector 211. One end of the fourth trace 222 is connected to the fourth connector 212, and the other end of the fourth trace 222 is connected to the second detection pad 223.

[0084] Understandably, before the second detection circuit 20 is activated, the fourth trace 222 and the second detection pad 223 are not electrically connected to a signal input line 102. Therefore, since the third trace 221 is located on one side of the signal input line 102, and the third trace 221 is close to the signal input line 102 it connects to, and the length of the third trace 221 is relatively short, the impedance difference between the data line 101 connected to the second detection circuit 20 and other data lines 101 can be reduced during the lamp lighting test, thereby reducing the impact on the test results of the lamp lighting test.

[0085] Optionally, the length of the third trace 221 is less than the length of the fourth trace 222. The shorter length of the third trace 221 reduces its impact on the data signal.

[0086] Optionally, in some embodiments of this application, the display panel 100 further includes a test line 106 and a third detection pad. The test line 106 is configured to transmit the stage transmission signal of the last stage of the gate drive circuit to the third detection pad. The test line 106 has a second common portion g2 shared with the fourth trace 222. A second cut-off position q2 located outside the second common portion g2 is provided on the test line 106.

[0087] Test line 106 is configured to transmit the stage transmission signal of the last stage of the gate drive circuit when the second detection circuit 20 is not enabled; when the second detection circuit 20 is enabled, test line 106 is cut off at the second cut position q2, so that the second detection circuit 20 forms a conductive path.

[0088] It is understandable that since the test line 106 and the second detection circuit 20 share some of the traces, it is not necessary to design the test line 106 and the second detection circuit 20 independently, so as to save the overall trace layout area.

[0089] When the second detection circuit 20 is not enabled, the test line 106 normally transmits the stage transmission signal of the last stage of the gate drive circuit. When the second detection circuit 20 is to be enabled, the test line 106 is cut at the second cut position q2, so that the second common part g2 is used to form a conductive path for the second detection circuit 20, while other parts of the test line 106 are not connected to the second detection circuit 20, which can ensure the accuracy of the second detection circuit 20 in detecting the second data signal.

[0090] In addition, in some embodiments, a portion of the test line 106 is used as part of the second detection circuit 20. Since the test line 106 is the trace for detecting the stage transmission signal of the gate drive circuit, the second common part g2 of the test line 106 is cut off after the gate drive circuit is detected, and it no longer has any impact on the detection of the gate drive circuit.

[0091] Optionally, in some embodiments of this application, the fourth trace 222 includes a third sub-section 22a and a fourth sub-section 22b, which are disposed in different layers. The third sub-section 22a and the fourth sub-section 22b are configured to be connected via a connection structure 23. At least a portion of the fourth sub-section 22b is a second common portion g2, and a second cut-off position q2 is disposed on the side of the test line 106 away from the second common portion g2.

[0092] Optionally, the second cutting position q2 of the test line 106 can be laser-cut.

[0093] Optionally, in some embodiments, the structure 23 to be connected is a via.

[0094] Optionally, in some embodiments of this application, the structure to be connected 23 is located on one side of the test line 106. The structure to be connected 23 includes a fifth connecting portion 23a and a sixth connecting portion 23b disposed in different layers, and the fifth connecting portion 23a and the sixth connecting portion 23b at least partially overlap. The fifth connecting portion 23a is connected to the third sub-portion 22a. One end of the fourth sub-portion 22b is connected to the sixth connecting portion 23b, and the other end of the fourth sub-portion 22b is connected to the second detection pad 223.

[0095] When the structure to be connected 23 is configured such that the fifth connection portion 23a and the sixth connection portion 23b are insulated when the second detection circuit 20 is not enabled; when the second detection circuit 20 is enabled, the fifth connection portion 23a and the sixth connection portion 23b are laser welded.

[0096] It is understandable that by setting up the laser-welded connection structure 23, when the gate drive circuit is detected, the fifth connection part 23a and the sixth connection part 23b are insulated, so that the line from the third sub-part 22a to the third trace 221 and the test line 106 are disconnected, reducing the impact of the second detection circuit 20 on the detection of the gate drive circuit.

[0097] Optionally, in some embodiments of this application, the second detection pad 223 and the third detection pad are the same detection pad. That is, the second common part g2 is connected to the second detection pad 223.

[0098] It is understandable that the second detection pad 223 and the third detection pad are the same detection pad in order to save one detection pad and thus save layout area.

[0099] exist Figure 6 middle, Figure 6 This is another structural schematic diagram of the display panel according to an embodiment of this application. Figure 6 The parts that differ from the above embodiments will be described in order to avoid redundancy.

[0100] exist Figure 6 middle, Figure 6 The first detection pad 123 and the second detection pad 223 are not shown. In some embodiments of this application, each data line 101 and the output terminal of the thin-film transistor t1 electrically connected thereto are connected via a lead 107. The first detection circuit 10 includes a first trace 121, a second trace 122, and a first detection pad 123, wherein the first trace 121 and the lead 107 are disposed on different layers. One end of the second trace 122 is connected to the first trace 121, and the other end of the second trace 122 is connected to the first detection pad 123, wherein the first detection pad 123 is configured as a contact probe.

[0101] In the display panel 100 viewed from above, the extension direction of the first trace 121 intersects the extension direction of the lead wire 107. Multiple lead wires 107 partially overlap with the same first trace 121. The portion of the first trace 121 that overlaps with the lead wire 107 is reused as a first connection portion 111, and the portion of the lead wire 107 that overlaps with the first trace 121 is reused as a second connection portion 112.

[0102] It is understandable that multiple leads 107 are used to partially overlap with the same first trace 121, and the overlapping portions of the leads 107 and the first trace 121 form a first group to be connected 11, so that each data line 101 corresponds to a first group to be connected 11. Therefore, the first detection circuit 10 can detect the first data signal of any data line 101. That is, whichever data line 101 needs to be detected, the first group to be connected 11 can be connected by laser. For example, if the first data signal of the second data line 101 needs to be detected, then the lead 107 connected to the second data line 101 and the first trace 121 can be connected by laser.

[0103] Secondly, the data lines 101 can be detected sequentially from the last data line 101 to the first data line 101, following their arrangement. For example, after detecting the last data line 101, a laser can be used to cut the portion of the first trace 121 that is electrically connected to the last data line 101, thus cutting off the first group 11 to be connected corresponding to the last data line 101. Then the second-to-last data line 101 can be detected, and so on, so that all data lines 101 can be detected.

[0104] Optionally, in some embodiments, the common trace 105 has a first common portion g1 shared with the second trace 122. The common trace 105 is provided with a first cutting position q1 located outside the first common portion g1.

[0105] When the first detection circuit 10 is not enabled, the common trace 105 transmits the common signal normally. When the first detection circuit 10 is to be enabled, the common trace 105 is cut at the first cut position q1, so that the first common part g1 is used to form a conductive path for the first detection circuit 10, while other parts of the common trace 105 are not connected to the first detection circuit 10, which can ensure the accuracy of the first detection circuit 10 in detecting the first data signal.

[0106] Optionally, in some embodiments of this application, the second trace 122 includes a first sub-section 12a and a second sub-section 12b, which are disposed on different layers and connected by a first via 12c. At least a portion of the second sub-section 12b is a first common portion g1. A first cut-off position q1 is disposed in the common trace 105 on the side of the first via 12c away from the first common portion g1 and adjacent to the first via 12c.

[0107] It is understandable that setting the first cutting position q1 on one side of the first via 12c allows the first via 12c to be used as a reference mark, making it easier to accurately cut the first cutting position q1.

[0108] Optionally, in some embodiments, the common trace 105 has a third common portion g3 shared with the fourth trace 222. The first common portion g1 includes the third common portion g3 and an extension g11, the extension g11 connecting the third common portion g3 and the first via 12c, and the common trace 105 is provided with a second cut position q2 located on the extension g11.

[0109] The common trace 105 is configured to transmit a common voltage when the first detection circuit 10 and the second detection circuit 20 are not enabled; when the second detection circuit 20 is enabled, the extension g11 is cut off at the second cutting position q2, so that the second detection circuit 20 forms a conductive path.

[0110] It is understandable that the common trace 105, the first detection circuit 10, and the second detection circuit 20 share some traces, so it is not necessary to design the common trace 105 and the first detection circuit 10 separately, in order to save the overall trace layout area.

[0111] It should be noted that the lighting test is performed first, followed by the detection by the first detection circuit 10, and then the detection by the second detection circuit 20. When the first detection circuit 10 and the second detection circuit 20 are not activated, the common trace 105 transmits the common signal normally. When the first detection circuit 10 is to be activated, the common trace 105 is cut at the first cutting position q1, so that the first common part g1 is used to form a conductive path for the first detection circuit 10, while other parts of the common trace 105 are not connected to the first detection circuit 10, which ensures the accuracy of the first detection circuit 10 in detecting the first data signal. When the second detection circuit 20 is to be activated, the extension g11 of the common trace 105 is cut at the second cutting position q2, so that the third common part g3 is used to form a conductive path for the second detection circuit 20, while other parts of the common trace 105 are not connected to the second detection circuit 20, which ensures the accuracy of the second detection circuit 20 in detecting the second data signal.

[0112] Optionally, in some embodiments of this application, the fourth trace 222 includes a third sub-section 22a and a fourth sub-section 22b, which are disposed on different layers and connected by a second via 12d. At least a portion of the fourth sub-section 22b is a third common portion g3. A second cut position q2 is disposed in the extension g11 on the side of the second via 12d away from the third common portion g3 and adjacent to the second via 12d.

[0113] It is understandable that setting the second cutting position q2 on one side of the second via 12d allows the second via 12d to be used as a reference mark, making it easier to accurately cut the second cutting position q2.

[0114] Optionally, the second cutting position q2 of the common trace 105 can be cut using laser cutting. It should be understood that in the liquid crystal display panel, the second cutting position q2 is blocked by the opposing substrate, so other methods cannot be used for cutting.

[0115] Optionally, in some embodiments, the structure of the second detection circuit 20 and its association with the test line 106 can also be the same as described above. Figures 1 to 5 The structure of the second detection circuit 20 in any corresponding embodiment is the same, so it will not be described again here. Please refer to the following for details. Figures 1 to 5 The explanation.

[0116] Please refer to Figure 7 The display device 1000 of this application embodiment includes a display panel 100 as described in any of the above embodiments.

[0117] It should be noted that in some embodiments, the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 in the non-activated state of the first detection circuit 10 and the second detection circuit 20 in the application embodiment. For details, please refer to the relevant descriptions of the non-activated state of the first detection circuit 10 and the second detection circuit 20. Figures 1 to 6 Therefore, it will not be elaborated further here.

[0118] In other embodiments, the structure of the display panel 100 of the display device 1000 of this application embodiment is similar to or the same as the structure of the display panel 100 of the present application embodiment. That is, the display panel 100 of the display device 1000 of this application embodiment also has a state structure in which the first detection circuit 10 and the second detection circuit 20 are not activated, and a state structure in which the first detection circuit 10 and the second detection circuit are activated. Specific details can be found by referring to the display panel 100 of any of the above embodiments, and therefore will not be repeated here.

[0119] Optionally, the display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptops, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, and ultra-mobile personal computers.

[0120] Furthermore, the display device 1000 according to some embodiments can be applied to wearable devices and can be used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays. Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays arranged on instrument panels, interior mirror displays replacing side mirrors in automobiles, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0121] The display device 1000 of this application embodiment includes a demultiplexing circuit 30 and a first detection circuit 10. Each demultiplexing unit 3a includes at least two thin-film transistors t1. The input terminals of the at least two thin-film transistors t1 are connected to the same signal input line 102, and the output terminal of each thin-film transistor t1 is connected to a data line 101. The first detection circuit 10 is configured to detect a first data signal transmitted from the output terminal of the thin-film transistor t1 of the demultiplexing unit 3a to the data line 101. The first detection circuit 10 includes a first connection group 11, which includes a first connection portion 111 and a second connection portion 112. The first connection portion 111 and the second connection portion 112 are disposed on different layers and at least partially overlap. The first connection group 11 is configured such that the first connection portion 111 and the second connection portion 112 are insulated when the first detection circuit 10 is not enabled.

[0122] Understandably, when the first detection circuit 10 is not activated, the first connection portion 111 and the second connection portion 112 of the first connection group 11 are insulated from each other, and the first detection circuit 10 is in an open circuit state. This prevents the lines from the first connection group 11 to the first detection pad 123 in the first detection circuit 10 from being connected in parallel with the data line 101, reducing the risk of impedance differences between the data lines 101 and thus reducing the impact on the lighting test.

[0123] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: The demultiplexing circuit includes multiple demultiplexing units, each of which includes at least two thin-film transistors. The input terminals of the at least two thin-film transistors are connected to the same signal input line, and the output terminal of each thin-film transistor is connected to a data line. A first detection circuit is configured to detect a first data signal at the output terminal of the thin-film transistor. The first detection circuit includes a first group to be connected, the first group to be connected includes a first connection portion and a second connection portion, the first connection portion and the second connection portion are disposed in different layers and at least partially overlap. The second detection circuit is configured to detect the second data signal of the signal input line; When the first connection group is configured to be disconnected, the first connection portion and the second connection portion are insulated.

2. The display panel according to claim 1, characterized in that, The first detection circuit includes a first trace, a second trace, and a first detection pad. The first trace is located on one side of the demultiplexing circuit, and the first detection pad is configured as a contact probe. One end of the first trace is connected to the output terminal of the thin-film transistor, the other end of the first trace is connected to the first connection portion, one end of the second trace is connected to the second connection portion, and the other end of the second trace is connected to the first detection pad.

3. The display panel according to claim 1, characterized in that, Each of the data lines and the output terminal of the thin-film transistor electrically connected thereto are connected by a lead wire. The first detection circuit includes a first trace, a second trace, and a first detection pad. The first trace and the lead wire are disposed on different layers. One end of the second trace is connected to the first trace, and the other end of the second trace is connected to the first detection pad. The first detection pad is configured as a contact probe. In the display panel viewed from above, the extension direction of the first trace intersects with the extension direction of the lead wire, and multiple leads wires overlap with the same portion of the first trace. The portion of the first trace that overlaps with the lead wire is reused as the first connection portion, and the portion of the lead wire that overlaps with the first trace is reused as the second connection portion.

4. The display panel according to any one of claims 2 to 3, characterized in that, When the first connection group is configured to enable the first detection circuit, the first connection part and the second connection part are connected.

5. The display panel according to claim 4, characterized in that, When the first connection group is configured to enable the first detection circuit, the first connection portion and the second connection portion are laser welded.

6. The display panel according to claim 2 or 3, characterized in that, The display panel also includes a common trace, which has a first common portion shared with the second trace; The common trace is configured to transmit a common voltage when the first detection circuit is not enabled.

7. The display panel according to claim 6, characterized in that, The common trace is provided with a first cutting position located outside the first common part. The common trace is configured to cut the common trace at the first cutting position when the first detection circuit is enabled, so that the first detection circuit forms a conductive path.

8. The display panel according to claim 7, characterized in that, The second trace includes a first sub-section and a second sub-section, which are disposed on different layers and connected by a first via. At least a portion of the second sub-section is the first common section, and the first cut position is disposed in the common trace on the side of the first via away from the first common section and adjacent to the first via.

9. The display panel according to claim 8, characterized in that, The second detection circuit includes a second group to be connected, the second group to be connected includes a third connection part and a fourth connection part, the third connection part and the fourth connection part are disposed on different layers and at least partially overlap; When the second group to be connected is configured to not enable the second detection circuit, the third connection portion and the fourth connection portion are insulated.

10. The display panel according to claim 9, characterized in that, When the second group to be connected is configured to enable the second detection circuit, the third connection part and the fourth connection part are connected.

11. The display panel according to claim 9, characterized in that, The second detection circuit includes a third trace, a fourth trace, and a second detection pad. The third trace is located on one side of the demultiplexing circuit, and the second detection pad is configured as a contact probe. One end of the third trace is connected to the signal input line, and the other end of the third trace is connected to the third connection part. One end of the fourth trace is connected to the fourth connection part, and the other end of the fourth trace is connected to the second detection pad.

12. The display panel according to claim 11, characterized in that, The display panel further includes a test line and a third detection pad. The test line is configured to transmit the stage transmission signal of the last stage of the gate drive circuit to the third detection pad. The test line has a second common portion shared with the fourth trace. The test line is configured to transmit the stage transmission signal of the last stage of the gate drive circuit when the second detection circuit is not enabled.

13. The display panel according to claim 12, characterized in that, The test line is provided with a second cutting position located outside the second common part. The test line is configured to cut at the second cutting position when the second detection circuit is enabled, so that the second detection circuit forms a conductive path.

14. The display panel according to claim 13, characterized in that, The fourth trace includes a third sub-section and a fourth sub-section, which are disposed in different layers and configured to be connected by a connection structure. At least a portion of the fourth sub-section is the second common section, and the second cut position is located on the side of the test trace away from the second common section.

15. The display panel according to claim 14, characterized in that, The structure to be connected is located on one side of the test line. The structure to be connected includes a fifth connecting part and a sixth connecting part arranged in different layers. The fifth connecting part and the sixth connecting part overlap at least partially. The fifth connecting part is connected to the third sub-part. One end of the fourth sub-part is connected to the sixth connecting part. The other end of the fourth sub-part is connected to the second detection pad. When the structure to be connected is configured such that the fifth connection portion and the sixth connection portion are insulated when the second detection circuit is not enabled.

16. The display panel according to claim 15, characterized in that, The structure to be connected is configured such that the fifth connection part and the sixth connection part are connected when the second detection circuit is enabled.

17. The display panel according to claim 15, characterized in that, The second detection pad and the third detection pad are the same detection pad.

18. The display panel according to claim 15, characterized in that, The display panel is configured for use in testing experiments.

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