Clock phase selection circuit, chip, clock phase selection method and electronic equipment

Abstract

The invention relates to a clock phase selection circuit, a chip, a clock phase selection method and an electronic device, and the circuit comprises a clock selection module which is used for selecting n selection signals in each clock period according to the sequence of n selection signals, selecting one of n clock signals with the same frequency and different phases as an input clock signal of the corresponding phase, and generating n effective clock signals according to each selection signal and the selected input clock signal of the corresponding phase; and the output module is used for performing logical operation processing on the n effective clock signals to generate an output clock signal. Under the control of the selection signal, the clock signals with different phases are selected as the input clock signals without burrs in each clock period, so that stable operation of a chip system can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of clock technology, and in particular to a clock phase selection circuit, a chip, a clock phase selection method and an electronic device. Background Art

[0002] In digital circuit design, the phase selection of the clock signal is crucial, as it ensures the synchronization and stability of the clock signal, thereby guaranteeing the normal operation of the digital circuit. However, in practical applications, when the multiplexer is used directly for clock switching, clock switching glitches are prone to occur. This glitch phenomenon can cause the chip system to enter a metastable state, affecting the normal operation of the chip system.

[0003] Therefore, how to achieve single-cycle glitch-free clock phase selection is a problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a clock phase selection circuit, a chip, a clock phase selection method and an electronic device. The technical solution of the present application is as follows:

[0005] The first embodiment of the present application provides a clock phase selection circuit, including:

[0006] A clock selection module, configured to select, in each clock cycle, one of n clock signals having the same frequency but different phases as an input clock signal of a corresponding phase according to a sequence of n selection signals, and generate n valid clock signals according to each of the selection signals and the selected input clock signal of the corresponding phase; wherein n is a positive integer greater than or equal to 2;

[0007] An output module, wherein the input end of the output module is connected to the output end of the clock selection module, and the output module is used to perform logic operation processing on the n valid clock signals to generate an output clock signal.

[0008] A second embodiment of the present application provides a chip, comprising: a clock phase selection circuit as described above.

[0009] The third aspect of the present application provides a clock phase selection method, including:

[0010] In each clock cycle, according to a sequence of n selection signals, one is selected from n clock signals with the same frequency but different phases as an input clock signal of a corresponding phase, and n valid clock signals are generated according to each of the selection signals and the selected input clock signal of the corresponding phase; wherein n is a positive integer greater than or equal to 2;

[0011] Perform logic operation processing on the n valid clock signals to generate an output clock signal.

[0012] The fourth aspect of the present application proposes an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the above-mentioned clock phase selection method is implemented.

[0013] The fifth aspect embodiment of the present application proposes a non-temporary computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the above-mentioned clock phase selection method are implemented.

[0014] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0015] The clock phase selection circuit, chip, electronic device and clock phase selection method of the embodiment of the present application select one clock signal of the corresponding phase from the n clock signals with the same frequency but different phases according to the sequence of n selection signals in each clock cycle through the clock selection module, and generate n valid clock signals according to each selection signal and the selected input clock signal of the corresponding phase, and perform logical operation processing on the n valid clock signals through the output module to generate an output clock signal. Under the control of the selection signal, the present application selects clock signals of different phases as input clock signals without glitches in each clock cycle, thereby ensuring the stable operation of the chip system.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute improper limitations on the present application.

[0018] Figure 1 is a schematic diagram of a clock phase selection circuit according to an embodiment of the present application;

[0019] Figure 2 is a circuit diagram of a clock phase selection circuit according to an embodiment of the present application;

[0020] Figure 3 is a working timing diagram of a clock phase selection circuit according to an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a chip according to an embodiment of the present application;

[0022] Figure 5 is a flow chart of a clock phase selection method according to an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to enable ordinary persons in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0026] The clock phase selection circuit, chip, clock phase selection method and electronic device of the embodiments of the present application are described below with reference to the accompanying drawings.

[0027] Figure 1 is a schematic diagram of a clock phase selection circuit according to an embodiment of the present application.

[0028] like Figure 1 As shown, the clock phase selection circuit 100 of the embodiment of the present application includes: a clock selection module 101 and an output module 102.

[0029] The clock selection module 101 is used to select one of the n clock signals clk_p[0:(n-1)] with the same frequency but different phases as the input clock signal of the corresponding phase in each clock cycle according to the sequence of n selection signals en[0:(n-1)], and generate n valid clock signals clk_gate_p[0:(n-1)] according to each selection signal and the selected input clock signal of the corresponding phase; wherein n is a positive integer greater than or equal to 2. The input end of the output module 102 is connected to the output end of the clock selection module 101, and the output module 102 is used to perform logic operation processing on the n valid clock signals clk_gate_p[0:(n-1)] to generate an output clock signal clk_out.

[0030] In this embodiment, the clock selection module 101 uses the selection signal en[0:(n-1)] to select the clock signal clk_p[0:(n-1)] with the same frequency but different phase in each clock cycle, and different selection signal sequences select different clock signal outputs, thereby realizing single-cycle glitch-free phase clock selection, and passing the generated valid clock signal clk_gate_p[0:(n-1)] to the output module 102. The output module 102 performs logical operation processing on the valid clock signal clk_gate_p[0:(n-1)] generated by the clock selection module 101, such as aggregation processing through a three-level OR gate, to generate an output clock signal clk_out, and completes the aggregation and output of the glitch-free phase selection result.

[0031] Therefore, the clock phase selection circuit 100 of the present application, under the control of the selection signal en[0:(n-1)], selects the clock signal clk_p[0:(n-1)] of different phases as the input clock signal without glitch in each clock cycle, thereby ensuring the stable operation of the chip system.

[0032] Combine the following Figure 2 The clock phase selection circuit 100 according to the embodiment of the present application is described.

[0033] like Figure 2 As shown, the clock selection module 101 includes: a first clock selection unit 103 , a second clock selection unit 104 and a third clock selection unit 105 .

[0034] The first clock selection unit 103 is used to generate a first valid clock signal clk_gate_p[0] according to a first selection signal en[0] and a first phase input clock signal clk_p[0]. The second clock selection unit 104 is used to use the first phase input clock signal clk_p[0] as a reference clock signal, and to generate second valid clock signals to i-th valid clock signals clk_gate_p[1:(i-1)] according to the second selection signal to i-th selection signal en[1:(i-1)] and the second phase input clock signal to i-th phase input clock signal clk_p[1:(i-1)]; wherein i is an integer greater than or equal to 1 and less than or equal to (n-1) / 2 rounded down. The third clock selection unit 105 is used to use the first phase input clock signal clk_p[0] as a reference clock signal, and generate the (i+1)th valid clock signal to the nth valid clock signal clk_gate_p[i:(n-1)] according to the (i+1)th selection signal to the nth selection signal en[i:(n-1)] and the (i+1)th phase input clock signal to the nth phase input clock signal clk_p[i:(n-1)].

[0035] like Figure 2 As shown, the first clock selection unit 103 includes: a first clock gating subunit 106; wherein, the enable terminal EN of the first clock gating subunit 106 receives the first selection signal en[0]; the clock terminal CP of the first clock gating subunit 106 receives the first phase input clock signal clk_p[0]; the first clock gating subunit 106 generates a first effective clock signal clk_gate_p[0] according to the first selection signal en[0] and the first phase input clock signal clk_p[0]; the output terminal Q of the first clock gating subunit 106 outputs the first effective clock signal clk_gate_p[0].

[0036] like Figure 2 As shown, the second clock selection unit 104 includes: a first trigger 107, a second trigger 108 and a second clock gating subunit 109; wherein, the input terminal D of the first trigger 107 receives the second selection signal to the i-th selection signal en[1:(i-1)]; the clock terminal CP of the first trigger 107 receives the first phase input clock signal clk_p[0] as a reference clock signal; the output terminal Q of the first trigger 107 is connected to the input terminal D of the second trigger 108; the clock terminal CP of the second trigger 108 receives the clock signal clkb_p[0] which is opposite in phase to the first phase input clock signal clk_p[0]; the output terminal Q of the second trigger 108 is connected to the enable terminal EN of the second clock gating subunit 109; the i-th selection signal en[1:(i-1)] is received by the second trigger 107; the clock terminal CP of the first trigger 107 receives the first phase input clock signal clk_p[0] as a reference clock signal; the output terminal Q of the second trigger 108 is connected to the enable terminal EN of the second clock gating subunit 109; the i-th selection signal en[1:(i-1)] is received by the second trigger 108; the clock terminal CP of the second trigger 108 receives the first phase input clock signal clkb_p[0] which is opposite in phase to the first phase input clock signal clk_p[0]; the output terminal Q of the second trigger 108 is connected to the enable terminal EN of the second clock gating subunit 109; the i-th selection signal en[1:(i-1)] is received by the second trigger 107; the clock terminal CP of the second trigger 108 receives the first phase input clock signal clkb_p[0] as a reference clock signal; the clock terminal CP of the second trigger 108 receives the first phase input clock signal clkb_p[0] as a reference The clock terminal CP of the second clock gating subunit 109 receives the second phase input clock signal to the i-th phase input clock signal clk_p[1:(i-1)]; the second clock gating subunit 109 uses the first phase input clock signal clk_p[0] as the reference clock signal, and generates the second valid clock signal to the i-th valid clock signal clk_gate_p[1:(i-1)] according to the second phase selection signal to the i-th phase selection signal and the second phase input clock signal to the i-th phase input clock signal clk_p[1:(i-1)] output by the second flip-flop 108; the output terminal Q of the second clock gating subunit 109 outputs the second valid clock signal to the i-th valid clock signal clk_gate_p[1:(i-1)].

[0037] like Figure 2As shown, the third clock selection unit 105 includes: a third flip-flop 110 and a third clock gating subunit 111; wherein the input terminal D of the third flip-flop 110 receives the (i+1)th selection signal to the nth selection signal en[i:(n-1)]; the clock terminal CP of the third flip-flop 110 receives the first phase input clock signal clk_p[0] as a reference clock signal; the output terminal Q of the third flip-flop 110 is connected to the enable terminal EN of the third clock gating subunit 111; the clock terminal CP of the third clock gating subunit 111 receives the (i+1)th phase input clock signal to the nth phase input clock signal clk_p[i:(n- 1)]; the third clock gating subunit 111 takes the first phase input clock signal clk_p[0] as the reference clock signal, and generates the (i+1)th effective clock signal to the nth effective clock signal clk_gate_p[i:(n-1)] according to the (i+1)th phase selection signal to the nth phase selection signal and the (i+1)th phase input clock signal to the nth phase input clock signal clk_p[i:(n-1)] output by the third flip-flop 110; the output terminal Q of the third clock gating subunit 111 outputs the (i+1)th effective clock signal to the nth effective clock signal clk_gate_p[i:(n-1)].

[0038] The clock selection module 102 of the present application fully considers the clock phase of each input clock signal, and can widen the upper limit of the operating frequency; for clocks without phase intervals, the first clock gating subunit 106 is directly used to complete the selection of the clock phase in accordance with a synchronous design method; for clocks with a phase interval less than half an input clock cycle, a first trigger 107 driven by the rising edge of the input clock signal and a second trigger 108 driven by the falling edge of the input clock signal are cascaded to shift the phase of the selection signal by half an input clock cycle, and the cascade is used as an enable signal of the second clock gating subunit 109 to complete the selection of the input clock phase. This design increases the timing margin between the selection signal and the selected input clock signal, relaxes the timing constraints, and widens the upper limit of the operating frequency; for clocks with a phase interval greater than half an input clock cycle, a third trigger 110 driven by the rising edge of the input clock signal is used in accordance with a synchronous design method, and the output of the third trigger 110 is used as the enable signal of the third clock gating subunit 111 to complete the selection of the input clock phase. This design simplifies the timing constraint requirements for the selection signal.

[0039] like Figure 2As shown, the output module 102 includes: a first OR gate 115; wherein the first input end of the first OR gate 115 receives a first valid clock signal clk_gate_p[0]; the second input end of the first OR gate 115 receives a valid clock signal from the second valid clock signal to the i-th valid clock signal clk_gate_p[1:(i-1)]; the third input end of the first OR gate 115 receives a valid clock signal from the (i+1)th valid clock signal to the n-th valid clock signal clk_gate_p[i:(n-1)]; the first OR gate 115 performs an OR operation on the first valid clock signal clk_gate_p[0], a valid clock signal from the second valid clock signal to the i-th valid clock signal clk_gate_p[1:(i-1)], and a valid clock signal from the (i+1)th valid clock signal to the n-th valid clock signal clk_gate_p[i:(n-1)] to generate an output clock signal clk_out; the output end of the first OR gate 115 outputs the output clock signal clk_out.

[0040] like Figure 2 As shown, the output module 102 also includes: a second OR gate 112, a third OR gate 113 and a fourth OR gate 114; wherein, the input end of the second OR gate 112 is connected to the output end Q of the first clock gating subunit 106, and the output end of the second OR gate 112 is connected to the first input end of the first OR gate 115; the input end of the third OR gate 113 is connected to the output end Q of the second clock gating subunit 109, and the output end of the third OR gate 113 is connected to the second input end of the first OR gate 115; the input end of the fourth OR gate 114 is connected to the output end Q of the third clock gating subunit 111, and the output end of the fourth OR gate 114 is connected to the third input end of the first OR gate 115.

[0041] The output module 102 of the phase selection result of the present application adopts a non-uniform logic circuit (a non-uniform logic circuit refers to a circuit that does not rely on the proportional relationship of the transistor size to realize the logic function, so as to ensure that only one path is turned on at any time, rather than both being turned on at the same time) to achieve this, so that the rising and falling edges of the output clock are more balanced, less affected by factors such as process, voltage, and temperature, and the output clock quality is better, with a duty cycle variation of less than 0.5%, and a clock jitter of less than 0.5ps. The high-quality output clock signal clk_out can also reduce the difficulty of timing convergence in the chip system, so that the operating frequency of the chip system can converge to a higher frequency.

[0042] Let's take n=8 as an example. Figure 3 The working sequence of the clock phase selection circuit 100 of the present application is described.

[0043] It should be noted that, when n=8, i=3.

[0044] like Figure 3 As shown, in the transparent transmission mode, the first clock selection unit 103 is enabled, the second clock selection unit 104 and the third clock selection unit 105 are not enabled, the phase of the output clock clk_out is consistent with the phase of the first phase input clock signal clk_p[0], and the frequency of the output clock clk_out is consistent with the frequency of the first phase input clock signal clk_p[0], that is, it remains unchanged.

[0045] In the frequency reduction defense mode, the first clock selection unit 103, the second clock selection unit 104, and the third clock selection unit 105 sequentially enable the selection signal clk_p[0:7], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0], including the following steps:

[0046] Step 1: In the first cycle, the first clock selection unit 103 is enabled, the first clock gating subunit 106 is turned on, and the phase of the output clock clk_out is consistent with the phase of the first phase input clock signal clk_p[0];

[0047] Step 2: In the second cycle, the second clock selection unit 104 is enabled, the second clock gating subunit 109 of the second phase input clock signal clk_p[1] path is turned on, the enable signal establishment time margin is 5 phase intervals, the holding time margin is 3 phase intervals, the output clock clk_out is consistent with the second phase input clock signal clk_p[1], and the output clock clk_out frequency is 8 / 9 of the first phase input clock signal clk_p[0] frequency;

[0048] Step 3: In the third cycle, the second clock selection unit 104 is enabled, and the second clock gating subunit 109 of the path of the third phase input clock signal clk_p[2] is turned on. The enable signal setup time margin is 6 phase intervals, and the hold time margin is 2 phase intervals. The phase of the output clock clk_out is consistent with the phase of the third phase input clock signal clk_p[2], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0].

[0049] Step 4: In the fourth cycle, the second clock selection unit 104 is enabled, the second clock gating subunit 109 of the path of the fourth phase input clock signal clk_p[3] is turned on, the enable signal establishment time margin is 7 phase intervals, the holding time margin is 1 phase interval, the phase of the output clock clk_out is consistent with the phase clk_p[3] of the fourth phase input clock signal, and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0050] Step 5: In the fifth cycle, the third clock selection unit 105 is enabled, the third clock gating subunit 111 of the path of the fifth phase input clock signal clk_p[4] is turned on, the enable signal establishment time margin is 4 phase intervals, the holding time margin is 4 phase intervals, the phase of the output clock clk_out is consistent with the phase of the fifth phase input clock signal clk_p[4], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0051] Step 6: In the sixth cycle, the third clock selection unit 105 is enabled, the third clock gating subunit 111 of the path of the sixth phase input clock signal clk_p[5] is turned on, the enable signal establishment time margin is 5 phase intervals, the holding time margin is 3 phase intervals, the phase of the output clock clk_out is consistent with the phase of the sixth phase input clock signal clk_p[5], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0052] Step 7: In the seventh cycle, the third clock selection unit 105 is enabled, the third clock gating subunit 111 of the path of the seventh phase input clock signal clk_p[6] is turned on, the enable signal establishment time margin is 6 phase intervals, the holding time margin is 2 phase intervals, the phase of the output clock clk_out is consistent with the phase of the seventh phase input clock signal clk_p[6], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0053] Step 8: In the eighth cycle, the third clock selection unit 105 is enabled, the third clock gating subunit 111 of the path of the eighth phase input clock signal clk_p[7] is turned on, the enable signal establishment time margin is 7 phase intervals, the holding time margin is 1 phase interval, the phase of the output clock clk_out is consistent with the phase of the eighth phase input clock signal clk_p[7], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0054] Step 9: In the ninth cycle, the first clock selection unit 103 is enabled, the first clock gating subunit 106 is turned on, the phase of the output clock clk_out is consistent with the phase of the first phase input clock signal clk_p[0], and the frequency of the output clock clk_out is 8 / 9 of the frequency of the first phase input clock signal clk_p[0];

[0055] Step 10: In the tenth cycle, the first clock selection unit 103 is enabled, the first clock gating subunit 106 is turned on, the phase of the output clock clk_out is consistent with the phase of the first phase input clock signal clk_p[0], and the frequency of the output clock clk_out is restored to be consistent with the frequency of the first phase input clock signal clk_p[0].

[0056] Therefore, for the first phase input clock signal clk_p[0], considering that it is consistent with the clock domain where the selection signal en[0] is located, a first clock gating subunit 106 can be used to complete clock gating and closing control, thereby achieving the single-cycle phase selection requirement;

[0057] For the second phase input clock signal to the fourth phase input clock signal clk_p[1:3], considering the inconsistency with the clock domain where the second selection signal to the fourth selection signal en[1:3] are located (the clock phase difference is one to three phase intervals), a positive and negative edge tapping scheme is adopted to achieve signal synchronization. The specific steps of the positive and negative edge beat scheme are as follows: first use the rising edge of the first phase input clock signal clk_p[0] to perform the first sampling (i.e., beat) on the second selection signal to the fourth selection signal en[1:3], thereby relaxing the timing constraints with the outside; then use the anti-clock clkb_p[0] with the opposite phase to the first phase input clock signal to perform the second sampling on the second selection signal to the fourth selection signal en[1:3]), thereby relaxing the timing constraints of the second clock gating subunit 109 enable signal and the second phase input clock signal to the fourth phase input clock signal clk_p[1:3], so that the timing margin of the setup time is increased by more than half a cycle, the timing margin of the setup time is between five and seven phase intervals, and the timing margin of the hold time is between one and three phase intervals;

[0058] For the fifth phase input clock signal to the eighth phase input clock signal clk_p[4:7], since they are inconsistent with the clock domain where the fifth selection signal to the eighth selection signal en[4:7] are located (the input clock signal differs by four to seven phase intervals), a synchronous design scheme is adopted to ensure the correct transmission of the signal. The specific implementation is as follows: the fifth selection signal to the eighth selection signal en[4:7] is sampled once using the rising edge of the first phase input clock signal clk_p[0] to relax the timing constraints with the outside, and the signal after synchronization processing is directly used as the enable signal of the third clock gating subunit 111. Through the synchronous design scheme, the timing margin of time can be established at four to seven phase intervals, and the timing margin of time can be maintained at one to four phase intervals.

[0059] The clock phase selection circuit 100 of the present application is based on the structure of a trigger and a clock gating subunit, and can achieve single-cycle glitch-free phase selection with a fast response speed. Under abnormal circumstances, the output clock signal clk_out will not generate glitches. Combined with the timing characteristics, for some paths with difficult timing convergence, the trigger is driven by the positive and negative edge clock signals, thereby increasing the timing margin of the internal timing path of the clock phase selection circuit 100, making the timing constraints of the present application more relaxed and the applicable frequency range wider. The phase selection result convergence is implemented by an OR gate, avoiding the power consumption and signal quality problems introduced by the logic, which not only simplifies the design complexity and reduces the difficulty of integration and development, but also optimizes the quality of the output clock signal clk_out and reduces the power consumption of the circuit.

[0060] Combine the following Figure 4 The application scenario of the clock phase selection circuit 100 shown is described.

[0061] like Figure 4 As shown, the n clock signals clk_p[0:(n-1)] of the clock phase selection circuit 100 with the same frequency but different phases come from the delay locked loop DLL 200, and the n selection signals en[0:(n-1)] of the clock phase selection circuit 100 are provided by the controller 300. According to these selection signals en[0:(n-1)], the clock phase selection circuit 100 selects one of the multiple clock signals clk_p[0:(n-1)] as an input clock signal in each clock cycle, and generates a corresponding valid clock signal clk_gate_p[0:(n-1)], and then performs logic operation processing on the n valid clock signals clk_gate_p[0:(n-1)] to generate an output clock signal clk_out. It should be noted that in this embodiment, the clock phase selection circuit 100, the delay locked loop DLL 200 and the controller 300 can be arranged on the same chip 1100.

[0062] All timing paths of the clock phase selection circuit 100 of the present application are synchronous timing paths. Therefore, when the delay locked loop DLL 200 is not locked or an abnormal situation occurs, the selection signal sequence state will be changed in a synchronous control manner to ensure that the output clock signal will not generate glitches.

[0063] For example, if you want to extend the clock period by 2 / 8, then Figure 3 The selection signal sequence state is changed in the working timing diagram shown as follows: en0 remains unchanged; en1 remains at 0; en2 shifts left by one cycle; en3 remains at 0; en4 shifts left by 2 cycles; en5 is 0; en6 shifts left by 3 cycles; en7 is 0.

[0064] For example, if you want to shorten the clock cycle by 1 / 8, then Figure 3 The selection signal sequence states are changed in the working timing diagram shown in the following order: en0, en7, en6, en5, en4, en3, en2, en1.

[0065] In summary, the clock phase selection circuit, chip, electronic device and clock phase selection method of the embodiments of the present application, the present application selects one clock signal of the corresponding phase from n clock signals with the same frequency but different phases according to the sequence of n selection signals in each clock cycle through the clock selection module, and generates n valid clock signals according to each selection signal and the selected input clock signal of the corresponding phase, and performs logical operation processing on the n valid clock signals through the output module to generate an output clock signal. Under the control of the selection signal, the present application selects clock signals of different phases as input clock signals without glitches in each clock cycle, thereby ensuring the stable operation of the chip system.

[0066] In order to implement the above embodiment, Figure 4 As shown, the present application also proposes a chip 1100 , which includes the above-mentioned clock phase selection circuit 100 .

[0067] The clock phase selection circuit 100 is used to select one of n clock signals with the same frequency but different phases as an input clock signal of a corresponding phase in each clock cycle according to a sequence of n selection signals, generate n valid clock signals according to each selection signal and the selected input clock signal of the corresponding phase, and perform logic operations on the n valid clock signals to generate an output clock signal; wherein n is a positive integer greater than or equal to 2.

[0068] like Figure 4 As shown, the chip 1100 of the embodiment of the present application further includes:

[0069] A delay locked loop DLL 200, wherein the output end of the delay locked loop DLL 200 is connected to the first input end of the clock phase selection circuit 100, and the delay locked loop DLL 200 is used to output n clock signals with the same frequency but different phases in each clock cycle;

[0070] The controller 300 has an output terminal connected to the second input terminal of the clock phase selection circuit 100 . The controller 300 is used to output n selection signals in each clock cycle.

[0071] In the embodiments of the present application, the chip 1100 may be an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0072] It should be noted that for details not disclosed in the chip 1100 of the embodiment of the present application, please refer to the above description of the clock phase selection circuit 100, which will not be repeated here.

[0073] The chip of the embodiment of the present application, through the above-mentioned clock phase selection circuit, can select one from n clock signals with the same frequency but different phases as the input clock signal of the corresponding phase in each clock cycle according to the sequence of n selection signals, and generate n valid clock signals according to each selection signal and the selected input clock signal of the corresponding phase, and perform logical operation processing on the n valid clock signals to generate an output clock signal. The chip of the embodiment of the present application, under the control of the selection signal, selects clock signals of different phases as input clock signals without glitches in each clock cycle, thereby ensuring the stable operation of the chip system.

[0074] Figure 5 is a flowchart of a clock phase selection method according to an embodiment of the present application.

[0075] like Figure 5 As shown, the clock phase selection method of the embodiment of the present application includes:

[0076] S51, in each clock cycle, according to a sequence of n selection signals, select one from n clock signals with the same frequency but different phases as an input clock signal of a corresponding phase, and generate n valid clock signals according to each selection signal and the selected input clock signal of the corresponding phase, wherein n is a positive integer greater than or equal to 2.

[0077] S52, performing logic operation processing on n valid clock signals to generate an output clock signal.

[0078] In one embodiment of the present application, n valid clock signals are generated according to each selection signal and the selected input clock signal of the corresponding phase, including:

[0079] Generate a first effective clock signal according to a first selection signal and a first phase input clock signal;

[0080] Using the first phase input clock signal as a reference clock signal, generating a second effective clock signal to an i-th effective clock signal according to the second selection signal to the i-th selection signal and the second phase input clock signal to the i-th phase input clock signal; wherein i is an integer greater than or equal to 1 and less than or equal to (n-1) / 2 rounded down;

[0081] The first phase input clock signal is used as the reference clock signal, and the (i+1)th effective clock signal to the nth effective clock signal are generated according to the (i+1)th selection signal to the nth selection signal and the (i+1)th phase input clock signal to the nth phase input clock signal.

[0082] It should be noted that for details not disclosed in the clock phase selection method of the embodiment of the present application, please refer to the details disclosed in the clock phase selection circuit of the embodiment of the present application, and the details will not be repeated here.

[0083] According to the clock phase selection method of the embodiment of the present application, in each clock cycle, according to the sequence of n selection signals, one is selected from n clock signals with the same frequency but different phases as the input clock signal of the corresponding phase, and n valid clock signals are generated according to each selection signal and the selected input clock signal of the corresponding phase, and then the n valid clock signals are processed by logical operation to generate an output clock signal. Under the control of the selection signal, the present application selects clock signals of different phases as input clock signals without glitches in each clock cycle, thereby ensuring the stable operation of the chip system.

[0084] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the above method embodiments is implemented.

[0085] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a message transceiver device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0086] Reference Figure 6 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0087] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0088] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0089] The power component 806 provides power to the various components of the electronic device 800. The power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0090] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0091] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0092] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0093] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0094] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0095] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0096] In order to implement the above-mentioned embodiments, the present application proposes a non-transitory computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the clock phase selection method as described above are implemented.

[0097] In order to implement the above embodiments, the present application proposes a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the clock phase selection method as described above are implemented.

[0098] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0099] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0100] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0101] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wirings (electronic devices), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0102] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA for short), a field programmable gate array (FPGA for short), etc.

[0103] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0104] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0105] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

[0106] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

[0107] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A clock phase selection circuit, characterized in that: include: A clock selection module, configured to select, in each clock cycle, one of n clock signals having the same frequency but different phases as an input clock signal of a corresponding phase according to a sequence of n selection signals, and generate n valid clock signals according to each of the selection signals and the selected input clock signal of the corresponding phase; wherein n is a positive integer greater than or equal to 2; An output module, wherein the input end of the output module is connected to the output end of the clock selection module, and the output module is used to perform logic operation processing on the n valid clock signals to generate an output clock signal.

2. The clock phase selection circuit according to claim 1, characterized in that: The clock selection module comprises: A first clock selection unit, configured to generate a first valid clock signal according to a first selection signal and a first phase input clock signal; a second clock selection unit, configured to use the first phase input clock signal as a reference clock signal, and generate a second effective clock signal to an i-th effective clock signal according to the second selection signal to the i-th selection signal and the second phase input clock signal to the i-th phase input clock signal; wherein i is an integer greater than or equal to 1 and less than or equal to (n-1) / 2 rounded down; A third clock selection unit is used to use the first phase input clock signal as a reference clock signal, and generate the (i+1)th effective clock signal to the nth effective clock signal according to the (i+1)th selection signal to the nth selection signal and the (i+1)th phase input clock signal to the nth phase input clock signal.

3. The clock phase selection circuit according to claim 2, characterized in that: The first clock selection unit includes: a first clock gating subunit; wherein, The enable terminal EN of the first clock gating subunit receives a first selection signal; The clock terminal CP of the first clock gating subunit receives a first phase input clock signal; The first clock gating subunit generates the first effective clock signal according to the first selection signal and the first phase input clock signal; The output terminal Q of the first clock gating subunit outputs the first valid clock signal.

4. The clock phase selection circuit according to claim 2, characterized in that: The second clock selection unit includes: a first trigger, a second trigger and a second clock gating subunit; wherein, The input terminal D of the first trigger receives the second selection signal to the i-th selection signal; The clock terminal CP of the first trigger receives a first phase input clock signal as the reference clock signal; The output terminal Q of the first trigger is connected to the input terminal D of the second trigger; The clock terminal CP of the second flip-flop receives a clock signal having a phase opposite to that of the first phase input clock signal; The output terminal Q of the second trigger is connected to the enable terminal EN of the second clock gating sub-unit; The clock terminal CP of the second clock gating subunit receives the second phase input clock signal to the i-th phase input clock signal; The second clock gating subunit uses the first phase input clock signal as the reference clock signal, and generates a second effective clock signal to an i-th effective clock signal according to the second phase selection signal to the i-th phase selection signal and the second phase input clock signal to the i-th phase input clock signal output by the second flip-flop; The output terminal Q of the second clock gating subunit outputs the second effective clock signal to the i-th effective clock signal.

5. The clock phase selection circuit according to claim 2, characterized in that: The third clock selection unit includes: a third trigger and a third clock gating subunit; wherein, The input terminal D of the third trigger receives the (i+1)th selection signal to the nth selection signal; The clock terminal CP of the third trigger receives the first phase input clock signal as the reference clock signal; An output terminal Q of the third trigger is connected to an enable terminal EN of the third clock gating subunit; The clock terminal CP of the third clock gating subunit receives the (i+1)th phase input clock signal to the nth phase input clock signal; The third clock gating subunit uses the first phase input clock signal as the reference clock signal, and generates the (i+1)th effective clock signal to the nth effective clock signal according to the (i+1)th phase selection signal to the nth phase selection signal and the (i+1)th phase input clock signal to the nth phase input clock signal output by the third flip-flop; The output terminal Q of the third clock gating subunit outputs the (i+1)th effective clock signal to the nth effective clock signal.

6. The clock phase selection circuit according to any one of claims 2 to 5, characterized in that: The output module comprises: a first OR gate; wherein, The first input terminal of the first OR gate receives the first valid clock signal; The second input terminal of the first OR gate receives a valid clock signal from the second valid clock signal to the i-th valid clock signal; The third input terminal of the first OR gate receives a valid clock signal from the (i+1)th valid clock signal to the nth valid clock signal; The first OR gate performs an OR operation on the first valid clock signal, one valid clock signal from the second valid clock signal to the i-th valid clock signal, and one valid clock signal from the (i+1)th valid clock signal to the nth valid clock signal to generate the output clock signal; The output terminal of the first OR gate outputs the output clock signal.

7. The clock phase selection circuit according to claim 6, characterized in that: The output module further includes: a second OR gate, a third OR gate and a fourth OR gate; wherein, The input end of the second OR gate is connected to the output end Q of the first clock gating sub-unit, and the output end of the second OR gate is connected to the first input end of the first OR gate; The input end of the third OR gate is connected to the output end Q of the second clock gating sub-unit, and the output end of the third OR gate is connected to the second input end of the first OR gate; The input end of the fourth OR gate is connected to the output end Q of the third clock gating sub-unit, and the output end of the fourth OR gate is connected to the third input end of the first OR gate.

8. A chip, characterized in that: include: A clock phase selection circuit as claimed in any one of claims 1 to 7.

9. The chip according to claim 8, characterized in that: The chip further comprises: A delay locked loop DLL, wherein the output end of the delay locked loop DLL is connected to the first input end of the clock phase selection circuit, and the delay locked loop DLL is used to output n clock signals with the same frequency but different phases in each clock cycle; A controller, wherein an output end of the controller is connected to a second input end of the clock phase selection circuit, and the controller is used to output n selection signals in each clock cycle.

10. A clock phase selection method, characterized in that: include: In each clock cycle, according to a sequence of n selection signals, one is selected from n clock signals with the same frequency but different phases as an input clock signal of a corresponding phase, and n valid clock signals are generated according to each of the selection signals and the selected input clock signal of the corresponding phase; wherein n is a positive integer greater than or equal to 2; Perform logic operation processing on the n valid clock signals to generate an output clock signal.

11. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the clock phase selection method according to claim 10 is implemented.

12. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the steps of the clock phase selection method according to claim 10 are implemented.

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