Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; a bit line extending in the first direction parallel to a top surface of the substrate and including a metal layer; an insulating cap structure including a first insulating cap pattern, a second overlay insulating pattern on the first insulating cap pattern, a third insulating cap pattern on the second insulating cap pattern, and a fourth insulating cap pattern on the third insulating cap pattern; a contact plug disposed adjacent to the bit line; a bonding pad disposed on the contact plug and extending on the insulating cap structure, the bonding pad including a first portion and a second portion on the first portion; and a bit line spacer disposed between the bit line and the contact plug and extending on one side of the insulating cap structure. The bottom surface of the first insulating cap pattern of the insulating cap structure contacts the metal layer of the bit line, and the top surface of the fourth insulating cap pattern of the insulating cap structure contacts the bottom surface of the second portion of the bonding pad.

Description

[0001] This application is a divisional application of the invention patent application filed on April 21, 2020, with application number "202010315963.6" and invention title "Integrated Circuit Device and Method of Manufacturing Thereof". Technical Field

[0002] The inventive concept relates to an integrated circuit device and a method of manufacturing the integrated circuit device, and more specifically, to an integrated circuit device including bit lines. Background Technology

[0003] As integrated circuit devices have rapidly miniaturized, the spacing between multiple wirings has decreased, as has the area occupied by these wirings and the conductive structures placed between them. Therefore, it is difficult to ensure sufficient contact area within the multiple wirings and conductive structures. Consequently, there is a need to develop a structure capable of suppressing the increase in resistance of densely arranged wirings within a limited area, and a method for implementing such a structure. Summary of the Invention

[0004] According to an aspect of the inventive concept, an integrated circuit device is provided having a structure capable of suppressing an increase in the resistance of wiring, the wiring being densely arranged within a limited area of ​​an integrated circuit device having a fine unit cell size due to the miniaturization of the integrated circuit device.

[0005] According to another aspect of the inventive concept, a method for manufacturing an integrated circuit device is provided, the integrated circuit device having a structure capable of suppressing the increase in resistance of wiring, the wiring being densely arranged within a limited area of ​​the integrated circuit device having a fine unit cell size according to the miniaturization of the integrated circuit device.

[0006] According to an embodiment, an integrated circuit device is provided, comprising: a conductive line formed on a substrate, the conductive line including a metal layer and extending in a first horizontal direction relative to an upper surface of the substrate; and an insulating cap structure covering the conductive line. The insulating cap structure includes: a first insulating cap pattern having a first density, the first insulating cap pattern being adjacent to the metal layer; and a second insulating cap pattern vertically spaced from the metal layer, with the first insulating cap pattern located between the second insulating cap pattern and the metal layer, the second insulating cap pattern having a second density greater than the first density.

[0007] According to another embodiment, an integrated circuit device is provided, comprising: a pair of bit lines extending parallel to each other on a substrate in a first horizontal direction relative to an upper surface of the substrate, the pair of bit lines being adjacent to each other in a second horizontal direction relative to the upper surface of the substrate; a pair of insulating cap structures respectively covering the pair of bit lines; and a contact structure extending in a vertical direction from between the pair of bit lines to between the pair of insulating cap structures, wherein each of the pair of bit lines includes a metal layer, and each of the pair of insulating cap structures includes: a first insulating cap pattern located on the metal layer, the first insulating cap pattern having a first density; and a second insulating cap pattern spaced apart from the metal layer, the first insulating cap pattern being located between the second insulating cap pattern and the metal layer, the second insulating cap pattern having a second density greater than the first density.

[0008] According to another embodiment, an integrated circuit device is provided, the integrated circuit device comprising: a substrate including a cell array region and a peripheral circuit region; a bit line located on the substrate in the cell array region, the bit line including a first metal layer; a first insulating cap structure covering the bit line in the cell array region; a gate electrode located on the substrate in the peripheral circuit region, the gate electrode including a second metal layer; and a second insulating cap structure covering the gate electrode in the peripheral circuit region, wherein each of the first insulating cap structure and the second insulating cap structure includes: a first insulating cap pattern having a first density; and a second insulating cap pattern spaced apart from the substrate and the first insulating cap pattern being located between the second insulating cap pattern and the substrate, the second insulating cap pattern having a second density greater than the first density, a first metal layer contacting the first insulating cap pattern included in the first insulating cap structure, the first metal layer including a first region doped with nitrogen (N) atoms, the first region extending toward the substrate from the interface between the first metal layer and the first insulating cap pattern in the first insulating cap structure and having a portion of the thickness of the first metal layer.

[0009] According to another embodiment, a method for manufacturing an integrated circuit device is provided. The method includes: forming conductive lines on a substrate, the conductive lines including a metal layer; and forming an insulating cap structure on the conductive lines, the insulating cap structure including a plurality of insulating cap patterns. The step of forming the insulating cap structure includes directly forming a first insulating cap layer on the metal layer, the first insulating cap layer having a first density. A second insulating cap layer is formed on the first insulating cap layer, the second insulating cap layer having a second density greater than the first density.

[0010] According to another embodiment, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a plurality of conductive layers stacked on a substrate, the plurality of conductive layers having a metal layer as the uppermost layer among the plurality of conductive layers; forming an insulating cap structure on the metal layer, the insulating cap structure including a first insulating cap pattern having a first density and a second insulating cap pattern having a second density greater than the first density; and forming bit lines by etching the plurality of conductive layers using the insulating cap structure as an etching mask.

[0011] According to another embodiment, a method for manufacturing an integrated circuit device is provided. The method includes: forming a plurality of conductive layers on a substrate in a cell array region and a peripheral circuit region, the plurality of conductive layers including a metal layer as the uppermost layer among the plurality of conductive layers; forming a first insulating cap structure on the plurality of conductive layers in the cell array region, the first insulating cap structure including a first insulating cap pattern and a second insulating cap pattern, the first insulating cap pattern having a first density and the second insulating cap pattern having a second density greater than the first density; forming a second insulating cap structure on the plurality of conductive layers in the peripheral circuit region, the second insulating cap structure including a third insulating cap pattern and a fourth insulating cap pattern, the third insulating cap pattern having a first density and the fourth insulating cap pattern having a second density; forming bit lines in the cell array region by etching the plurality of conductive layers using the first insulating cap structure as a mask; and forming gate electrodes in the peripheral circuit region by etching the plurality of conductive layers using the second insulating cap structure as an etching mask. Attached Figure Description

[0012] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 It is a block diagram of an integrated circuit device according to an embodiment of the inventive concept;

[0014] Figure 2 This is a plan view illustrating an example arrangement in an integrated circuit device according to an embodiment of the inventive concept;

[0015] Figure 3 This is illustrated in an embodiment according to the inventive concept. Figure 2 A layout diagram of components in the cell array region of an integrated circuit device;

[0016] Figure 4A and Figure 4B The integrated circuit device according to the embodiment of the inventive concept is along Figure 3 A sectional view taken by lines A-A' and B-B';

[0017] Figure 4C Embodiments based on the inventive concept Figure 2A cross-sectional view of the CORE / PERI peripheral circuit region of an integrated circuit device;

[0018] Figure 5 yes Figure 4A An enlarged sectional view of the dashed area "Q1" in the image;

[0019] Figures 6A to 6C This is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0020] Figure 7 yes Figure 6A An enlarged sectional view of the dashed area "Q2" in the image;

[0021] Figures 8A to 8Q It is a cross-sectional view used to describe a method of manufacturing an integrated circuit device according to one or more embodiments in the order of processing; and

[0022] Figures 9A to 9C It is a cross-sectional view used to describe a method of manufacturing an integrated circuit device according to one or more embodiments in the order of processing. Detailed Implementation

[0023] In the following description, one or more embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals denote the same elements in the drawings, and their detailed descriptions are omitted.

[0024] Figure 1 This is a block diagram of an integrated circuit device 100 according to one or more embodiments. Figure 1 An example of an integrated circuit device 100 including a dynamic random access memory (DRAM) device is shown.

[0025] Reference Figure 1 The integrated circuit device 100 includes a first region 22 and a second region 24. The first region 22 may be a memory cell region of a DRAM device, and the second region 24 may be a peripheral circuit region of a DRAM device. The first region 22 may include a memory cell array 22A. In the memory cell array 22A, multiple memory cells for storing data may be arranged in the row and column directions. The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60 for receiving commands (CMD), a mode register group / extended mode register group (MRS / EMRS) circuit 62, an address buffer 64 for receiving addresses (ADD), and a data input / output circuit 66 for input / output data (DQ).

[0026] Figure 2 It is shown Figure 1 A plan view of an exemplary arrangement structure of the integrated circuit device 100.

[0027] Reference Figure 2 The integrated circuit device 100 includes a plurality of first regions 22. Each of the plurality of first regions 22 may be surrounded by a second region 24. Each of the plurality of first regions 22 may include a cell array region MCA of a DRAM device, and the second region 24 may include a core region and a region for forming peripheral circuitry of the DRAM device. The core region (hereinafter referred to as the "peripheral circuitry region") may include, as described above, a cell array region MCA of the plurality of first regions 22. Figure 1 The memory cell array 22A is described.

[0028] The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a junction block CJT. Multiple bit line sense amplifiers may be arranged in the sense amplifier block S / A. The junction block CJT may be located at the point where the sub-word line driver block SWD and the sense amplifier block S / A intersect. Ground drivers and power drivers for driving the bit line sense amplifiers may be arranged alternately in the junction block CJT. Peripheral circuitry such as inverter chains and input / output circuits may be further formed in the second region 24.

[0029] Figure 3 It is used to show Figure 2 The layout diagram of the elements in the cell array region MCA shown is illustrated.

[0030] Reference Figure 3 The cell array region MCA may include multiple cell active regions A1. Each of the multiple cell active regions A1 may be arranged to have a long axis in an inclined direction relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction). Multiple word lines WL may extend parallel to each other in the X direction intersecting the multiple cell active regions A1. Multiple bit lines (or conductive lines) BL may extend parallel to each other along the second horizontal direction (Y direction) on the multiple word lines WL. The multiple bit lines BL may be connected to the multiple cell active regions A1 via direct contacts DC. Multiple buried contacts BC may be formed between two adjacent bit lines from the multiple bit lines BL. The multiple buried contacts BC may be arranged in a row along the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple conductive pads LP may be formed on the multiple buried contacts BC respectively. The multiple buried contacts BC and the multiple conductive pads LP may connect the lower electrode (not shown) of the capacitor formed on the multiple bit lines BL to the cell active region A1. Each of the multiple conductive bonding pads LP can be stacked with a corresponding portion of the buried contact BC.

[0031] Figures 4A to 4C This is a cross-sectional view showing an integrated circuit device 200 according to one or more embodiments. Figure 4Aand Figure 4B This is a cross-sectional view showing an exemplary structure of a portion of the cell array region MCA in integrated circuit device 200. Figure 4C This is a cross-sectional view showing an exemplary structure of a portion of the peripheral circuit region CORE / PERI in integrated circuit device 200. The cell array region MCA of integrated circuit device 200 may have, for example... Figure 3 The layout shown is shown in the image. Figure 4A It shows along Figure 3 The cross section intercepted by line A-A' Figure 4B It shows along Figure 3 The cross section taken by line B-B'.

[0032] Figure 5 yes Figure 4A An enlarged sectional view of the dashed area "Q1" in the image.

[0033] Reference Figures 4A to 4C and Figure 5 Integrated circuit device 200 can be Figures 1 to 3 This is a portion of the integrated circuit device 100 shown. The integrated circuit device 200 includes a substrate 210 having a cell array region MCA and a peripheral circuit region CORE / PERI. An isolation trench T1 is formed in the substrate 210, and an isolation layer 212 is formed in the isolation trench T1. Each of a plurality of cell active regions A1 is defined in the substrate 210 within the cell array region MCA by the isolation layer 212. A peripheral active region A2 may be defined in the substrate 210 within the peripheral circuit region CORE / PERI by the isolation layer 212.

[0034] The substrate 210 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 210 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 210 may include impurity-doped conductive regions (e.g., well regions) or impurity-doped structures. The isolation layer 212 may include an oxide layer, a nitride layer, or a combination thereof.

[0035] In the cell array region MCA, multiple word line trenches T2 extending in the first horizontal direction (X direction) are formed in the substrate 210, and multiple gate dielectric layers 216, multiple gate lines 218, and multiple buried insulating layers 220 are formed in the multiple word line trenches T2. The multiple gate lines 218 can be connected to... Figure 3The multiple word lines WL shown correspond to each other. Multiple recessed spaces 220R can be formed in the upper surface of the buried insulating layer 220. Multiple gate dielectric layers 216 can each include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, or a high-k dielectric layer having a dielectric constant greater than that of the silicon oxide layer. For example, multiple gate dielectric layers 216 can each include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2. Multiple gate lines 218 can each include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof. Multiple buried insulating layers 220 can each include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or combinations thereof.

[0036] In the cell array region MCA, a buffer layer 222 may be formed on the substrate 210. The buffer layer 222 may include a first insulating layer 222A and a second insulating layer 222B. Each of the first insulating layer 222A and the second insulating layer 222B may include an oxide layer, a nitride layer, or a combination thereof. A plurality of direct contacts DC may be arranged on a plurality of cell active regions A1. Each direct contact DC may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0037] Multiple bit lines BL can extend along a second horizontal direction (Y direction) on a substrate 210 and multiple direct contacts DC. Each of the multiple bit lines BL can be connected to the cell active region A1 via a corresponding one of the direct contacts DC. Each of the multiple bit lines BL may include a lower conductive pattern 230B, an intermediate conductive pattern 232B, and an upper conductive pattern 234B sequentially stacked on the substrate 210. The upper conductive pattern 234B (i.e., the uppermost layer of the bit line BL) may include metal. The lower conductive pattern 230B may include doped polysilicon. The intermediate conductive pattern 232B may include TiN, TiSiN, W, tungsten silicide, or combinations thereof. In one or more embodiments, the intermediate conductive pattern 232B may include TiN, TiSiN, or combinations thereof, while the upper conductive pattern 234B may include W.

[0038] In an example embodiment, multiple insulating cap structures CSCs can be vertically stacked on multiple bit lines BL. The multiple bit lines BL can be covered by the multiple insulating cap structures CSC. For example, each of the multiple insulating cap structures CSC can cover the upper surface of a corresponding bit line BL. The multiple bit lines BL and the multiple insulating cap structures CSC can extend parallel to each other in a second horizontal direction (Y direction).

[0039] Each insulating cap structure CSC may include a first insulating cap pattern 236C, a second insulating cap pattern 238C, an insulating film pattern 244C, and a third insulating cap pattern 250C, sequentially stacked on an upper conductive pattern 234B of a bit line BL. In the plurality of insulating cap structures CSCs, the bottom surface of the first insulating cap pattern 236C may contact the upper surface of the upper conductive pattern 234B. The bottom surface of the second insulating cap pattern 238C may contact the upper surface of the first insulating cap pattern 236C. Unless the context otherwise indicates, the term “contact” or the phrase “contact with” as used herein refers to a direct connection (i.e., touch).

[0040] In each of the plurality of insulating cover structures CSC, the first insulating cover pattern 236C and the second insulating cover pattern 238C may have different densities from each other. In one or more embodiments, in the first insulating cover pattern 236C and the second insulating cover pattern 238C, the first insulating cover pattern 236C closer to the upper conductive pattern 234B of the bit line BL may have a first density, and the second insulating cover pattern 238C separated from the upper conductive pattern 234B of the bit line BL and with the first insulating cover pattern 236C between them may have a second density greater than the first density. The insulating film pattern 244C and the third insulating cover pattern 250C may have a second density similar to that of the second insulating cover pattern 238C. In the first horizontal direction (X direction), the first insulating cover pattern 236C, the second insulating cover pattern 238C, the insulating film pattern 244C, and the third insulating cover pattern 250C may have substantially the same width. Unless the context or other statements otherwise indicate otherwise, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical” or “substantially equal” can be completely identical or equal, or can be identical or equal within acceptable variations that may occur, for example, due to manufacturing processes.

[0041] In one or more embodiments, the first insulating cover pattern 236C and the second insulating cover pattern 238C may comprise the same material as each other. In other embodiments, the first insulating cover pattern 236C and the second insulating cover pattern 238C may comprise different materials as each other. The first insulating cover pattern 236C may comprise a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cover pattern 238C, the insulating film pattern 244C, and the third insulating cover pattern 250C may all comprise a silicon nitride layer. The thickness of the first insulating cover pattern 236C in the vertical direction (Z direction) may be smaller than the thickness of the second insulating cover pattern 238C in the vertical direction (Z direction). For example, the first insulating cover pattern 236C may have a thickness of about 20 Å to about 400 Å, and the thickness of the second insulating cover pattern 238C may be larger than the thickness of the first insulating cover pattern 236C. Terms such as “about” or “approximately” may reflect amounts, dimensions, orientations, or layouts that vary only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, the range of "about 0.1 to about 1" can cover a range such as 0%-5% deviation near 0.1 and 0% to 5% deviation near 1, especially if such deviations maintain the same effect as the listed range.

[0042] In one or more embodiments, the upper conductive pattern 234B may include a nitrogen atom diffusion region (i.e., a region doped with nitrogen atoms) in its upper region. The nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234B and the first insulating cap pattern 236C toward the substrate 210 to a portion of the thickness of the upper conductive pattern 234B. The thickness (length in the Z direction) of the nitrogen atom diffusion region may be from about 0.01% to about 10% of the total thickness (length in the Z direction) of the upper conductive pattern 234B. For example, the nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234B and the first insulating cap pattern 236C to a thickness of about 5 Å to about 40 Å, or have a thickness of about 5 Å to about 40 Å in the upper conductive pattern 234B, but the thickness of the nitrogen atom diffusion region is not limited thereto.

[0043] In the nitrogen atom diffusion region, nitrogen (N) atoms can be in a diffused state without being chemically bonded to other atoms included in the upper conductive pattern 234B. In one or more embodiments, when the upper conductive pattern 234B includes a tungsten (W) layer and the first insulating cap pattern 236C includes a silicon nitride layer, the nitrogen atom diffusion region in the upper conductive pattern 234B may include a tungsten (W) layer formed of tungsten (W) atoms, nitrogen (N) atoms distributed within the tungsten crystal structure included in the W layer (i.e., between tungsten (W) atoms) without being chemically bonded to the tungsten (W) atoms of the tungsten crystal structure of the W layer, and tungsten nitride particles diffused in the W layer. The tungsten nitride particles may include chemical bonds between W and N. In an example embodiment, the nitrogen atom diffusion region may be the upper part of the W layer, the upper part of the W layer being doped with nitrogen (N) atoms and including tungsten nitride particles distributed within the upper part of the W layer. The thickness of the first region (i.e., the nitrogen atom diffusion region) may be from about 0.01% to about 10% of the total thickness of the W layer.

[0044] The sidewalls of the multiple bit lines BL and the sidewalls of the insulating cover structure CSC can be covered by multiple insulating spacers 252. The multiple insulating spacers 252 can extend parallel to the multiple bit lines BL in a second horizontal direction (Y direction). Each of the multiple insulating spacers 252 can include an oxide layer, a nitride layer, an air spacer, or a combination thereof. In this specification, the term "air" can mean the atmosphere or include spaces containing other gases that may be present during the manufacturing process.

[0045] Multiple insulating barriers 254 and multiple conductive plugs 256 can be arranged in a row along a second horizontal direction (Y direction) between multiple bit lines BL and multiple insulating cap structures CSC. The multiple insulating barriers 254 fill multiple recessed spaces 220R formed in the upper surface of the buried insulating layer 220, and each insulating barrier 254 can be arranged between two conductive plugs 256 spaced apart from each other along the second horizontal direction (Y direction). The opposite sidewalls of each of the multiple conductive plugs 256 in the second horizontal direction (Y direction) can be covered by the multiple insulating barriers 254. The multiple conductive plugs 256 arranged in a row along the second horizontal direction (Y direction) can be insulated from each other by the multiple insulating barriers 254. Each of the multiple insulating barriers 254 can include a silicon nitride layer. The multiple conductive plugs 256 can constitute... Figure 3 The diagram shows multiple buried contacts BC. A direct contact DC and a pair of conductive plugs 256 facing each other with the direct contact DC located between them can be connected to different unit active regions A1 from multiple unit active regions A1.

[0046] Multiple metal silicide layers 258A and multiple conductive bonding pads LP can be formed on multiple conductive plugs 256. The metal silicide layers 258A and conductive bonding pads LP can be arranged to overlap the conductive plugs 256 in a vertical direction. Each of the multiple conductive bonding pads LP can be connected to the conductive plug 256 via the metal silicide layer 258A. The multiple conductive bonding pads LP can at least partially cover the upper surface of the third insulating cap pattern 250C to be vertically overlapped with some of the multiple bit lines BL. The conductive plugs 256, the metal silicide layers 258A, and the conductive bonding pads LP can form a contact structure CST that connects the lower electrode (not shown) of the capacitor formed on the conductive bonding pads LP to the cell active region A1.

[0047] The metal silicide layer 258A may include cobalt silicide, nickel silicide, or manganese silicide. Each of the plurality of conductive pads LP may include a conductive barrier layer 262 and a main conductive layer 264. The conductive barrier layer 262 may include Ti, TiN, or a combination thereof. The main conductive layer 264 may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the main conductive layer 264 may include W. The plurality of conductive pads LP may have an island pattern shape on a plane. The plurality of conductive pads LP may be electrically insulated from each other by an insulating layer 270 that fills the insulating space 270S around each of the plurality of conductive pads LP. The insulating layer 270 may include a silicon nitride layer, a silicon oxide layer, or a combination thereof.

[0048] In the peripheral circuit region CORE / PERI, the gate structure PG can be formed on the substrate 210. The gate structure PG may include a gate dielectric layer 224, a gate electrode 240, and an insulating cap structure CSP sequentially stacked on the peripheral active region A2.

[0049] The gate dielectric layer 224 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric layer with a dielectric constant greater than that of silicon oxide. The gate electrode 240 may include a lower conductive pattern 230P, an intermediate conductive pattern 232P, and an upper conductive pattern 234P. The lower conductive pattern 230P, intermediate conductive pattern 232P, and upper conductive pattern 234P may each comprise the same material as the lower conductive pattern 230B, intermediate conductive pattern 232B, and upper conductive pattern 234B included in the bit line BL in the cell array region MCA.

[0050] The insulating cap structure CSP may include a first insulating cap pattern 236P and a second insulating cap pattern 238P. In the insulating cap structure CSP, the bottom surface of the first insulating cap pattern 236P may contact the upper surface of the upper conductive pattern 234P of the gate electrode 240. The bottom surface of the second insulating cap pattern 238P may contact the upper surface of the first insulating cap pattern 236P. In the insulating cap structure CSP, the first insulating cap pattern 236P and the second insulating cap pattern 238P may have different densities from each other. In one or more embodiments, in the first insulating cap pattern 236P and the second insulating cap pattern 238P, similar to the first insulating cap pattern 236C in the cell array region MCA, the first insulating cap pattern 236P closer to the upper conductive pattern 234P of the gate electrode 240 may have a first density. Similar to the second insulating cover pattern 238C in the cell array region MCA, the second insulating cover pattern 238P, separated from the upper conductive pattern 234P of the gate electrode 240 and with the first insulating cover pattern 236P between them, can have a second density greater than the first density. In a horizontal direction parallel to the main surface 210M of the substrate 210, the width of the first insulating cover pattern 236P is substantially the same as the width of the second insulating cover pattern 238P.

[0051] In one or more embodiments, the first insulating cover pattern 236P and the second insulating cover pattern 238P may comprise the same material as each other. In another embodiment, the first insulating cover pattern 236P and the second insulating cover pattern 238P may comprise different materials as each other. The first insulating cover pattern 236P may comprise a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cover pattern 238P may comprise a silicon nitride layer.

[0052] In one or more embodiments, the upper conductive pattern 234P of the gate electrode 240 may include a nitrogen atom diffusion region in a portion of its upper region. The nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234P of the gate electrode 240 and the first insulating cap pattern 236P toward the substrate 210 to a point within the thickness of the upper conductive pattern 234P. The thickness (length in the Z direction) of the nitrogen atom diffusion region may be from about 0.01% to about 10% of the total thickness (length in the Z direction) of the upper conductive pattern 234P. For example, the nitrogen atom diffusion region may extend from the interface between the upper conductive pattern 234P and the first insulating cap pattern 236P to a thickness of about 5 Å to about 40 Å, or have a thickness of about 5 Å to about 40 Å within the upper conductive pattern 234P, but the thickness of the nitrogen atom diffusion region is not limited thereto.

[0053] In the nitrogen atom diffusion region, N atoms can be in a diffused state without being chemically bonded to other atoms included in the upper conductive pattern 234P. In one or more embodiments, when the upper conductive pattern 234P includes a W layer and the first insulating cap pattern 236P includes a silicon nitride layer, the nitrogen atom diffusion region in the upper conductive pattern 234P may include a W layer formed of W atoms, N atoms distributed within (i.e., between W atoms) of the tungsten crystal structure included in the W layer without being chemically bonded to the W atoms of the tungsten crystal structure of the W layer, and tungsten nitride particles diffused in the W layer. The tungsten nitride particles may include chemical bonds between W and N.

[0054] The opposing sidewalls of the gate structure PG may be covered by insulating spacers 242. Insulating spacers 242 may include oxide layers, nitride layers, or combinations thereof. The gate structure PG and insulating spacers 242 may be covered by an insulating film 244. The insulating film 244 may include a silicon nitride layer. An interlayer insulating layer 246 filling the space around the gate structure PG may be formed on the insulating film 244. The interlayer insulating layer 246 may include, but is not limited to, Tonen silazane (TOSZ). The gate structure PG, insulating film 244, and interlayer insulating layer 246 may be covered by a third insulating capping layer 250. The third insulating capping layer 250 may include a silicon nitride layer.

[0055] In the peripheral circuit region CORE / PERI, the contact space CS2 extends vertically through the third insulating cap layer 250, the interlayer insulating layer 246, and the insulating film 244, and then extends into the peripheral active region A2 of the substrate 210. Multiple conductive patterns CNPs can be formed on the third insulating cap layer 250. The multiple conductive patterns CNPs can extend on the third insulating cap layer 250 in various planar shapes. Each of the multiple conductive patterns CNPs can serve as a contact plug, which extends vertically through the contact space CS2 through the third insulating cap layer 250, the interlayer insulating layer 246, and the insulating film 244. Similar to the multiple conductive bonding pads LP formed in the cell array region MCA, each of the multiple conductive patterns CNPs can include a conductive barrier layer 262 and a main conductive layer 264. A metal silicide layer 258B can be located between the peripheral active region A2 and each of the multiple conductive patterns CNPs. The metal silicide layer 258B can include cobalt silicide, nickel silicide, or manganese silicide.

[0056] Figures 6A to 6C This is a cross-sectional view showing an integrated circuit device 300 according to one or more embodiments. Figure 6A and Figure 6B This is a cross-sectional view showing an exemplary structure of a portion of the cell array region MCA in the integrated circuit device 300. Figure 6CThis is a cross-sectional view showing an exemplary structure of a portion of the peripheral circuit region CORE / PERI in integrated circuit device 300. The cell array region MCA of integrated circuit device 300 may have, for example... Figure 3 The layout shown is shown in the image. Figure 6A It shows along Figure 3 The cross section intercepted by line A-A' Figure 6B It shows along Figure 3 The cross section taken by line B-B'.

[0057] Figure 7 It is shown that it includes Figure 6A An enlarged cross-sectional view of some components in the dashed area "Q2".

[0058] Reference Figures 6A to 6C and Figure 7 The integrated circuit device 300 has the same characteristics as the one mentioned above. Figures 4A to 4C and Figure 5 The integrated circuit device 200 shown has a similar structure. The integrated circuit device 300 may include multiple insulating cap structures CSC3 covering multiple bit lines BL. The insulating cap structures CSC3 may have the same structure as the referenced one. Figure 4A and Figure 5 The insulating cover structure CSC shown has a similar structure. However, the insulating cover structure CSC3 includes a first insulating cover pattern 336C, instead of... Figure 4A The first insulating cover pattern of CSC is 236C.

[0059] The bottom surface of the first insulating cover pattern 336C can contact the upper surface of the upper conductive pattern 234B. The bottom surface of the second insulating cover pattern 238C can contact the upper surface of the first insulating cover pattern 336C.

[0060] In each of the plurality of insulating cover structures CSC3, the first insulating cover pattern 336C and the second insulating cover pattern 238C may have different densities from each other. In one or more embodiments, the first insulating cover pattern 336C may have a first density, and the second insulating cover pattern 238C may have a second density that is greater than the first density.

[0061] In the first horizontal direction (X direction), the first insulating cover pattern 336C and the second insulating cover pattern 238C can have different minimum widths. That is, in the first horizontal direction (X direction), the minimum width of the first insulating cover pattern 336C is smaller than the minimum width of the second insulating cover pattern 238C. Due to the width difference between the first insulating cover pattern 336C and the second insulating cover pattern 238C in the first horizontal direction (X direction), the undercut region can be formed near the point where the sidewalls of the first insulating cover pattern 336C and the bottom surfaces of the second insulating cover pattern 238C intersect. The detailed structure of the first insulating cover pattern 336C is similar to that shown in the reference. Figure 4A , Figure 4B and Figure 5 The structure of the first insulating cover pattern 236C is described.

[0062] The sidewalls of the multiple bit lines BL and the sidewalls of the insulating cover structure CSC3 can be covered by multiple insulating spacers 352. Each of the multiple insulating spacers 352 may include a protruding sidewall 352S projecting toward the first insulating cover pattern 336C. ​​The detailed structure of the multiple insulating spacers 352 is similar to that described above. Figure 4A , Figure 4B and Figure 5 The detailed structure of the multiple insulating spacers 252 is described.

[0063] Multiple conductive plugs 256 and multiple insulating barriers 354 may be arranged in a row along a second horizontal direction (Y direction) between multiple bit lines BL and multiple insulating cap structures CSC3. Each of the multiple insulating barriers 354 may include a protruding sidewall 354S projecting toward the first insulating cap pattern 336C. ​​The detailed structure of the multiple insulating barriers 354 is similar to that described above. Figure 4A , Figure 4B and Figure 5 The detailed structure of the multiple insulating fences 254 is described.

[0064] Multiple metal silicide layers 258A and multiple conductive bonding pads LP3 can be formed on multiple conductive plugs 256. The conductive bonding pads LP3 can be stacked vertically with the conductive plugs 256 and the metal silicide layers 258A. The conductive plugs 256, the metal silicide layers 258A, and the conductive bonding pads LP3 can constitute a contact structure CST3 connecting a lower electrode (not shown) of a capacitor formed on the conductive bonding pads LP3 to the active region A1 of the cell. A portion of the contact structure CST3 may include a protruding sidewall projecting toward the first insulating cap pattern 336C. ​​For example, as... Figure 6AAs shown, each of the plurality of conductive bonding pads LP3 may include a protruding sidewall LP3S projecting toward the first insulating cap pattern 336C. ​​Each of the plurality of conductive bonding pads LP3 may include a conductive barrier layer 362 and a main conductive layer 364. Both the conductive barrier layer 362 and the main conductive layer 364 may include a protruding sidewall projecting toward the first insulating cap pattern 336C at a portion corresponding to the protruding sidewall LP3S. The conductive bonding pads LP3 include protruding sidewalls LP3S on opposite sides in the first horizontal direction (X direction), therefore, the conductive bonding pads LP3 may have non-uniform widths. For example, the conductive bonding pads LP3 may have a first portion having a first width and a second portion having a second width. The first portion is located between two adjacent first insulating cap patterns 336C, and the second portion is located between two adjacent second insulating cap patterns 238C. The first width and the second width are measured in the first horizontal direction (X direction). The first width may be larger than the second width. Therefore, the volume of the conductive bonding pad LP3 located between two adjacent first insulating cover patterns 336C can be larger than the volume of the conductive bonding pad LP3 excluding the protruding sidewalls LP3S. As described above, since the conductive bonding pad LP3 includes a portion with an increased volume due to the protruding sidewalls LP3S, the resistance of the conductive bonding pad LP3 can be reduced.

[0065] exist Figure 6A In the contact structure CST3, the sidewall of the conductive bonding pad LP3 faces the first insulating cover pattern 336C, and correspondingly, a protruding sidewall LP3S is formed on the conductive bonding pad LP3, but one or more embodiments are not limited thereto. For example, when the upper surface of the conductive plug 256 included in the contact structure CST3 has a greater than Figure 6A When the conductive plug 256 is at a high level and its sidewall faces the first insulating cover pattern 336C, the conductive plug 256 may have a protruding sidewall that protrudes toward the first insulating cover pattern 336C.

[0066] The detailed structure of multiple conductive bonding pads LP3 is similar to that described above. Figure 4A , Figure 4B and Figure 5 The detailed structure of the multiple conductive bonding pads LP is described. The detailed structure of the conductive barrier layer 362 and the main conductive layer 364 is similar to that described above. Figure 4A , Figure 4B and Figure 5 The detailed structures of the conductive barrier layer 262 and the main conductive layer 264 are described.

[0067] In the peripheral circuit region CORE / PER1, a gate structure PG3 can be formed on the peripheral active region A2. The gate structure PG3 includes an insulating cap structure CSP3. The insulating cap structure CSP3 can have... Figure 4CThe insulating cap structure CSP shown has a similar structure. However, the insulating cap structure CSP3 includes a first insulating cap pattern 336P instead of... Figure 4C The first insulating cover pattern is 236P.

[0068] In the horizontal direction, the minimum width of the first insulating cover pattern 336P is smaller than the minimum width of the second insulating cover pattern 238P. Due to the width difference between the first insulating cover pattern 336P and the second insulating cover pattern 238P in the horizontal direction, the undercut region can be formed near the point where the sidewalls of the first insulating cover pattern 336P and the bottom surface of the second insulating cover pattern 238P intersect. The detailed structure of the first insulating cover pattern 336P is similar to that shown in the reference. Figure 4C The structure of the first insulating cover pattern 236P is described.

[0069] The opposing sidewalls of the gate structure PG3 can be covered by an insulating spacer 342. The insulating spacer 342 may include a protruding sidewall 342S projecting toward the first insulating cap pattern 336P. The detailed structure of the insulating spacer 342 is similar to that described above. Figure 4C The detailed structure of the insulating spacer 242 is described.

[0070] Figures 8A to 8Q This is a cross-sectional view used to describe a method of manufacturing an integrated circuit device according to one or more embodiments, arranged in a processing order. Reference will be made below. Figures 8A to 8Q Description of manufacturing reference Figures 4A to 4C The method of the integrated circuit device 200 is shown. Figures 8A to 8Q In the text, (a) indicates the order of manufacture. Figure 3 (a) is a cross-sectional view taken by line A-A', and (b) is a cross-sectional view of a portion of the peripheral circuit region CORE / PERI according to the processing order.

[0071] Reference Figure 8A Multiple isolation trenches T1 and multiple isolation layers 212 filling the multiple isolation trenches T1 are formed in a substrate 210 having a cell array region MCA and a peripheral circuit region CORE / PERI. The multiple isolation layers 212 can define multiple cell active regions A1 in the cell array region MCA of the substrate 210 and define peripheral active regions A2 in the peripheral circuit region CORE / PERI.

[0072] Multiple word line trenches T2 extending parallel to each other can be formed in the substrate 210 of the cell array region MCA (see Figure 4BTo form multiple word line trenches T2 with steps on their bottom surfaces, the isolation layer 212 and the substrate 210 are etched using separate etching processes to differentiate the etching depth of the isolation layer 212 from that of the substrate 210. After cleaning the resulting structure with the multiple word line trenches T2, multiple gate dielectric layers 216, multiple gate lines 218, and multiple buried insulating layers 220 can be sequentially formed in the multiple word line trenches T2. Impurity ions are implanted into the opposite sides of the multiple gate lines 218 in the multiple cell active regions A1 to form multiple source / drain regions on the multiple cell active regions A1. In one or more embodiments, the multiple source / drain regions can be formed before the multiple gate lines 218 are formed.

[0073] Subsequently, a buffer layer 222 is formed on the substrate 210 in the cell array region MCA, and a gate dielectric layer 224 is formed on the substrate 210 in the peripheral circuit region CORE / PERI.

[0074] Reference Figure 8B A lower conductive layer 230 is formed on the buffer layer 222 in the cell array region MCA and on the gate dielectric layer 224 in the peripheral circuit region CORE / PERI. The lower conductive layer 230 may include doped polysilicon.

[0075] Reference Figure 8C A mask pattern M21 is formed on the lower conductive layer 230. Then, the lower conductive layer 230, exposed through openings M21O in the cell array region MCA, is etched. Next, the exposed portion of the substrate 210 and part of the isolation layer 212, which are the result of the etching process, are etched to form direct contact vias DCH for the cell active regions A1 of the exposed substrate 210. The mask pattern M21 may include an oxide layer, a nitride layer, or a combination thereof. A photolithography process can be performed to form the mask pattern M21.

[0076] Reference Figure 8D Remove mask pattern M21 (see Figure 8C ), forming a direct contact DC in each of the direct contact hole DCH.

[0077] In an exemplary process for forming the direct contact DC, a conductive layer is formed in the direct contact hole DCH and on top of the lower conductive layer 230 to a thickness sufficient to fill the direct contact hole DCH, and the conductive layer may be etched back only to remain in the direct contact hole DCH. The conductive layer may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof.

[0078] Reference Figure 8EAn intermediate conductive layer 232 and an upper conductive layer 234 are sequentially formed on the lower conductive layer 230 and the direct contact DC in the cell array region MCA and the peripheral circuit region CORE / PERI. Each of the intermediate conductive layer 232 and the upper conductive layer 234 may include TiN, TiSiN, W, tungsten silicide, or combinations thereof. In one or more embodiments, the intermediate conductive layer 232 includes TiN, TiSiN, or combinations thereof, and the upper conductive layer 234 may include W.

[0079] Reference Figure 8F A first insulating capping layer 236 is formed on the upper conductive layer 234 in the cell array region MCA and the peripheral circuit region CORE / PERI.

[0080] To form the first insulating capping layer 236, a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process can be performed at a relatively low first temperature. The first temperature can be selected in the range of about 500°C to about 700°C. For example, the first temperature can be selected in the range of about 600°C to about 650°C. The first insulating capping layer 236 may include a silicon nitride layer. In this case, in the CVD or ALD process for forming the first insulating capping layer 236, a gas including SiH4, Si2Cl2H2, SiH6, Si2H6, Si3H8, or combinations thereof is used as a Si-containing precursor, and a gas including NH3, N2, NO, N2O, or combinations thereof can be used as an N-containing precursor. However, one or more embodiments are not limited to the examples above.

[0081] Because the deposition process is performed at a relatively low first temperature when the first insulating capping layer 236 is formed, the formation of WN, which could result from the reaction between the nitrogen-containing (N) precursor and the metal (e.g., W) included in the upper conductive layer 234, or from undesirable diffusion of N atoms from the first insulating capping layer 236 to the upper conductive layer 234, can be suppressed or reduced during the formation of the first insulating capping layer 236. Therefore, the formation of insulating metal nitrides (e.g., WN) between the upper conductive layer 234 and the first insulating capping layer 236 can be suppressed or reduced.

[0082] In one or more embodiments, during the formation of the first insulating capping layer 236, N atoms included in the first insulating capping layer 236 can diffuse to the upper conductive layer 234. As a result, after the formation of the first insulating capping layer 236, a nitrogen atom diffusion region is formed from the interface between the first insulating capping layer 236 and the upper conductive layer 234 over a portion of the thickness of the upper conductive layer 234. (Refer to above) Figures 4A to 4C The detailed structure of the nitrogen atom diffusion region is described.

[0083] Reference Figure 8GA second insulating capping layer 238 is formed on the first insulating capping layer 236 in the cell array region MCA and the peripheral circuit region CORE / PERI.

[0084] To form the second insulating capping layer 238, a CVD or ALD process can be performed at a relatively high second temperature. The second temperature is higher than the first temperature. For example, the second temperature can be selected in the range of about 700°C to about 800°C. The second insulating capping layer 238 may include a silicon nitride layer. In this case, the method for forming the second insulating capping layer 238 is the same as described above. Figure 8F The method for forming the first insulating cap 236 is the same as described.

[0085] The above can be performed either in-situ or out-of-situ. Figure 8F The process for forming the first insulating cap layer 236 described above and referenced above Figure 8G The process for forming the second insulating capping layer 238 is described. In one embodiment, to form the first insulating capping layer 236 and the second insulating capping layer 238 continuously in situ within the same chamber, the first insulating capping layer 236 and the second insulating capping layer 238 can be formed separately by a CVD process, wherein the deposition temperature of the first insulating capping layer 236 can be lower than the deposition temperature of the second insulating capping layer 238. In another embodiment, to form the first insulating capping layer 236 and the second insulating capping layer 238 non-in situ, the first insulating capping layer 236 can be formed by an ALD process at a relatively low first temperature, and the second insulating capping layer 238 can be formed by a CVD process at a relatively high second temperature.

[0086] Since the deposition temperature of the second insulating capping layer 238 is higher than that of the first insulating capping layer 236, the density of the second insulating capping layer 238 can be greater than that of the first insulating capping layer 236.

[0087] Reference Figure 8H In the peripheral circuit region CORE / PERI, the gate dielectric layer 224, lower conductive layer 230, intermediate conductive layer 232, upper conductive layer 234, first insulating cap layer 236, and second insulating cap layer 238 are patterned using a mask pattern (not shown) as an etching mask. Then, a gate structure PG including the gate dielectric layer 224, gate electrode 240, first insulating cap pattern 236P, and second insulating cap pattern 238P is formed in the peripheral circuit region CORE / PERI. The gate electrode 240 may include a lower conductive pattern 230P, an intermediate conductive pattern 232P, and an upper conductive pattern 234P.

[0088] Reference Figure 8IAn insulating spacer 242 is formed on the opposite sidewall of the gate structure PG in the peripheral circuit region CORE / PERI, and an ion implantation process is performed to form a source / drain region in the peripheral active region A2 on the opposite side of the gate structure PG.

[0089] Subsequently, an insulating film 244 is formed to completely cover the exposed surfaces of the cell array region MCA and the peripheral circuit region CORE / PERI. The insulating film 244 can contact the upper surface of the second insulating cap layer 238 in the cell array region MCA and can contact the upper surface of the second insulating cap pattern 238P in the peripheral circuit region CORE / PER. The insulating film 244 can be contacted by referring to the above... Figure 8G The process for forming the second insulating cap 238 is the same as or similar to the process described.

[0090] In the peripheral circuit region CORE / PERI, an interlayer insulating layer 246 is formed to fill the space surrounding the gate structure PG and the insulating film 244. The interlayer insulating layer 246 may have a planarized upper surface.

[0091] Reference Figure 8J A third insulating capping layer 250 is formed on the insulating film 244 and the planarized interlayer insulating layer 246 in the cell array region MCA and the peripheral circuit region CORE / PERI. The third insulating capping layer 250 can be formed by referring to the above. Figure 8G The process for forming the second insulating cap 238 is the same as or similar to the process described.

[0092] Reference Figure 8K In the state where the third insulating cap layer 250 is covered by a mask pattern M22 in the peripheral circuit region CORE / PERI, the third insulating cap layer 250, the insulating film 244, the second insulating cap layer 238 and the first insulating cap layer 236 are patterned in the cell array region MCA by photolithography, and then multiple insulating cap structures CSC are formed, each including a first insulating cap pattern 236C, a second insulating cap pattern 238C, an insulating film pattern 244C and a third insulating cap pattern 250C stacked sequentially on the upper conductive layer 234.

[0093] Reference Figure 8LIn a state where the third insulating cap layer 250 is covered by a mask pattern M22 in the peripheral circuit region CORE / PERI, the upper conductive layer 234, the intermediate conductive layer 232, and the lower conductive layer 230 are etched in the cell array region MCA using multiple insulating cap structures CSC as etching masks, and then multiple bit lines BL, each including a lower conductive pattern 230B, an intermediate conductive pattern 232B, and an upper conductive pattern 234B, are formed. The resulting structure with multiple bit lines BL can be cleaned and dried. In one or more embodiments, the cleaning process of the resulting structure with multiple bit lines BL can be performed using diluted HF (DHF). The drying process can be performed using isopropyl alcohol (IPA). After the multiple bit lines BL are formed, the line space LS can be retained between the bit lines BL. Due to the etching process used to form the multiple bit lines BL, the height of the third insulating cap pattern 250C in the insulating cap structure CSC can be reduced.

[0094] Reference Figure 8M Multiple insulating spacers 252 are formed to cover the sidewalls of multiple bit lines BL and the sidewalls of multiple insulating cap structures CSC. The multiple insulating spacers 252 can fill the direct contact hole DCH around the direct contact DC.

[0095] Reference Figure 8N In the state where the third insulating capping layer 250 is covered by a mask pattern M22 in the peripheral circuit region CORE / PERI, multiple insulating barriers 254 are formed between multiple bit lines BL in the cell array region MCA (see Figure 4B The line space LS is divided into multiple contact spaces CS1. Multiple insulating barriers 254 can be stacked vertically with the gate line 218. A line space LS can be divided by multiple insulating barriers 254, such that multiple contact spaces CS1 can each have a cylindrical shape. Subsequently, the structures exposed through the multiple contact spaces CS1 can be partially removed to form multiple recessed spaces RS, each recessed space RS exposing the cell active region A1 of the substrate 210 located between bit lines BL. While forming the multiple insulating barriers 254 and multiple recessed spaces RS, the third insulating cover pattern 250C and the insulating spacer 252 are exposed to various etching process atmospheres, which can further reduce the height of the third insulating cover pattern 250C and the insulating spacer 252.

[0096] Reference Figure 8O In the peripheral circuit region CORE / PERI, a mask pattern M22 is used (see...) Figure 8MIn the state of covering the third insulating cover layer 250, a plurality of conductive plugs 256 are formed in the unit array region MCA, wherein the plurality of conductive plugs 256 respectively fill the plurality of recessed spaces RS between the bit lines BL and partially fill the contact space CS1 between the bit lines BL.

[0097] Remove mask pattern M22 (see) Figure 8N To expose the third insulating capping layer 250 in the peripheral circuit region CORE / PERI, and then, with the mask pattern (not shown) covering the cell array region MCA, the third insulating capping layer 250, the interlayer insulating layer 246, and the insulating film 244 are etched in the peripheral circuit region CORE / PERI to form a plurality of contact spaces CS2 on the substrate 210 that expose the peripheral active region A2. Afterwards, the mask pattern (not shown) covering the cell array region MCA is removed, and then a metal silicide layer 258A is formed in the cell array region MCA on the conductive plugs 256 exposed through the plurality of contact spaces CS1, and a metal silicide layer 258B is formed in the peripheral circuit region CORE / PERI on the surface of the peripheral active region A2 exposed through the plurality of contact spaces CS2. In one or more embodiments, the metal silicide layers 258A and 258B can be formed simultaneously. In another embodiment, the metal silicide layers 258A and 258B can be formed by processes that are separate from each other.

[0098] Reference Figure 8P The conductive layer 260 covers the exposed surfaces of the substrate 210 in the cell array region MCA and the peripheral circuit region CORE / PERI. The conductive layer 260 may include a conductive barrier layer 262 and a main conductive layer 264.

[0099] Reference Figure 8Q A conductive layer 260 is patterned in the cell array region MCA and the peripheral circuit region CORE / PERI. Multiple conductive bonding pads LP are then formed from the conductive layer 260 in the cell array region MCA, and multiple conductive patterns CNP are formed from the conductive layer 260 in the peripheral circuit region CORE / PERI. The multiple conductive bonding pads LP can be disposed on a metal silicide layer and can be partially stacked with multiple bit lines BL in the vertical direction.

[0100] Based on the above reference Figures 8A to 8Q The described method for manufacturing an integrated circuit device 200 involves forming a first insulating cap layer 236 directly on the bit lines BL within the insulating cap structure CSC at a relatively low temperature when forming multiple insulating cap structures CSC covering multiple bit lines BL. This suppresses or reduces the formation of undesirable insulating metal nitride layers at the interfaces between the multiple bit lines BL and the insulating cap structure CSC. Consequently, the increase in resistance of the multiple bit lines BL can be reduced.

[0101] Figures 9A to 9C This is a cross-sectional view used to describe a method of manufacturing an integrated circuit device 300 according to one or more embodiments, arranged in a processing order. Reference will be made below. Figures 9A to 9C Description of manufacturing reference Figures 6A to 6C The method of the integrated circuit device 300 is shown. Figures 9A to 9C In the text, (a) indicates the order of manufacture. Figure 3 (a) is a cross-sectional view taken by line A-A', and (b) is a cross-sectional view of a portion of the peripheral circuit region CORE / PERI according to the processing order.

[0102] Reference Figure 9A In the peripheral circuit region CORE / PERI, refer to the above. Figures 8A to 8H The gate structure PG3, comprising a gate dielectric layer 224, a gate electrode 240, a first insulating cap pattern 236P, and a second insulating cap pattern 238P, is formed in the same manner as described. Subsequently, the exposed sidewalls of the first insulating cap pattern 236P are partially removed by a selective etching process utilizing the difference between the densities of the first and second insulating cap patterns 238P, thus forming a first insulating cap pattern 336P with a minimum width smaller than that of the second insulating cap pattern 238P. The selective etching process for forming the first insulating cap pattern 336P can be performed using an etchant such as DHF.

[0103] Reference Figure 9B According to the above reference Figures 8I to 8L The described manufacturing process, for Figure 9A The resulting structure is fabricated using a process for forming multiple insulating cap structures CSCs and multiple bit lines BLs within the cell array region MCA. However, in the embodiment, reference is made above. Figure 8I In the described process, an insulating spacer 342 is formed having a protruding sidewall 342S protruding toward the first insulating cover pattern 336P.

[0104] Subsequently, in the cell array region MCA, partial removal is performed using a selective etching process. Figure 8K The exposed sidewalls of the first insulating cover pattern 236C are used to form the first insulating cover pattern 336C, the selective etching process utilizing... Figure 8K The density of the first insulating cover pattern 236C differs from the densities of the second insulating cover pattern 238C, the insulating film pattern 244C, and the third insulating cover pattern 250C in the insulating cover structure CSC. The first insulating cover pattern 336C has a minimum width smaller than that of the second insulating cover pattern 238C. A selective etching process for forming the first insulating cover pattern 336C can be performed using an etchant such as DHF.

[0105] Reference Figure 9C , can be Figure 9B The resulting structure is executed as described above. Figure 8M The described process. However, instead of... Figure 8M The plurality of insulating spacers 252 may be formed in an embodiment having protruding sidewalls 352S protruding toward the first insulating cover pattern 336C.

[0106] After that, Figure 9C The resulting structure is executed Figures 8N to 8Q The process shown is for manufacturing Figures 6A to 6C The integrated circuit device 300 shown is illustrated.

[0107] Based on the above reference Figures 9A to 9C The described method for manufacturing an integrated circuit device 300 involves forming multiple insulating cap structures CSC3 covering multiple bit lines BL. A first insulating cap pattern 336C (wherein the first insulating cap pattern 336C contacts the bit lines BL) in the insulating cap structure CSC3 is obtained from a film formed at a relatively low temperature. Therefore, the formation of undesirable insulating metal nitride layers at the interfaces between the multiple bit lines BL and the insulating cap structure CSC3 can be suppressed or reduced, and an increase in the resistance of the multiple bit lines BL can be prevented. Furthermore, in the insulating cap structure CSC3, the sidewall profile of the insulating cap structure CSC3 can be optimized by utilizing the difference between the density of the first insulating cap pattern 336C and the density of the second insulating cap pattern 238C. Therefore, the volume of the multiple conductive structures (e.g., multiple conductive bonding pads LP3) between the bit lines BL can be increased to suppress an increase in the resistance of the multiple conductive structures and improve the reliability of the integrated circuit device.

[0108] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor device, comprising: Base; Bit lines, on a substrate, extend in a first direction parallel to the top surface of the substrate and include a metal layer; An insulating cover structure, on the positioning line, includes a first insulating cover pattern, a second insulating cover pattern on the first insulating cover pattern, a third insulating cover pattern on the second insulating cover pattern, and a fourth insulating cover pattern on the third insulating cover pattern. The contact plug is positioned adjacent to the bit line; A bonding pad is disposed on a contact plug and extends on an insulating cap structure, the bonding pad comprising a first portion and a second portion thereof on the first portion; as well as The position line spacer is arranged between the position line and the contact plug, and extends on one side of the insulating cover structure. Among them, the metal layer of the contact line on the bottom surface of the first insulating cover pattern of the insulating cover structure. The top surface of the fourth insulating cover pattern of the insulating cover structure contacts the bottom surface of the second part of the bonding pad.

2. The semiconductor device as claimed in claim 1, wherein, The bonding pad includes a barrier layer and a conductive layer.

3. The semiconductor device as claimed in claim 1, wherein, The top surface of the position line spacer contacts the bottom surface of the second part of the bonding pad.

4. The semiconductor device as claimed in claim 1, wherein, Bit line spacers include oxides and / or nitrides.

5. The semiconductor device as claimed in claim 1, wherein, The lower width of the first portion of the mating pad in the second direction is greater than the upper width of the contact plug in the second direction, which is parallel to the top surface of the substrate and perpendicular to the first direction.

6. The semiconductor device of claim 1, wherein, The top surface of the first portion of the bonding pad is substantially coplanar with the top surface of the fourth insulating cover pattern of the insulating cover structure and / or the top surface of the bit spacer.

7. The semiconductor device of claim 1, wherein, Each of the first to fourth insulating cover patterns of the insulating cover structure includes silicon nitride.

8. The semiconductor device of claim 1, wherein, The metal layer of the bit line includes tungsten (W).

9. The semiconductor device of claim 1, wherein, The metal layer of the bit line includes nitrogen.

10. The semiconductor device of claim 1, wherein, The position line spacer contacts the side surface of each of the first to fourth insulating cover patterns of the insulating cover structure.

11. A semiconductor device, comprising: The base includes the unit region and the surrounding region; Unit conductive lines are arranged in the unit region of the substrate and include a first metal layer; The unit insulating cover structure is located on the unit conductive line; Peripheral conductive lines are arranged in the peripheral region of the substrate and include a second metal layer; The outer insulating cover structure is located on the outer conductive line; The first wiring is arranged on one side of the unit insulation cover structure and extends on the top surface of the unit insulation cover structure; as well as The second wiring is located on the outer insulating cover structure. The unit insulating cover structure includes: a first unit insulating cover pattern; a second unit insulating cover pattern on the first unit insulating cover pattern; a third unit insulating cover pattern on the second unit insulating cover pattern; and a fourth unit insulating cover pattern on the third unit insulating cover pattern. In this configuration, the first unit insulating cover pattern of the unit insulating cover structure contacts the first metal layer of the unit conductive wire, and the fourth unit insulating cover pattern of the unit insulating cover structure contacts the first wiring. The outer insulating cover structure includes: a first outer insulating cover pattern; a second outer insulating cover pattern on the first outer insulating cover pattern; a third outer insulating cover pattern on the second outer insulating cover pattern; and a fourth outer insulating cover pattern on the third outer insulating cover pattern. The first peripheral insulating cover pattern of the peripheral insulating cover structure contacts the second metal layer of the peripheral conductive wire, and the fourth peripheral insulating cover pattern of the peripheral insulating cover structure contacts the second wiring.

12. The semiconductor device of claim 11, wherein, Each of the first to fourth unit insulating cover patterns in the unit insulating cover structure includes silicon nitride. Each of the first to fourth peripheral insulation cover patterns of the peripheral insulation cover structure includes silicon nitride.

13. The semiconductor device of claim 11, wherein, The first wiring uses the same material as the second wiring.

14. The semiconductor device of claim 11, further comprising: The unit conductive wire spacer is located between the unit insulating cover structure and the first wiring. Among them, the first to fourth unit insulating cover patterns of the unit conductive wire spacer contact the unit insulating cover structure.

15. A semiconductor device, comprising: The substrate includes a device isolation layer defining a first active region and a second active region; Bitline structure, on a first active region of a substrate, includes a conductive line pattern and an insulating cap pattern on the conductive line pattern, the conductive line pattern including a metal layer; The contact plug is arranged adjacent to the bit line structure and is disposed on the second active region and on the device isolation layer; A mating pad is arranged on the contact plug and extends over the insulating cover pattern of the bit line structure; as well as The bit line spacer is arranged between the contact plug and the conductive wire pattern of the bit line structure, and extends on one side of the insulating cover pattern of the bit line structure. The insulating cover pattern of the bit line structure includes: a first insulating cover pattern; a second insulating cover pattern on the first insulating cover pattern; a third insulating cover pattern on the second insulating cover pattern; and a fourth insulating cover pattern on the third insulating cover pattern. In this configuration, the first insulating cover pattern of the bit line structure contacts the metal layer of the conductive line pattern of the bit line structure. The fourth insulating cover pattern of the bit line structure contacts the bonding pad. The width of the lower portion of the mating pad is greater than the width of the upper portion of the contact plug, and The side surface of each of the first to fourth insulating cover patterns of the bit line spacer contact bit line structure insulating cover pattern.

16. The semiconductor device of claim 15, wherein, Bit line spacers include oxides and / or nitrides.

17. The semiconductor device of claim 15, wherein, The bonding pad includes a barrier layer and a conductive layer.

18. The semiconductor device of claim 15, wherein, Each of the first to fourth insulating cover patterns in the bit-line structure includes silicon nitride.

19. The semiconductor device of claim 15, wherein, The top surface of the position line spacer contacts the mating pad.

20. The semiconductor device of claim 15, wherein, The metal layer of the conductive line pattern in the bitline structure includes tungsten (W) and / or nitrogen (N).

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