Structure and method for testing negative bias temperature instability of semiconductor device, and computer program product

Abstract

The invention relates to the technical field of semiconductor manufacturing, and provides a semiconductor device negative bias temperature instability test structure and method, and a computer program product. According to the invention, the semiconductor device to be tested is maintained at a constant temperature through temperature pre-stabilization, and the influence of the temperature on the threshold voltage drift value error is reduced or even avoided; the method comprises the following steps of: circularly applying stress negative bias voltage which is progressively increased according to a preset rule to a grid electrode of a semiconductor device to be tested at a preset time interval, and reducing a recovery effect caused by rapid relaxation of current carriers; the current change is synchronously measured in real time, so that the recovery loss caused by delayed measurement is avoided. According to the invention, the problem that the measurement error of the existing NBTI test is large is solved, the measurement error caused by the recovery effect is reduced, and the high reliability of the NBTI test is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a test structure and method for negative bias temperature instability of a semiconductor device, and a computer program product. Background Art

[0002] With the reduction of the geometric size of microelectronic devices, the characteristics of integrated circuits are more sensitive to micro defects. Various process technologies are getting closer and closer to their basic reliability limits, and reliability problems are becoming more and more prominent. Among them, Negative Bias Temperature Instability (NBTI) is an important factor affecting the reliability of MOS devices. NBTI refers to the performance degradation phenomenon that occurs in PMOS devices under negative bias voltage and high temperature, specifically manifested as an increase in gate leakage current, a negative drift of the threshold voltage, a decrease in subthreshold swing, a decrease in transconductance and saturation drain current, etc. The existing NBTI test methods for semiconductor devices usually apply a stress negative bias voltage to the semiconductor device to be tested for a certain period of time, and then apply a test voltage after removing the stress negative bias voltage, measure the change of specific parameters of the semiconductor device, obtain the change law of parameter degradation with stress time, and thus evaluate the life of the semiconductor device. Usually, when the parameter degradation reaches a certain level, it is used as the criterion for device failure.

[0003] Please refer to Figure 1 , which is a schematic diagram of an existing NBTI test structure for semiconductor devices. Studying the NBTI of PMOS devices, it is found that the existing DC I d -V g The process of measuring NBTI is divided into a stress stage and a recovery stage. In the stress stage, the source s, drain d, and substrate (such as P+sub) body electrode b are grounded, and a stress negative bias voltage V stress is applied to the gate g. An electro-stress-measurement-electro-stress mode is adopted, that is, the stress is interrupted for measurement every once in a while, and then the stress is applied again. In the recovery stage, the stress negative bias voltage V stress is removed, and a test voltage V measure is applied for measurement; the experiment is carried out at room temperature. The semiconductor device is pressurized and measured by a semiconductor parameter analyzer. For PMOS devices, the typical value is -100 mV to ensure that the device operates in the linear region, and a quasi-static scan voltage (the typical scan range for PMOS devices is 0 to -1 V) is applied to the gate g to obtain the I d -V g curve of the device at each moment. The threshold voltage V th can be obtained by using the linear extrapolation method.

[0004] In the existing NBTI test method, from removing the stress negative bias voltage V stress to applying the test voltage V measureDuring the process, the gate g is grounded to GND, that is, V g from V stress is converted to GND and then to V measure . This causes a serious recovery effect in the existing NBTI test. There are large errors in the subsequent device electrical parameter tests of static parameters such as the threshold voltage V th , linear drain current, etc. At the same time, when a stress negative bias voltage is applied to the gate g, the temperature change further increases the fluctuation of the test data, thus unable to accurately reflect the impact caused by the NBTI effect of the semiconductor device. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a test structure, method and computer program product for negative bias temperature instability of semiconductor devices, which can solve the problem of large measurement errors in existing NBTI tests, reduce the measurement errors caused by the recovery effect, and achieve high reliability of NBTI tests.

[0006] To solve the above problems, the present invention provides a test structure for negative bias temperature instability of semiconductor devices, including: a reference parameter calibration module for measuring and obtaining an initial drain current when a reference voltage is synchronously applied to the gate and drain of the semiconductor device to be tested; a constant temperature module for performing temperature pre-stabilization to maintain the semiconductor device to be tested at a constant temperature; a stress application and dynamic gate voltage control module for cyclically applying a stress negative bias voltage to the gate of the semiconductor device to be tested and a first bias voltage to the drain of the semiconductor device to be tested at a preset time interval, wherein the stress negative bias voltage applied in each round increases according to a preset rule; and a sampling and processing module for collecting the real-time drain current at the end of each round of stress negative bias voltage application, calculating and obtaining a threshold voltage drift value as a degradation amount according to the current stress negative bias voltage and the real-time drain current, and ending the cycle when the number of cycles reaches a preset number or the threshold voltage drift value reaches a preset threshold.

[0007] To solve the above problems, the present invention also provides a method for testing the negative bias temperature instability of a semiconductor device, comprising the following steps: calibration and preprocessing of reference parameters, measuring and obtaining an initial drain current when a reference voltage is synchronously applied to the gate and drain of the semiconductor device to be tested, and using a constant temperature module for temperature pre-stabilization to maintain the semiconductor device to be tested at a constant temperature; stress application and dynamic gate voltage control, cyclically applying a stress negative bias voltage to the gate of the semiconductor device to be tested and a first bias voltage to the drain of the semiconductor device to be tested at a preset time interval, wherein the stress negative bias voltage applied in each cycle increases according to a preset rule; and current monitoring and degradation amount extraction, collecting the real-time drain current at the end of each application of the stress negative bias voltage, calculating and obtaining a threshold voltage drift value as the degradation amount based on the current stress negative bias voltage and the real-time drain current, and ending the cycle when the number of cycles reaches a preset number or the threshold voltage drift value reaches a preset threshold.

[0008] To solve the above problems, the present invention also provides a computer program product, comprising a computer program which, when executed by a processor, implements the steps of the above method of the present invention.

[0009] In the above technical solution, the semiconductor device to be tested is maintained at a constant temperature through temperature pre-stabilization, reducing or even avoiding the influence of temperature on the threshold voltage drift value error; by cyclically applying a stress negative bias voltage increasing according to a preset rule to the gate of the semiconductor device to be tested at a preset time interval, the recovery effect caused by the rapid relaxation of carriers is reduced, and the error can be reduced to <5%; by synchronously measuring the current change in real time, the recovery loss caused by delayed measurement is avoided, and the error is further compressed to 2%-3%. Further, high-precision current monitoring and degradation amount extraction are realized through dual-channel synchronous acquisition; through electric field strength optimization, the recovery effect in fast pulse measurement is reduced, and the detection accuracy of the threshold voltage drift value is improved. The present invention solves the problem of large measurement error in the existing NBTI test, reduces the measurement error caused by the recovery effect, and realizes the high reliability of the NBTI test. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0011] Figure 1 FIG. is a schematic diagram of the existing NBTI test structure of a semiconductor device;

[0012] Figure 2Schematic diagram of a test structure for negative bias temperature instability of a semiconductor device provided by an embodiment of the present invention;

[0013] Figure 3 Flowchart of a test method for negative bias temperature instability of a semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0015] Please refer to Figure 2 , which is a schematic diagram of a test structure for negative bias temperature instability of a semiconductor device provided by an embodiment of the present invention. As Figure 2 shown, the test structure described in this embodiment includes: a reference parameter calibration module 21, a constant temperature module 22, a stress application and dynamic gate voltage control module 23, and a sampling and processing module 24. The semiconductor device 20 to be tested has a source electrode s, a drain electrode d, a gate electrode g, and a substrate body electrode b.

[0016] Specifically, the reference parameter calibration module 21 is used to measure and obtain the initial drain current I 0 when a reference voltage V 0 is synchronously applied to the gate g and the drain d of the semiconductor device 20 to be tested. The constant temperature module 22 is used to perform temperature pre-stabilization to maintain the semiconductor device 20 to be tested at a constant temperature. The stress application and dynamic gate voltage control module 23 is used to cyclically apply a stress negative bias voltage V stress to the gate g of the semiconductor device 20 to be tested at a preset time interval, and apply a first bias voltage V d to the drain d of the semiconductor device 20 to be tested; wherein, the stress negative bias voltage V stress applied in each round increases according to a preset rule. The sampling and processing module 24 is used to collect the real-time drain current I stress at the end of each round of stress negative bias application, and calculate and obtain a threshold voltage drift value ΔV stress as a degradation amount according to the current stress negative bias voltage V stress and the real-time drain current I th ; the sampling and processing module 24 is further used to end the cycle when the number of cycles reaches a preset number or the threshold voltage drift value ΔV th reaches a preset threshold.

[0017] In some embodiments, the reference parameter calibration module 21 measures and obtains the initial drain current I 0 specifically as follows: applying a reference voltage V 0, a reference voltage V is synchronously applied to the drain d 0 , and the drain current in the linear region is measured as the initial drain current I 0 . In some embodiments, the reference voltage V 0 can ensure that the semiconductor device 20 to be measured operates in the linear region, and the measurement accuracy can reach ±0.1 nA. In some embodiments, the reference voltage V 0 can be set to be close to or equal to a predetermined reference threshold voltage V th0 . Specifically, the range of the reference voltage V 0 is 50 - 100 mV. The reference threshold voltage V th0 can be extracted from the I d -V g curve by using the second-order differential method, or can be determined by the inflection point method of the transfer characteristic curve; the obtained reference threshold voltage V th0 error < ±2 mV. It should be noted that the measured parameters of the semiconductor device and the values of the voltages applied to each terminal need to satisfy that the semiconductor device is in the linear region, but it does not mean that the parameters are invalid in the non-linear region.

[0018] In some embodiments, the constant temperature module 22 includes a thermoelectric cooler (Thermoelectric cooler, abbreviated as TEC), and the ceramic heating plate of the thermoelectric cooler is attached to the back of the wafer of the semiconductor device 20 to be measured to heat and control the temperature of the wafer. The thermoelectric cooler, also called a semiconductor cooler, is a heat dissipation device made by using the Peltier effect (also known as the thermoelectric effect). In other embodiments, other constant temperature methods can also be selected to maintain the semiconductor device 20 to be measured at a constant temperature. In some embodiments, the constant temperature is 125°C ± 0.3°C, and the required operating temperatures for testing different semiconductor devices include but are not limited to 125°C.

[0019] Research shows that due to the self-heating effect, the operating temperature of the semiconductor device may be very high. Temperature is a significant condition affecting NBTI. When a stress negative bias voltage is applied to the gate, the temperature change further increases the fluctuation of the test data, and the threshold voltage drift value ΔV th error is significantly affected by temperature stability. And in this embodiment, by adding the constant temperature module 22, the semiconductor device 20 to be measured is maintained at a constant temperature, reducing or even avoiding the influence of the temperature on the threshold voltage drift value ΔV th error, so as to accurately reflect the influence caused by the NBTI effect of the semiconductor device.

[0020] In some embodiments, the stress application and dynamic gate voltage control module 23 is further configured to dynamically adjust the stress negative bias voltage V ox according to the gate oxide layer thickness T stress, to maintain the electric field strength E ox within the range of 8 - 12 MV / cm (with a fluctuation of <±3%). Specifically, the thickness T of the gate oxide layer ox can be directly obtained through process parameters or TEM measurement; considering the difference between the actual stress negative bias voltage V stress and the flat-band voltage V FB , the voltage drop V across the gate oxide layer ox = V stress - V FB , and the electric field strength E ox = V ox / T ox . Through the optimization of the electric field strength, the recovery effect in the fast pulse measurement can be reduced in the NBTI stress test, and the detection accuracy of the threshold voltage drift value ΔV th can be improved.

[0021] In some embodiments, the stress negative bias voltage is a short pulse voltage with an application time Δt less than 10 ms. Specifically, a sub-millisecond stress pulse can be applied: a short pulse stress with Δt = 5 ms (< the upper limit of 10 ms) is used, and the fast voltage switching (switching the stress negative bias voltage V stress , with a switching time < 500 ns) is realized through the NBTI test machine itself to suppress the recovery effect. Among them, the sub-millisecond stress pulse less than 10 ms includes but is not limited to Δt = 5 ms.

[0022] In some embodiments, the preset time interval between the stress application and the dynamic gate voltage control module 23 applying the stress negative bias voltage V stress to the gate g of the semiconductor device 20 to be measured can be the same or different; the application times of the stress negative bias voltage V stress can be the same or different.

[0023] In some embodiments, the stress negative bias voltage V stress increases according to an exponential law, and the growth rate S is 1.05 - 1.15. Specifically, V stressi = S^(i - 1)·V stress(i-1) ; S = 1.05 - 1.15. For example: V stress → 1.1V stress → 1.21V stress Linear gradient. By using a linearly gradient stress negative bias voltage (instead of a step change), the recovery effect caused by the rapid relaxation of carriers is reduced, and the error can be reduced to < 5%. Then, by synchronously measuring the real-time change of the real-time drain current I stress (it is also possible to further measure, such as the sub-threshold leakage current I sub or the channel current I d ), the recovery loss caused by the existing delayed measurement is avoided, and the error is further compressed to 2% - 3%.

[0024] In some embodiments, the first bias voltage V d is 0V, which can eliminate the interference of channel carrier recombination on the release of interface state charges. That is, the drain is synchronously applied with the reference voltage V 0 during the reference parameter calibration and preprocessing stage and remains at 0V during the stress stage.

[0025] In some embodiments, the sampling and processing module 24 is further configured to synchronously collect the real-time drain current I stress and background noise at a sampling frequency greater than or equal to 20MHz, and use differential amplification technology to improve the current resolution to 0.1pA level. High-precision current monitoring and degradation amount extraction are achieved through dual-channel synchronous acquisition. The degradation amount, that is, the calculated threshold voltage drift value ΔV th .

[0026] When the number of cycles reaches a preset number or the threshold voltage drift value ΔV th reaches a preset threshold, the loop ends. The end point of the total NBTI loop is jointly determined by the preset threshold or the number of cycles, and the specific value can be dynamically adjusted according to the test objectives (such as process verification, model fitting, etc.). In some embodiments, it can be set that when the threshold voltage drift value ΔV th reaches 10% - 20% of the reference threshold voltage V th0 , the loop is terminated. At this time, the corresponding stress negative bias voltage V stress value is usually in the range of 1.5 - 2 times the reference threshold voltage V th0 (specifically depending on the process node).

[0027] In some embodiments, the sampling and processing module 24 is further configured to insert a retest of the initial drain current I stress after each round of collecting the real-time drain current I 0 . That is, after each round of collecting the real-time drain current I stress , the gate is switched to apply the reference voltage V 0 , the drain is synchronously applied with V 0 , and the initial drain current I 0 in the linear region is measured again. By inserting a retest of the initial drain current I 0 (interval <1ms) in each round of loop, the temperature drift and instrument drift errors are eliminated.

[0028] In some embodiments, the threshold voltage drift ΔV stress is calculated once every time the stress negative bias voltage V th increases. Specifically, the threshold voltage drift value is calculated using the following formula:

[0029]

[0030] wherein, ΔV thi is the threshold voltage drift value after the i-th cycle, I 0 is the initial drain current, I stressi is the real-time drain current after the i-th cycle, V stressi is the stress negative bias voltage after the i-th cycle, V th0 is a pre-determined reference threshold voltage.

[0031] In this embodiment, the test structure further includes: a model dynamic correction and verification module (not shown); the model dynamic correction and verification module is configured to establish a degradation model according to the threshold voltage drift value, and fit the threshold voltage drift value with the cumulative stress time to establish a combined power law-reaction diffusion model, and form a quantization model by combining the degradation model and the power law-reaction diffusion model to quantify the threshold voltage drift value; wherein, abnormal data points are removed by the 3σ principle to ensure that the fitting determination coefficient is greater than 0.99.

[0032] Based on the same inventive concept, the present invention further provides a method for testing the negative bias temperature instability of a semiconductor device, which can adopt the above-mentioned test structure for the negative bias temperature instability of a semiconductor device of the present invention to solve the problem of large measurement error in the existing NBTI test, reduce the measurement error caused by the recovery effect, and achieve high reliability of the NBTI test.

[0033] Please refer to Figure 2 and Figure 3 , wherein, Figure 3 is a flowchart of a method for testing the negative bias temperature instability of a semiconductor device provided by an embodiment of the present invention.

[0034] As Figure 3 shown, the method for testing the negative bias temperature instability of a semiconductor device in this embodiment includes the following steps: S1, calibration and preprocessing of reference parameters, measuring and obtaining the initial drain current when a reference voltage is synchronously applied to the gate and drain of the semiconductor device to be tested, and using a constant temperature module to perform temperature pre-stabilization to maintain the semiconductor device to be tested at a constant temperature; S2, stress application and dynamic gate voltage control, cyclically applying a stress negative bias voltage to the gate of the semiconductor device to be tested and a first bias voltage to the drain of the semiconductor device to be tested at a preset time interval, wherein the stress negative bias voltage applied in each round increases according to a preset rule; and S3, current monitoring and extraction of degradation amount, collecting the real-time drain current at the end of each round of stress negative bias voltage application, calculating and obtaining the threshold voltage drift value according to the current stress negative bias voltage and the real-time drain current, and ending the cycle when the number of cycles reaches a preset number or the threshold voltage drift value reaches a preset threshold.

[0035] Regarding step S1, calibration and preprocessing of reference parameters, when a reference voltage is synchronously applied to the gate and drain of the semiconductor device to be measured, an initial drain current is measured and obtained, and a constant temperature module is used for temperature pre-stabilization to maintain the semiconductor device to be measured at a constant temperature.

[0036] In some embodiments, a reference voltage V can be applied to the gate g of the semiconductor device 20 to be measured 0 , and a reference voltage V is synchronously applied to the drain d 0 , and the drain current in the linear region is measured as the initial drain current I 0 . In some embodiments, the reference voltage V 0 can ensure that the semiconductor device 20 to be measured operates in the linear region, and the measurement accuracy can reach ±0.1 nA. In some embodiments, the reference voltage V 0 can be set to be close to or equal to a predetermined reference threshold voltage V th0 . Specifically, the range of the reference voltage V 0 is 50 - 100 mV. The reference threshold voltage V th0 can be extracted from the I d - V g curve by using the second-order differential method, or can be determined by the inflection point method of the transfer characteristic curve; the obtained reference threshold voltage V th0 has an error < ±2 mV. It should be noted that the measured parameters of the semiconductor device and the values of the voltages applied to each terminal need to satisfy that the semiconductor device is in the linear region, but it does not mean that the parameters are invalid in the non-linear region.

[0037] In some embodiments, a thermoelectric cooler (TEC) can be used. The ceramic heating plate of the thermoelectric cooler is attached to the back of the wafer of the semiconductor device 20 to be measured to heat and control the temperature of the wafer. In other embodiments, other constant temperature methods can also be selected to maintain the semiconductor device 20 to be measured at a constant temperature. In some embodiments, the constant temperature is 125°C ± 0.3°C, and the required operating temperatures for testing different semiconductor devices include but are not limited to 125°C.

[0038] Regarding step S2, stress application and dynamic gate voltage control, a stress negative bias voltage is cyclically applied to the gate of the semiconductor device to be measured and a first bias voltage is applied to the drain of the semiconductor device to be measured at a preset time interval, wherein the stress negative bias voltage applied in each round increases according to a preset rule.

[0039] In some embodiments, the stress negative bias voltage is a short-pulse voltage with an application time Δt less than 10 ms. Specifically, a sub-millisecond stress pulse can be applied: a short-pulse stress with Δt = 5 ms (< the upper limit of 10 ms) is used, and fast voltage switching (switching the stress negative bias voltage V stress , with a switching time < 500 ns) is achieved through the NBTI test machine itself to suppress the recovery effect. Among them, the sub-millisecond stress pulses less than 10 ms include but are not limited to Δt = 5 ms.

[0040] In some embodiments, in the step S2, the stress negative bias voltage V stress is applied to the gate g of the semiconductor device 20 to be tested, and the preset time intervals can be the same or different; the application times of the stress negative bias voltage V stress can be the same or different.

[0041] In some embodiments, the stress negative bias voltage V stress increases according to an exponential law, and the growth rate S is 1.05 - 1.15. Specifically, V stressi = S^(i - 1)·V stress(i-1) ; S = 1.05 - 1.15. For example: V stress → 1.1V stress → 1.21V stress Linear gradient. By using a linearly graded stress negative bias voltage (instead of a step change), the recovery effect caused by the rapid relaxation of carriers is reduced, and the error can be reduced to < 5%. Then, by synchronously measuring the change of the real-time drain current I stress in real time (it is also possible to further measure, such as the sub-threshold leakage current I sub or the channel current I d ), the recovery loss caused by the existing delayed measurement is avoided, and the error is further compressed to 2% - 3%.

[0042] In some embodiments, the first bias voltage V d is 0V, which can eliminate the interference of channel carrier recombination on the release of interface state charges. That is, the drain is synchronously applied with the reference voltage V 0 during the reference parameter calibration and preprocessing stage and remains at 0V during the stress stage.

[0043] In some embodiments, the step S2 further includes: dynamically adjusting the stress negative bias voltage V ox according to the gate oxide layer thickness T stress of the semiconductor device 20 to be tested, so as to maintain the electric field strength E ox within the range of 8 - 12 MV / cm (with a fluctuation of < ±3%). Specifically, the gate oxide layer thickness T ox can be directly obtained through process parameters or TEM measurement; considering the actual stress negative bias voltage Vstress The difference from the flat-band voltage V FB , the voltage drop V ox on the gate oxide layer = V stress - V FB . The electric field strength E ox = V ox / T ox . Through the optimization of the electric field strength, the recovery effect in the fast pulse measurement can be reduced in the NBTI stress test, and the detection accuracy of the threshold voltage drift value ΔV th can be improved.

[0044] Regarding step S3, current monitoring and degradation amount extraction, the real-time drain current is collected at the end of each round of stress negative bias application, and the threshold voltage drift value is calculated based on the current stress negative bias and the real-time drain current as the degradation amount, and the loop ends when the number of cycles reaches the preset number or the threshold voltage drift value reaches the preset threshold.

[0045] In some embodiments, step S3 specifically includes: synchronously collecting the real-time drain current I stress and the background noise at a sampling frequency greater than or equal to 20 MHz, and using the differential amplification technology to improve the current resolution to 0.1 pA level. High-precision current monitoring and degradation amount extraction are achieved through dual-channel synchronous acquisition. The degradation amount, that is, the calculated threshold voltage drift value ΔV th .

[0046] The loop ends when the number of cycles reaches the preset number or the threshold voltage drift value ΔV th reaches the preset threshold. The end point of the total NBTI loop is jointly determined by the preset threshold or the number of cycles, and the specific value can be dynamically adjusted according to the test objectives (such as process verification, model fitting, etc.). In some embodiments, it can be set to terminate the loop when the threshold voltage drift value ΔV th reaches 10% - 20% of the reference threshold voltage V th0 . At this time, the corresponding stress negative bias V stress value is usually in the range of 1.5 - 2 times the reference threshold voltage V th0 (specifically depending on the process node).

[0047] In some embodiments, step S3 further includes: inserting a retest of the initial drain current I stress after each round of collecting the real-time drain current I 0 . That is, after each round of collecting the real-time drain current I stress , the gate is switched to apply the reference voltage V 0 , the drain is synchronously applied with V 0 , and the initial drain current I 0 in the linear region is measured again.By inserting an initial drain current I 0 Repeated measurement (interval <1ms) eliminates temperature drift and instrument drift errors.

[0048] In some embodiments, the stress negative bias voltage V stress Each time the threshold voltage increases, the threshold voltage drifts ΔV th Calculate once. Specifically, the threshold voltage drift value is calculated using the following formula:

[0049]

[0050] Where, ΔV thi is the threshold voltage drift value after the i-th cycle, I 0 is the initial drain current, I stressi is the real-time drain current after the i-th cycle, V stressi is the stress negative bias after the i-th cycle, V th0 is a predetermined reference threshold voltage.

[0051] In this embodiment, the method further includes: establishing a degradation model according to the threshold voltage drift value, and fitting the threshold voltage drift value with the cumulative stress time to establish a power law-reaction diffusion joint model, combining the degradation model with the power law-reaction diffusion joint model to form a quantitative model to quantify the threshold voltage drift value; wherein, the abnormal data points are eliminated by the 3σ principle to ensure that the fitting determination coefficient is greater than 0.99 (i.e., R 2 >0.99).

[0052] According to the threshold voltage drift value ΔV th The degradation model established is used to describe the device parameter degradation caused by the NBTI effect. Its core is to fit the degradation trend through experimental data. The degradation model derivation is often combined with the power law-reaction diffusion joint model to form a joint model, which maps the experimental data into a computable mathematical expression to quantify the threshold voltage drift value ΔV th .

[0053] Specifically, the fitting formula of the power law-reaction diffusion joint model is:

[0054]

[0055] Where, ΔV th is the threshold voltage drift value, E is the electric field strength applied to the semiconductor device to be tested, V stress is the stress negative bias, e is the charge of a single electron, Q is the interface trap charge density, τ is the recovery time constant, t is the accumulated stress time, and n is the time index.

[0056] E: The electric field strength applied to the semiconductor device under test, which accelerates the carrier migration and defect generation. Considering the actual stress negative bias voltage V stress and the difference from the flat-band voltage V FB , the voltage drop V ox = V stress - V FB , and the electric field strength E ox = V ox / T ox .

[0057] V stress : The stress negative bias voltage applied to the gate of the semiconductor device under test, which determines the chemical reaction rate at the device interface.

[0058] e: The electric charge of a single electron, a fundamental physical constant. e = 1.602×10 -19 C (Coulomb).

[0059] Q: The interface trap charge density, which is jointly determined by hydrogen atom diffusion and chemical reaction. It can be calculated through the flat-band voltage offset value (ΔV FB ) of the high-frequency C-V curve: Q = C ox ΔV FB / e. In the NBTI test, Q approaches 2.5 - 3.5 cm / MV

[0060] τ: The recovery time constant (≈1 ms), which reflects the dynamic balance between the diffusion process and the chemical reaction rate at the interface. Specifically, the recovery time constant τ can be expressed by the following formula:

[0061] τ ∝ D -1 ·R(Q) -1 .

[0062] Among them, D is the diffusion coefficient of hydrogen atoms in the gate oxide layer. Tracer atom method: At a specific temperature, by measuring the relationship between the diffusion distance and time of atoms or vacancies in the material and combining with Fick's law to calculate the D value. In the NBTI research of MOSFET, through high-temperature stress experiments, D ≈ 10 -14 cm 2 / s, and the high-temperature is 125°C. R(Q) is the reaction rate term; The fitting of R(Q): For the interface trap generation of silicon-based oxide layers, experiments show that R(Q) = k·Q, where k ≈ 10 -3 s -1 (fitted through the saturation characteristics of ΔV th ).

[0063] t: The cumulative stress time.

[0064] n: The time exponent (usually written as ΔV th ∝ tn ), which is a key parameter describing the growth rate of the threshold voltage drift value ΔV th with the cumulative stress time t. In the NBTI test, n approaches 0.15 - 0.25. Specifically, the time exponent n can be determined by the following relationship:

[0065]

[0066] D is the diffusion coefficient of hydrogen atoms in the gate oxide layer, D ≈ 10 -14 cm 2 / s; Kr is the interface reaction rate constant, Kr = 10 -3 -10 -1 s -1 , (Kr = Q / (t·[H]0) is obtained from the interface trap charge density, and [H]0 is the hydrogen concentration).

[0067] Error verification: Comparing the measurement results of the existing step stress method (error > 20%) and the measurement results of the test method provided by the present invention for the same semiconductor device, as shown in Table 1 below. (Error < 3%)

[0068] Technical indicators Existing methods The method of the present invention <![CDATA[ΔV th Measurement error]]> >10％ <3％ Single test time 1 - 2 hours <30 minutes Temperature stability ±1℃ ±0.3℃ Electric field uniformity ±10％ ±3％

[0069] Table 1: Comparison of the measurement results of the existing step stress method and the test method provided by the present invention for the same semiconductor device

[0070] It can be seen from Table 1 that the measurement results obtained by using the test method provided by the present invention solve the problem of large measurement errors in the existing NBTI test, reduce the measurement errors caused by the recovery effect, and achieve high reliability of the NBTI test; and reduce the single - test time, which can improve the test efficiency.

[0071] Furthermore, the method further includes: real - time monitoring of the drift trend of the threshold voltage drift value ΔV th through LabVIEW or Python scripts, and dynamically adjusting the increasing growth rate S of the stress negative bias voltage V stress . By integrating a reference parameter calibration module, a constant - temperature module, a stress application and dynamic gate voltage control module, and a sampling and processing module, and through hardware collaborative control, the whole process of stress loading - measurement - data processing is automated, and the cycle error < 1 μs. The dynamic adjustment of the increasing growth rate S of the stress negative bias voltage V stress can be achieved through the test machine platform settings, and the dynamic adjustment rules of the growth rate S coefficient can be generated according to the multi - physical - field coupling simulation. For example, tools such as Sentaurus TCAD can be used to simulate temperature (T), gate voltage (V g ), and gate oxide layer thickness (T oxAfter the impact on NBTI, a dynamic adjustment rule for the growth rate S coefficient is generated.

[0072] In the above embodiments, the semiconductor device to be tested is maintained at a constant temperature through temperature pre-stabilization, reducing or even avoiding the influence of temperature on the threshold voltage drift value error; by cyclically applying a stress negative bias voltage that increases according to a preset rule to the gate of the semiconductor device to be tested at a preset time interval, the recovery effect caused by the rapid relaxation of carriers is reduced, and the error can be reduced to <5%; by synchronously measuring the current change in real time, the recovery loss caused by delayed measurement is avoided, and the error is further compressed to 2%-3%. Further, high-precision current monitoring and degradation amount extraction are achieved through dual-channel synchronous acquisition; through electric field strength optimization, the recovery effect in fast pulse measurement is reduced, and the detection accuracy of the threshold voltage drift value is improved. The present invention solves the problem of large measurement errors in existing NBTI tests, reduces the measurement errors caused by the recovery effect, and realizes high reliability in NBTI tests.

[0073] Based on the same inventive concept, the present invention also provides a computer program product, including a computer program, which when executed by a processor implements the steps of the foregoing method of the present invention.

[0074] Based on the same inventive concept, the present invention also provides a computer device, including: a memory for storing a computer program; a processor connected to the memory for executing the computer program to implement the steps of the foregoing method of the present invention.

[0075] Based on the same inventive concept, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the steps of the foregoing method of the present invention.

[0076] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided by the present invention can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus (Ram Bus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0077] It should be noted that in the above embodiments, each embodiment focuses on the differences from other embodiments. For the same / similar parts among the embodiments, reference can be made to each other.

[0078] The terms "including" and "having" and their variants involved in the documents of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. Unless the context clearly indicates, it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context and can be used to describe a feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but instead, and also at least in part depending on the context, allows for the existence of other factors that are not necessarily explicitly described. Additionally, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention.

[0079] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A test structure for negative bias temperature instability of a semiconductor device, characterized in that: include: A reference parameter calibration module, used for measuring and obtaining an initial drain current when a reference voltage is synchronously applied to the gate and drain of the semiconductor device to be tested; A constant temperature module, used for pre-stabilizing the temperature so as to maintain the semiconductor device to be tested at a constant temperature; A stress application and dynamic gate voltage control module, used to cyclically apply a stress negative bias voltage to the gate of the semiconductor device under test and a first bias voltage to the drain of the semiconductor device under test at preset time intervals, wherein the stress negative bias voltage applied in each round increases according to a preset rule; as well as The sampling and processing module is used to collect the real-time drain current at the end of each round of stress negative bias application, and calculate the threshold voltage drift value as the degradation amount according to the current stress negative bias and the real-time drain current, and end the cycle when the number of cycles reaches a preset number or the threshold voltage drift value reaches a preset threshold.

2. The test structure for negative bias temperature instability of a semiconductor device according to claim 1, characterized in that: The constant temperature module comprises a thermoelectric cooler, and a ceramic heating plate of the thermoelectric cooler is attached to the back side of the wafer of the semiconductor device to be tested so as to heat and control the temperature of the wafer.

3. The test structure for negative bias temperature instability of a semiconductor device according to claim 1, characterized in that: The reference voltage can ensure that the semiconductor device under test operates in the linear region, and the range of the reference voltage is 50-100mV; the constant temperature is 125℃±0.3℃; the stress negative bias is a short pulse voltage with an application time of less than 10ms; the stress negative bias increases exponentially and the growth rate is 1.05-1.15; the first bias voltage is 0V.

4. The test structure for negative bias temperature instability of a semiconductor device according to claim 1, characterized in that: The sampling and processing module is further used to synchronously collect the real-time drain current and background noise at a sampling frequency greater than or equal to 20 MHz, and use differential amplification technology to improve the current resolution to 0.1 pA level.

5. A method for testing negative bias temperature instability of a semiconductor device, characterized in that: The steps include: Reference parameter calibration and preprocessing, measuring and obtaining the initial drain current when the reference voltage is synchronously applied to the gate and drain of the semiconductor device to be tested, and using a constant temperature module to perform temperature pre-stabilization to maintain the semiconductor device to be tested at a constant temperature; Stress application and dynamic gate voltage control, cyclically applying a stress negative bias voltage to the gate of the semiconductor device under test and applying a first bias voltage to the drain of the semiconductor device under test at a preset time interval, wherein the stress negative bias voltage applied in each round increases according to a preset rule; as well as Current monitoring and degradation amount extraction, collecting real-time drain current at the end of each round of stress negative bias application, and calculating the threshold voltage drift value as the degradation amount based on the current stress negative bias and the real-time drain current, and ending the cycle when the number of cycles reaches a preset number or the threshold voltage drift value reaches a preset threshold.

6. The method according to claim 5, characterized in that The reference voltage can ensure that the semiconductor device under test operates in the linear region, and the range of the reference voltage is 50-100mV; the constant temperature is 125℃±0.3℃; the stress negative bias is a short pulse voltage with an application time of less than 10ms; the stress negative bias increases exponentially and the growth rate is 1.05-1.15; the first bias voltage is 0V.

7. The method according to claim 5, characterized in that The steps of stress application and dynamic gate voltage control specifically include: The stress negative bias voltage is dynamically adjusted according to the gate oxide layer thickness of the semiconductor device to be tested, so as to maintain the electric field strength within the range of 8-12 MV / cm.

8. The method according to claim 5, characterized in that The steps of current monitoring and degradation amount extraction specifically include: At the end of each round of negative bias stress application, the real-time drain current and background noise are synchronously collected at a sampling frequency greater than or equal to 20 MHz, and the current resolution is improved to 0.1 pA level using differential amplification technology; and After each round of collecting the real-time drain current, a retest of the initial drain current is inserted.

9. The method according to claim 5, characterized in that The steps of current monitoring and degradation amount extraction specifically include: The threshold voltage drift value is calculated using the following formula: Where, ΔV thi is the threshold voltage drift value after the i-th cycle, I0 is the initial drain current, I stressi is the real-time drain current after the i-th cycle, V stressi is the stress negative bias after the i-th cycle, V th0 is a predetermined reference threshold voltage.

10. The method according to claim 5, characterized in that The method further comprises: A degradation model is established according to the threshold voltage drift value, and a power law-reaction diffusion joint model is established by fitting the threshold voltage drift value with the accumulated stress time, and a quantization model is formed by combining the degradation model with the power law-reaction diffusion joint model to quantify the threshold voltage drift value; Among them, the 3σ principle was used to eliminate abnormal data points to ensure that the fitting determination coefficient was greater than 0.

99.

11. The method according to claim 10, characterized in that The fitting formula of the power law-reaction diffusion joint model is: Where, ΔV th is the threshold voltage drift value, E is the electric field strength applied to the semiconductor device to be tested, V stress is the stress negative bias, e is the charge of a single electron, Q is the interface trap charge density, τ is the recovery time constant, t is the accumulated stress time, and n is the time index.

12. The method according to claim 5, characterized in that The method further comprises: The drift trend of the threshold voltage drift value is monitored in real time through LabVIEW or Python script, and the incremental growth rate of the stress negative bias voltage is dynamically adjusted.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 5 to 12 are implemented.

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