Layout and wiring cooperation method and device for eliminating odd ring violation, equipment and medium

Abstract

The application provides a layout and wiring cooperative odd loop violation elimination method and device, equipment and medium, which are applied to the technical field of integrated circuit layout and wiring, the possible power connection or ground connection via regions are created by systematically traversing each standard cell, and potential odd loop violations are detected in these regions, and the prohibited regions where the power connection or ground connection via cannot be placed are marked, so that the prohibited regions can be avoided when the power connection or ground connection via is placed in the layout legalization stage. Through the cooperative feedback mechanism between the layout and the wiring, the odd loop problem that cannot be solved in the wiring stage can be eliminated in advance, the design efficiency is significantly improved, the design process of the integrated circuit is optimized, and the design cost is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit placement and routing technology, specifically to a method, apparatus, device, and medium for collaboratively eliminating odd-numbered loop violations in placement and routing. Background Technology

[0002] As semiconductor manufacturing process nodes continue to shrink, the spacing between adjacent vias becomes increasingly smaller, making it difficult to meet the minimum resolution requirements of photolithography systems. To address this, Double-Patterning Technology (DPT) has emerged. It decomposes complex patterns originally designed on a single mask layer into multiple different mask layers, ensuring that the via spacing within each mask layer is greater than the minimum resolution of the photolithography system.

[0003] In integrated circuit design, when an odd number of vias form a closed loop and the spacing between each adjacent via is less than the minimum lithographic spacing, these vias cannot be separated. This phenomenon is called "odd-number loop violation".

[0004] Currently, solutions to odd-numbered loop violations mainly focus on the routing phase, specifically removing and rerouting the lines in areas where odd-numbered loop violations occur during detailed routing. However, since power / ground vias (pg vias) are fixed during the layout phase, existing methods cannot completely eliminate odd-numbered loop violations.

[0005] Therefore, a new integrated circuit placement and routing design method is needed. Summary of the Invention

[0006] In view of this, embodiments of this specification provide a method, apparatus, device, and medium for collaborative elimination of odd-numbered loop violations through placement and routing. By identifying and avoiding potential odd-numbered loop violations during the placement phase, odd-numbered loops that cannot be resolved during the routing phase are eliminated, thereby optimizing the integrated circuit design process and improving production efficiency and the quality of the final product.

[0007] The embodiments in this specification provide the following technical solutions:

[0008] This specification provides an embodiment of a method for collaboratively eliminating odd-numbered loop violations in integrated circuit placement and routing, including:

[0009] For each standard cell, perform the following traversal to determine prohibited areas where power or ground vias cannot be placed:

[0010] Based on the physical structure of existing through-holes in the standard cell, create areas where power or grounding through-holes may be placed to obtain candidate areas;

[0011] Odd-number loop violation detection is performed on the candidate area to determine whether the pre-placed power supply or grounding via and the functional via form an odd-number loop violation.

[0012] If an odd number of loops are violated, the corresponding candidate area is marked as a prohibited area so that the prohibited area is skipped during the layout legalization stage when placing power or grounding vias.

[0013] This specification also provides an integrated circuit placement and routing collaborative elimination device for odd-numbered loop violations, which includes: a candidate region generation module and an odd-numbered loop violation detection module;

[0014] The candidate region generation module creates regions where power or grounding vias may be placed based on the physical structure of existing vias in the standard unit, thus obtaining candidate regions.

[0015] The odd-numbered loop violation detection module is used to perform odd-numbered loop violation detection on the candidate area and determine whether the pre-placed power supply or grounding through hole and the functional through hole form an odd-numbered loop violation.

[0016] If an odd number of cycles is formed, which is a violation, the corresponding candidate region will be marked as a prohibited region.

[0017] This specification also provides an electronic device, including:

[0018] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: a method for collaborative elimination of odd-numbered loop violations in integrated circuit layout and routing as described in any one of this application.

[0019] This specification also provides a computer storage medium storing computer-executable instructions that, when executed by a processor, perform: the method for collaborative elimination of odd-numbered loop violations in integrated circuit layout and routing as described in any one of this application.

[0020] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0021] By systematically traversing each standard cell, regions where power or ground vias may be placed are created, and potential odd-numbered loop violations are detected in these regions. Prohibited regions where power or ground vias cannot be placed are marked, thus avoiding these prohibited regions when placing power or ground vias during the placement legalization stage. Through the collaborative feedback mechanism between placement and routing, odd-numbered loop problems that cannot be resolved during the routing stage can be eliminated in advance, significantly improving design efficiency, optimizing the integrated circuit design process, and reducing design costs. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This application describes a method for collaboratively eliminating odd-numbered loop violations in integrated circuit placement and routing. Figure 1 ;

[0024] Figure 2 This is a flowchart of the odd-numbered ring violation detection process in this application;

[0025] Figure 3 This application describes a method for collaboratively eliminating odd-numbered loop violations in integrated circuit placement and routing. Figure 2 . Detailed Implementation

[0026] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0027] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0029] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0030] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0031] In the current integrated circuit design process, the placement stage and the routing stage are handled separately and independently.

[0032] The traditional design flow is to place first and then route, with each stage executed strictly linearly. The initial layout generated in the placement phase is optimized during the placement legitimization stage to meet specific design rules and constraints (such as minimum spacing and alignment requirements), determining the final positions of standard cells. After placement legitimization, pin access vias are created for the input / output pins of each standard cell to establish electrical connections in subsequent routing stages.

[0033] If an odd-number loop violation (a closed loop formed by an odd number of vias with a spacing smaller than the lithography requirement) is detected during the routing phase, the area with the odd-number loop violation needs to be removed and rerouted. However, since the power / ground vias (PGVs) are fixed during the placement phase, the resulting odd-number loop violation cannot be eliminated by routing adjustments, and repeated rework increases iteration costs.

[0034] In view of this, the inventors discovered through research and improvement that the current method of removing and redistributing the wires in the odd-numbered loop violation area, which only adjusts the signal vias, cannot eliminate the odd-numbered loop violation problem. Moreover, unresolved odd-numbered loop violations can lead to lithography failure or electrical short circuits, thereby reducing the chip manufacturing yield.

[0035] Based on this, this specification proposes a method for collaboratively eliminating odd-numbered ring violations in integrated circuit placement and routing. The overall idea is as follows: First, pin access vias are created. Then, each standard cell is systematically traversed. Based on the via location and lithography rules, candidate regions for placing power / ground vias (pg vias) are created. Odd-numbered ring violations are detected, and candidate regions with detected odd-numbered ring violations are marked as forbidden boxes. This guides the placement of power / ground vias during the placement legalization stage to avoid these forbidden boxes. As a result, the violation regions of pg vias can be resolved during the placement stage, avoiding the burden of repairing odd-numbered ring violations encountered during the routing stage. This significantly improves the efficiency of the entire design process, reduces design iterations, lowers costs, and ultimately improves the quality and reliability of integrated circuit products.

[0036] It should be noted that this application creates pin accesses before the layout legalization stage and identifies prohibited areas where power or ground vias cannot be placed. This allows the risk of potential odd-numbered loop violations to be considered during the layout stage and the violation locations of PG vias to be eliminated in advance, effectively preventing the occurrence of odd-numbered loop violations. This solves the problem that traditional solutions struggle to address during the routing stage and significantly improves the accuracy and reliability of the design.

[0037] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0038] like Figure 1 As shown in the embodiments of this specification, a method for collaboratively eliminating odd-numbered loop violations in integrated circuit placement and routing is provided, including:

[0039] For each standard cell, perform the following traversal to determine prohibited areas where power or ground vias cannot be placed:

[0040] Step S1: Based on the physical structure of the existing through holes in the standard cell, create areas where power supply or grounding through holes may be placed to obtain candidate areas;

[0041] Specifically, a detailed examination is conducted on each standard cell, using the physical structure of existing vias (such as location and shape information) to simulate the placement of power or ground connections (Power / Ground via, pg via) and identify possible candidate areas.

[0042] Step S2: Perform odd-numbered loop violation detection on the candidate area to determine whether the pre-placed power supply or grounding via and the functional via form an odd-numbered loop violation.

[0043] If an odd number of loops are violated, the corresponding candidate area is marked as a prohibited area so that the prohibited area is skipped during the layout legalization stage when placing power or grounding vias.

[0044] Specifically, odd-ring violation detection is performed on these potential candidate areas to assess whether placing vias will result in an odd-ring violation with functional vias. If the detection results indicate a violation risk, the corresponding candidate area will be marked as a forbidden box to guide the subsequent layout process to avoid placing vias in these areas.

[0045] In some embodiments, the standard cell is generated by rotating or flipping the basic cells in the basic cell library;

[0046] Perform the following operations on each basic unit in the aforementioned basic unit library:

[0047] Based on the internal structure of each basic unit, logical deduction is performed to identify candidate areas where power or grounding vias may be placed, and odd-numbered loop violation detection is performed on the candidate areas. Candidate areas where power or grounding vias cannot be placed are marked as prohibited areas.

[0048] By transforming coordinates, the marked forbidden regions in the base cell are adapted to all standard cells generated by rotation or flipping operations to ensure the correct inheritance of forbidden regions.

[0049] Specifically, by centrally managing prohibited areas during the standard cell library design phase, the efficiency and reliability of the layout phase can be significantly improved.

[0050] In the standard cell library, the basic cell (libcell) is the basic cell template that makes up the standard cell template (such as AND gate, flip-flop, etc.), and has a fixed internal structure (including via positions, metal layer connections, etc.).

[0051] The standard cell is generated by flipping libcell at different angles. That is, only the orientation of the standard cell is changed to adapt to the layout requirements, and the relative position of the via is not changed.

[0052] During the libcell design phase, PG via regions that may lead to odd-numbered cycle violations are pre-deduced and marked as forbidden regions (forbidden boxes). Since the standard cells subsequently generated by flipping inherit the internal structure of libcell, including the relative positions of vias, the standard cell instances generated by flipping automatically inherit the forbidden boxes of the original libcell. That is, there is no need to create a separate forbidden box for each flipped cell; it only needs to be defined once at the libcell level, simplifying the design process and thus saving a lot of design time and resources.

[0053] For example, if a libcell contains a pg via and there is a region around it that forms an odd-numbered ring (marked as a forbidden box), and the libcell is rotated 180° to generate a new standard cell, the position of the pg via will rotate with the whole, that is, the relative position of the forbidden box will also rotate synchronously, so that the odd-numbered ring violation can still be effectively avoided in the new direction.

[0054] In some embodiments, when performing odd-numbered loop violation detection on the candidate region, if the functional via only has obstacle vias, then the current power supply or ground via and all obstacle vias are subjected to odd-numbered loop detection. If an odd-numbered loop violation occurs, the corresponding candidate region is marked as a prohibited region.

[0055] If the functional via includes obstacle vias and pin access vias, then the current power supply or ground via, all obstacle vias, and all pin access vias are sequentially subjected to odd-numbered loop detection. If all combinations of pin access vias result in an odd-numbered loop violation, then the corresponding candidate area is marked as a prohibited area.

[0056] like Figure 2 As shown, each PG via is subjected to odd-number loop detection with other functional vias (such as obstacle vias and pin access vias). If there is no pin access via, the current PG via is subjected to odd-number loop detection with all obstacle vias (OBs vias) in the standard cell. The distance between the PG via and all OBS vias is checked to see if it is less than the minimum distance of the photolithography process. If a closed loop consisting of an odd number of vias is formed, a violation occurs, and the PG via area is marked as a forbidden box.

[0057] For example, if the current PG via forms a triangular loop with two OBS vias and the spacing is illegal, then placing a PG via at this location is prohibited.

[0058] If a pin access via exists, then perform odd-numbered loop detection on the current PG via, all obsvia in the standard cell, and each pin access via on the pin. If an odd-numbered loop is generated for each pin access via, it means that there is no selectable pin access via on that pin, and the PG via area is marked as a forbidden box.

[0059] For example, if the current PG via, an OBS via, and three different pin access vias form three odd-numbered rings, then placing a PG via in this area is prohibited, and this area is marked as a forbidden box.

[0060] If at least one pin access via does not form an odd number of rings, the area can still be used to place a PG via.

[0061] In conjunction with the above embodiments, after all standard units have been traversed, as follows: Figure 3 As shown, all prohibited areas are passed to the layout legalization stage to guide the placement of power or ground vias to avoid the prohibited areas, thereby preventing odd-ring violations that cannot be eliminated in the detailed routing stage after layout is completed.

[0062] During implementation, odd-numbered ring violations that may be caused by fixed PG vias are detected during the wiring phase. Violation areas are marked as forbidden boxes, and these forbidden boxes are fed back to the layout legalization phase.

[0063] Used to guide the placement of PG vias. That is, during the layout legitimization phase, prohibited areas are skipped, and other legal locations are selected to place the PG vias.

[0064] During the layout legitimization phase, when preparing to place PG vias, it checks whether the candidate location is within a previously marked prohibited area. If the candidate location is a prohibited area, it skips that location and selects another legal area to place the PG via. This solves the problem of odd-numbered ring violations from the source, thereby avoiding the problem of odd-numbered rings that cannot be repaired due to fixed PG vias during the detailed routing phase, and improving the quality of integrated circuit design and the success rate of manufacturing.

[0065] Based on the same inventive concept, this application also provides an integrated circuit layout and routing collaborative elimination device for odd-numbered loop violations, the integrated circuit layout and routing collaborative elimination device for odd-numbered loop violations comprising: a candidate region generation module and an odd-numbered loop violation detection module;

[0066] The candidate region generation module creates regions where power or grounding vias may be placed based on the physical structure of existing vias in the standard unit, thus obtaining candidate regions.

[0067] The odd-numbered loop violation detection module is used to perform odd-numbered loop violation detection on the candidate area and determine whether the pre-placed power supply or grounding through hole and the functional through hole form an odd-numbered loop violation.

[0068] If an odd number of cycles is formed, which is a violation, the corresponding candidate region will be marked as a prohibited region.

[0069] In some embodiments, the integrated circuit placement and routing collaborative elimination of odd-numbered loop violations device further includes:

[0070] Forbidden Zone Transfer Module;

[0071] The prohibited area transfer module is used to transfer all prohibited areas to the layout legalization stage after all standard cells have been traversed, so as to guide the placement of power or grounding vias.

[0072] In some embodiments, the odd-ring violation detection module also determines the type of functional via. If only obstacle vias exist, the current power supply or ground via and all obstacle vias are subjected to odd-ring detection. If an odd-ring violation occurs, the corresponding candidate area is marked as a prohibited area.

[0073] If both obstacle vias and pin access vias exist simultaneously, the current power or ground via, all obstacle vias, and all pin access vias will be sequentially subjected to odd-numbered loop detection. If all combinations of pin access vias result in an odd-numbered loop violation, the corresponding candidate area will be marked as a prohibited area.

[0074] Based on the same inventive concept, this application also provides an electronic device, comprising:

[0075] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: an integrated circuit placement and routing collaborative method for eliminating odd-numbered loop violations as described in any embodiment of this application, or an integrated circuit placement legalization stage placement method.

[0076] Based on the same inventive concept, this application also provides a computer storage medium storing computer-executable instructions, which, when executed by a processor, perform: the integrated circuit layout and routing collaborative elimination of odd-numbered loop violations method as described in any embodiment of this application, or the integrated circuit layout legalization stage placement method.

[0077] It should be noted that the computer storage medium may include, but is not limited to: portable disk, hard disk, random access memory, read-only memory, erasable programmable read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof.

[0078] In possible implementations, the present invention may also provide the data processing as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform several steps of the method described in any of the foregoing embodiments.

[0079] The program code for executing the present invention can be written in any combination of one or more programming languages. The program code can be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on a remote device.

[0080] This application creates a non-placeable region for PG vias for each standard cell based on the odd-ring rule. This avoids the generation of odd-ring violations during the placement phase and eliminates odd-ring violations that cannot be resolved during the routing phase, significantly improving the efficiency and quality of detecting and eliminating odd-ring violations during the detailed routing phase. Furthermore, this invention is also applicable to Triple-Patterning Technology (MPT).

[0081] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the descriptions of the embodiments described later are relatively simple, and relevant parts can be referred to the descriptions of the foregoing embodiments.

[0082] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for collaboratively eliminating odd-numbered loop violations in integrated circuit placement and routing, characterized in that, include: For each standard cell, perform the following traversal to determine prohibited areas where power or ground vias cannot be placed: Based on the physical structure of existing through holes in the standard cell, create areas for placing power supply or grounding through holes to obtain candidate areas; Odd-number loop violation detection is performed on the candidate area to determine whether the pre-placed power supply or grounding via and the functional via form an odd-number loop violation. If an odd number of loops are violated, the corresponding candidate area is marked as a prohibited area so that the prohibited area is skipped during the layout legalization stage when placing power or grounding vias. When performing odd-numbered loop violation detection on the candidate area, if the functional via only has obstacle vias, then the current power supply or ground via and all obstacle vias will be subjected to odd-numbered loop detection. If an odd-numbered loop violation occurs, the corresponding candidate area will be marked as a prohibited area. If the functional via includes obstacle vias and pin access vias, then the current power supply or ground via, all obstacle vias, and all pin access vias are sequentially subjected to odd-numbered loop detection. If all combinations of pin access vias result in an odd-numbered loop violation, then the corresponding candidate area is marked as a prohibited area.

2. The method for collaborative elimination of odd-numbered loop violations in integrated circuit placement and routing according to claim 1, characterized in that, The standard cell is generated by rotating or flipping the basic cells in the basic cell library; Perform the following operations on each basic unit in the aforementioned basic unit library: Based on the internal structure of each basic unit, the candidate areas for placing power supply or grounding vias are logically deduced, and the candidate areas are subjected to odd-numbered ring violation detection. Candidate areas that cannot be placed with power supply or grounding vias are marked as prohibited areas. By transforming coordinates, the marked forbidden regions in the base cell are adapted to all standard cells generated by rotation or flipping operations to ensure the correct inheritance of forbidden regions.

3. The method for collaborative elimination of odd-numbered loop violations in integrated circuit placement and routing according to claim 1, characterized in that, The method for collaboratively eliminating odd-numbered ring violations in integrated circuit placement and routing also includes: After all standard cells have been traversed, all prohibited areas are passed to the layout legalization stage to guide the placement of power or ground vias to avoid the prohibited areas.

4. A device for collaboratively eliminating odd-numbered loop violations in integrated circuit layout and wiring, characterized in that, The integrated circuit layout and routing collaborative elimination device for odd-numbered loop violations includes: a candidate region generation module and an odd-numbered loop violation detection module; The candidate region generation module creates a region for placing power supply or grounding vias based on the physical structure of existing vias in the standard unit, thus obtaining candidate regions. The odd-numbered loop violation detection module is used to perform odd-numbered loop violation detection on the candidate area and determine whether the pre-placed power supply or grounding through hole and the functional through hole form an odd-numbered loop violation. If an odd number of cycles are formed, which is a violation, the corresponding candidate region will be marked as a prohibited region. The odd-numbered ring violation detection module also includes determining the type of functional through-hole. If only obstacle through-holes exist, the current power supply or grounding through-hole and all obstacle through-holes will be subjected to odd-numbered ring detection. If an odd-numbered ring violation occurs, the corresponding candidate area will be marked as a prohibited area. If both obstacle vias and pin access vias exist simultaneously, the current power or ground via, all obstacle vias, and all pin access vias will be sequentially subjected to odd-numbered loop detection. If all combinations of pin access vias result in an odd-numbered loop violation, the corresponding candidate area will be marked as a prohibited area.

5. The integrated circuit layout and wiring collaborative elimination of odd-numbered loop violations according to claim 4, characterized in that, The integrated circuit layout and wiring collaborative elimination of odd-numbered ring violations device also includes: a prohibited area transmission module; The prohibited area passing module is used to pass all prohibited areas to the layout legalization stage after all standard cells have been traversed, so as to guide the placement of power or grounding vias to avoid the prohibited areas.

6. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform: the integrated circuit layout and routing collaborative elimination of odd-numbered ring violations method as described in any one of claims 1-3.

7. A computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which, when executed by a processor, perform: the method for collaborative elimination of odd-numbered loop violations in integrated circuit layout and routing as described in any one of claims 1-3.

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