Access error correction for content addressable memory

Abstract

The present disclosure provides access error correction for content addressable memory. Examples of the present disclosure provide a method for detecting and correcting errors in a summation content addressable memory (Σ-CAM) (i.e., "access" error correction) when the Σ-CAM performs a computational task. The method involves adding redundant columns to the Σ-CAM that is used to store a task-driven matrix (i.e., a matrix having values that are consistent with the computational task). Examples can utilize an encoder to compute redundant values for the redundant columns such that the Σ-CAM stores codewords of a linear code (C) in each row. Examples also modify the linear code (C) that is used to compute the redundant values. That is, examples modify the linear code (C) such that it includes an all-ones vector. With this modification, systems of the present disclosure can detect and correct errors in an output vector from the Σ-CAM based on this modified / specialized linear code (C).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 609,652, filed December 13, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally involves data computation tasks. Background Technology

[0004] Content-addressable memory (“CAM”) is a computational memory in which data is searched by content rather than location. When a “word” is input into a CAM, the CAM searches for that word in its content. If the CAM finds the word (i.e., “returns a match”), then the CAM returns the address of the location where the found word was located. The individual cells of a CAM (referred to herein as CAM cells) can be arranged into rows and columns to form a CAM. Depending on the configuration, the corresponding CAM rows or columns connecting the outputs that make up the CAM cells can be called match lines.

[0005] Summation CAM (Σ-CAM) (sometimes called Hamming-distance CAM) is a special type of CAM configured to sum the outputs from CAM cells arranged along their respective columns. In other words, Σ-CAM can refer to... A CAM is composed of CAM cell arrays, where some internal state values Each CAM unit Implement function The internal state of Σ-CAM programming can be represented as an array (matrix). ,in Representative as well as Representative column The input to Σ-CAM can include row vectors (e.g., search keys). ,in As a tribute to the journey The inputs to all CAM units. The corresponding columns of Σ-CAM (corresponding to the matching lines). It can calculate along the corresponding column (Right now The integer sum of the outputs of the Σ-CAM cells arranged in a Σ-CAM array. These integer sums form the output row vector of the Σ-CAM, i.e. Therefore, Σ-CAM calculates the input vector and the vector along the Σ-CAM. Hamming distance between the contents of CAM cells in each column of the column. Summary of the Invention

[0006] In one aspect, this disclosure provides a computing system comprising: a summation content-addressable memory (CAM) including CAM cells arranged in a number of l rows and n columns, wherein the summation CAM is configured to sum the outputs from a number of l CAM cells connected along corresponding columns of the n columns; and one or more processing resources operable to program the CAM cells to store a matrix A having a dimension of l x n, wherein each row of the matrix A includes a codeword of a linear code C, and the linear code C includes an all-one vector of dimension n as the codeword.

[0007] In one aspect, this disclosure provides a computing system comprising: one or more processing resources operable to: program a summation content-addressable memory (CAM) to store a matrix A having dimension l x n, wherein: each row of the matrix A includes a codeword of a linear code C, and the linear code C includes an all-one vector of dimension n as the codeword; and detect and correct one or more errors in an output vector c from the summation CAM based on the linear code C.

[0008] In one aspect, this disclosure provides a method for a content-addressable memory (CAM), comprising: programming the CAM to store a matrix A having dimension l x n, wherein: each row of the matrix A includes a codeword of a linear code C, and the linear code C includes an all-one vector of dimension n as the codeword; and detecting and correcting one or more errors in an output vector c from the CAM based on the linear code C. Attached Figure Description

[0009] This disclosure is described in detail with reference to the following figures, based on one or more various examples. The figures are provided for illustrative purposes only and depict only examples.

[0010] Figure 1 An example truth table is described according to the technical examples of this disclosure.

[0011] Figure 2 An encoding mapping algorithm based on the technical examples of this disclosure is described.

[0012] Figure 3 A table of example values ​​is described according to the technical examples of this disclosure.

[0013] Figure 4 A table of example values ​​is described according to the technical examples of this disclosure.

[0014] Figure 5 A table of example values ​​is described according to the technical examples of this disclosure.

[0015] Figure 6 An example CAM unit according to the technical examples of this disclosure is described.

[0016] Figure 7 An example CAM-based circuit according to the technical examples of this disclosure is described.

[0017] Figure 8 An example diagram illustrating an example of the technology according to this disclosure is provided, showing a comparison between a threshold voltage and the voltage output of a matching line associated with a column of a CAM cell in a summing CAM.

[0018] Figure 9 A block diagram of an example computer system in which the various examples described herein can be implemented is described.

[0019] The accompanying drawings are not exhaustive and do not limit this disclosure to the precise form disclosed. Detailed Implementation

[0020] Examples of the techniques disclosed herein provide a method for detecting and correcting errors in Σ-CAM (i.e., "on-access" error correction) when Σ-CAM performs computational tasks.

[0021] This disclosed "access" error correction method improves upon "offline" error detection / correction methods. Such "offline" error detection / correction methods typically involve detection procedures that interfere with the normal operation of a hardware accelerator during computational tasks, and therefore must be executed "offline." For example, another method for detecting errors in a CAM might involve applying a sequence of test vectors to the CAM to detect programming errors and other circuit-based errors. The application of test vectors may be unrelated to the computational task the CAM is performing, otherwise it would interfere with the computational task. Therefore, this method would be executed "offline." In contrast, the error detection and correction method of this disclosure involves correcting the output vectors generated by the Σ-CAM while the Σ-CAM performs a specified computational task. Therefore, this method is computationally more efficient (i.e., consumes less processing resources, time, and power) compared to other "offline" error detection and correction methods.

[0022] The example leverages the insight that Σ-CAM operates similarly to a vector-matrix multiplier (sometimes referred to as a dot product engine) to achieve the advantages provided by "access" error detection and correction. Utilizing this insight, the example uniquely applies error correction methods used for vector-matrix multipliers to Σ-CAM. The applied method involves adding redundant columns to the Σ-CAM, which is already used to store the task-driven matrix (i.e., a matrix with values ​​consistent with the computation task). The example can utilize one or more processing resources (e.g., an encoder) to compute redundant values ​​for the redundant columns so that the Σ-CAM stores codewords of linear code (C) in each row. To further adapt this method for new / specific types of hardware accelerators (i.e., Σ-CAM), the example modifies the linear code (C) used to compute the redundant values. That is, the example modifies the linear code (C) to include all-one vectors. With this modification, the system of this disclosure can detect and correct errors in the output vector from the Σ-CAM based on this modified / specific linear code (C).

[0023] For example, a system of the present disclosure may include: a) a Σ-CAM comprising CAM units arranged in a number (l) rows and a number (n) columns, wherein the Σ-CAM is configured to sum the outputs from the number (l) CAM units connected along the corresponding columns in the number (n) columns; and b) one or more processing resources for programming the CAM units to store a matrix (A) having a dimension (l x n), wherein: i) each row of the matrix (A) comprises a codeword of a linear code (C), and ii) the linear code (C) comprises an all-one vector of dimension (n) as a codeword.

[0024] In the above system, the CAM units connected along a number (k) of a number (n) column may include task-driven CAM units. Correspondingly, the CAM units connected along a number (nk) of a number (n) column may include redundant CAM units. Therefore, a corresponding row of the Σ-CAM includes a number (k) of task-driven CAM units and a number (nk) of redundant CAM units. Thus, programming the Σ-CAM to store a matrix (A) of dimension (lxn) may include: a) programming the number (k) of task-driven CAM units in the corresponding row to store task-driven values ​​corresponding to the computation task; b) calculating the redundancy values ​​of the number (nk) of redundant CAM units in the corresponding row based on the programmed task-driven values ​​and the linear code (C); and c) programming the number (nk) of redundant CAM units in the corresponding row to store the calculated redundancy values ​​such that the corresponding row stores the codeword of the linear code (C). In some implementations, calculating the redundancy values ​​of the number (nk) redundant CAM units in a given row may include calculating the redundancy values ​​of the number (nk) redundant CAM units in a given row such that the task-driven value and the redundancy value comprise a sequence of one and zero as defined by the linear code (C).

[0025] In the above system, one or more processing resources may be further used to detect and correct one or more errors in the output vector (c) from the Σ-CAM based on linear codes (C). In some implementations, the output vector (c) may have a dimension (n). Accordingly, the output vector (c) may include a concatenation of a task-driven output vector (c') and a redundant output vector (c''). Here, the task-driven output vector (c') may have a dimension (k) and correspond to the sum of the following: (1) a vector-matrix product between the transformation of the input vector (x) of dimension (l) received by the Σ-CAM and the task-driven storage matrix (A') of dimension (lxk) stored by the task-driven CAM unit of the Σ-CAM; and (2) a vector product between an all-one vector of dimension (n) and a constant value (e.g., see Equation 4 below). Relatedly, the redundant output vector (c'') may have a dimension (nk) and correspond to the sum of the following two items: (1) the vector-matrix product between the transformation of the input vector (x) and the redundant storage matrix (A'') of dimension (lx (nk)) stored by the redundant CAM cells of Σ-CAM; and (2) the vector product between an all-one vector of dimension (n) and a constant value (e.g., see Equation 4 below). Furthermore, one or more processing resources may detect and correct one or more errors in the task-driven output vector (c') based on (e.g., by comparison) the linear code (C) and the redundant output vector (c'').

[0026] In some embodiments of the above system, the corresponding CAM unit of Σ-CAM may include one or more programmable memristors. Here, programming the corresponding CAM unit may include programming the conductance of one or more programmable memristors.

[0027] Examples of the techniques disclosed herein will be described in more detail below. It should be understood that the following description is for illustrative purposes only and should not be construed as limiting the principles disclosed herein.

[0028] This article presents several methods for handling errors. -CAM access correction coding schemes. These schemes can be applied to binary... -CAM (sometimes referred to in this article) -BCAM) and ternary -CAM (sometimes referred to in this article) -TCAM). All schemes require redundancy allocation. -CAM rows, so that when the input vector is applied With -CAM, errors in the output vector can be corrected, provided that their quantity (measured by Hamming metric or ...) is not exceeded. - (Measured by measurement) does not exceed the specified value. In the case of -BCAM -BCAM operates similarly to a discrete vector matrix (VM) multiplier. Therefore, it is used for The error correction scheme of this disclosure for BCAM is based on schemes already proposed for such multipliers. Due to the presence of wildcards (sometimes called "ignorant" symbols), such schemes are applicable to... -TCAM may be more complex. Therefore, it is used for The scheme of this disclosure of TCAM uses a special type of positional binary representation of integer pairs, wherein the representations of the two integers in any pair do not share 1 at the same position.

[0029] Examples of the techniques disclosed herein will be described in more detail below with reference to sections I through VIII.

[0030] Part I: Introduction to Symbols From this application onward, the following symbols will be used. For This application uses Represents a subset of integers Represents a set This application will use shorthand symbols. to indicate And use For integer vectors This application uses respectively and To represent its Hamming weights and -norm. For matrix Or if ,OK -vectors) and subsets This application order express of A submatrix, which is formed by columns indexed by X. For such that of ,symbol Divide by The remainder. Modulo. express.

[0031] make The XOR function is used to test inequalities for each... It is defined by the following formula: Equation 1 in The brackets represent Iverson (which evaluates to 1 if its argument is true, otherwise 0). As mentioned above, -CAM can refer to A device composed of CAM unit arrays, wherein some internal state values Each CAM unit Implement function This application represents the internal state as an array (matrix). ,in Indicates line Represents column .right -CAM inputs can include row vectors (e.g., "search key"). ,in As a tribute to the journey The input of all CAM units. - Each column in CAM (corresponding to a matching line) Calculate the integer sum of the outputs of the CAM cells along this column. Equation 2 These integers and formations -CAM's output row vector .therefore, -CAM calculates the input vector and along -CAM Hamming distance between the contents of CAM cells in each column of the column.

[0032] From this point forward, the symbols used in this application will be... to indicate The vector, whose terms are given by the right side of Equation 2. That is, when the input vector... Applied to matrices that are programmed as internal states -CAM It is the result of the calculation. . The zero terms in the matrix are called "matches", and ordinary binary CAM (BCAM) can be viewed as quantized. -CAM, its output is binary. -vector (It points to the column where the match occurs).

[0033] -CAM is a proposed model for accelerators used to calculate Hamming distances in various applications, and there are various designs for its CAM cells (using CMOS as well as resistor technology) and the circuitry for calculating Hamming distances along each column. In these designs, the CAM cells are typically... To achieve the value, set some high conductivity. .when At this time, the CAM cells are effectively open (i.e., have zero conductance). One method for obtaining the Hamming distance is to fix the voltage level of the matching line and measure the current flowing through each column of the CAM. This current is typically proportional to the number of high-conductance CAM cells along the column. In various applications of interest, the matrix... The frequency of modification is much lower than that of the input vector. .

[0034] Inaccuracies in programming CAM units, manufacturing defects, and noise during output vector reading can all lead to errors in the actual row vector reading. Unlike the correct vector Example factors. An error vector can be defined as... The following vectors in:

[0035] The faulty CAM unit generated an erroneous output, and that output remains... In the case of [the CAM unit], the output at the column containing that CAM unit will be [the output]. 1. Changes. This application refers to such events as - Error. Then, - norm Bounded below - The number of errors, where the equation is satisfied if all faulty CAM cells along the same column occur in the same direction. A key point of this application is this situation, where one of the design parameters of this disclosure would be tolerable. The largest -norm , its (without considering the matrix) (When the internal state is in the middle) can be used as the maximum tolerable number. Or a proxy for a faulty CAM unit. However, this application will also consider the case where a faulty CAM unit may have a significant impact on the column output, in which case... This indicates that it is tolerable. The maximum Hamming weight. Thereafter, depending on the context, "error count" in this application may refer to... or .

[0036] One purpose of this disclosure is to provide Access error correction in CAM provides an encoding scheme (and its variants will be given below). To this end, this disclosure applies a framework for integer vector matrix (VM) multipliers. -CAM, this is because there is a close relationship between the functions of these two devices. Specifically, it can be seen from Equation 2. Equation 3 in On behalf of the entire bank - Vector. Next is... Equation 4 in, .

[0037] In other words, up to the addition multiples of all-unique vectors, -CAM execution Vector multiplication in Matrix multiplication in the context of mathematics.

[0038] With this in mind, the example programming matrix of this disclosure technique So that The front of the middle The item will carry -CAM target calculation, while The rest The items will contain redundant symbols, which can be used to detect or correct computational errors. Therefore, the programming... matrix Will have structure Equation 5 in and Input vector The output row vector of the calculation will be ,in It is a target calculation. It is a redundant part.

[0039] Given a positive integer ,and , -CAM encoding scheme is a pair ,in It is an encoding mapping that makes for each ,picture For some It has the form of equation 5, and “e” It is a decoding map (where "e" indicates decoding failure).

[0040] gather

[0041] It is by A induced code and its members are called codewords. That is, And his coding is when All possible Within the matrix and exist All possible This application will include all possible output vectors obtainable within the range of the input vector. and These represent the length and dimension of the encoding scheme, respectively. For the row vector resulting from the combined encoding scheme... This application uses the symbols respectively. and to indicate its - prefix and -suffix This notation standard has also been extended to matrix.

[0042] Given and the specified number of errors (Depend on -Measured using a metric or Hamming metric), the goal is to have the minimum possible... Encoding scheme So that for each and , The corresponding codeword of - prefix In appearance It can recover correctly even with one or fewer errors. That is, for each read vector... The following equation holds true such that :

[0043] (Alternatively, It can be given. (This will be maximized). Note that decoding mapping may not be necessary. To restore redundant parts . More generally, given a non-negative integer and If for each computed output vector and the corresponding read vector If the following conditions are maintained, then the encoding scheme It is considered correctable Errors and detection One error (in) -in measurement or Hamming measurement).

[0044] if ,but .

[0045] Otherwise, if ,but ,“e” .

[0046] The minimum distance (represented as) ) is defined as The ones with different - The minimum value between any two codewords of the prefix Hamming distance:

[0047] The results below provide more details.

[0048] Proposal 1. Order For encoding mapping and let and If the integer is non-negative, then the following condition is met:

[0049] Therefore, there exists a decoding mapping. “e” This makes the encoding scheme It can be corrected Errors and detection One error.

[0050] Unless otherwise stated, It will be separable, meaning for each row index. , line The content will only be line (instead of) The function (in other rows) for all It will be the same, and will not depend on In the case of a separable encoder, this application assumes The domain and range are respectively and .

[0051] For (separable) The set of all images. This can be derived from Equation 3 (or Equation 4).

[0052] Especially for each , , and when When it is even Therefore, the example uses an encoding scheme. ,in For inclusion of Environment module on subset of For inclusion of The above has an environment module of (a subset of the intersection points), and also satisfies Thus making For the sake of simplicity, this application generally assumes the following: .

[0053] For the matrix in In special cases like this, such an encoding scheme can be obtained by modifying the construction of the vector matrix multiplier. Those modifications might involve length... The above requires some mild conditions, but without causing loss in redundancy. This application will begin by describing a scheme in Part II, which is derived from a modification of the Hamming metric construction of a vector-matrix multiplier. As a general construction, this construction is perhaps the simplest, and it conforms to… - Both metric and Hamming metric. When with compared to When small enough, for Other (however more complex) constructions exist for the metric. These constructions are discussed in Parts VI and VII of this application.

[0054] In Part III (and subsequent parts), this application will consider a cell based on ternary content-addressable memory (TCAM). —A variant of CAM. TCAM is an extension of ordinary binary CAM, in which the internal state values ​​of CAM cells and the inputs of CAM cells are allowed to use a third "wildcard" notation. (Sometimes referred to as "don't care" or "always match" symbols). Therefore, the input and status letters of the CAM unit are... And each CAM unit implements Figure 1 The functions defined in truth table 100 (The restrictions on the last two rows and two columns of truth table 100 are the same as those on the function in Equation 1) Consistent).

[0055] Symbol wildcards The introduction of this method has a significant impact on the encoding scheme of this disclosure. In particular, the example utilizes a special type of positional binary representation of integer pairs, where the representations of the two integers in any pair do not share a 1 at the same position. This representation, referred to as a bi-spanner in this application, may be a separate interest, and its properties will be shown in Part IV. Compared to -CAM, the present disclosure is used for The construction of TCAM increases redundancy by approximately 60%.

[0056] This application will conclude with the discussion in Part VIII.

[0057] II. Construction based on Hamming-metric code This application demonstrates a (separable) construction of a vector-matrix multiplier, with features for... - CAM modifications. For the purposes of this construction, the set of permissible error modes is characterized by two parameters: including the faulty CAM unit. The largest number in Columns, and each column's - Maximum number of errors ("internal errors") .Right now, and Using error vectors respectively Hamming weights and - The norm is an upper bound. Therefore Corresponding to the maximum number of occurrences - Error, and at most one such error occurs per column. (Take...) Will include - The maximum number of errors is In this situation, finally, take... This corresponds to the Hamming metric, where the maximum The columns may be incorrect, without further assuming that each column is correct. - The number of errors.

[0058] Given number of columns Upper bound on the number of error columns and each column - Upper bound on the number of errors ,make Let be an odd prime number and let Example selected in The corresponding Hamming metric linearity on - Error Correction Code C is assumed to satisfy the following three conditions.

[0059] a) It contains characters with all-one-code.

[0060] b) It is systematic, that is, there is a one-to-one mapping. : This makes it possible for each ,picture have As its - prefix.

[0061] c) It has a highly efficient bounded-distance decoder For the received words The decoder returns the true error vector. The condition is .

[0062] parameter and The relationship is

[0063] This application will then proceed through its description in the given line. The actions described above define the (separable) encoder of the proposed coding scheme. .Will As The vector in the code is first expanded into C codewords by the C system encoder. Equation 6 in Now, in the next step of constructing the vector matrix multiplier, for each Redundant symbols It can be extended to its 2-based representation. ,Right now, Equation 7 in

[0064] Here, instead of Equation 7, the example will represent Set as The vector in the vector makes Equation 8 in By changing its last item to from Obtained. Due to Therefore, the multiplier in equation 8 It is a reversible module .because Therefore, the extension in Equation 8 is indeed always possible (sometimes with two different representations). -vector In addition, for Examples can be taken (Even if another representation is possible, it will be chosen).

[0065] Finally, similar to vector-matrix multipliers, in Below The image is defined as:

[0066] in

[0067] Figure 2 The encoding mapping algorithm 200 is summarized. The encoding process of a typical row in CAM. It can be seen that... And in On The linear span is in The module on To understand the properties of this module, define... To make each vector

[0068] in Mapped to the image below :

[0069] (Among them MODs) The operation is applied on a per-component basis. It is homomorphic and it will Mapped to C. Conversely, this means that examples can (efficiently) map any... Decoding into the correct codeword in C, under the condition that... The number of error symbols in (and therefore in) (in China) not exceeding Furthermore, if In each item - The number of errors does not exceed Then from the inequality The example can correct all of these errors.

[0070] Specifically, C is... The case of the normalized extended primitive BCH code above, which satisfies conditions a)-(c) above, and also some of its abbreviations. The upper bound of redundancy obtained in the example is limited by the following formula.

[0071] Among them when The equation remains unchanged (this is a scheme worth noting). Because... Therefore, redundancy manifests as Equation 9 (in The constant multiplier in the term and (Proportional)

[0072] Example 1. For In this case, each column can tolerate at most one - Error, example taken Accordingly

[0073] In particular, for Example obtained , and when You can get twice as much (i.e.) However, for By using Replacing the BCH code with a preparata code would achieve a better result. The resulting redundancy is only... The example can also be constructed using the redundancy of Part VI, having two... - The added benefit is that errors can also occur in the same column of the array.

[0074] Example 2. For In this case, an example can be taken. In this case, the example becomes redundant and The following is an approximation of the ratio between them:

[0075] However, due to Equation 9 The rounding in the item, if the example selects Therefore, the example will have less redundancy:

[0076] For large In Equation 9 The term actually becomes 1, and the redundant expression becomes approximately... .

[0077] Let's review, in Normalized extended primitive (BCH code C) (for some) It has length This includes all-one codewords, therefore it satisfies condition a). This condition also applies to any codeword obtained by shortening the C on the 0 terms of any non-zero codeword of C (possibly after rescaling the coordinates). For example, for Any appropriate divisor Code C contains individual code characters Each Hamming weight is Their support overlaps only at the coordinates corresponding to code locator 0. Furthermore, all other non-zero terms are 1. Therefore, for any C code Hamming weights are (if Divide by )or (Otherwise). That is, while satisfying condition a), the example can achieve all these code lengths by shortening C. For the actual range of parameters, The example has enough divisors (in particular, it can always be divided by 2 and 1). Divisible). For example, when At that time, the example can be taken In this case, for The values ​​are respectively and Or when At that time, the example can be taken ,in this case .

[0078] III. Extension to Σ-TCAM This section describes the access error correction problem in Σ-TCAM, specifically based on TCAM cells (i.e., a specific type of CAM cell). -CAM. If the input vector item It is a wildcard symbol So, along the Σ-TCAM The TCAM unit will produce an all-zero vector, thus having no effect on the output vector. Therefore, in the following discussion, we can assume that the input vector... middle.

[0079] for This application uses symbols to represent Indicates in -TCAM's internal state vector (in .for This application order express The vector in the input symbol is Its item is along the way The output of the TCAM unit. Therefore, And for and any :

[0080] in short, Equation 10 Then, equation 3 becomes Equation 11 It should be noted that, due to For - cells (i.e., CAM cells programmed to store wildcards), the following relationship no longer holds: .

[0081] Equation 11 shows -TCAM execution Vector multiplication in The following matrix multiplication operations: Equation 12 in and yes Matrix, whose rows are and However, it's important to note that vectors... and They must be disjoint, that is, they cannot have 1 at the same position. Now, if the example is a separable encoder... Applicable to (non-intersecting) Then the examples can finally be obtained in their redundant parts. and Intersecting rows as well as

[0082] Therefore, if the TCAM unit is The array is considered as in Equation 12 Matrix, then used for The encoding scheme for TCAM may itself be inseparable. However, the dependencies between rows in the matrix may be limited to the same row corresponding to the TCAM cells in the physical array. The row pairs, i.e. and On the other hand, unlike the settings in Part II, due to the relationship This requirement is no longer valid, therefore the example can remove the requirement that the all-one vector is a codeword in the inducing code (which is the context module containing the inducing code). This requirement (of the code words in the text).

[0083] Therefore, the construction of vector-matrix multipliers is applicable to -TCAM may differ from that described in Part II. Specifically, the example makes C, D, and E the same as defined in Part II, except... The choice will be made differently below, and the example may no longer require condition a) (which requires C to include all-one codewords). Given two representations -TCAM along the given row The vector of outputs of each unit (As in Equation 10), an example can be given by applying the C system encoder to both vectors as in Equation 6. as well as

[0084] To generate the codeword of C and However, the extension of equation 7 will become... Equation 13 in and exist The two are non-intersecting. It is the selected A fixed integer vector in the form of such that for any pair All of them can satisfy equation 13. A simple choice for such vectors is...

[0085] Here, In addition, examples can be selected. (correspondingly, ), so that its front (correspondingly, its back) All terms are zero. However, as mentioned above, the redundancy of the scheme is... This means that, with the second part Compared to -CAM, This simple choice can double the redundancy. One goal is to do better than this simple solution; for this purpose, the example introduces the following definitions.

[0086] make Abelian group, and ordered A subset of. In On The bi-spanner is Multiple sets of elements This makes it possible for each pair They all exist in a state of non-intersection. subset of and , making as well as Equation 14 Equivalent land, will Writing Vectors There exist two disjoint vectors. , making as well as Equation 15 The representation in Equation 13 corresponds to the case where, ,in It is a prime number (But values ​​will be considered in later examples) (Not necessarily a prime number). For ,make Let be the largest integer such that for any Having in The size of the top is The bi-spanner. Figure 3 The rightmost column in Table 300 lists The values ​​were found through an exhaustive computer search. For a given... Example Selection In order to make The minimum value, thus allowing for any All examples satisfy Equation 13. For those covered by Table 300... Range of values This can be seen This will be less than the value in the simple selection / solution above. Furthermore, as shown in the next section, this generally holds true. The example will also use a bi-spanner, which will be discussed later in other structures.

[0087] Example 3. Referring to the parameters in Example 1, for Examples can be taken (While a simpler construction would require taking) ).vector Is The bi-spanner. Figure 4 Table 400 shows The values ​​of the elements (as in Equation 15) and the contents of the TCAM cell. (Due to symmetry, only the following need to be listed) The opposite The rest of the pairs are... and Switch between them, and in ). and Example 1 (example taken) middle Compared to -CAM construction, -TCAM construction increases redundancy times.

[0088] Example 4. Referring to the parameters in Example 2, if the example selects... So, because Therefore, the example can be taken (instead of taking as in Example 3) In this case, with Compared to -CAM, -TCAM redundancy only increased :

[0089] vector The bi-spanner, and Figure 5 Table 500 shows the corresponding contents of the TCAM unit.

[0090] Interestingly, in Example 2, by selecting... The savings achieved in the example did not propagate to -TCAM: For Example now take The result is with -CAM has increased redundancy compared to other systems. :

[0091] IV. Properties of Bi-Spanner In this section, this application will present the sequences defined in Part III. Some properties of the sequence. In particular, the application shows that the sequence... It converges to a limit greater than 0.622. Therefore, for a given... The strategy is to choose the minimum, so that... produce The redundancy of TCAM is (asymptotically) smaller than that of the corresponding... -CAM redundancy (While the simple method mentioned above would double the redundancy).

[0092] for For some positive integers

[0093]

[0094] In this case, the construction of a bi-spanner may have an additional requirement, namely... The terms are all positive and For any make And for disjoint subsets make Under the conditions The following example shows how equation 14 can be rewritten as: Equation 16 because It can be as small as Furthermore, due to the assumption Since all values ​​are positive, the example can be derived from Equation 16 for each Especially Equation 17 Conversely, with Start and satisfy having for all Equation 17 for the equality of infinite sequences Generate a sequence of integers Equation 19 Each is the largest For the largest , Having Size is full-positive bi-spanner From the examples in Equation 17 (when expressed in terms of equality) and Equation 18, we can obtain...

[0095] And through the Summarize and That is, the growth rate of these sequences is

[0096] Figure 3 Table 300 shows The first few values.

[0097] Now, for any positive integer , And in On Any bi-spanner (when taking the modulus) At that time, according to Component modulo is also The bi-spanner. Therefore. In fact, if It can also have negative terms, even though the example still requires... The sum of the terms in the equation equals The example could also be done better. Using... To represent the largest integer For the largest integer , bi-spanner Make The example has And for sufficiently large The inequality is strict. (See Proposal 2 and Equation 22 below; for...) The example already has .

[0098] Examples can be taken a step further and examined in set on The bi-spanner. Represents the largest integer For the largest integer , Having in The size of the top is bi-spanner, sequence and

[0099] Equation 19 Related.

[0100] In fact, On Any bi-spanner is also The bi-spanner. Furthermore, any bi-spanner of the latter is also... A bi-spanner, and its sum can be made zero by adding at most one element.

[0101] sequence It is non-decreasing and it is super-multiplicative, that is... Equation 20 For any :if and They are in On and The bi-spanner, then and Equation 21 yes The bi-spanner. Therefore, according to Fekete's lemma example, we have:

[0102] The limit in the last equation (which is) and The growth rates of both will subsequently be determined by To represent. Found through computer search. The lower bound of the first few values exist Figure 3 As shown in Table 300. Specifically, the example is obtained. Equation 22 here, Strictly greater than The growth rate. In the next proposition, the application shows... Too The growth rate.

[0103] Proposal 2.

[0104] prove When taking the modulus On Any bi-spanner for On The bi-spanner. Therefore. ,and Equation 23 Conversely, given ,make And assume yes The size of the top is A bi-spanner. Examples can be found... As An integer vector in the array. Let... On The smallest bi-spanner and let This indicates its size. It's important to note that... (It possesses the same equality as when simply constructing a bi-spanner). Therefore Equation 24 yes On The bi-spanner. In fact, given any ,exist Make

[0105] This means that there exists

[0106]

[0107] because yes The bi-spanner exists Make

[0108] The last two equations mean that in equation 24 yes The size of the top is of The bi-spanner. Therefore. ,so Equation 25 The results are derived from equations 23 and 25.

[0109] Therefore, the example leads to the following conclusion.

[0110] The final inequality is derived from a simple counting proof. Specifically:

[0111] V. -CAM and -Single in TCAM - Error Correction This section describes The case where there is at most one in the entire array (where there is at most one) - Error). This situation corresponds to the parameter in Part II. .in -CAM's construction produces approximately Redundancy (see Example 1), and in Part II on The application of TCAM has led to increased redundancy. Reach approximately (See Example 3).

[0112] This section showcases... 1)] redundancy - The construction of CAM. The corresponding construction of -TCAM will have minimal redundancy. , making Especially for sufficiently large The redundancy may be less than (See Proposal 2 and Equation 22).

[0113] Given code length ,make This will be a redundancy in the construction, making ,make

[0114] The vector of the code locator in (where It meets the following conditions.

[0115] i) The item is The non-zero elements in.

[0116] ii) For any two distinct indexes (unless both are present) middle):

[0117] iii) .

[0118] Can be for each Construct such a vector .

[0119] one- - Error correction encoder Will Mapped to , making Equation 26 (Right now (This is the 2-based representation of the left side of equation 26). Therefore, by The code is The following modules are subsets of the above:

[0120] Therefore, under conditions i)-iii), it is always possible to correct the preceding events in any vector within that module. Any one of the coordinates The change of 1.

[0121] To make this scheme applicable -CAM, which only requires This application shows that when The time is not a power of 2 (i.e. When this is the case, it can always be achieved by appropriately selecting the code locator.

[0122] The example first uses a code locator, making The items form a set

[0123] (It should be noted that,) According to condition (ii), its requirement will be from (Excluded from the middle). Assumptions The terms are increasing. Unless when In this situation .use To represent the first vertex (modulus) of the code locator ): Equation 27 if The example ends (but this rarely happens). By negation... It can be obtained , making

[0124] In this case, there exists index pairs , making and exist China is different and MOD .when and When both are negated, the first vertex You can then make the mold The value is 0. For each n > 9, - An item can be positive.

[0125] Take the above structure For odd numbers, an extra parity bit is added; the example can also detect two. - Error (corresponding to) ), and the extended module will contain vectors .

[0126] TCAM's modification to the construction of the vector-matrix multiplier is mentally similar to what was done in the example in Part II. That is, the example changes condition iii) to: iii) ,in yes The bi-spanner.

[0127] Therefore, the choice should be made. , making To ensure the quality of such bi-spanners. To detect two... - Error, the example uses two extra bits to record the two possible values ​​of the parity bit.

[0128] Example 5. Suppose we want to have of -CAM seeks single - Error correction coding scheme. Example with optional redundancy. To be the smallest, so that

[0129] The result is .

[0130] for -TCAM, examples can be selected To be the smallest, so that

[0131] Figure 3 Table 300 stops at The smaller value, but the example can be used The general recursion (which is equation 17 in which there are equality relations) is used to obtain a feasible solution. and Explicit expressions. Specifically, for The examples are obtained respectively. Accordingly, examples can be taken. This is because

[0132] Alternatively, the example can use supermultiplication from equations 20 and 21. This can be seen from Table 300.

[0133] This means that examples can be taken. .

[0134] VI. Double - Error Correction This section describes The case where there are at most two in the entire array (i.e., at most two) - Error), which contains the construction of Part II The situation is as noted in Example 1. - The construction of CAM has approximately The redundancy, while the construction in this section has Redundancy.

[0135] Let be a prime number and define ,as well as (Separable) coding schemes have dimension. ,length and the resulting redundancy For this construction, an example can be made using a vector of code locators that satisfies conditions i)-iii) in Part V. This application defines Encoding Mapping vector Mapping to vector This makes the following four conditions true.

[0136] Formula 28 Formula 29 Formula 30 Formula 31 By using the encoder in Equation 26 Applied to Equation 29 can be achieved (using Replace one of them n Equation 30 means form MOD The representation based on 2. Equation 31 means The last item in is Parity check bit. yes The module on A subset of all vectors satisfying conditions 29-31 (in the formula) Instead It is composed of ) . It is worth noting here that That is, it can correct what happens. any vector in the front At most two of any patterns within a coordinate system (possibly in the same coordinate system). The change in 1. As described in Part V, by ensuring belong The example applies the encoding scheme of the vector-matrix multiplier to... -CAM. As stated in Part V, it can be assumed that... That's right, it exists. Index pairs , making and exist China is different and MOD ,in It is the first moment of the code locator defined in Equation 27. Using...

[0137] The third moment of the code locator can be a non-zero modulus. (And the zero first moment). The method for obtaining such code locators is described below.

[0138] Assumption and The above Two in the index pair, of which

[0139] Examples may not be available.

[0140] Conversely, this could mean for at least one pair in a pair, such as Once the example is negated and The value will become zero (modulo). ),and It may be nonzero. In fact, otherwise there would exist with... -norm 2 Two different vectors in the module, these two vectors will The same set of co-sets: one in position One has 1 (otherwise it is 0), and the other has 1 at position. It has a value of 1. However, this would mean This is a contradiction.

[0141] Now assume The example modifies equation 30 in two ways. First, the example uses vectors. To replace vector , where vector It is by... The last item was changed to (As shown in Equation 8) and obtained. Next, the example multiplies the right side of Equation 30 by the following (non-zero) defined constant.

[0142] because ,therefore Not divided by Therefore, equation 30 becomes

[0143] (Compare with Equation 8). It can be proven that the obtained module Still has 2- - Error correction and Equations 29 and 32 are satisfied. Furthermore, when... It also satisfies equation 31 when the number is odd. .

[0144] when When the number is even, the example can be further modified to have an extra redundant bit (i.e., set...). And replace equation 31 with, for example,

[0145] ).

[0146] exist In the case of -TCAM, the currently disclosed modifications to the scheme for the vector-matrix multiplier are similar to those described in Parts III and V. Specifically, the example selection... To be the minimum value, such that Example setting The example also takes , making for On bi-spanner (See condition (iii) in Part V). Equations 28-31 now become, for each :

[0147] in and They are disjoint (note in particular that two bits are assigned to the parity check in the last equation).

[0148] VII. Many -Correction This section describes the application of any number of... of - Correction of errors.

[0149] Correctable given design - Number of errors ,make Let be a prime number and define and In addition, let To satisfy conditions (i)-(iii) in part V Integer vectors in the array. ,use Represents an integer vector and order express Integer matrices, their behavior , That is, when regarded as When the matrix is ​​on, Is Berlekamp code The parity check matrix. Let For any Integer matrices, such that And define the following in The module on:

[0150] when At that time, it was known The minimum Lee distance is at least Therefore, = Equation 33 for within The above equation also holds for any coset.

[0151] make For the first The encoder in the section (where will) Replace with ), and ordered (in Examples can be calculated. The following check vectors

[0152]

[0153] In addition, if the example is selected This makes its first column a standard unit vector. Then the example (from )get The example can be expanded. Each item in Its 2-based representation : Equation 34 Now consider the encoding mapping defined as follows: , Equation 35 in

[0154] if ,in Therefore, according to Equation 33 and Proposition 1, in of -Assuming the suffix is ​​error-free, examples can be found from recover It can be done by... The applied dimension is linear - - The error correction code's (second) encoder ensures this assumption. The example can recursively continue this process, but if the example only does [something] in the second step... - If there is overlap, then the example can end with the following total redundancy. Equation 36 in That is the final code length. Therefore, for... In comparison Most of the redundancy is caused by the first coding level.

[0155] To make this scheme applicable -CAM, as shown in Part VI. And as it is done in the example, the example uses Replace the vector in equation 34 .consider The checksum of a completely one vector in the array:

[0156] in The first column is the standard unit vector. (Review) and

[0157] Therefore, it can be seen that ,and By choosing appropriately Examples may have

[0158] In this case, the example yields equation 35. Below It looks like a completely one vector. This argument applies to any subsequent recursive coding step, especially when the step is simply repeated. Therefore, this application shows that, with the choice of parameters as described in Part VI, it is guaranteed that the all-one vector is a codeword of an induced code.

[0159] Compare Equation 36 with the redundancy of the construction in Part II, if the example replaces in Equation 9. Therefore, the example will often yield a value that is less than the value obtained in equation 36 (even when...). (Time). This is because in equation 36 Item, in and Compared to when it's not small, it becomes indispensable.

[0160] Finally, for -TCAM, example uses On The bi-spanner substitution equation 34 .

[0161] VIII. Ordinary BCAM and TCAM Although this application involves -CAM and - TCAM error correction schemes, but such schemes are applicable to the more general BCAM and TCAM (which can be considered as -CAM -TCAM, where the integer sum of the outputs of the CAM cells along each column is replaced by the two's complement of their logical OR, is also useful. This is achieved by copying each column. Next, the example can be drawn from any array. Recovery from errors is possible, but the redundancy is excessive.

[0162] The error correction problem of BCAM has been explored in several papers. The proposed solution involves hardware modifications to the sensing amplifier along each matching line: "matching" is redefined as the sum of the (integer) values ​​of the outputs of the CAM cells along a column, not exceeding a specified threshold (therefore, the improved device is effectively quantized). -CAM; ordinary BCAM corresponds to In such devices, examples can be used. Error-correcting binary codes encode the contents of each column and correspondingly encode the input vector. Then, the reading will be the same as / similar to the reading of error-free BCAM, provided that the number of errors per column does not exceed [a certain threshold]. For TCAM, displaying this method would require at least a simple representation of the contents of each column. - Overlapping redundancy (leading to excessive redundancy).

[0163] Figure 6 An example CAM unit 600 according to the present disclosure is described.

[0164] As mentioned above, CAMs can be divided into "binary" or "ternary" types. A binary CAM ("BCAM"), composed of BCAM units, operates on (and stores) input patterns containing binary bits of "0" and "1". A ternary CAM ("TCAM"), composed of TCAM units, operates on (and stores) input patterns containing binary bits of "0", "1", and "X" values. The "X" value is sometimes referred to as the "ignore" value or the "wildcard" value. When searching for an input pattern in a TCAM, "X" will return a match for either a "0" or "1" bit. Therefore, searching for the input pattern "10X1" will return a match for either "1001" bits or "1011".

[0165] As mentioned above, the CAM-based circuits of this disclosure may utilize BCAM / BCAM units or TCAM / TCAM units, depending on the implementation method.

[0166] CAM unit 600 illustrates an example of a 4-transistor-2-memristor (4T2M) TCAM unit that can be used in CAM-based circuits of the present disclosure. For example, CAM unit 600 may illustrate an example task-driven CAM unit programmed to store task-driven values ​​consistent with a computational task. CAM unit 600 may also illustrate an example redundant CAM unit programmed to store redundant values.

[0167] As shown, the CAM unit 600 includes a switching transistor T1 connected to the data line SL and a switching transistor T1 connected to the inverting data line SL. The switching transistor T2. As described above, across the data line SL and the inverting data line. The voltage can correspond to a value / item (e.g., a voltage signal) of the input vector applied to the CAM, where the CAM unit 600 is part of the CAM. For example, the voltage across the data line SL can correspond to a value / item (e.g., logic 1) of the input vector, while the voltage across the inverting data line... The voltage can correspond to the negative version of the value / item of the input vector (such as logic zero). Memristor M2 is connected to switching transistor T1, and memristor M1 is connected to switching transistor T2. As shown, the gates of switching transistors T1 and T2 are connected to word line WL, which biases switching transistors T1 and T2. Immediately before and during the search / match operation, the voltage of word line WL can rise above a threshold, thereby activating switching transistors T1 and T2. When switching transistor T1 is activated, it provides an electrical connection between data line SL and memristor M2. In contrast, when switching transistor T1 is not activated (i.e., when the voltage across word line WL is below the threshold), data line SL is electrically disconnected from memristor M2. Similarly, when switching transistor T2 is activated, it provides an inverted data line. The electrical connection between the transistor T2 and memristor M1. In contrast, when the switching transistor T2 is not activated (i.e., when the voltage across word line WL is below the threshold), the inverting data line... The memristor M1 can be electrically disconnected. Therefore, the inclusion of switching transistors T1 and T2 ensures that memristors M1 and M2 are disconnected from the data lines of CAM unit 600 when no search / match operation is performed, which reduces the overall power consumption of CAM unit 100.

[0168] As shown, memristors M1 and M2 are connected in series to form a resistive voltage divider 602. The output voltage of the resistive voltage divider 602 (i.e., the voltage across the common node G) is applied to the gate of the matching line transistor T4 to control its activation. When the matching line transistor T4 is activated, it can discharge (i.e., “pull down”) the voltage across the matching line ML. For example, if the voltage applied to the gate of the matching line transistor T4 exceeds a threshold, then the matching line transistor T4 will activate and discharge (i.e., “pull down”) the voltage across the matching line ML – returning to mismatch. In contrast, when the voltage applied to the gate of the matching line transistor T4 is less than or equal to the threshold, the matching line transistor T4 may not be activated. Therefore, the matching line transistor T4 will not discharge (i.e., “pull down”) the voltage across the matching line ML – thus returning to match. Although in Figure 6 The specific example describes the "pull-down" logic, but it should be understood that in other examples, the CAM unit 600 can implement the "pull-up" logic.

[0169] As described above, the CAM unit 600 can be programmed to store task-driven or redundant values ​​by programming the conductances of memristors M1 and M2. While the conductances of the programmed memristors M1 and M2 typically remain unchanged (unless reprogrammed), the output voltage of the resistor divider 602 (i.e., the voltage at the common node G) will be based on the data line SL and the inverting data line from memristors M2 and M1, respectively. The voltage received changes. For example, memristors M1 and M2 can be programmed to a first conductance state (e.g., a logic zero conductance state corresponding to a negative literal), i.e., when the voltage received from data line SL and the inverting data line changes. When the received voltage represents logic one, this state causes the output voltage of the resistor divider to be high (e.g., exceeding a threshold), thus affecting the voltage across the data line SL and the inverting data line. The voltage represents a logic 1, activating the matching line transistor T4 and returning to mismatch. In contrast, memristors M1 and M2 can be programmed to a second conductance state (e.g., a logic 1 conductance state corresponding to a non-negative literal), i.e., when the voltage from the data line SL and the inverting data line... When the received voltage represents logic zero, this state causes the output voltage of the resistor divider to be high (e.g., exceeding a threshold), thus causing the voltage to rise across the data line SL and the inverting data line. The voltage represents the activation of the matched-line transistor T4 when logic zero is reached and the mismatch is returned. In various examples, memristors M1 and M2 can be programmed to a third conductance state (e.g., a wildcard conductance state), i.e., regardless of whether it is from the data line SL or the inverting data line. The received voltage represents either logic zero or logic one. This state allows the output voltage of the resistor divider to remain low (e.g., below a threshold), thereby ensuring that the matching line transistor T4 remains inactive, and when crossing the data line SL and the inverting data line... The voltage represents a logic zero or logic one, and a match is returned.

[0170] As shown, the service line transistor T3 can work in conjunction with the switching transistors T1 and / or T2 to program the conductance of memristors M1 and M2 using the service line SX.

[0171] It should be understood that CAM unit 600 is merely one example of a CAM unit that can be included in CAM-based circuits of the present technology. In other embodiments, CAM unit 600 may include a BCAM unit or a TCAM unit with different configurations, such as a CMOS-based CAM unit, a 6-transistor-2-memristor (6T2M) CAM unit, a 3-terminal CAM unit, a 16-transistor (16T) TCAM unit, etc.

[0172] Figure 7 An example CAM-based circuit 700 according to the present disclosure is described.

[0173] As shown, the CAM-based circuit 700 may include a Σ-CAM 710 and one or more processing resources (not shown for simplicity) for programming the Σ-CAM 710 and detecting one or more errors in the output vector (c) from the Σ-CAM 700. As shown, the output vector (c) may consist of values ​​c0-c... n-1composition.

[0174] As mentioned above, Σ-CAM (sometimes also called Hamming distance CAM) is a special type of CAM configured to sum the outputs from CAM cells arranged along their respective columns. In other words, Σ-CAM can refer to the summation of the outputs from CAM cells. CAM composed of arrays, where some internal state values Each CAM unit Implement function The internal state of Σ-CAM programming can be represented as an array (matrix). ,in Representative List The input to Σ-CAM can include row vectors (e.g., search keys). ,in As a tribute to the journey The input to all CAM units. The corresponding columns of Σ-CAM (corresponding to the matching rows). It can calculate along the corresponding column The sum of integers output by the arranged CAM units, i.e. These integers and their sum form the output row vector of Σ-CAM, i.e. Therefore, Σ-CAM calculates the input vector and the vector along the Σ-CAM. Hamming distance between the contents of CAM cells in each column of the column.

[0175] As an illustrative example, Σ-CAM710 includes a sequence of numbers (n), i.e., from... Figure 7 The leftmost column from 0 to Figure 7 The rightmost column n-1 Σ-CAM710 also includes a number (l) rows, i.e., from Figure 7 Top row 0 to Figure 7 bottom row l-1 .

[0176] For ease of reference, CAM cells arranged along column 0 and row 0 can be referred to as CAM cells. 0,0 Similarly, along the column n-1 Hexing l-1 An arrangement of CAM units can be called a CAM unit. n-1,l-1， And so on.

[0177] The CAM units that make up Σ-CAM 710 can include various types of CAM units, including BCAM units or TCAM units (e.g., Figure 6 Example CAM unit 600 in the example.

[0178] As shown in the figure, the CAM units arranged along the common row of Σ-CAM710 are electrically connected along a common data line. For example, the CAM units in row 0 are electrically connected along the first data line, and each CAM unit can receive the input value x0. Similarly, the rows... l-1 CAM unit along the l th The data cable is electrically connected, and each CAM unit can receive the input value x accordingly. l-1 Here, the input value is x0-x. l-1 It can include the component values ​​of the input vector (x).

[0179] As shown in the figure, CAM cells arranged along the common column of Σ-CAM710 are electrically connected along a common matching line. For example, CAM cells connected along column 0 are electrically connected along matching line ML0. Similarly, along the column... n-1 The connected CAM unit is along the matching line ML n-1 Electrical connection.

[0180] As shown in the figure (and as described above), the Σ-CAM710 can be configured to sum the outputs from CAM cells arranged along the respective columns. The final sum can be output by the matching line associated with the respective column.

[0181] For example (as mentioned above) Figure 6 As described above, when a CAM unit (e.g., CAM unit 600) returns a mismatch, the CAM unit can be configured to pull down the voltage of the matching line to which the CAM unit is connected. Therefore, the Σ-CAM710 can effectively sum / count the number of mismatches (or conversely, the number of matches) returned by the CAM unit of the corresponding column by reading the final voltage output of the matching line associated with the corresponding column.

[0182] For the purpose of conceptual explanation, Figure 8 Example Figure 800 illustrates a comparison between a threshold voltage and the voltage output of the matching line associated with the corresponding column of the Σ-CAM710. As shown, the threshold voltage is 0.9 AU volts, and the matching line voltage is compared to the threshold voltage at three discrete times: t = 10.00 AU sec; t = 10.25 AU sec; t = 10.50 AU sec. If the matching line returns three matches (as shown by curve 802), the matching line voltage will exceed the threshold voltage three times. If the matching line returns two matches (as shown by curve 804), the matching line voltage will exceed the threshold voltage twice. If the matching line returns one match (as shown by curve 806), the matching line voltage will exceed the threshold voltage once. If the matching line returns zero matches (as shown by curve 808), the matching line voltage will exceed the threshold voltage zero times. Here, the threshold voltage and sensing / comparison time can be strategically selected to accommodate this relationship.

[0183] As described above, the CAM-based circuit 700 can detect and correct errors in the Σ-CAM710 (i.e., "access" error correction) when the Σ-CAM710 performs computational tasks.

[0184] This "accessible" error correction method improves upon "offline" error detection / correction methods. Such "offline" error detection / correction methods typically involve test programs that would interfere with the normal operation of the hardware accelerator during computational tasks, and therefore must be executed "offline." For example, another method for detecting errors in a CAM might involve applying a sequence of test vectors to the CAM to detect programming errors and other circuit-based errors. The applied test vectors may be unrelated to the computational task the CAM is performing, otherwise they would disrupt the computation. Therefore, this method would be executed "offline." In contrast, the CAM-based circuit 700 can correct the output vectors generated by the Σ-CAM710 while the Σ-CAM710 performs a specified computational task. Therefore, this method is computationally more efficient (i.e., consumes less processing resources, time, power, etc.) compared to other "offline" error detection and correction methods.

[0185] The CAM-based circuit 700 leverages the insight that Σ-CAM operates similarly to a vector-matrix multiplier (sometimes referred to as a dot product engine) to achieve the advantages provided by "access" error detection and correction. Utilizing this insight, the CAM-based circuit 700 uniquely applies error correction methods used for vector-matrix multipliers to Σ-CAM. The applied method involves adding redundant columns to the Σ-CAM 710. The CAM-based circuit 700 can utilize one or more processing resources (e.g., an encoder) to compute redundancy values ​​for the redundant columns so that the Σ-CAM 710 stores codewords of linear code (C) in each row. To further adapt this method for new / specific types of hardware accelerators (i.e., Σ-CAM 710), the CAM-based circuit 700 can modify the linear code (C) used to compute the redundancy values. That is, the CAM-based circuit 700 can modify the linear code (C) to include all-one vectors. With this modification, the CAM-based circuit 700 can detect and correct errors in the output vector from the Σ-CAM 710 based on this modified / specificated linear code (C).

[0186] For example (and as described above), the CAM-based circuit 700 may include: a) a Σ-CAM 710, which includes CAM cells arranged in a number (l) rows and a number (n) columns, wherein the Σ-CAM 710 is configured to sum the outputs from the number (l) CAM cells connected along the corresponding columns in the number (n) columns; and b) one or more processing resources for programming the CAM cells to store a matrix (A) having a dimension (l x n), wherein: i) each row of the matrix (A) includes a codeword of a linear code (C), and ii) the linear code (C) includes an all-one vector of dimension (n) as a codeword.

[0187] In Σ-CAM710, CAM units connected along a number (k) of a number (n) column may include task-driven CAM units. Correspondingly, CAM units connected along a number (nk) of a number (n) column may include redundant CAM units. Therefore, a corresponding row of Σ-CAM710 includes a number (k) of task-driven CAM units and a number (nk) of redundant CAM units. Thus, programming Σ-CAM710 to store a matrix (A) of dimension (lxn) may include: a) programming the number (k) of task-driven CAM units in the corresponding row to store task-driven values ​​corresponding to the computation task; b) calculating redundancy values ​​for the number (nk) of redundant CAM units in the corresponding row based on the programmed task-driven values ​​and the linear code (C); and c) programming the number (nk) of redundant CAM units in the corresponding row to store the calculated redundancy values ​​such that the corresponding row stores the codeword of the linear code (C). In some implementations, calculating the redundancy values ​​of the number (nk) redundant CAM units in a given row may include calculating the redundancy values ​​of the number (nk) redundant CAM units in a given row such that the task-driven value and the redundancy value comprise a sequence of one and zero as defined by the linear code (C).

[0188] In the CAM-based circuit 700, one or more processing resources may be further used to detect and correct one or more errors in the output vector (c) from the Σ-CAM 710 based on linear codes (C). In some embodiments, the output vector (c) may have a dimension (n). Accordingly, the output vector (c) may include a concatenation of a task-driven output vector (c') and a redundant output vector (c''). Here, the task-driven output vector (c') may have a dimension (k) and correspond to the sum of the following: (1) a vector-matrix product between the transformation of the input vector (x) of dimension (l) received by the Σ-CAM 710 and the task-driven storage matrix (A') of dimension (lxk) stored by the task-driven CAM unit of the Σ-CAM 710; and (2) a vector product between an all-one vector of dimension (n) and a constant value (e.g., see Equation 4 below). Relatedly, the redundant output vector (c'') may have a dimension (nk) and correspond to the sum of the following two items: (1) the vector-matrix product between the transformation of the input vector (x) and the redundant storage matrix (A'') of dimension (lx (nk)) stored by the redundant CAM cells of the Σ-CAM710; and (2) the vector product between an all-one vector of dimension (n) and a constant value (e.g., see Equation 4 above). Furthermore, one or more processing resources may detect and correct one or more errors in the task-driven output vector (c') based on (e.g., by comparison) the linear code (C) and the redundant output vector (c'').

[0189] Figure 9 A block diagram of an example computer system 900 is described, in which various examples described herein can be implemented. The computer system 900 can also be used to calculate redundancy values ​​and detect / correct redundancy from... Errors in the output vector of -CAM (e.g., Σ-CAM710).

[0190] Computer system 900 includes a bus 912 or other communication mechanism for transmitting information, and one or more hardware processors 904 coupled to the bus 912 to process information. The hardware processor 904 may be, for example, one or more general-purpose microprocessors.

[0191] Computer system 900 also includes main memory 906, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 912 for storing information and instructions to be executed by processor 904. Main memory 906 can also be used to store temporary variables or other intermediate information during the execution of instructions by processor 904. When stored in storage media accessible to processor 904, such instructions make computer system 900 a dedicated machine customized to perform the operations specified in the instructions.

[0192] The computer system 900 also includes a read-only memory (ROM) 908 or other static storage devices coupled to the bus 902 for storing static information and instructions for the processor 904. Storage devices 910, such as disks, optical discs, or USB thumb drives (flash drives), are provided and coupled to the bus 902 for storing information and instructions.

[0193] Computer system 900 may be coupled via bus 902 to display 912, such as a liquid crystal display (LCD) (or touchscreen), for displaying information to the computer user. Input device 914, including alphanumeric keys and other keys, is coupled to bus 902 for transmitting information and command selections to processor 904. Another type of user input device is cursor control 916, such as a mouse, trackball, or cursor arrow keys, for transmitting directional information and command selections to processor 904 and for controlling cursor movement on display 912. In some embodiments, the same directional information and command selections as cursor control may be received via touch on a touchscreen without a cursor.

[0194] The computing system 900 may include a user interface module to implement a GUI, which may be stored as executable software code executed by the computing device in a mass storage device. For example, such and other modules may include components such as software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0195] Generally, terms such as “component,” “engine,” “system,” “database,” and “data storage” as used herein can refer to logic embodied in hardware or firmware, or to a set of software instructions written in a programming language such as Java, C, or C++ that may have entry and exit points. Software components can be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpreted programming language such as BASIC, Perl, or Python. It is understood that software components can be invoked from other components or from themselves, and / or can be invoked in response to detected events or interrupts. Software components configured to execute on a computing device can be provided on computer-readable media such as optical discs, digital video discs, flash drives, disks, or any other tangible media, or as digital downloads (and may be initially stored in a compressed or installable format, requiring installation, decompression, or decryption before execution). Such software code can be stored, partially or entirely, on a memory device executing the computing device for execution by the computing device. Software instructions can be embedded in firmware, such as EPROM. It is also understood that hardware components may consist of connected logic units, such as gates and flip-flops, and / or may consist of programmable units, such as programmable gate arrays or processors.

[0196] Computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic. The combination of this custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic with the computer system enables computer system 900 to be a dedicated machine or to program computer system 900 as a dedicated machine. According to one embodiment, the techniques described herein are executed by computer system 900 in response to processor 904 executing one or more sequences of one or more instructions contained in main memory 906. These instructions may be read into main memory 906 from another storage medium, such as storage device 910. Executing the sequence of instructions included in main memory 906 causes processor 904 to perform the processing steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0197] As used herein, the term "non-transitory media" and similar terms refer to any medium that stores data and / or instructions that enable a machine to operate in a particular manner. Such non-transitory media can include non-volatile media and / or volatile media. Non-volatile media include, for example, optical discs or magnetic disks, such as storage device 910. Volatile media include dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cartridges, and the same networking versions.

[0198] Non-transitory media differ from transmission media but can be used in conjunction with them. Transmission media participate in the transmission of information between non-transitory media. For example, transmission media include coaxial cables, copper wires, and optical fibers, including the conductors that form bus 902. Transmission media can also take the form of sound waves or light waves, such as those generated during radio wave and infrared data communication.

[0199] Computer system 900 also includes a communication interface 918 coupled to bus 902. Network interface 918 provides bidirectional data communication coupled to one or more network links connected to one or more local networks. For example, communication interface 918 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem providing a data communication connection to a corresponding type of telephone line. As another example, network interface 918 may be a local area network (LAN) card providing a data communication connection to a compatible LAN (or a WAN component communicating with a WAN). Wireless links may also be implemented. In any such implementation, network interface 918 transmits and receives electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information.

[0200] Network links typically provide data communication to other data devices via one or more networks. For example, a network link may provide connectivity to a host computer or a data device operated by an Internet Service Provider (ISP) via a local network. The ISP, in turn, provides data communication services through a global packet data communication network now commonly referred to as the "Internet." Both local networks and the Internet use electrical, electromagnetic, or optical signals that carry digital data streams. Signals through various networks and on network links, as well as signals through communication interface 918 (which carries digital data to and from computer system 900), are example forms of transmission media.

[0201] Computer system 900 can send messages and receive data, including program code, via a network, network link, and communication interface 918. In the Internet example, the server can send requested code for an application via the Internet, ISP, local network, and communication interface 918.

[0202] The received code may be executed by processor 904 when it is received, and / or stored in storage device 910 or other non-volatile memory for later execution.

[0203] Each of the processes, methods, and algorithms described in the preceding sections can be embodied in code components executed by one or more computer systems or computer processors, including computer hardware, and can be fully or partially automated. One or more computer systems or computer processors can also operate to support the execution of related operations in a “cloud computing” environment or as “Software as a Service” (SaaS). Processes and algorithms can be implemented, partially or entirely, in dedicated circuitry. The various features and processes described above can be used independently of each other or can be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular sequence, and associated blocks or states can be executed in other suitable sequences, or can be executed in parallel or in some other way. Blocks or states can be added to or removed from the disclosed example embodiments. The execution of certain operations or processes can be distributed among computer systems or computer processors, residing not only within a single machine but also deployed across multiple machines.

[0204] As used herein, the circuit can be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms can be used to compose the circuit. In implementation, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be shared, partially or wholly, in one or more circuits. Although elements of various features or functions can be described independently or claimed as separate circuits, these features and functions can be shared in one or more common circuits, and such description does not require or imply the need for separate circuits to implement such features or functions. In the case where the circuit is implemented entirely or partially using software, such software can be implemented to operate in conjunction with a computing or processing system capable of performing the functions described, such as computer system 900.

[0205] As used herein, the term “or” may be understood in an inclusive or exclusive sense. Furthermore, descriptions of the singular form of a resource, operation, or structure should not be interpreted as excluding the plural form. Unless explicitly stated otherwise, or otherwise understood in the context in which they are used, conditional languages ​​such as “may,” “can,” “possibly,” or “may” are generally intended to express that certain implementations include, while others do not, certain features, elements, and / or steps.

[0206] Unless otherwise expressly stated, the terms and phrases used herein, and their variations thereof, should be understood as open-ended rather than restrictive. Adjectives such as “regular,” “traditional,” “normal,” “standard,” “known,” and similar terms should not be construed as limiting the described item to a given time period or to items available at a given time, but rather should be interpreted as encompassing regular, traditional, normal, or standard techniques that may be available or known now or at any future time. In some instances, the presence of expansive words and phrases (such as “one or more,” “at least,” “but not limited to”) or other similar phrases should not be interpreted as an expectation or need for a narrower scope where such expansive phrases might not be present.

Claims

1. A computing system, comprising: A summation content addressable memory (CAM) includes CAM cells arranged in a number of l rows and n columns, wherein the summation CAM is configured to sum the outputs from a number of l CAM cells connected along the corresponding columns of the n columns; as well as One or more processing resources are operated to program the CAM unit to store a matrix A having dimension l x n, wherein: Each row of matrix A includes the codeword of linear code C, and The linear code C comprises a vector of dimension n, which is a completely one vector, as the codeword.

2. The computing system according to claim 1, wherein: The CAM units connected along the k columns of the n columns include task-driven CAM units; and The CAM units connected along the n columns include redundant CAM units, such that the corresponding rows of the summation CAM include k task-driven CAM units and nk redundant CAM units.

3. The computing system of claim 2, wherein programming the summation CAM to store the matrix A having dimension l x n comprises: The k task-driven CAM units in the corresponding rows are programmed to store task-driven values ​​that correspond to the computation task; The redundancy values ​​of the corresponding row of nk redundant CAM units are calculated based on the programmed task-driven value and the linear code C. as well as The corresponding row is programmed with the number of nk redundant CAM units to store the calculated redundancy value, such that the corresponding row stores the codeword of the linear code C.

4. The computing system according to claim 3, wherein calculating the redundancy value of the n^k redundant CAM units in the corresponding row based on the programmed task-driven value and the linear code C comprises: Calculate the redundancy values ​​of the n^k redundant CAM units in the corresponding row, such that the task-driven value and the redundancy values ​​comprise a sequence of ones and zeros as defined by the linear code C.

5. The computing system of claim 2, wherein the one or more processing resources are operated for: Based on the linear code C, one or more errors in the output vector c from the summation CAM are detected and corrected.

6. The computing system according to claim 5, wherein: The output vector c has dimension n; The output vector c includes a concatenation of the task-driven output vector c' and the redundant output vector c''; The task-driven output vector c' has dimension k and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x of dimension l received by the summing CAM and the task-driven storage matrix A' of dimension lxk stored by the task-driven CAM unit of the summing CAM, and The vector product between a single vector of dimension n and a constant value; The redundant output vector c'' has dimension nk and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x and the redundant storage matrix A'' of dimension lx (nk) stored by the redundant CAM cells of the summing CAM, and The vector product between the all-one vector of dimension n and the constant value; and Detecting and correcting one or more errors in the output vector c from the summing CAM based on the linear code C includes detecting and correcting one or more errors in the task-driven output vector c' based on the linear code C and the redundant output vector c''.

7. The computing system according to claim 1, wherein: The corresponding CAM unit of the summation CAM includes one or more programmable memristors; and Programming the corresponding CAM unit includes programming the conductance of one or more programmable memristors.

8. A computing system, comprising: One or more processing resources, said one or more processing resources being operated for: The programmatically sums the content-addressable memory CAM to store a matrix A with dimension l x n, where: Each row of matrix A includes the codeword of linear code C, and The linear code C comprises a fully one vector of dimension n as its codeword; and Based on the linear code C, one or more errors in the output vector c from the summation CAM are detected and corrected.

9. The computing system according to claim 8, further comprising the summation CAM.

10. The computing system according to claim 9, wherein: The summation CAM comprises CAM cells arranged in l rows and n columns; and The summation CAM is configured to sum the outputs from l CAM cells connected along the corresponding columns of the n columns.

11. The computing system of claim 10, wherein the one or more processing resources are operated for: The corresponding k task-driven CAM units are programmed to store task-driven values ​​that correspond to the computation task; The redundancy values ​​of the corresponding row of nk redundant CAM units are calculated based on the programmed task-driven value and the linear code C. as well as The corresponding row is programmed with the number of nk redundant CAM units to store the calculated redundancy value, such that the corresponding row stores the codeword of the linear code C.

12. The computing system of claim 11, wherein calculating the redundancy value of the n^k redundant CAM units of the corresponding row based on the programmed task-driven value and the linear code C comprises: Calculate the redundancy values ​​of the n^k redundant CAM units in the corresponding row, such that the task-driven value and the redundancy values ​​comprise a sequence of ones and zeros as defined by the linear code C.

13. The computing system according to claim 11, wherein: The output vector c has dimension n; The output vector c includes a concatenation of the task-driven output vector c' and the redundant output vector c''; The task-driven output vector c' has dimension k and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x of dimension l received by the summing CAM and the task-driven storage matrix A' of dimension lxk stored by the task-driven CAM unit of the summing CAM, and The vector product between a single vector of dimension n and a constant value; The redundant output vector c'' has dimension nk and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x and the redundant storage matrix A'' of dimension lx (nk) stored by the redundant CAM cells of the summing CAM, and The vector product between the all-one vector of dimension n and the constant value; and Detecting and correcting one or more errors in the output vector c from the summing CAM based on the linear code C includes detecting and correcting one or more errors in the task-driven output vector c' based on the linear code C and the redundant output vector c''.

14. The computing system according to claim 8, wherein: The corresponding CAM unit of the summation CAM includes one or more programmable memristors; and Programming the corresponding CAM unit includes programming the conductance of one or more programmable memristors.

15. A method for a content-addressable memory (CAM), comprising: Write a program to sum CAM to store a matrix A with dimension l x n, where: Each row of matrix A includes the codeword of linear code C, and The linear code C comprises a fully one vector of dimension n as its codeword; and Based on the linear code C, one or more errors in the output vector c from the summation CAM are detected and corrected.

16. The method of claim 15, wherein: The summation CAM comprises CAM cells arranged in l rows and n columns; and The summation CAM is configured to sum the outputs from l CAM cells connected along the corresponding columns of the n columns.

17. The method of claim 16, wherein programming the summation CAM to store the matrix A having dimension l x n comprises: The corresponding k task-driven CAM units are programmed to store task-driven values ​​that correspond to the computation task; The redundancy values ​​of the corresponding row of nk redundant CAM units are calculated based on the programmed task-driven value and the linear code C. as well as The corresponding row is programmed with the number of nk redundant CAM units to store the calculated redundancy value, such that the corresponding row stores the codeword of the linear code C.

18. The method of claim 17, wherein calculating the redundancy value of the n^k redundant CAM units of the corresponding row based on the programmed task-driven value and the linear code C comprises: Calculate the redundancy values ​​of the n^k redundant CAM units in the corresponding row, such that the task-driven value and the redundancy values ​​comprise a sequence of ones and zeros as defined by the linear code C.

19. The method of claim 17, wherein: The output vector c has dimension n; The output vector c includes a concatenation of the task-driven output vector c' and the redundant output vector c''; The task-driven output vector c' has dimension k and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x of dimension l received by the summing CAM and the task-driven storage matrix A' of dimension lxk stored by the task-driven CAM unit of the summing CAM, and The vector product between a single vector of dimension n and a constant value; The redundant output vector c'' has dimension nk and corresponds to the summation of the following: The vector-matrix product between the transformation of the input vector x and the redundant storage matrix A'' of dimension lx (nk) stored by the redundant CAM cells of the summing CAM, and The vector product between the all-one vector of dimension n and the constant value; and Detecting and correcting one or more errors in the output vector c from the summing CAM based on the linear code C includes detecting and correcting one or more errors in the task-driven output vector c' based on the linear code C and the redundant output vector c''.

20. The method of claim 15, wherein: The corresponding CAM unit of the summation CAM includes one or more programmable memristors; and Programming the corresponding CAM unit includes programming the conductance of one or more programmable memristors.

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