A hybrid multilevel converter common mode voltage determination and suppression method

Abstract

The present application relates to the technical field of converter, in particular to a hybrid multi-level converter common-mode voltage determination and suppression method, comprising defining the region to which the three-phase voltage reference wave corresponding to the hybrid multi-level converter belongs at a certain moment according to the hybrid multi-level converter; determining the state to which the three-phase voltage reference wave belongs at the moment; determining the common-mode voltage amplitude corresponding to the state to which the three-phase voltage reference wave belongs at the moment according to the determined state to which the three-phase voltage reference wave belongs at the moment; determining the voltage basic information corresponding to the zero sequence voltage to be injected according to the corresponding three-phase voltage reference wave at the moment; inputting the corresponding zero sequence voltage and suppressing the common-mode voltage according to the determined voltage basic information corresponding to the zero sequence voltage to be injected.

Description

Technical Field

[0001] This invention relates to the field of converter technology, and more specifically to a method for determining and suppressing the common-mode voltage of a hybrid multilevel converter. Background Technology

[0002] In key application scenarios such as high-capacity motor drives, energy storage, and new energy grid connection, multilevel converters have become a highly regarded technical solution due to their significant advantages such as high voltage, high power rating, and excellent harmonic performance.

[0003] However, hybrid multilevel converters face a serious problem in practical applications: compared to two-level converters, the causes of common-mode voltage in hybrid multilevel converters are more complex. For example, in the field of high-capacity motor drives, excessive common-mode voltage can lead to a series of serious consequences. On the one hand, it can cause damage to motor bearings, shorten the motor's lifespan, and increase equipment maintenance costs; on the other hand, strong electromagnetic interference can affect the normal operation of surrounding electronic equipment and reduce the stability of the entire system. Currently, there is a significant lack of methods for determining and suppressing the common-mode voltage of hybrid multilevel converters. Existing technologies are insufficient for accurately determining and analyzing its common-mode voltage, thus hindering the implementation of effective targeted suppression measures.

[0004] Therefore, there is an urgent need for a method for determining and suppressing common-mode voltage in hybrid multilevel converters, which can quickly determine and suppress common-mode voltage, thereby improving the determination efficiency and suppression reliability of common-mode voltage. Summary of the Invention

[0005] One of the objectives of this invention is to provide a method for determining and suppressing common-mode voltage in a hybrid multilevel converter, which enables rapid determination and suppression of common-mode voltage, thereby improving the determination efficiency and suppression reliability of common-mode voltage.

[0006] To achieve the above objectives, a method for determining and suppressing the common-mode voltage of a hybrid multilevel converter is provided, comprising the following steps:

[0007] S1. Based on the hybrid multilevel converter, define the region to which the three-phase voltage reference wave of the hybrid multilevel converter belongs at a certain moment;

[0008] S2. Based on the defined region to which the three-phase voltage reference wave belongs, and using a preset state determination strategy, determine the state to which the three-phase voltage reference wave belongs at that moment.

[0009] S3. Based on the determined state of the three-phase voltage reference wave at that moment, and based on the preset correlation table between the state of the three-phase voltage reference wave and the common-mode voltage, determine the common-mode voltage amplitude corresponding to the state of the three-phase voltage reference wave at that moment.

[0010] S4. Based on the common-mode voltage amplitude at that moment, determine whether to inject zero-sequence voltage. If the determination result is yes, then based on the common-mode voltage amplitude at that moment, determine the basic voltage information corresponding to the zero-sequence voltage to be injected. The basic voltage information includes the voltage frequency, waveform, voltage amplitude of the zero-sequence voltage, and the modulation ratio range corresponding to the injected zero-sequence voltage.

[0011] S5. Based on the basic voltage information corresponding to the zero-sequence voltage to be injected, input the corresponding zero-sequence voltage and suppress the common-mode voltage.

[0012] The technical principle and effects of this solution: In this solution, based on the characteristics of the hybrid multilevel converter, the region where the three-phase voltage reference wave corresponding to the converter is located at a certain moment is clearly defined. This step is the basis for subsequent analysis. By dividing the region, the three-phase voltage reference wave under different conditions can be handled more effectively.

[0013] After defining the region to which the three-phase voltage reference wave belongs, the specific state of the three-phase voltage reference wave at that moment is determined according to a preset state determination strategy. Since the state of the three-phase voltage reference wave has already been determined, and the preset correlation table stores the correspondence between different states and common-mode voltage, the common-mode voltage amplitude corresponding to that state at that moment can be directly looked up and determined from the table. This method of obtaining the common-mode voltage amplitude through a pre-established correlation table simplifies the calculation process and improves processing efficiency.

[0014] The basic information of the zero-sequence voltage to be injected is determined based on the current three-phase voltage reference waveform. This basic information includes the voltage frequency, waveform, and voltage amplitude. For example, when the common-mode voltage amplitude exceeds a certain threshold, a zero-sequence voltage of a specific frequency and amplitude needs to be injected for suppression.

[0015] After determining the basic information of the zero-sequence voltage, the corresponding zero-sequence voltage is input into the system. Through the interaction between the zero-sequence voltage and the original system voltage, common-mode voltage suppression is achieved. The injection of the zero-sequence voltage changes the voltage distribution of the system, reducing the common-mode voltage to an acceptable range, thereby improving the system's performance and stability.

[0016] By defining the three-phase voltage reference wave region, determining its state, and using the correlation table, the common-mode voltage amplitude of the hybrid multilevel converter at different times can be accurately determined, providing a reliable basis for subsequent suppression measures. This enables the rapid and simple determination of the common-mode voltage at each time, providing a basic model for common-mode voltage suppression.

[0017] The system determines whether to inject zero-sequence voltage based on the common-mode voltage amplitude and accurately identifies the basic information of the zero-sequence voltage. This allows for the determination of the optimal injected zero-sequence voltage, effectively suppressing common-mode voltage, improving the system's electromagnetic compatibility and stability, and reducing interference to other devices in the system. Effective suppression of common-mode voltage contributes to improving the performance of hybrid multilevel converters.

[0018] This method, through predefined regions, state determination strategies, and association tables, can adapt to the operational requirements of hybrid multilevel converters under different operating conditions, exhibiting strong flexibility and adaptability, and is capable of handling various complex operating situations.

[0019] Furthermore, the hybrid multilevel converter includes phase a, phase b, and phase c, as well as a DC side and a load side; phases a, b, and c are connected in parallel; each of phases a, b, and c includes four bridge arms and a flying capacitor C. fx ;

[0020] The DC side includes a DC voltage source V. dc 3 DC bus capacitors C d1 C d2 C d3 The first capacitor C1 and the second capacitor C2;

[0021] The three DC bus capacitors C d1 C d2 C d3 With DC voltage source V dc The first capacitor C1 and the second capacitor C2 are connected in series and connected to the three DC bus capacitors C d1 C d2 C d3 The capacitors are connected in parallel; a first neutral point O is provided between the first capacitor C1 and the second capacitor C2.

[0022] The four bridge arms include four sets of switching devices, namely S x1 S′ x1 S x2 S′ x2 S x3 S′ x3 S x4 S′ x4 ;

[0023] The S x1 The first terminal is connected to the DC bus capacitor C d1 The positive terminal is connected to the positive terminal, and the second terminal is connected to S′. x1 The first end and S x2 The second end; the S′ x1 The first end is also related to S x2The first terminal is connected to the second terminal, and the second terminal is connected to the DC bus capacitor C. d1 The negative electrode; the S x2 The second end is connected to S x3 The first end; the S x4 The first terminal is connected to the DC bus capacitor C. d3 The positive terminal is connected to the second terminal, and the second terminal is connected to S′. x2 The first end and S′ x4 The first end; the S′ x4 The second terminal is connected to the DC bus capacitor C. d3 The negative electrode; the S′ x2 The second end is connected to S′ x3 The first end; the S x3 The second end and the S′ x3 The second end of each is connected to the load side;

[0024] The S x2 The second end and S x3 The first terminal is connected to a flying capacitor C. fx The positive electrode, the S′ x2 The second end and S′ x3 The first terminal is connected to a flying capacitor C. fx The negative electrode.

[0025] Beneficial effects: By combining the control of four bridge arms and multiple sets of switching devices, multi-level output can be achieved. Compared with traditional two-level converters, multi-level output can make the output voltage waveform closer to a sine wave, reduce the harmonic content of the output voltage, and improve power quality. This is very advantageous for loads connected to the AC power grid or those with high power quality requirements, as it can reduce harmonic pollution to the power grid and adverse effects on the load.

[0026] Due to the adoption of a multi-level structure, each switching device withstands a relatively low voltage. In a traditional two-level converter, the switching device needs to withstand the entire DC bus voltage. However, in this hybrid multi-level converter, through a reasonable combination of circuit topology and switching states, each switching device only needs to withstand a portion of the DC bus voltage. This allows for the selection of switching devices with lower withstand voltage ratings, reducing device costs and improving system reliability, as switching devices under lower voltage stress typically have a longer lifespan.

[0027] The DC side employs a combination of multiple capacitors, enhancing its energy storage capacity and voltage stability. The parallel and series connections of these capacitors effectively filter out DC voltage ripple, providing a more stable DC power input to the converter.

[0028] Furthermore, the load side includes an inductor and a resistor; the first terminal of the inductor is connected to S. x3The second end and the S′ x3 The second end of the inductor is connected to the first end of the resistor. The second ends of the resistors corresponding to phases a, b, and c are connected to each other. The second end of the resistor is provided with a second neutral point n.

[0029] Beneficial effects: Inductors have the characteristic of impeding changes in current. Connecting an inductor to the load side can filter the multi-level voltage output of the converter and smooth the output current waveform.

[0030] Furthermore, the definition formula for defining the region to which the three-phase voltage reference wave of the hybrid multilevel converter belongs at a certain moment is as follows:

[0031]

[0032] In the formula, m a f is the modulation ratio, ranging from [0,1]; ac This is the output frequency.

[0033] Beneficial effects: By including the output frequency as a variable in the formula, the definition can be adapted to different output frequency requirements. Whether in low-frequency or high-frequency applications, the corresponding three-phase voltage reference wave can be generated by adjusting the output frequency value, meeting the output frequency requirements of different loads and expanding the application range of hybrid multilevel converters.

[0034] Furthermore, the preset state determination strategy is as follows:

[0035] Based on the preset flag bit judgment logic, determine the flag bits corresponding to phase a, phase b, and phase c respectively;

[0036] The preset flag determination logic is as follows:

[0037] like It is then defined as being in the "lower" region, and the flag is incremented by 1.

[0038] like It is then defined as being in the "middle" region, and the flag is incremented by 0.

[0039] like It is then defined as being in the "upper" region, and the flag is incremented by 2.

[0040] By adding the corresponding flag bits of phases a, b, and c, and based on the preset state judgment logic, the state of the three-phase voltage reference wave at that moment is obtained during the change of the three-phase voltage reference wave.

[0041] Beneficial effects: By dividing the amplitude range of the three-phase voltage reference wave into three distinct intervals ("lower" region, "middle" region, and "upper" region), and setting corresponding flag bit change rules for each interval ("lower" region flag bit +1, "middle" region flag bit +0, "upper" region flag bit +2), the determination of the state of each phase voltage reference wave becomes simple and intuitive. This clear rule and simple calculation method (adding flag bits) greatly simplifies the process of determining the state in complex three-phase voltage changes, reduces computational complexity and processing difficulty, and improves the efficiency of state determination.

[0042] Furthermore, the preset state judgment logic is as follows:

[0043] The sum of the flag bits equals 5, indicating state 1: "Up", "Up", "Down"; at this time, the common-mode voltage is [-V]. dc / 18.5V dc / 18];

[0044] The sum of the flag bits equals 4, indicating state 2: "Down", "Down", "Up"; the common-mode voltage is -5V at this time. dc / 18,V dc / 18];

[0045] The sum of the flag bits equals 2, indicating state 3: "Middle", "Middle", "Up"; at this time, the common-mode voltage is [-V]. dc / 18,V dc / 6];

[0046] The sum of the flag bits equals 1, indicating state 4: "Middle", "Middle", "Down"; at this time, the common-mode voltage is [-V]. dc / 6,V dc / 18];

[0047] The sum of the flag bits equals 0, indicating state 5: "Middle" "Middle" "Middle"; at this time, the common-mode voltage is [-V dc / 6,V dc / 6];

[0048] The sum of the flag bits equals 3, placing it in state 6: "Up", "Middle", "Down". If the sum of the voltage reference waveforms in the "Up" state and the "Middle" state is greater than 4 / 3, and the sum of the voltage reference waveforms in the "Down" state and the "Middle" state is greater than 2 / 3, then the common-mode voltage is [-V]. dc / 18,V dc / 6];

[0049] If the sum of the voltage reference waveform in the "upper" state and the voltage reference waveform in the "middle" state is less than or equal to 4 / 3, and the sum of the voltage reference waveform in the "lower" state and the voltage reference waveform in the "middle" state is less than or equal to 2 / 3, then the common-mode voltage is [-Vdc / 6,V dc / 18];

[0050] If the sum of the voltage reference waveform in the "upper" state and the voltage reference waveform in the "middle" state is greater than 4 / 3, or the sum of the voltage reference waveform in the "lower" state and the voltage reference waveform in the "middle" state is greater than 2 / 3, then the common-mode voltage is [-V]. dc / 18,V dc / 18]. Beneficial effects: By classifying the three-phase voltage reference wave states corresponding to the sum of different flag bits in detail and clearly defining the common-mode voltage range for each state, the common-mode voltage of the hybrid multilevel converter can be accurately determined under various operating conditions. This allows for targeted measures to suppress the common-mode voltage during system design and control, based on the specific state and common-mode voltage range, avoiding adverse effects of excessively high common-mode voltage on the system, such as electromagnetic interference and equipment insulation damage, thereby improving the reliability and stability of the system.

[0051] The state judgment logic considers various complex situations, such as in state 6 where the common-mode voltage range is further determined based on different combinations of voltage reference waveform values. This comprehensive consideration enables the system to adapt to various situations with different amplitude and phase combinations of three-phase voltage reference waveforms, enhancing the system's adaptability to complex operating conditions. Even when the voltage reference waveform exhibits fluctuations or anomalies, the system can accurately determine the common-mode voltage range based on the state judgment logic and take corresponding measures to ensure the normal operation of the system, thus improving its robustness.

[0052] Furthermore, determining the basic voltage information corresponding to the zero-sequence voltage to be injected based on the three-phase voltage reference wave at that moment includes the following steps:

[0053] Based on the three-phase voltage reference wave corresponding to that moment, the frequency of the zero-sequence voltage to be injected is determined to be three times the output frequency, and the corresponding waveform is a sine wave.

[0054] The corresponding zero-sequence voltage amplitude is calculated according to the preset zero-sequence voltage amplitude calculation formula.

[0055] The preset formula for calculating the zero-sequence voltage amplitude is as follows:

[0056] Beneficial effects: The common-mode voltage determination and suppression method for hybrid multilevel converters provided by this invention suppresses the common-mode voltage amplitude by injecting the optimal zero-sequence voltage. It has a good suppression effect in various output states and is implemented in the controller through software code. It has the advantages of good effect, low cost and simple implementation. Attached Figure Description

[0057] Figure 1 This is a flowchart of the common-mode voltage determination and suppression method for a hybrid multilevel converter in Embodiment 1 of the present invention;

[0058] Figure 2 This is a topology diagram of the hybrid multilevel converter in Embodiment 1 of the present invention;

[0059] Figure 3 This is a flowchart illustrating the implementation of the common-mode voltage determination and suppression method for the hybrid multilevel converter in Embodiment 1 of the present invention.

[0060] Figure 4 This is a reference waveform diagram before and after the injection of zero-sequence voltage in Embodiment 1 of the present invention;

[0061] Figure 5 The above are experimental waveforms before and after the injection of zero-sequence voltage in Embodiment 1 of the present invention. Detailed Implementation

[0062] The following detailed description illustrates the specific implementation method:

[0063] Example 1

[0064] A method for determining and suppressing common-mode voltage in a hybrid multilevel converter, basically as follows: Figure 1 , Figure 2 and Figure 3 As shown, it includes the following steps:

[0065] S1. Based on the hybrid multilevel converter, define the region to which the three-phase voltage reference wave of the hybrid multilevel converter belongs at a certain moment;

[0066] The hybrid multilevel converter includes phase a, phase b, and phase c, as well as a DC side and a load side; phases a, b, and c are connected in parallel; each of phases a, b, and c includes four bridge arms and a flying capacitor C. fx ;

[0067] The DC side includes a DC voltage source V. dc 3 DC bus capacitors C d1 C d2 C d3 The first capacitor C1 and the second capacitor C2;

[0068] The three DC bus capacitors C d1 C d2 C d3 With DC voltage source V dc The first capacitor C1 and the second capacitor C2 are connected in series and connected to the three DC bus capacitors C d1 C d2 C d3The capacitors are connected in parallel; a first neutral point O is provided between the first capacitor C1 and the second capacitor C2.

[0069] The four bridge arms include four sets of switching devices, namely S x1 S′ x1 S x2 S′ x2 S x3 S′ x3 S x4 S′ x4 ;

[0070] The S x1 The first terminal is connected to the DC bus capacitor C d1 The positive terminal is connected to the positive terminal, and the second terminal is connected to S′. x1 The first end and S x2 The second end; the S′ x1 The first end is also related to S x2 The first terminal is connected to the second terminal, and the second terminal is connected to the DC bus capacitor C. d1 The negative electrode; the S x2 The second end is connected to S x3 The first end; the S x4 The first terminal is connected to the DC bus capacitor C. d3 The positive terminal is connected to the second terminal, and the second terminal is connected to S′. x2 The first end and S′ x4 The first end; the S′ x4 The second terminal is connected to the DC bus capacitor C. d3 The negative electrode; the S′ x2 The second end is connected to S′ x3 The first end; the S x3 The second end and the S′ x3 The second end of each is connected to the load side;

[0071] The S x2 The second end and S x3 The first terminal is connected to a flying capacitor C. fx The positive electrode, the S′ x2 The second end and S′ x3 The first terminal is connected to a flying capacitor C. fx The negative electrode.

[0072] The load side includes an inductor and a resistor; the first end of the inductor is connected to S. x3 The second end and the S′ x3 The second end of the inductor is connected to the first end of the resistor. The second ends of the resistors corresponding to phases a, b, and c are interconnected. The second end of the resistor is provided with a second neutral point n. In this embodiment, the DC voltage source V dc=180V, all capacitors have a capacitance of 0.18mF, the resistance on the load side is 20Ω, and the inductance on the load side is 2.6mH.

[0073] The defining formula for defining the region to which the three-phase voltage reference wave of the hybrid multilevel converter belongs at a certain moment is as follows:

[0074]

[0075] In the formula, m a f is the modulation ratio, ranging from [0,1]; ac f is the output frequency. In this embodiment, f ac =50Hz, switching frequency is 6000Hz.

[0076] S2. Based on the defined region to which the three-phase voltage reference wave belongs, and using a preset state determination strategy, determine the state to which the three-phase voltage reference wave belongs at that moment.

[0077] The preset state determination strategy is as follows:

[0078] Based on the preset flag bit judgment logic, determine the flag bits corresponding to phase a, phase b, and phase c respectively;

[0079] The preset flag determination logic is as follows:

[0080] like It is then defined as being in the "lower" region, and the flag is incremented by 1.

[0081] like It is then defined as being in the "middle" region, and the flag is incremented by 0.

[0082] like It is then defined as being in the "upper" region, and the flag is incremented by 2.

[0083] By adding the corresponding flag bits of phases a, b, and c, and based on the preset state judgment logic, the state of the three-phase voltage reference wave at that moment is obtained during the change of the three-phase voltage reference wave.

[0084] The preset state judgment logic is as follows:

[0085] The sum of the flag bits equals 5, indicating state 1: "Up", "Up", "Down"; at this time, the common-mode voltage is [-V]. dc / 18.5V dc / 18];

[0086] The sum of the flag bits equals 4, indicating state 2: "Down", "Down", "Up"; the common-mode voltage is -5V at this time. dc / 18,V dc / 18];

[0087] The sum of the flag bits equals 2, indicating state 3: "Middle", "Middle", "Up"; at this time, the common-mode voltage is [-V]. dc / 18,V dc / 6];

[0088] The sum of the flag bits equals 1, indicating state 4: "Middle", "Middle", "Down"; at this time, the common-mode voltage is [-V]. dc / 6,V dc / 18];

[0089] The sum of the flag bits equals 0, indicating state 5: "Middle" "Middle" "Middle"; at this time, the common-mode voltage is [-V dc / 6,V dc / 6];

[0090] The sum of the flag bits equals 3, placing it in state 6: "Up", "Middle", "Down". If the sum of the voltage reference waveforms in the "Up" state and the "Middle" state is greater than 4 / 3, and the sum of the voltage reference waveforms in the "Down" state and the "Middle" state is greater than 2 / 3, then the common-mode voltage is [-V]. dc / 18,V dc / 6];

[0091] If the sum of the voltage reference waveform in the "upper" state and the voltage reference waveform in the "middle" state is less than or equal to 4 / 3, and the sum of the voltage reference waveform in the "lower" state and the voltage reference waveform in the "middle" state is less than or equal to 2 / 3, then the common-mode voltage is [-V dc / 6,V dc / 18];

[0092] If the sum of the voltage reference waveform in the "upper" state and the voltage reference waveform in the "middle" state is greater than 4 / 3, or the sum of the voltage reference waveform in the "lower" state and the voltage reference waveform in the "middle" state is greater than 2 / 3, then the common-mode voltage is [-V]. dc / 18,V dc / 18].

[0093] S3. Based on the determined state of the three-phase voltage reference wave at that moment, and based on the preset correlation table between the state of the three-phase voltage reference wave and the common-mode voltage, determine the common-mode voltage amplitude corresponding to the state of the three-phase voltage reference wave at that moment.

[0094] S4. Based on the three-phase voltage reference wave corresponding to this moment, determine the basic voltage information corresponding to the zero-sequence voltage to be injected. The basic voltage information includes the voltage frequency, waveform, and voltage amplitude of the zero-sequence voltage.

[0095] The determination of the basic voltage information corresponding to the zero-sequence voltage to be injected, based on the three-phase voltage reference wave at that moment, includes the following steps:

[0096] Based on the three-phase voltage reference wave at that moment, the frequency corresponding to the zero-sequence voltage to be injected is determined to be three times the output frequency, and the corresponding waveform is a sine wave. In this embodiment, since the moment when the common-mode voltage amplitude is at its maximum coincides with the peak value of the three-phase voltage reference wave, the zero-sequence voltage frequency is chosen to be three times the output frequency, and the waveform is defined as a sine wave. Therefore, the injected zero-sequence voltage V... z and the three-phase voltage reference wave V′ after injection refx It can be represented as, where m z Zero-sequence voltage amplitude:

[0097] V′ refx =V refx +V z

[0098] V z =m z sin(3×2πf ac t)

[0099] According to the preset zero-sequence voltage amplitude calculation formula, the corresponding zero-sequence voltage amplitude is calculated. In this embodiment, since the common-mode voltage is large in states 1, 2, 3, and 4, the above states can be removed by injecting zero-sequence voltage. The magnitude of the injected amplitude is the distance between the intersection of the two-phase voltage reference waves and 2 / 3 of the distance.

[0100] The preset formula for calculating the zero-sequence voltage amplitude is as follows:

[0101]

[0102] like Figure 4 The figure shown is a reference waveform before and after the injection of zero-sequence voltage.

[0103] Common-mode power supply suppression is achieved by injecting zero-sequence voltage, which, compared to the traditional PS-PWM modulation method, can achieve m a When the common-mode voltage is [0.45, 0.74] and [0.87, 1.00], it will suppress the common-mode voltage to [-V]. dc / 18,V dc / 18], the same can be done in m a When the common-mode voltage is [0.74, 0.87], it will be suppressed to [-V]. dc / 6,V dc / 6], and it will not affect output performance. To better illustrate the effect, such as Figure 5 As shown, m a=0.9, experimental waveforms before and after zero-sequence voltage injection. The experimental results show that the method disclosed in this embodiment for suppressing common-mode power supply by injecting zero-sequence voltage has a good common-mode voltage suppression effect.

[0104] S5. Based on the basic voltage information corresponding to the zero-sequence voltage to be injected, input the corresponding zero-sequence voltage and suppress the common-mode voltage.

[0105] The above descriptions are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, based on the guidance provided in this application, improve and implement this solution in combination with their own capabilities. Some typical well-known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A method for determining and suppressing common-mode voltage in a hybrid multilevel converter, characterized in that: Includes the following steps: S1. Based on the hybrid multilevel converter, define the region to which the three-phase voltage reference wave of the hybrid multilevel converter belongs at a certain moment; the definition formula is: In the formula, The modulation ratio is within a certain range. ; For output frequency; S2. Based on the defined region to which the three-phase voltage reference wave belongs, and using a preset state determination strategy, determine the state of the three-phase voltage reference wave at that moment; the preset state determination strategy is: Based on the preset flag judgment logic, determine Mutually, Mutually, Each phase corresponds to a specific flag bit; The preset flag determination logic is as follows: like If it is, then it is defined as being in the "lower" region, and the flag is incremented by 1. like If it is, then it is defined as being in the "middle" region, and the flag is incremented by 0. like If it is, then it is defined as being in the "upper" region, and the flag is incremented by 2. Will Mutually, Mutually, The flag bits corresponding to each phase are added together, and based on the preset state judgment logic, the state of the three-phase voltage reference wave at that moment is obtained during the change of the three-phase voltage reference wave. The preset state judgment logic is as follows: The sum of the flag bits equals 5, indicating state 1: "Up" "Up" "Down"; at this time, the common-mode voltage is... ; The sum of the flag bits equals 4, indicating state 2: "Down" "Down" "Up"; at this time, the common-mode voltage is... ; The sum of the flag bits equals 2, placing it in state 3: "Middle" "Middle" "Up"; at this time, the common-mode voltage is... ; The sum of the flag bits equals 1, indicating state 4: "Middle" "Middle" "Down"; at this time, the common-mode voltage is... ; The sum of the flag bits equals 0, indicating state 5: "Middle" "Middle" "Middle"; at this time, the common-mode voltage is... ; The sum of the flag bits equals 3, placing it in state 6: "Up", "Middle", "Down". If the sum of the voltage reference waveforms in the "Up" state and the "Middle" state is greater than 4 / 3, and the sum of the voltage reference waveforms in the "Down" state and the "Middle" state is greater than 2 / 3, then the common-mode voltage is... ; If the sum of the voltage reference wave in the "upper" state and the voltage reference wave in the "middle" state is less than or equal to 4 / 3, and the sum of the voltage reference wave in the "lower" state and the voltage reference wave in the "middle" state is less than or equal to 2 / 3, then the common-mode voltage is: ; If the sum of the voltage reference waveform in the "upper" state and the voltage reference waveform in the "middle" state is greater than 4 / 3, or if the sum of the voltage reference waveform in the "lower" state and the voltage reference waveform in the "middle" state is greater than 2 / 3, then the common-mode voltage is: ; S3. Based on the determined state of the three-phase voltage reference wave at that moment, and based on the preset correlation table between the state of the three-phase voltage reference wave and the common-mode voltage, determine the common-mode voltage amplitude corresponding to the state of the three-phase voltage reference wave at that moment. S4. Based on the three-phase voltage reference wave corresponding to this moment, determine the basic voltage information corresponding to the zero-sequence voltage to be injected. The basic voltage information includes the voltage frequency, waveform, and voltage amplitude of the zero-sequence voltage. S5. Based on the basic voltage information corresponding to the zero-sequence voltage to be injected, input the corresponding zero-sequence voltage and suppress the common-mode voltage.

2. The method for determining and suppressing common-mode voltage of a hybrid multilevel converter according to claim 1, characterized in that: The hybrid multilevel converter includes Mutually, Mutually, Phase, and DC side and load side; the Mutually, Mutually, Parallel connection configuration; Mutually, Mutually, Each phase includes four bridge arms and a flying capacitor. ; The DC side includes a DC voltage source. 3 DC bus capacitors First capacitor Second capacitor ; The three DC bus capacitors With DC voltage source The first capacitor is connected in series. Second capacitor Series connection with 3 DC bus capacitors Parallel connection; the first capacitor Second capacitor A first neutral point is set between them. ; The four bridge arms include four sets of switching devices, namely: , , , ; The The first terminal is connected to the DC bus capacitor. The positive terminal is connected to the first terminal, and the second terminal is connected to the second terminal. The first end and The second end; the The first end is also with The first end is connected to the second end, and the second end is connected to the DC bus capacitor. The negative electrode; the Second end connection The first end; the The first end is connected to the DC bus capacitor. The positive terminal, the second terminal connected The first end and The first end; the The second end is connected to the DC bus capacitor. The negative electrode; the Second end connection The first end; the The second end and the The second end of each is connected to the load side; The The second end and The first end is connected to a flying capacitor. The positive electrode, the The second end and The first end is connected to a flying capacitor. The negative electrode.

3. The method for determining and suppressing common-mode voltage of a hybrid multilevel converter according to claim 2, characterized in that: The load side includes an inductor and a resistor; the first end of the inductor is connected to... The second end and the The second end of the inductor is connected to the first end of the resistor. Mutually, Mutually, The second ends of the resistors corresponding to the phases are connected to each other, and the second ends of the resistors are provided with a second neutral point. .

4. The method for determining and suppressing common-mode voltage of a hybrid multilevel converter according to claim 3, characterized in that: The determination of the basic voltage information corresponding to the zero-sequence voltage to be injected, based on the three-phase voltage reference wave at that moment, includes the following steps: Based on the three-phase voltage reference wave corresponding to that moment, the frequency of the zero-sequence voltage to be injected is determined to be three times the output frequency, and the corresponding waveform is a sine wave. The corresponding zero-sequence voltage amplitude is calculated according to the preset zero-sequence voltage amplitude calculation formula; the preset zero-sequence voltage amplitude calculation formula is as follows: .

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