Memory and electronic device

Abstract

The present disclosure relates to a memory and an electronic device for improving the reliability of the memory. The memory includes a multi-layer array of memory cells stacked along a vertical substrate direction, the array of memory cells including a plurality of memory cells arranged along a first direction and a second direction parallel to the substrate, the first direction and the second direction intersecting, the memory cell including at least one transistor, an isolation shielding structure penetrating through the array of memory cells in each layer and located between two transistors of two memory cells adjacent along the second direction, the isolation shielding structure including an isolation layer and a conductive shielding layer, the isolation layer penetrating through the array of memory cells in each layer and located at least between channel regions of the two transistors in each layer of the array of memory cells, the conductive shielding layer penetrating through the array of memory cells in each layer and insulated from the two transistors by the isolation layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and electronic device. Background Technology

[0002] Memory in semiconductor devices typically comprises memory cells. For example, each memory cell includes at least one transistor, such as a 1T1C or 2T memory cell. As memory integration increases and cell size shrinks further, signal interference between cells increases, which negatively impacts memory reliability. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure provide a memory and an electronic device that help improve the reliability of the memory.

[0004] According to some embodiments, this disclosure provides a memory, including:

[0005] A multilayer memory cell array is stacked along a direction perpendicular to the substrate. The memory cell array includes multiple memory cells arranged along a first direction and a second direction parallel to the substrate. The first direction and the second direction intersect. Each memory cell contains at least one transistor.

[0006] An isolation shielding structure extends through each layer of the memory cell array and is located between two transistors of two adjacent memory cells along the second direction; the isolation shielding structure includes an isolation layer and a conductive shielding layer.

[0007] The isolation layer extends through each layer of the memory cell array and is located at least between the channel regions of two transistors in each layer of the memory cell array;

[0008] The conductive shielding layer extends through each layer of the memory cell array and is insulated from the two transistors by the isolation layer.

[0009] In some embodiments, it further includes: a reference electrode located between the substrate and each of the memory cell arrays, the reference electrode extending on the substrate; wherein,

[0010] The conductive shielding layer, extending toward the substrate, extends to and is electrically connected to the reference electrode, which is connected to a voltage terminal that can provide a constant potential.

[0011] In some embodiments, the isolation shielding structures include a plurality of isolation shielding structures located between different memory cells of the memory cell array, each of the isolation shielding structures extending toward the substrate and connected to the same reference electrode.

[0012] In some embodiments, the memory cell includes a first transistor, the first transistor including an annular first semiconductor layer extending in a direction perpendicular to the substrate; the memory also includes: a plurality of first bit lines;

[0013] Each of the first bit lines extends in the second direction and is electrically connected to the sidewall of each of the first semiconductor layers in the corresponding column of the memory cells;

[0014] The isolation shielding structure is located between the outer walls of two adjacent first semiconductor layers in a column of memory cells, and extends in a first direction to the sidewall of the bit line.

[0015] In some embodiments, it also includes: a plurality of first word lines;

[0016] The first word line extends along a direction perpendicular to the substrate; the first semiconductor layer surrounds the outer wall of the first word line;

[0017] The outer wall of the first semiconductor layer is in contact with the isolation layer, and the isolation layer is in contact with the conductive shielding layer.

[0018] In some embodiments, the storage unit further includes: a capacitor;

[0019] The capacitor includes: a first electrode electrically connected to the first semiconductor layer, and a dielectric layer and a second electrode sequentially disposed on the side of the first electrode opposite to the first semiconductor layer;

[0020] The first bit line, the first semiconductor layer, and the first electrode are arranged sequentially in the first direction;

[0021] The isolation shielding structure extends in a first direction from one end near the first bit line to between two adjacent first electrodes.

[0022] In some embodiments, the memory cell further includes: a second transistor electrically connected to the memory node; the second transistor includes an annular second semiconductor layer extending in a direction perpendicular to the substrate and disposed insulated from the memory node; the memory further includes: a plurality of second bit lines; wherein,

[0023] The second bit line extends along the second direction in a plane parallel to the substrate and is electrically connected to the second semiconductor layer in the corresponding column of the memory cell; the first bit line, the first transistor of the memory cell, the memory node, the second transistor and the second bit line are arranged sequentially in the first direction;

[0024] The isolation shielding structure extends from the first bit line to the storage node and is located between two adjacent storage nodes along the second direction.

[0025] In some embodiments, the storage node is the main gate of the second transistor, or,

[0026] The second transistor further includes a main gate and a back gate. The main gate is located within a via surrounding the second semiconductor layer and is insulated from the second bit line, and is connected to the second word line. The memory node is the back gate of the second transistor.

[0027] In some embodiments, the isolation shielding structure extends in a first direction from one end near the first bit line between two adjacent memory nodes.

[0028] In some embodiments, the isolation layer is a hollow annular film extending toward the substrate, and the conductive shielding layer is located within the hollow annular film.

[0029] According to some embodiments, another aspect of this disclosure provides an electronic device including the memory as described above.

[0030] The embodiments disclosed herein may have, or at least have, the following advantages:

[0031] In this embodiment, an isolation shielding structure penetrating the memory cell array is provided between two transistors in two adjacent memory cells along a second direction. This isolation shielding structure includes: an isolation layer penetrating at least the channel regions of the two transistors in each memory cell array, and a conductive shielding layer penetrating the memory cell array, located within the isolation layer, and insulated from the two transistors by the isolation layer. Therefore, the isolation shielding structure in this embodiment can effectively reduce the signal interference between transistor channels in adjacent memory cells. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a memory provided in some embodiments; wherein, Figure 1 Figure (a) in the diagram is a top view of the memory structure shown. Figure 1 Figure (b) is Figure 1 (a) Figure 1 A cross-sectional view of the structure along the AA direction. Figure 1 Figure (c) is Figure 1 (a) Figure 1A cross-sectional view of the structure along the BB direction;

[0034] Figure 2 for Figure 1 The diagram shows the equivalent circuit of a storage cell in the memory.

[0035] Figure 3 for Figure 1 The diagram shows a comparison of the equivalent circuit principles of the memory before and after the isolation shielding structure is installed; among them, Figure 3 Figure (a) in the middle is Figure 1 The diagram shown is the equivalent circuit schematic before the memory is equipped with an isolation shielding structure. Figure 3 Figure (b) is Figure 1 The diagram shows the equivalent circuit schematic of the memory after an isolation and shielding structure has been set.

[0036] Figure 4 This is a schematic diagram of another memory structure provided in some embodiments; wherein, Figure 4 Figure (a) in the diagram is a top view of the memory structure shown. Figure 4 Figure (b) is Figure 4 (a) Figure 1 A cross-sectional view of the structure along the AA direction. Figure 4 Figure (c) is Figure 4 (a) Figure 1 A cross-sectional structural diagram along the BB direction. Figure 4 Figure (d) in the middle is Figure 4 (a) Figure 1 A cross-sectional view of the structure along the CC direction;

[0037] Figure 5 for Figure 4 The diagram shows the equivalent circuit of a storage cell in the memory.

[0038] Figure 6 for Figure 4 The diagram shows a comparison of the equivalent circuit principles of the memory before and after the isolation shielding structure is installed; among them, Figure 6 Figure (a) in the middle is Figure 4 The diagram shown is the equivalent circuit schematic before the memory is equipped with an isolation shielding structure. Figure 6 Figure (b) is Figure 4 The diagram shows the equivalent circuit schematic of the memory after an isolation and shielding structure has been set.

[0039] Figure 7 This is a schematic diagram of another memory structure provided in some embodiments; wherein, Figure 7 Figure (a) in the diagram is a top view of the memory structure shown. Figure 7 Figure (b) is Figure 7 (a) Figure 1 A cross-sectional view of the structure along the AA direction. Figure 7 Figure (c) is Figure 7 (a) Figure 1 A cross-sectional structural diagram along the BB direction. Figure 7 Figure (d) in the middle is Figure 7 (a) Figure 1 A cross-sectional view of the structure along the CC direction;

[0040] Figure 8 for Figure 7 The diagram shows the equivalent circuit of a memory cell with an n-type read transistor in the memory.

[0041] Figure 9 for Figure 7 The diagram shows a comparison of the equivalent circuit principles of the memory before and after the isolation shielding structure is installed; among them, Figure 9 Figure (a) in the middle is Figure 7 The diagram shown is the equivalent circuit schematic before the memory is equipped with an isolation shielding structure. Figure 9 Figure (b) is Figure 7 The diagram shows the equivalent circuit schematic after the memory is equipped with an isolation and shielding structure. Attached image description:

[0043] U - memory cell, T1 - first transistor, T2 - second transistor, C1 - capacitor, C2 - voltage regulating capacitor, BL and WBL - first bit line, RBL - second bit line, WL and WWL - first word line, RWL - second word line, GND - ground line, SN - memory node, S1 - middle area, S2 - bend area;

[0044] 1-Substrate, 2-Isolation shielding structure, 21-Isolation layer, 22-Conductive shielding layer, 3-Reference electrode, 41-First semiconductor layer, 42-First gate dielectric layer, 51-First isolation structure, 52-Second isolation structure, 53-Third isolation structure, 61-First electrode, 62-Dielectric layer, 63-Second electrode, 71-Second semiconductor layer, 72-Second gate dielectric layer, 73-Third gate dielectric layer, 81-First dielectric layer, 82-Second dielectric layer. Detailed Implementation

[0045] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0047] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0050] Currently, with the rapid development of integrated circuit manufacturing processes, the physical distance between devices is becoming smaller and smaller. This makes it easier for signal interference to occur between adjacent memory cells. For example, signal interference can easily occur between the channels of transistors in two adjacent memory cells, or between the capacitors in two adjacent 1T1C memory cells, or between the storage nodes (SNs) in two adjacent 2T memory cells. These types of interference can easily affect the reliability of the memory.

[0051] In 2T storage cell applications, when the storage cells in the memory are in standby mode, the storage nodes are in a floating state. The capacitive coupling between the storage nodes and the storage nodes of other storage cells can easily affect the capacitance of the storage nodes, thereby affecting the reliability of the memory.

[0052] Based on this, embodiments of the present disclosure provide a memory that helps improve the reliability of a two-dimensional or three-dimensional memory cell array.

[0053] The following uses a three-dimensional storage cell array as an example to illustrate this application.

[0054] Please see Figure 1 and Figure 2 In some embodiments, the memory includes a multi-layer memory cell array and multiple isolation shielding structures 2.

[0055] For example, a multilayer memory cell array is stacked along a direction perpendicular to the substrate 1 (e.g., the Z direction). The memory cell array includes multiple memory cells U arranged in rows along a first direction parallel to the substrate 1 (e.g., the X direction) and in columns along a second direction parallel to the substrate 1 (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect, for example, orthogonal. That is, the multiple memory cells U can be arrayed in a plane parallel to the substrate 1 and periodically stacked from bottom to top along the direction perpendicular to the substrate 1 to obtain a three-dimensional memory.

[0056] Exemplarily, substrate 1 is a supporting substrate, which has at least one base, such as a silicon substrate. Whether other functional devices are mounted on this base is not limited in this application. For example, substrate 1 may comprise a substrate composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 1 can be a single-layer structure or a multi-layer structure. For example, substrate 1 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0057] For example, the storage unit U can be a 1T or 2T storage unit, and whether the storage unit also has a capacitor is not specifically limited in this application. For example, the storage unit can be a 1T1C storage unit or a 2T0C storage unit.

[0058] In some embodiments, please continue reading Figure 1 and Figure 2 The memory cell U adopts a 1T1C structure, including a first transistor T1 and a capacitor C1 electrically connected. An isolation shielding structure 2 is located between the two first transistors T1 of two adjacent memory cells U along a second direction (e.g., the Y direction). The isolation shielding structure 2 includes an isolation layer 21 and a conductive shielding layer 22. The isolation layer 21 extends through each layer of the memory cell array and is located at least between the channel regions of two adjacent first transistors T1 in each layer of the memory cell array. The conductive shielding layer 22 extends through each layer of the memory cell array and is insulated from the two transistors through the isolation layer.

[0059] In some embodiments, the conductive shielding layer 22 has a constant potential to shield signal interference between memory cells.

[0060] In some embodiments, the conductive shielding layer 22 can be provided with a constant potential by a voltage terminal to shield interference signals.

[0061] The conductive shielding layer 22 can be insulated from the two transistors by two separate insulating layers, or by a single insulating layer. The two insulating layers can be made of the same material or different materials.

[0062] For example, the isolation layer is a hollow annular film extending toward the substrate, and the conductive shielding layer 22 is located inside the hollow annular film. In this case, the isolation layer is a single isolation layer that is simultaneously insulated from two transistors.

[0063] In some embodiments, two adjacent memory cells U in the second direction (column direction) are connected to the same bit line or to different bit lines.

[0064] For example, the isolation layer 21 is formed of an insulating material, such as a low-K dielectric layer like silicon oxide.

[0065] For example, the conductive shielding layer 22 is formed of a conductive material, such as a metallic material or a doped semiconductor material (e.g., conductive polycrystalline silicon).

[0066] For example, the isolation layer is a hollow annular film extending toward the substrate. This can be understood as the isolation layer 21 having holes or gaps extending toward the substrate, which are located on the upper and lower surfaces of the isolation layer 21 relative to the substrate. For example, when the isolation layer 21 is an annular film, the isolation layer 21 may have holes that penetrate through each layer of the memory cell array. Alternatively, for example, when the isolation layer 21 is a block structure extending along the row direction (e.g., the X direction), its holes may be provided on the side surfaces between the main surfaces; and it is also permissible for the block structure to be located only between two adjacent memory cells U or between two adjacent rows of memory cells U.

[0067] For example, the isolation layer 21 can be formed with vias or gaps on the insulating layer between the semiconductor layers. Furthermore, the isolation layer 21 contacts the channel region of the first transistor T1, and the conductive shielding layer within the via or gap completely covers the channel regions of both transistors to achieve better signal shielding.

[0068] In some examples, please combine Figure 1 As understood from Figures (a) and (b), the memory also includes: a plurality of first word lines WL. The first word lines WL are linear structures extending along a direction perpendicular to the substrate 1 (e.g., the Z direction). The first transistor T1 includes: a first semiconductor layer 41 insulatingly surrounding the first word lines WL. That is, the first semiconductor layer 41 may be annular and extend along a direction perpendicular to the substrate 1 (e.g., the Z direction), and a first gate dielectric layer 42 may be disposed between the first semiconductor layer 41 and the first word lines WL. The capacitor C1 includes: a first electrode 61 electrically connected to the first semiconductor layer 41, and a dielectric layer 62 and a second electrode 63 sequentially disposed on the side of the first electrode 61 facing away from the first semiconductor layer 41.

[0069] Therefore, in this embodiment of the present disclosure, an isolation shielding structure 2 that penetrates through each layer of the memory cell array is provided between the two first transistors T1 of two adjacent memory cells U along the second direction (e.g., the Y direction). In conjunction with the aforementioned description of the isolation shielding structure 2, the isolation shielding structure 2 in this embodiment of the present disclosure can effectively reduce signal interference between the channel regions (i.e., the first semiconductor layer 41) between the two first transistors T1 in adjacent memory cells U, thereby improving the reliability of the memory.

[0070] In some embodiments, please refer to Figure 1 In Figure (c), the memory further includes a reference electrode 3 configured to provide a constant potential to the conductive shielding layer 22. The reference electrode 3 may be located at the top or bottom of each memory cell array. When the reference electrode 3 is located at the bottom of each memory cell array, it may be located on the substrate 1. The number of reference electrodes 3 may be at least one. The conductive shielding layer 22 extends in a direction toward the substrate 1, and the reference electrode 3 extends on the substrate. The conductive shielding layer 22 extends to and is electrically connected to the reference electrode 3.

[0071] In some embodiments, please combine Figure 1 As understood from Figures (b) and (c), there are multiple isolation shielding structures 2, each located between adjacent first transistors T1 at different positions. For example, in memory cells connected by a bit line, an isolation shielding structure 2 is disposed between the transistors of any two adjacent memory cells.

[0072] The conductive shielding layer 22 in each isolation shielding structure 2 is electrically connected to the same reference electrode 3. That is, the conductive shielding layer 22 of each isolation shielding structure 2 in the memory can share the same reference electrode 3. The same reference electrode 3 can be a planar common electrode or a common electrode integrally connected in a grid pattern.

[0073] For example, reference electrode 3 is a ground electrode and is connected to a ground terminal. This ground electrode can also be connected to the ground electrode of the capacitor in the 1T1C of the storage cell U. For example, in the 1T1C storage cell U, the outer plate of the capacitor (i.e., the second electrode 63) is connected to the reference electrode 3.

[0074] It should be added that, in the example where reference electrode 3 is a ground electrode, this ground electrode can also be electrically connected to other components in the memory that require grounding.

[0075] It is worth mentioning that, in some embodiments, the memory further includes: a voltage terminal electrically connected to the reference electrode 3. Figure 1 (Not shown in the image). The voltage terminal refers to the voltage terminal that can provide a constant voltage, but the voltage value output to the storage cell can be adjusted as needed. The reference electrode 3 is adjusted to provide different constant potentials to tune the threshold voltage Vth of the first transistor T1. In this way, by adjusting the constant potential of the reference electrode 3 through the voltage terminal, it is beneficial to regulate the threshold voltage Vth of the first transistor T1, ensuring that the threshold voltage of the transistor operates within the normal range.

[0076] In some embodiments, please continue reading Figure 1 The memory also includes a plurality of first bit lines BL and a plurality of first isolation structures 51. Each first bit line BL extends in a plane parallel to the substrate 1 along a second direction (e.g., the Y direction) and is electrically connected to the sidewall of each first semiconductor layer 41 in the corresponding column memory cell U. Each first isolation structure 51 is located between the outer sidewalls of two adjacent first semiconductor layers 41 in a column memory cell U and extends to the first bit line BL, which is isolated from the first bit line by an insulating layer.

[0077] For example, such as Figure 1 As shown, every two adjacent memory cells U along the row direction (e.g., the X direction) are mirror-symmetric with respect to the first isolation structure 51. For example, along the direction away from the first isolation structure 51, the capacitor C1 in the memory cell U is located on the side of the corresponding first transistor T1 away from the first bit line BL.

[0078] For example, please refer to Figure 1The capacitor C1 can be obtained by first laterally etching the target layer material to form a capacitor pre-placement trench, and then sequentially forming the first electrode 61, dielectric layer 62, and second electrode 63 within the capacitor pre-placement trench. Accordingly, in two adjacent memory cells U located on the same side of the first isolation structure 51 along the row direction (e.g., the X direction), the second electrode 63 of the capacitor C1 is electrically connected as a single structure, and the two adjacent memory cells U located on the same side of the first isolation structure 51 along the row direction (e.g., the X direction) can share the same isolation shielding structure 2, which helps to simplify the structure and fabrication process of the memory.

[0079] For example, the first line BL, the first semiconductor layer 41, and the first electrode 61 are arranged sequentially in a first direction (e.g., the X direction). The isolation shielding structure 2 extends from the first line BL to the first electrode 61 and is located between two adjacent first electrodes 61 in a second direction (e.g., the Y direction).

[0080] Based on the above, regarding Figure 1 The memory shown, Figure 3 The diagram shows a comparison of the equivalent circuit principles before and after the isolation shielding structure 2 is installed in the memory; where, for example... Figure 3 As shown in Figure (a), before the memory is equipped with the isolation shielding structure 2, there may be parasitic capacitance between the first semiconductor layer 41 of the two first transistors T1 of adjacent memory cells U connected by the same bit line, resulting in signal interference. Figure 3 In Figure (a), the dashed line below the gate of the transistor represents the location of the channel, and the area between the two dashed lines indicates parasitic capacitance. Figure 3 (b) and Figure 6 The dashed line below the gate in the diagram has a similar meaning; it does not represent logic circuitry but rather an indicator line. For example... Figure 3 As shown in Figure (b), after the isolation shielding structure 2 is set in the memory, the exposed sidewalls of the first semiconductor layers 41 of the two first transistors T1 of adjacent memory cells U can form a parasitic capacitance with the isolation shielding structure 2 with an external fixed voltage (i.e. a constant potential), thereby improving the reliability of the memory and ensuring that at least the channel region of the first transistor T1 is not affected by changes in external signals, thereby ensuring the stability of the performance parameters of the first transistor T1, such as ensuring the stability of the threshold voltage of the first transistor T1.

[0081] In other embodiments, please refer to Figures 4-9The memory cell U adopts a 2T0C structure, including a first transistor T1 and a second transistor T2 electrically connected to the first transistor T1 and the memory node SN. The second transistor T2 includes an annular second semiconductor layer 71 extending along a direction perpendicular to the substrate 1 (e.g., the Z direction) and disposed insulated from the memory node SN. An isolation shielding structure 2 is located between two adjacent memory cells U along a second direction (e.g., the Y direction). For example, the first transistor T1 and the second transistor T2 in any memory cell U are arranged in a first direction (e.g., the X direction), and the isolation shielding structure 2 is located between corresponding two first transistors T1 and between corresponding two second transistors T2, respectively. The isolation shielding structure 2 includes an isolation layer 21 and a conductive shielding layer 22. The isolation layer 21 is located at least between the channel regions of two adjacent first transistors T1 in each layer of the memory cell array. The conductive shielding layer 22 is located in the isolation layer 21 and is insulated from each transistor in the two adjacent memory cells U through the isolation layer 21.

[0082] In some embodiments, the conductive shielding layer has a constant potential to shield against signal interference.

[0083] For example, the first transistor T1 is a write transistor and the second transistor T2 is a read transistor.

[0084] In some examples, please combine Figure 4 Figure (d) in the middle and Figure 5 It is understood that the storage node SN is the main gate of the second transistor T2. The storage node SN is in contact with the sidewall of the first semiconductor layer 41 in the first transistor T1 and is insulated by the second gate dielectric layer 72 and the second semiconductor layer 71 of the second transistor T2.

[0085] In other examples, please combine Figure 7 Figure (d) in the middle and Figure 8 Understanding that memory node SN is the back gate of the second transistor T2, the dashed line connecting SN in the diagram signifies the back gate. Memory node SN is in contact with the sidewall of the first semiconductor layer 41 in the first transistor T1 and is insulated from the second semiconductor layer 71 of the second transistor T2 through the second gate dielectric layer 72. The second transistor T2 also includes a main gate, which is located within a via surrounding the second semiconductor layer 71 and is insulated from the second bit line RBL, and connected to the second word line RWL. The main gate of the second transistor T2 may, for example, be an integral structure with the second word line RWL and is insulated from the second semiconductor layer 71 of the second transistor T2 through the third gate dielectric layer 73.

[0086] In some embodiments, please refer to Figures 4-9The memory also includes: multiple first bit lines WBL, multiple first isolation structures 51, multiple second bit lines RBL, and multiple second isolation structures 52. The first bit lines WBL and RBL extend along a second direction (e.g., the Y direction) in a plane parallel to the substrate 1. The first bit lines WBL are electrically connected to the sidewalls of the first semiconductor layers 41 in the corresponding column memory cells U, and the second bit lines RBL are electrically connected to the sidewalls of the second semiconductor layers 71 in the corresponding column memory cells U. The memory cells U are located within the interval between the first bit lines WBL and the second bit lines RBL.

[0087] For example, such as Figures 4-9 As shown, the first isolation structure 51 and the second isolation structure 52 extend along a second direction (e.g., the Y direction). Each first isolation structure 51 is located between the outer walls of two adjacent first semiconductor layers 41 in a column of memory cells, extending in the first direction to the first bit line WBL and isolated from the first bit line by an insulating layer. Each pair of adjacent memory cells U along the row direction (e.g., the X direction) can be mirror-symmetrical about the first isolation structure 51 or the second isolation structure 52. For example, each pair of adjacent memory cells U along the row direction (e.g., the X direction) can be mirror-symmetrical about the first isolation structure 51, and along a direction away from the first isolation structure 51, the second transistor T2 in memory cell U is located on the side of the corresponding first transistor T1 away from the first bit line WBL.

[0088] Accordingly, such as Figures 4-9 As shown, a column of memory cells U is electrically connected to a first bit line WBL and a second bit line RBL, respectively. A first isolation structure 51 is located between the two first bit lines WBL electrically connected to adjacent columns of memory cells U and covers the sidewall of the first bit line WBL. A second isolation structure 52 is located between the two second bit lines RBL electrically connected to adjacent columns of memory cells U and covers the sidewall of the second bit line RBL. An isolation shielding structure 2 is located on the side of the first bit line WBL away from the first isolation structure 51, on the side of the second bit line RBL away from the second isolation structure 52, between two adjacent first semiconductor layers 41 along the second direction (e.g., the Y direction), and between two adjacent memory nodes SN along the second direction (e.g., the Y direction). That is, the first bit line WBL, the first transistor T1, the memory node SN, the second transistor T2, and the second bit line RBL can be arranged sequentially in the first direction (e.g., the X direction). The isolation shielding structure 2 extends from the first bit line WBL to the memory node SN and is located between two adjacent memory nodes SN along the second direction (e.g., the Y direction).

[0089] For example, the first semiconductor layer 41 in the first transistor T1 is a fully encircling semiconductor layer. The second semiconductor layer 71 in the second transistor T2 has openings in its sidewalls. The second bit line RBL is connected to the opening region of the second semiconductor layer 71. For example, the second bit line RBL can be connected to a third isolation structure 53 within the opening region of the second semiconductor layer 71 (e.g., Figure 4 (as shown in the diagram); or, for example, the second bit line RBL can be connected to the third gate dielectric layer 73 covering the second word line RWL within the opening region of the second semiconductor layer 71 (as shown in the diagram); Figure 7 (as shown in the image).

[0090] In some embodiments, the same as the aforementioned embodiment where the storage unit U is a 1T1C structure, please refer to... Figure 4 Figure (c) in the middle and Figure 7 In Figure (c), the memory further includes at least one reference electrode 3 located between the substrate 1 and the memory cell array. A conductive shielding layer 22 extends in a direction perpendicular to the substrate 1, and the reference electrode 3 extends in a direction parallel to the substrate 1. The conductive shielding layer 22 in the isolation shielding structure 2 extends to and is electrically connected to the reference electrode 3, which is configured to provide a constant potential to the conductive shielding layer 22.

[0091] For example, such as Figure 4 Figure (c) in the middle and Figure 7 As shown in Figure (c), there are multiple isolation shielding structures 2, located between transistors at different positions. The conductive shielding layer 22 in each isolation shielding structure 2 is electrically connected to the same reference electrode 3. That is, the conductive shielding layer 22 of each isolation shielding structure 2 in the memory can share the same reference electrode 3. The same reference electrode 3 can be a planar common electrode or a common electrode integrally connected in a mesh pattern.

[0092] For example, reference electrode 3 is a ground electrode. Furthermore, in some examples, this ground electrode may also be electrically connected to other components in the memory that require a ground connection.

[0093] It is worth mentioning that, in some embodiments, the memory further includes: a voltage terminal electrically connected to the reference electrode 3. Figures 4-9 (Not shown in the diagram). The voltage terminal is configured to adjust the reference electrode 3 to provide different constant potentials corresponding to the threshold voltage of the first transistor T1. Thus, by adjusting the constant potential of the reference electrode 3 through the voltage terminal, the threshold voltage Vth of the first transistor T1 in the memory cell U is controlled.

[0094] It should be added that, Figure 4 and Figure 7Two different 2T0C structures of memory cell U are shown. It is understood that, depending on the different internal components and connections of the memory cell U, the structure of the memory cell U is not limited to the descriptions in the foregoing embodiments, and there can be other variations and applications. This disclosure does not limit these aspects.

[0095] Therefore, in this embodiment of the present disclosure, an isolation shielding structure 2 is provided between two adjacent memory cells U along the second direction (e.g., the Y direction). Referring to the aforementioned description of the isolation shielding structure 2, a portion of the isolation shielding structure 2 is located between two adjacent first semiconductor layers 41 along the second direction (e.g., the Y direction). This not only helps to shield the first semiconductor layer 41 (i.e., the channel of the first transistor T1) from external signals through the isolation shielding structure 2, but also effectively improves the performance and reliability of the first transistor T1 by adjusting the threshold voltage Vth of the first transistor T1 through the control of the constant potential provided by the reference electrode 3. The other portion of the isolation shielding structure 2 is located between two adjacent memory nodes SN along the second direction (e.g., the Y direction). While ensuring the isolation effect between adjacent memory nodes SN, the isolation shielding structure 2 effectively reduces the coupling effect between adjacent memory nodes SN, thereby improving the stability of the memory nodes SN. Thus, this embodiment of the present disclosure can effectively reduce the influence of external signals (e.g., adjacent memory cells U) on memory cells U, and correspondingly improve the performance and stability of the first transistor T1, thereby improving the performance and reliability of the memory. This embodiment of the present disclosure is particularly applicable to the standby state of memory cells in a memory.

[0096] In some embodiments, the structure of the storage unit U is as follows: Figure 4 The memory further includes: multiple first word lines (WWL), multiple second word lines (RWL), and multiple third isolation structures (53). Please refer to... Figure 4 and Figure 5 Understanding that both the first word line WWL and the second word line RWL extend along a direction perpendicular to the substrate 1 (e.g., the Z direction). A first semiconductor layer 41 insulatingly surrounds the periphery of the first word line WWL, and a first gate dielectric layer 42 is disposed between the first semiconductor layer 41 and the first word line WWL. The outer sidewall of the first semiconductor layer 41 contacts the isolation layer 21, and the isolation layer 21 contacts the conductive shielding layer 22. A second semiconductor layer 71 surrounds the second word line RWL and is electrically connected to the second word line RWL. The isolation shielding structure 2 also contacts the outer sidewall of the second semiconductor layer 71. A third isolation structure 53 is located between the second word line RWL and the second bit line RBL, which are electrically connected to the corresponding memory cell U.

[0097] For example, the memory node SN includes a film layer extending along a direction perpendicular to the substrate 1 (e.g., the Z direction) and surrounding the outer wall of the second semiconductor layer 71; the isolation shielding structure extends in a first direction from one end near the first bit line between two adjacent memory nodes.

[0098] The film layer includes a central region S1 and a bent region S2 that bends along the central region S1 toward the second bit line RBL. The two sides of the central region S1 are connected to the first semiconductor layer 41 and to the second semiconductor layer 71 through a gate insulating layer (e.g., the second gate dielectric layer 72). The bent region S2 extends along a first direction (e.g., the X direction) and surrounds the two opposite sidewalls of the second semiconductor layer 71.

[0099] Accordingly, the isolation shielding structure 2 is in contact with the outer wall of the second semiconductor layer 71.

[0100] Based on the above, regarding Figure 4 The memory shown, Figure 6 The diagram shows a comparison of the equivalent circuit principles before and after the isolation shielding structure 2 is installed in the memory; where, for example... Figure 6 As shown in Figure (a), before the memory is equipped with the isolation shielding structure 2, there may be parasitic capacitance between the two memory nodes SN of adjacent memory cells U, resulting in signal interference; as Figure 6 As shown in Figure (b), after the isolation shielding structure 2 is set in the memory, the two memory nodes SN of adjacent memory cells U and the exposed sidewalls of the semiconductor layer of each transistor can form a parasitic capacitance with the isolation shielding structure 2 with a fixed external voltage (i.e. a constant potential), thereby improving the reliability of the memory, ensuring that the channel regions of each memory node SN and each transistor are not affected by changes in external signals, and thus ensuring the stability of the performance parameters of each transistor and memory node SN, especially ensuring the stability of the threshold voltage of each first transistor T1.

[0101] In other embodiments, the structure of the storage unit U is as follows: Figure 7 The memory also includes: multiple first word lines (WWL), multiple ground lines (GND), and multiple second word lines (RWL). Please refer to... Figure 7 and Figure 8Understanding that the first word line WWL, the ground line GND, and the second word line RWL all extend along a direction perpendicular to the substrate 1 (e.g., the Z direction). A first semiconductor layer 41 insulates around the periphery of the first word line WWL, and a first gate dielectric layer 42 is provided between the first semiconductor layer 41 and the first word line WWL. The outer sidewall of the first semiconductor layer 41 contacts the isolation layer 21, and the isolation layer 21 contacts the conductive shielding layer 22. A second semiconductor layer 71 surrounds the ground line GND and is electrically connected to the ground line GND. The second word line RWL is located between the ground line GND and the second bit line RBL, and is insulated from the ground line GND, the second bit line RBL, and the second semiconductor layer 71; for example, the surface of the second word line RWL is covered with a third gate dielectric layer 73. The isolation shielding structure 2 also contacts the outer sidewall of the second semiconductor layer 71.

[0102] For example, the memory node SN includes a film layer extending along a direction perpendicular to the substrate 1 (e.g., the Z direction) and surrounding the outer sidewall of the second semiconductor layer 71; the film layer includes a central region S1 and a bent region S2 that bends along the central region S1 toward the second bit line RBL. The two sides of the central region S1 are connected to the first semiconductor layer 41 and to the second semiconductor layer 71 through a gate insulating layer (e.g., the second gate dielectric layer 72). The bent region S2 extends along a first direction (e.g., the X direction) and surrounds the two opposite sidewalls of the second semiconductor layer 71.

[0103] Accordingly, the isolation shielding structure 2 is in contact with the outer wall of the second semiconductor layer 71.

[0104] For example, reference electrode 3 is a ground electrode, and ground wire GND is also electrically connected to reference electrode 3.

[0105] Based on the above, regarding Figure 7 The memory shown, Figure 9 The diagram shows a comparison of the equivalent circuit principles before and after the isolation shielding structure 2 is installed in the memory; where, for example... Figure 9 As shown in Figure (a), before the memory is equipped with the isolation shielding structure 2, there may be parasitic capacitance between the two memory nodes SN of adjacent memory cells U, resulting in signal interference; as Figure 9 As shown in Figure (b), after the isolation shielding structure 2 is set in the memory, the two memory nodes SN of adjacent memory cells U and the exposed sidewalls of the semiconductor layer of each transistor can form a parasitic capacitance with the isolation shielding structure 2 with a fixed external voltage (i.e. a constant potential), thereby improving the reliability of the memory, ensuring that the channel regions of each memory node SN and each transistor are not affected by changes in external signals, and thus ensuring the stability of the performance parameters of each transistor and memory node SN, especially ensuring the stability of the threshold voltage of each first transistor T1.

[0106] Figure 9In the diagram, the dashed line below the main gate of the read transistor represents the back gate connected to the SN. The dashed line below the gate of the write transistor does not represent any circuit structure, but rather serves as an indicator of the channel location to show the parasitic capacitance below the channel.

[0107] It should be added that, in some embodiments, in any layer of memory cell U array arranged parallel to the substrate 1, each first line BL or WBL and memory node SN can be patterned based on the same conductive material layer. Accordingly, the conductive material layer can be alternately stacked with the first dielectric layer 81 matching the distribution layer number and target layer number of memory cells U to manufacture the memory. In addition, a second dielectric layer 82 can be disposed on the surface of the top first dielectric layer 81. The second dielectric layer 82 can be, for example, a hard mask layer, to protect the underlying layer structure during the patterning of the conductive material layer and the first dielectric layer 81, and to ensure the pattern morphology after etching. The materials of the first dielectric layer 81 and the second dielectric layer 82 can be selected according to requirements.

[0108] This disclosure also provides an electronic device, such as a data storage device, a photocopier, a network device, a home appliance, an instrument, a mobile phone, or a computer, which has data storage capabilities. This electronic device may include the memory described in the foregoing embodiments. The electronic device also possesses the technical advantages of the aforementioned memory, and will not be detailed here.

[0109] In some embodiments, the electronic device includes a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. The structure of the memory can be referred to the relevant descriptions in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.

[0110] In some embodiments, external control devices such as processors or actuators coupled to the memory may also be integrated on the circuit board. For example, the electronic device also includes a processor integrated on the circuit board. The processor is coupled to the memory and is capable of controlling read and write operations on the memory.

[0111] In some embodiments, the memory may be dynamic random access memory.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A memory, characterized in that, include: A multilayer memory cell array is stacked along a direction perpendicular to the substrate. The memory cell array includes multiple memory cells arranged along a first direction and a second direction parallel to the substrate. The first direction and the second direction intersect. Each memory cell contains at least one transistor. An isolation shielding structure extends through each layer of the memory cell array and is located between two transistors of two adjacent memory cells along the second direction; the isolation shielding structure includes an isolation layer and a conductive shielding layer. The isolation layer extends through each layer of the memory cell array and is located at least between the channel regions of two transistors in each layer of the memory cell array; The conductive shielding layer extends through each layer of the memory cell array and is insulated from the two transistors by the isolation layer; the conductive shielding layer has a constant potential and is used to shield signal interference between the memory cells; The memory cell includes a first transistor, the first transistor including an annular first semiconductor layer extending along a direction perpendicular to the substrate; the memory also includes: a plurality of first bit lines; each first bit line extends in a second direction and is electrically connected to the sidewall of each first semiconductor layer in a corresponding column of memory cells; the isolation shielding structure is located between the outer sidewalls of two adjacent first semiconductor layers in a column of memory cells and extends in a first direction to the sidewall of the first bit line.

2. The memory of claim 1, wherein, Also includes: A reference electrode is located between the substrate and each of the memory cell arrays, the reference electrode extending on the substrate; wherein... The conductive shielding layer, extending toward the substrate, extends to and is electrically connected to the reference electrode, which is connected to a voltage terminal that can provide a constant potential.

3. The memory of claim 2, wherein, The device includes multiple isolation shielding structures located between different memory cells in the memory cell array, each of which extends toward the substrate and is connected to the same reference electrode.

4. The memory of claim 1, wherein, Also includes: Multiple first-letter lines; The first word line extends along a direction perpendicular to the substrate; the first semiconductor layer surrounds the outer wall of the first word line; The outer wall of the first semiconductor layer is in contact with the isolation layer, and the isolation layer is in contact with the conductive shielding layer.

5. The memory of claim 1, wherein, The storage unit further includes: a capacitor; The capacitor includes: a first electrode electrically connected to the first semiconductor layer, and a dielectric layer and a second electrode sequentially disposed on the side of the first electrode opposite to the first semiconductor layer; The first bit line, the first semiconductor layer, and the first electrode are arranged sequentially in the first direction; The isolation shielding structure extends in a first direction from one end near the first bit line to between two adjacent first electrodes.

6. The memory of claim 1, wherein, The memory cell further includes: a second transistor electrically connected to the memory node and the first transistor; the second transistor includes an annular second semiconductor layer extending in a direction perpendicular to the substrate and insulated from the memory node; the memory further includes: a plurality of second bit lines; wherein... The second bit line extends along the second direction in a plane parallel to the substrate and is electrically connected to the second semiconductor layer in the corresponding column of the memory cell; the first bit line, the first transistor of the memory cell, the memory node, the second transistor and the second bit line are arranged sequentially in the first direction; The isolation shielding structure extends from the first bit line to the storage node and is located between two adjacent storage nodes along the second direction.

7. The memory according to claim 6, characterized in that, The storage node is the main gate of the second transistor, or... The second transistor further includes a main gate and a back gate. The main gate is located within a via surrounding the second semiconductor layer and is insulated from the second bit line, and is connected to the second word line. The storage node is the back gate of the second transistor.

8. The memory of claim 6, wherein, The isolation shielding structure extends in a first direction from one end near the first bit line to between two adjacent storage nodes.

9. The memory of claim 1, wherein, The isolation layer is a hollow annular film extending toward the substrate, and the conductive shielding layer is located within the hollow annular film.

10. An electronic device, comprising: Includes the memory as described in any one of claims 1-9.

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