Semiconductor structure and method of manufacturing the same, memory, electronic device
By employing isotropic etching technology and top-down etching methods, the complex manufacturing process of stepped structures in 3D memory was solved, achieving efficient manufacturing of stepped structures and simplifying the process flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2023-12-13
- Publication Date
- 2026-06-16
Smart Images
Figure CN120152275B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the semiconductor field, and in particular to a semiconductor structure and its manufacturing method, a memory, and an electronic device. Background Technology
[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of device structures, the process has been transformed from planar to three-dimensional, that is, the arrangement of memory cells in three-dimensional space, which has become the main development direction of current memory structure research.
[0003] Currently, in 3D memory, when wiring bit lines at different heights, each layer's bit lines need to be wired individually. However, as the number of stacked layers of memory cells increases to hundreds or thousands, the number of individual wiring processes also needs to increase by hundreds or thousands, which significantly increases the complexity of the manufacturing process. Therefore, the manufacturing of staircase structures is particularly important. Summary of the Invention
[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure and its manufacturing method, a memory, and an electronic device to achieve efficient manufacturing of stepped structures.
[0005] To achieve the above objectives, in a first aspect, some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, including:
[0006] A substrate is provided, and a stacked structure is formed on one side of the substrate; the stacked structure includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers.
[0007] The stacked structure is etched along the direction perpendicular to the substrate to form etch trenches extending along the first direction.
[0008] A sacrificial material layer is formed within the etched trenches;
[0009] An isotropic etching process is used to etch the sacrificial material layer, and simultaneously, from top to bottom, each target material layer is sequentially etched along the direction parallel to the substrate to expose the sidewalls in the etching trench, so that the retained portion of each target material layer forms a first step, and multiple first steps are arranged along the second direction to form an initial stepped structure; wherein, the second direction intersects with the first direction.
[0010] Using each first step as a mask, adjacent transfer material layers are etched to form second steps corresponding to the retained portions of each transfer material layer, thus obtaining a stepped structure.
[0011] In some embodiments, the etching selectivity ratios between different target material layers and sacrificial material layers are different.
[0012] In some embodiments, the thickness of the transfer material layer is positively correlated with the width of the second step formed by the adjacent transfer material layer below it.
[0013] In some embodiments, the size of the etched trench in the second direction is negatively correlated with the step width difference between any two adjacent first steps.
[0014] In some embodiments, the method of etching the sacrificial material layer using an isotropic etching process and simultaneously etching the sidewalls of each target material layer exposed in the etching trench in a direction parallel to the substrate from top to bottom includes: symmetrically etching the sidewalls of each target material layer exposed in the etching trench on opposite sides in a second direction to form an initial stepped structure symmetrically arranged with the etching trench as the center.
[0015] In some embodiments, the sacrificial material layer includes a plurality of subselective regions spaced apart along the vertical substrate direction and corresponding one-to-one with the target material layer; wherein the etching selectivity ratios between the target material layer and the sacrificial material layers in different subselective regions are different.
[0016] In some embodiments, before forming a stacked structure on one side of the substrate, the manufacturing method further includes: forming an isolation barrier on one side of the substrate; wherein the stacked structure is formed on one side of the isolation barrier, and etched trenches expose the sidewalls of the isolation barrier facing the stacked structure.
[0017] In some embodiments, the number of stacked target material layers is greater than a first threshold; the step of etching the sacrificial material layer using an isotropic etching process, and simultaneously etching the sidewalls of each target material layer exposed in the etching trench from top to bottom along a direction parallel to the substrate, further includes:
[0018] The target material layer and the corresponding transfer material layer of the target layer number are used as etching units; the target layer number is less than or equal to the second threshold, and the second threshold is less than or equal to half of the first threshold.
[0019] The sacrificial material layer corresponding to each etching unit is etched one by one from top to bottom. After the target material layer in the etching unit is etched and the transfer material layer in the etching unit is etched to form the initial second step, the sacrificial material layer corresponding to the next etching unit is etched.
[0020] In some embodiments, the target material layer is an insulating material layer and the transfer material layer is a conductive material layer; or, the target material layer is a conductive material layer and the transfer material layer is an insulating material layer.
[0021] In some embodiments, the target material layer is an insulating material layer, and the transfer material layer is a conductive material layer; before obtaining the stepped structure, the manufacturing method further includes: using each first step as a mask to etch adjacent transfer material layers so that the retained portion of each transfer material layer forms a second step.
[0022] A first filling layer is formed in the etched trench and the removal area of each target material layer. The material of the first filling layer is the same as that of the transfer material layer. The etching of adjacent transfer material layers using each first step as a mask also includes etching the first filling layer.
[0023] In some embodiments, the method for manufacturing the semiconductor structure further includes: after obtaining the stepped structure, forming a second filling layer that covers the stepped structure and fills the etched trenches.
[0024] Secondly, according to some embodiments, this disclosure also provides a semiconductor structure, including:
[0025] Substrate.
[0026] A stacked structure, located on one side of a substrate, includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers; the stacked structure has etched trenches.
[0027] A sacrificial material layer is used to fill the etched trenches.
[0028] The target material layer is configured to form multiple first steps arranged along a second direction after etching; the transfer material layer is configured to form second steps after etching using adjacent first steps as masks, so that each first step and each second step constitutes a stepped structure.
[0029] In some embodiments, the semiconductor structure further includes: an isolation barrier located on one side of the stacked structure along a direction parallel to the substrate; wherein a sacrificial material layer is located between the isolation barrier and the stacked structure.
[0030] Thirdly, according to some embodiments, this disclosure also provides a memory including: at least one stepped structure; wherein the stepped structure is obtained by etching a semiconductor structure as described in the second aspect of the embodiments of this application; the stepped structure includes: a plurality of first steps stacked along a direction perpendicular to the substrate, and a second step located between any two adjacent first steps.
[0031] Fourthly, according to some embodiments, this disclosure also provides an electronic device, including: a memory as described in the third aspect of the embodiments of this application.
[0032] The embodiments disclosed herein may have, or at least have, the following advantages:
[0033] In this embodiment, an isotropic etching process is used to etch the sacrificial material layer, and simultaneously, from top to bottom, the sidewalls of each target material layer exposed in the etching trench are etched sequentially along the direction parallel to the substrate. Utilizing the different etching times of different target material layers in the spatial dimension, a stepped structure of multiple target material layers is formed in one step. Then, using the target material layer as a mask, adjacent transfer material layers are etched, realizing the transfer of the stepped structure between the target material layer and the corresponding transfer material layer, forming a stepped structure of the transfer material layer, thereby obtaining a stepped structure. Thus, compared to related technologies that use multiple sets of adjustment-etching cycles to create stepped partitions and multiple replication etching processes to form a stepped structure, this solution only requires a single photomask pattern definition to achieve the manufacturing of multi-layer stepped structures, thereby reducing the complexity of the process steps and achieving efficient manufacturing of stepped structures.
[0034] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure as provided in some embodiments;
[0037] Figure 2 This is a three-dimensional schematic diagram of a structure obtained after forming etched trenches, provided in some embodiments;
[0038] Figure 3 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some embodiments;
[0039] Figure 4 This is a three-dimensional schematic diagram of a structure obtained after forming the first step, provided in some embodiments;
[0040] Figure 5 This is a three-dimensional schematic diagram of a structure obtained after forming a first filling layer, provided in some embodiments;
[0041] Figure 6 This is a three-dimensional schematic diagram of a stepped structure provided in some embodiments;
[0042] Figure 7This is a three-dimensional schematic diagram of a structure obtained after forming a second filling layer, provided in some embodiments;
[0043] Figure 8 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0044] Figure 9 A flowchart illustrating a method for manufacturing a semiconductor structure as provided in some other embodiments;
[0045] Figure 10 This is a three-dimensional schematic diagram of a structure obtained after forming etched trenches, provided in some other embodiments;
[0046] Figure 11 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0047] Figure 12 This is a three-dimensional schematic diagram of the structure obtained after forming the first step, provided in some other embodiments;
[0048] Figure 13 This is a three-dimensional schematic diagram of a structure obtained after forming the first filling layer, provided in some other embodiments;
[0049] Figure 14 This is a three-dimensional schematic diagram of a stepped structure provided in some other embodiments;
[0050] Figure 15 This is a three-dimensional schematic diagram of a structure obtained after forming a second filling layer, provided in some other embodiments;
[0051] Figure 16 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0052] Figure 17 This is a three-dimensional schematic diagram of a structure obtained after forming an initial first step, provided in some embodiments;
[0053] Figure 18 This is a three-dimensional schematic diagram of a structure obtained after forming an initial second step, provided in some embodiments;
[0054] Figure 19 This is a three-dimensional schematic diagram of a structure obtained after etching to expose a transfer material layer, as provided in some embodiments;
[0055] Figure 20 This is a three-dimensional schematic diagram of a structure obtained after forming the first step, provided in some other embodiments;
[0056] Figure 21This is a three-dimensional schematic diagram of a stepped structure provided in some of the embodiments;
[0057] Figure 22 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0058] Figure 23 This is a three-dimensional schematic diagram of the structure obtained after forming the initial first step, provided in some other embodiments;
[0059] Figure 24 This is a three-dimensional schematic diagram of the structure obtained after forming the initial second step, provided in some other embodiments;
[0060] Figure 25 This is a three-dimensional schematic diagram of a structure obtained after etching to expose the transfer material layer, as provided in some other embodiments;
[0061] Figure 26 A three-dimensional schematic diagram of the structure obtained after forming the first step is provided in some other embodiments;
[0062] Figure 27 This is a three-dimensional schematic diagram of a stepped structure provided in some of the embodiments;
[0063] Figure 28 This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0064] Figure 29 This is a three-dimensional schematic diagram of a structure obtained after forming an initial first step, provided in some other embodiments;
[0065] Figure 30 This is a three-dimensional schematic diagram of a structure obtained after forming an initial second step, provided in some other embodiments;
[0066] Figure 31 This is a three-dimensional schematic diagram of a structure obtained after etching to expose the transfer material layer, as provided in some other embodiments;
[0067] Figure 32 A three-dimensional schematic diagram of the structure obtained after forming the first step is provided in some other embodiments;
[0068] Figure 33 This is a three-dimensional schematic diagram of a stepped structure provided in some of the embodiments;
[0069] Figure 34 This is a three-dimensional schematic diagram of a structure obtained after forming a second filling layer, provided in some other embodiments;
[0070] Figure 35This is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer, provided in some other embodiments;
[0071] Figure 36 This is a three-dimensional schematic diagram of a structure obtained after forming an initial first step, provided in some other embodiments;
[0072] Figure 37 This is a three-dimensional schematic diagram of a structure obtained after forming an initial second step, provided in some other embodiments;
[0073] Figure 38 This is a three-dimensional schematic diagram of a structure obtained after etching to expose the transfer material layer, as provided in some other embodiments;
[0074] Figure 39 A three-dimensional schematic diagram of the structure obtained after forming the first step is provided in some other embodiments;
[0075] Figure 40 This is a three-dimensional schematic diagram of a stepped structure provided in some of the embodiments;
[0076] Figure 41 This is a three-dimensional schematic diagram of a structure obtained after forming a second filling layer, provided in some other embodiments;
[0077] Figure 42 This is a top view schematic diagram of a memory provided in some embodiments;
[0078] Figure 43 This is a three-dimensional schematic diagram of a structure obtained after forming an initial target material layer and an initial transfer material layer, provided in some embodiments;
[0079] Figure 44 This is a three-dimensional schematic diagram of a structure obtained after forming a target material layer and transferring a material layer, provided in some embodiments.
[0080] Explanation of reference numerals in the attached figures:
[0081] 1-Substrate, 2-Stacked structure, 21-Target material layer, 22-Transfer material layer, 210-Initial target material layer, 220-Initial transfer material layer, U-Etching unit, G-Etching trench, 3-Sacrificial material layer, 31-Sub-selection region, 4-Step structure, 41-First step, 42-Second step, 41A-Initial first step, 42A-Initial second step, 5-Isolation barrier, 6-Isolation layer, 71-First fill layer, 72-Second fill layer, 81-Gate, 82-Gate dielectric layer, 83-Semiconductor layer, 9-Photoresist pattern, 91-Etching protection layer, WL-Word line, BL-Bit line, CBL-Common bit line, C-Capacitor, CT-Lead. Detailed Implementation
[0082] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0084] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0085] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0086] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.
[0087] In three-dimensional memory, the staircase structure based on metal-oxide stacking has attracted widespread attention. The staircase structure can be constructed by alternating layers of multiple insulating layers and multiple conductive layers, so that the signal lines connecting the corresponding memory cells can be brought out using any conductive layer, thus solving the problem of difficult signal line bringing out after three-dimensional stacking of memory cells.
[0088] Current manufacturing methods require multiple cycles of adjustment and etching to create stepped partitions, and multiple replicate etching processes to form the stepped structure. However, as the number of stacked layers of storage cells in 3D memory increases, this method of manufacturing stepped structures that requires repeated etching becomes increasingly complex. Therefore, a more efficient method for manufacturing stepped structures is urgently needed.
[0089] Based on this, some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, which helps to reduce the complexity of the process steps and achieve efficient manufacturing of stepped structures.
[0090] Firstly, please refer to Figures 1-6 This disclosure provides a method for manufacturing a semiconductor structure, including the following steps S100 to S500.
[0091] S100, please refer to Figure 1 and Figure 2 A substrate 1 is provided, and a stacked structure 2 is formed on one side of the substrate 1. The stacked structure 2 includes a plurality of target material layers 21 stacked along a direction perpendicular to the substrate 1, and a transfer material layer 22 located between any two adjacent target material layers 21.
[0092] In some embodiments, please refer to Figure 2 The substrate 1 has an isolation layer 6 on its surface. The isolation layer 6 is disposed between the substrate 1 and the stacked structure 2 to protect the substrate 1 from being etched.
[0093] In some examples, the stacked structure 2 is stacked starting with the target material layer 21. The isolation layer 6 is formed of a different material from the target material layer 21.
[0094] For example, the insulating layer 6 can be made of insulating materials such as nitrides, oxides, or oxynitrides. The insulating layer 6 is, for example, a silicon nitride layer or a silicon oxide layer.
[0095] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0096] In some embodiments, the thicknesses of the multiple target material layers 21 can be the same or different, and the thicknesses of the multiple transfer material layers 22 can be the same or different. The thicknesses of the target material layers 21 and the transfer material layers 22 can be set according to specific process requirements. Furthermore, the stacked structure 2 may include multiple pairs of alternately stacked target material layers 21 and transfer material layers 22. For example, the stacked structure 2 may include 32 pairs, 64 pairs, 128 pairs, or more than 128 pairs of target material layers 21 and transfer material layers 22. It should be noted that although a specific number of pairs of target material layers 21 and transfer material layers 22 is exemplified here, other numbers of pairs of target material layers 21 and transfer material layers 22 may be used in other embodiments, and this disclosure does not impose any limitations on this.
[0097] S200, please refer to Figure 1 and Figure 2 The stacked structure 2 is etched along the direction perpendicular to the substrate 1 to form an etched trench G extending along a first direction (e.g., the Y direction).
[0098] In some embodiments, please refer to Figure 2 The etching trench G can penetrate the stacked structure 2 and extend to the substrate 1, or it can penetrate only a few pairs of target material layers 21 and transfer material layers 22 of the stacked structure 2. It should be noted that, in the embodiments of this disclosure, the number of steps in the final stepped structure is less than or equal to the number of pairs of target material layers 21 and transfer material layers 22 penetrated by the etching trench G.
[0099] For example, the etched trench G can be formed by dry etching based on a photomask.
[0100] S300, please refer to Figure 1 and Figure 3 A sacrificial material layer 3 is formed within the etched trench G.
[0101] For example, the sacrificial material layer 3 is formed using a deposition process, including but not limited to physical vapor deposition, chemical vapor deposition, epitaxial deposition, or atomic layer deposition.
[0102] For example, after forming the sacrificial material layer 3 in the etched trench G, the method of manufacturing the semiconductor structure further includes: using a polishing process to make the surface of the sacrificial material layer 3 away from the substrate 1 flush with the surface of the stacked structure 2 away from the substrate 1, the polishing process including but not limited to chemical mechanical polishing (CMP) process.
[0103] S400, please refer to Figure 1 and Figure 4 The sacrificial material layer 3 is etched using an isotropic etching process, and the target material layer 21 is simultaneously etched from top to bottom along the direction parallel to the substrate 1 to expose the sidewalls in the etching trench G, so that the retained portion of each target material layer 21 forms a first step 41, and multiple first steps 41 are arranged in an initial stepped structure along a second direction (e.g., the X direction); wherein the second direction (e.g., the X direction) intersects with the first direction (e.g., the Y direction).
[0104] In this step, it should be noted that there is a high etching selectivity between the target material layer 21 and the transfer material layer 22, so that only the sacrificial material layer 3 and the target material layer 21 are etched, without etching the transfer material layer 22.
[0105] For example, the isotropic etching process can be wet etching, or it can be isotropic dry remote plasma source (RPS) etching or vapor phase etching.
[0106] It should be noted that in isotropic etching processes, when etching the same material, the etching rate is the same in all directions.
[0107] In this embodiment, isotropic etching is used. It is understood that since etching proceeds from top to bottom from the opening of the etching trench G away from the substrate 1, the sidewalls of the corresponding target material layer 21 exposed within the etching trench G are also etched layer by layer from top to bottom. This results in different etching times for each target material layer 21 in the spatial dimension; that is, the upper layer has a longer etching time, while the lower layer has a shorter etching time, and the etching rate is the same in all directions. Therefore, please refer to... Figure 4 This allows the retained portion of each target material layer 21 to form a first step 41, and multiple first steps 41 are arranged along a second direction (e.g., the X direction) to form an initial stepped structure.
[0108] In this embodiment of the present disclosure, when forming the first step 41, the sidewalls of each target material layer 21 exposed in the etching trench G are etched sequentially based on the etching depth of the sacrificial material layer 3 in the etching trench G, so that each target material layer 21 is etched only in the second direction (e.g., the X direction). This can effectively avoid the photoresist side-biting problem existing in the prior art, enhance the controllability of the formation of the stepped structure 4, break through the layer limit, and realize the manufacturing of an infinite stepped structure 4.
[0109] S500, please refer to Figure 1 , Figure 5 and Figure 6 Using each first step 41 as a mask, the adjacent transfer material layers 22 are etched respectively, so that the retained part of each transfer material layer 22 forms a second step 42, thus obtaining a stepped structure 4.
[0110] For example, please refer to Figure 5 Before performing step S500, the method for manufacturing the semiconductor structure further includes forming a first filling layer 71 in the removal area of the etch trench G and each target material layer 21; wherein the material of the first filling layer 71 may be the same as the material of the transfer material layer 22.
[0111] For example, the material of the first filling layer 71 can be W, or it can be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polycrystalline silicon), conductive metal oxide semiconductors (such as indium tin oxide), etc. It can also be SiNx, doped polycrystalline silicon, amorphous silicon, doped polycrystalline silicon germanium, AsGa, AlAsGa, InP, etc., semiconductors or dielectric materials.
[0112] For example, please refer to Figure 6 The etching process of the first step 41 adjacent to the transfer material layer 22 includes dry etching.
[0113] For further explanation, please refer to the following. Figure 6 Using each first step 41 as a mask, the adjacent transfer material layer 22 below it is self-aligned and etched, which can realize the transfer of the step pattern corresponding to any first step 41 between adjacent film layers. It can be understood that each first step 41 and the corresponding second step 42 below it have the same projection on the substrate 1 and constitute the same step.
[0114] In this embodiment, the stepped structure 4 is efficiently manufactured using an isotropic etching process. Furthermore, by utilizing the high etching selectivity between the target material layer 21 and the transfer material layer 22, the transfer of the stepped structure between film layers can be achieved. Compared to existing technologies, this embodiment eliminates the need for step partitioning; it only requires a single photomask pattern definition (i.e., forming the etching trench G), and the multi-layer stepped structure 4 is manufactured using isotropic and self-aligned etching processes. This reduces the complexity of the manufacturing process and achieves efficient manufacturing of the stepped structure 4.
[0115] In some embodiments, the target material layer 21 is an insulating material layer and the transfer material layer 22 is a conductive material layer; or, the target material layer 21 is a conductive material layer and the transfer material layer 22 is an insulating material layer.
[0116] In some possible implementations, the target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer.
[0117] For example, the target material layer 21 can be SiO2 or SiN. x AlO x HfO x TiO x SiO x N y SiO x C z N y Or other insulating materials;
[0118] For example, the transfer material layer 22 can be W, or it can be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polycrystalline silicon), conductive metal oxide semiconductors (such as indium tin oxide), etc., or it can be SiN. x Semiconductors or dielectric materials such as doped polycrystalline silicon, amorphous silicon, doped polycrystalline silicon germanium, AsGa, AlAsGa, and InP.
[0119] For example, both the target material layer 21 and the sacrificial material layer 3 are insulating material layers, and the materials used in the target material layer 21 and the sacrificial material layer 3 can be the same or different.
[0120] For example, the sacrificial material layer 3 can be SiO2 material with different growth conditions or doping types than the target material layer 21, or it can be SiN. x AlO x HfO x TiO x SiO x N y SiO x C z N y Or other insulating materials.
[0121] In some other possible implementations, the target material layer 21 is a conductive material layer and the transfer material layer 22 is an insulating material layer.
[0122] For example, the target material layer 21 can be W, or it can be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polycrystalline silicon), conductive metal oxide semiconductors (such as indium tin oxide), etc., or it can be SiN. x Semiconductors or dielectric materials such as doped polycrystalline silicon, amorphous silicon, doped polycrystalline silicon germanium, AsGa, AlAsGa, and InP.
[0123] For example, the transfer material layer 22 can be SiO2 or SiN. x AlO x HfO x TiO x SiO x N y SiO x C z N y Or other insulating materials.
[0124] For example, both the target material layer 21 and the sacrificial material layer 3 are conductive material layers, and the materials used in the target material layer 21 and the sacrificial material layer 3 can be the same or different.
[0125] For example, the sacrificial material layer 3 can be TiN, W, or Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polycrystalline silicon), conductive metal oxide semiconductors (such as indium tin oxide), and other conductive materials.
[0126] It is worth mentioning that, in this embodiment of the disclosure, the width of each step in the stepped structure 4 can be controlled by adjusting one or more of the following methods: adjusting the etching selectivity ratio of each target material layer 21 relative to the sacrificial material layer 3, adjusting the thickness of the transfer material layer 22, or adjusting the width of the etching trench G.
[0127] In some embodiments, the etching rate of the sacrificial material layer 3 is less than or equal to the etching rate of the target material layer 21. Thus, as the etching depth of the sacrificial material layer 3 changes, it is advantageous to ensure that the target material layer 21 can have the required etching amount to form a step with the target step width.
[0128] In some embodiments, the etching selectivity ratios between different target material layers 21 and sacrificial material layers 3 are different. For example, different etching selectivity ratios between target material layers 21 and sacrificial material layers 3 can be achieved by using different doping types, doping concentrations, or different growth conditions for different target material layers 21. Alternatively, in other examples, different etching selectivity ratios between sacrificial material layers 3 and each target material layer 21 can be achieved by using different doping types, doping concentrations, or different growth conditions for different regions of the sacrificial material layer 3 corresponding to different target material layers 21.
[0129] In this embodiment of the disclosure, it should be explained that when the sacrificial material layer 3 is etched from top to bottom, the etching of each target material layer 21 is also performed simultaneously. Thus, by adjusting the etching selectivity ratio between the sacrificial material layer 3 and each target material layer 21, the etching rate difference between each target material layer 21 and the sacrificial material layer 3 can be controlled, thereby achieving control over the step width and enhancing the controllability of the formation of the stepped structure 4.
[0130] For example, the higher the etching selectivity of the target material layer 21 relative to the sacrificial material layer 3, the wider the first step 41 that can be formed by the underlying target material layer 21.
[0131] In some embodiments, the thickness of the transfer material layer 22 is positively correlated with the width of the second step 42 formed by the adjacent transfer material layer 22 below it.
[0132] Here, please refer to Figure 3 and Figure 4 Understanding that a greater thickness of the transfer material layer 22 results in a longer etching time for the sacrificial material layer 3 in the corresponding thickness region. This allows for a relatively longer etching time for the target material layer 21 above the transfer material layer 22, while the etching time for the target material layer 21 below the transfer material layer 22 is relatively shorter. This facilitates the formation of a first step 41 with a larger width below the transfer material layer 22. Consequently, the adjacent transfer material layer 22 below can be etched using the first step 41 as a mask to form a second step 42 with a larger width. Conversely, a smaller thickness of the transfer material layer 22 results in a shorter etching time for the sacrificial material layer 3 in the corresponding thickness region. This allows for a relatively shorter etching time for the target material layer 21 above the transfer material layer 22, while the etching time for the target material layer 21 below the transfer material layer 22 is relatively longer. This facilitates the formation of a first step 41 with a smaller width below the transfer material layer 22. Consequently, the adjacent transfer material layer 22 below can be etched using the first step 41 as a mask to form a second step 42 with a smaller width.
[0133] In this embodiment of the disclosure, the thickness of the transfer material layer 22 is controlled to adjust the step width, thereby enhancing the controllability of the formation of the stepped structure 4.
[0134] In some embodiments, the size of the etched trench G in the second direction (e.g., the X direction) is negatively correlated with the step width difference between any two adjacent first steps 41.
[0135] It needs to be explained that the dimension of the etching trench G in the second direction (e.g., the X direction) is its width. The smaller the width of the etching trench G, the slower the downward etching rate of the sacrificial material layer 3 within the trench G, due to the etching loading effect. This allows for a relatively increased etching time for the upper target material layer 21 and a relatively decreased etching time for the lower target material layer 21, thus facilitating a larger step width difference between adjacent first steps 41. Conversely, the larger the width of the etching trench G, the faster the downward etching rate of the sacrificial material layer 3 within the trench G, due to the etching loading effect. This allows for a relatively decreased etching time for the upper target material layer 21 and a relatively increased etching time for the lower target material layer 21, thus facilitating a smaller step width difference between adjacent first steps 41.
[0136] In this embodiment of the disclosure, by controlling the width of the etching trench G (i.e., the dimension in the second direction), the step width difference between adjacent first steps 41 (and adjacent second steps 42) can be adjusted, thereby enhancing the controllability of the formation of the stepped structure 4.
[0137] In some embodiments, please combine Figure 3 and Figure 4 Understand that in step S400, the sacrificial material layer 3 is etched using an isotropic etching process, and the sidewalls of each target material layer 21 exposed in the etching trench G are simultaneously etched sequentially from top to bottom along the direction parallel to the substrate 1. This includes: symmetrically etching the sidewalls of each target material layer 21 exposed in the etching trench G on opposite sides in the second direction (e.g., the X direction) to form an initial stepped structure symmetrically arranged with the etching trench G as the center.
[0138] In this embodiment of the disclosure, based on the same etching trench G, an initial stepped structure symmetrically arranged with the etching trench G as the center can be formed by synchronous etching on both opposite sides of it in a second direction (e.g., the X direction). Figure 4 As shown in the figure, this helps to improve production efficiency and reduce production costs.
[0139] For example, the sidewalls of the etch trench G exposed by symmetrical etching of each target material layer 21 on opposite sides in the second direction can be exposed by hydrogen fluoride vapor etching.
[0140] In some embodiments, please refer to Figure 7 After performing step S500, the method for manufacturing the semiconductor structure further includes: after obtaining the stepped structure 4, forming a second filling layer 72 that covers the stepped structure 4 and fills the etched trench G.
[0141] For example, the second filler layer 72 is an insulating material layer. In some examples, if the target material layer 21 is an insulating material layer, the material of the second filler layer 72 is the same as the material of any target material layer 21. In other examples, if the target material layer 21 is a conductive material layer, the material of the second filler layer 72 is the same as the material of the transfer material layer 22.
[0142] For example, the material of the second filling layer 72 can be SiO2, or it can be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.
[0143] It should be added that, in some embodiments, the material of the sacrificial material layer 3 can be an oxide; wherein, by selecting the type of oxide of the sacrificial material layer 3, it can be ensured that the etching rates of the target material layer 21 and the sacrificial material layer 3 are different, so as to achieve the control of the width of the first step 41.
[0144] In other embodiments, please refer to Figure 8 The sacrificial material layer 3 includes multiple sub-selection regions 31 that are spaced apart along the direction perpendicular to the substrate 1 and correspond one-to-one with the target material layer 21; wherein the etching selectivity ratio between the target material layer 21 and the sacrificial material layer 3 of different sub-selection regions 31 is different.
[0145] For example, the material of the sacrificial material layer 3 includes silicon oxide, and the etching selectivity between each sub-selective region 31 and the sacrificial material layer 3 can be different by using different doping types, different doping concentrations or different growth conditions in different sub-selective regions 31.
[0146] In some embodiments, please refer to Figure 9 and Figure 10 Before forming the stacked structure 2 on one side of the substrate 1, the manufacturing method further includes: forming an isolation barrier 5 on one side of the substrate 1; wherein the stacked structure 2 is formed on one side of the isolation barrier 5, and the etched trench G exposes the sidewall of the isolation barrier 5 facing the stacked structure 2.
[0147] For example, step S100 can be specifically manifested as follows: Figure 9 The step S110 is shown.
[0148] In some examples, the isolation barrier 5 and the isolation layer 6 may be made of the same material or different materials.
[0149] For example, the isolation barrier 5 and the isolation layer 6 are made of the same material. The isolation barrier 5 and the isolation layer 6 can be patterned after the isolation material layer is formed, for example, by using a dry etching process to form a stacked structure receiving groove in the isolation material layer, so as to facilitate the subsequent formation of the stacked structure 2 in the stacked structure receiving groove.
[0150] In some examples, the isolation barrier 5 is made of a different material than the target material layer 21.
[0151] For example, the insulating barrier 5 can be made of insulating materials such as nitrides, oxides, or oxynitrides. The insulating barrier 5 is, for example, silicon nitride or silicon oxide.
[0152] Therefore, in some embodiments where the isolation barrier 5 is formed, please refer to Figure 10 The laminated structure 2 is formed on one side of the isolation barrier 5. After etching to form the etching trench G, the etching trench G exposes the sidewall of the isolation barrier 5 facing the laminated structure 2. Here, the etching trench G can be formed at the junction of the laminated structure 2 and the isolation barrier 5.
[0153] Please see Figure 11 A sacrificial material layer 3 is formed within the etched trench G.
[0154] Please see Figure 12 Each target material layer 21 is etched on the side of the etching trench G opposite to the isolation barrier 5 in the second direction, exposing the sidewalls inside the etching trench G to form an initial stepped structure distributed on the side of the etching trench G away from the isolation barrier 5 in the second direction (e.g., the X direction).
[0155] Please see Figure 13 A first filling layer 71 is formed in the etched trench G and the removal area of each target material layer 21. The material of the first filling layer 71 can be the same as the material of the transfer material layer 22.
[0156] Please see Figure 14 Using each first step 41 as a mask, the adjacent transfer material layer 22 and the first filling layer 71 are etched to form each second step 42, thereby obtaining the stepped structure 4.
[0157] Please see Figure 15 A second filling layer 72 is formed to cover the stepped structure 4 and fill the etched trenches G.
[0158] In some embodiments, please refer to Figures 16-21 The number of stacked layers of the target material layer 21 is greater than the first threshold. In step S400, the sacrificial material layer 3 is etched using an isotropic etching process, and each target material layer 21 exposed in the etching trench G is simultaneously etched sequentially from top to bottom along the direction parallel to the substrate 1. This can also be implemented in the following manner.
[0159] Please see Figure 16 The target material layer 21 and the corresponding transfer material layer 22 of the target layer number are used as etching units U; the target layer number is less than or equal to the second threshold, and the second threshold is less than or equal to half of the first threshold.
[0160] For example, different etching units U correspond to the same number of target layers. However, it is understandable that different etching units U correspond to different numbers of target layers.
[0161] Here, when the number of stacked layers of the target material layer 21 in the stacked structure 2 is greater than the first threshold, the target layer number matching process condition selection setting corresponding to the etching unit U can eliminate the effect of the lateral etching rate of the target material layer 21 slowing down as the etching depth of the sacrificial material layer 3 increases, so as to facilitate the manufacturing of the stepped structure 4 to break through the layer number limit, thereby realizing the efficient manufacturing of the stepped structure 4 with an unlimited number of layers.
[0162] Please see Figures 17-21The sacrificial material layer 3 corresponding to the etching unit U is etched one by one from top to bottom. After the target material layer 21 in the etching unit U is etched to form the initial first step 41A and the transfer material layer 22 in the etching unit U is etched to form the initial second step 42A, the sacrificial material layer 3 corresponding to the next etching unit U is etched.
[0163] Here, the etching unit U includes a target material layer 21 and a transfer material layer 22 for the target layer pair. The initial first step 41A and the initial second step 42A refer to the intermediate structures of the first step 41 and the second step 42 formed in the previous etching unit U when the sacrificial material layer 3 corresponding to the next etching unit U is etched. Furthermore, the initial first step 41A and the initial second step 42A (i.e., the intermediate structures of the first step 41 and the second step 42) continue to be etched in the etching process of subsequent etching units U until the final step structure 4 is obtained (i.e., the etching for forming the steps ends).
[0164] The following illustration uses the etching of two etching units U to obtain the stepped structure 4 as an example. However, it can be understood that in some examples, the stepped structure 4 can also be obtained after etching away all the sacrificial material layer 3.
[0165] Please see Figure 17 Along the direction close to the substrate 1, the sacrificial material layer 3 corresponding to the first etching unit U is etched to form an etching trench G on one side of the sidewall of the first etching unit U, and the target material layer 21 of the target number of layers is etched based on the etching trench G to form an initial first step 41A.
[0166] Please see Figure 18 Using the initial first step 41A as a mask, the transfer material layers 22 in the first etching unit U are self-aligned and etched to form the initial second step 42A.
[0167] It is understood that in some embodiments, please refer to Figure 18 and Figure 19 Understandably, after etching to form the initial second step 42A, if the top initial first step 41A is an insulating step and the top target material layer 21 in the second etching unit U is an insulating material layer, then the top insulating step and the exposed portion of the top insulating material layer in the second etching unit U can be etched away first. Alternatively, after forming the first filling layer 71 that fills the etching trench G and covers the resulting structure, the first filling layer 71 and the corresponding transfer material layers 22 can be etched simultaneously to form the initial second step 42A. The material of the first filling layer 71 can be the same as that of the transfer material layer 22.
[0168] Please see Figure 20The sacrificial material layer 3 corresponding to the second etching unit U is etched so that the etching trench G extends along the direction close to the substrate 1 to one side of the sidewall of the second etching unit U, and the target material layers 21 in the first etching unit U and the second etching unit U are etched based on the etching trench G to form the first step 41.
[0169] Please see Figure 21 Using the first step 41 as a mask, the transfer material layers 22 in the first etching unit U and the second etching unit U are self-aligned and etched to form the second step 42.
[0170] Therefore, in this embodiment of the present disclosure, the sacrificial material layer 3 corresponding to different etching units U can be etched at different times based on the same photomask to form etching trenches G in segments and to sequentially etch the corresponding target material layer 21 laterally. Furthermore, it can be understood that after etching the sacrificial material layer 3 or after the etching of the sacrificial material layer 3 is completed, the resulting steps correspond to the first step 41 and the second step 42.
[0171] In some embodiments, please refer to Figure 21 The target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer. Each etching unit U located on opposite sides of the etching trench G in the second direction (e.g., the X direction) can form a stepped structure 4 with double-sided steps symmetrically arranged around the etching trench G after performing the corresponding etching process.
[0172] In other embodiments, please refer to Figures 22-27 The target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer. Each etching unit U located on the side of the etching trench G facing away from the isolation barrier 5 in the second direction (e.g., the X direction) can form a stepped structure 4 with a single-sided step after performing the corresponding etching process.
[0173] The following illustration uses the example of etching two etching units U to obtain a stepped structure 4 with a single-sided step. However, it can be understood that in some examples, the stepped structure 4 can also be obtained after etching away all the sacrificial material layer 3.
[0174] Please see Figure 22 and Figure 23 Along the direction close to the substrate 1, the sacrificial material layer 3 corresponding to the first etching unit U is etched to form an etching trench G on one side of the sidewall of the first etching unit U, and the etching trench G exposes one sidewall of the isolation barrier 5; the target material layer 21 with the target number of layers is etched based on the etching trench G to form the initial first step 41A.
[0175] Please see Figure 24Using each initial first step 41A as a mask, the transfer material layers 22 in the first etching unit U are self-aligned and etched to form the initial second step 42A.
[0176] It is understood that in some embodiments, please refer to Figure 24 and Figure 25 Understandably, after etching to form the initial second step 42A, if the top initial first step 41A is an insulating step and the top target material layer 21 in the second etching unit U is an insulating material layer, then the top insulating step and the exposed portion of the top insulating material layer in the second etching unit U can be etched away first. Alternatively, after forming the first filling layer 71 that fills the etching trench G and covers the resulting structure, the first filling layer 71 and the corresponding transfer material layers 22 can be etched simultaneously to form the initial second step 42A. The material of the first filling layer 71 can be the same as that of the transfer material layer 22.
[0177] Please see Figure 26 The sacrificial material layer 3 corresponding to the second etching unit U is etched so that the etching trench G extends to one side of the sidewall of the second etching unit U in the direction close to the substrate, and the target material layers 21 in the first etching unit U and the second etching unit U are etched based on the etching trench G to form the first step 41.
[0178] Please see Figure 27 Using the first step 41 as a mask, the transfer material layers 22 in the first etching unit U and the second etching unit U are self-aligned and etched to form the second step 42.
[0179] In some other embodiments, please refer to Figures 28-34 The target material layer 21 is a conductive material layer, and the transfer material layer 22 is an insulating material layer. Each etching unit U located on opposite sides of the etching trench G in the second direction (e.g., the X direction) can form a stepped structure 4 with double-sided steps symmetrically arranged around the etching trench G after performing the corresponding etching process.
[0180] Here, the etching steps of each etching unit U can be carried out with reference to the manufacturing process of the stepped structure 4 with double-sided steps in some of the aforementioned embodiments, and will not be described in detail here.
[0181] In some other embodiments, please refer to Figures 35-41 The target material layer 21 is a conductive material layer, and the transfer material layer 22 is an insulating material layer. Each etching unit U located on the side of the etching trench G facing away from the isolation barrier 5 in the second direction (e.g., the X direction) can form a stepped structure with a single-sided step after performing the corresponding etching process.
[0182] Here, the etching steps of each etching unit U can be carried out with reference to the manufacturing process of the stepped structure 4 of the single-sided step in some of the aforementioned embodiments, and will not be described in detail here.
[0183] Secondly, this disclosure also provides a semiconductor structure according to some embodiments. It should be noted that this structure also possesses the technical advantages of the aforementioned semiconductor structure manufacturing method. For technical features that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions of the technical features in the aforementioned embodiments; detailed descriptions will not be repeated below.
[0184] In some embodiments, please refer to Figure 3 , Figure 8 , Figure 11 , Figure 16 , Figure 22 and Figure 28 The semiconductor structure includes a substrate 1, a stacked structure 2, and a sacrificial material layer 3. The stacked structure 2 is located on one side of the substrate 1 and includes a plurality of target material layers 21 stacked along a direction perpendicular to the substrate 1, and a transfer material layer 22 located between any two adjacent target material layers 21. The stacked structure 2 has etching trenches G. The sacrificial material layer 3 fills the etching trenches G. The target material layers 21 are configured to form a plurality of first steps 41 arranged along a second direction after etching. The transfer material layer 22 is configured to form second steps 42 after etching, using adjacent first steps 41 as masks, so that each first step 41 and each second step 42 constitutes a stepped structure 4.
[0185] In some embodiments, the target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer.
[0186] In other embodiments, the target material layer 21 is a conductive material layer, and the transfer material layer 22 is an insulating material layer.
[0187] In some embodiments, please refer to Figure 3 and Figure 8 The semiconductor structure also includes an isolation layer 6 disposed between the substrate 1 and the stacked structure 2.
[0188] In some embodiments, please refer to Figure 11 , Figure 22 and Figure 35 The semiconductor structure further includes an isolation barrier 5 located on one side of the stacked structure 2 along the direction parallel to the substrate 1; wherein the sacrificial material layer 3 is located between the isolation barrier 5 and the stacked structure 2.
[0189] In some embodiments, the etching selectivity ratios between different target material layers 21 and sacrificial material layers 3 are different.
[0190] In some examples, the sacrificial material layer 3 includes a plurality of subselective regions 31 spaced apart along the direction perpendicular to the substrate 1 and corresponding one-to-one with the target material layer 21; wherein the etching selectivity ratio between the target material layer 21 and the sacrificial material layer 3 of different subselective regions 31 is different.
[0191] In some embodiments, the thickness of the transfer material layer 22 (i.e., its dimension in the direction perpendicular to the substrate 1) is positively correlated with the width of the second step to be formed in the adjacent transfer material layer below it.
[0192] In some embodiments, the size of the etched trench G in the second direction (e.g., the X direction) is negatively correlated with the step width difference between any two adjacent first steps to be formed.
[0193] Thirdly, this disclosure also provides a memory according to some embodiments. It should be noted that the memory also possesses the technical advantages of the aforementioned semiconductor structure and its manufacturing method. For the parts that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions in the above embodiments, which will not be described in detail below.
[0194] In some embodiments, the memory includes at least one stepped structure 4; wherein the stepped structure 4 can be obtained by etching a semiconductor structure as described in the second aspect of the present disclosure. The stepped structure 4 includes a plurality of first steps 41 stacked along a direction perpendicular to the substrate 1, and a second step 42 located between any two adjacent first steps 41.
[0195] Here, it can be understood that the manufacturing method of etching the aforementioned semiconductor structure to form the stepped structure 4 can be performed with reference to the relevant etching steps in the semiconductor structure manufacturing method described in the first aspect of the present disclosure.
[0196] Furthermore, the distribution location, quantity, and number of stacked steps of the stepped structure 4 within the memory in this embodiment can all be set to match specific requirements. This embodiment does not impose any limitations on these aspects.
[0197] Figure 42 An exemplary top view of a memory structure is provided. See also Figure 42The memory includes an array region and a peripheral region. A stepped structure 4 can be disposed in the peripheral region. The memory also includes multiple memory cells arrayed in the array region. A memory cell includes, for example, a transistor T and a capacitor C. The transistor T includes a gate 81 and a gate dielectric layer 82 and a semiconductor layer 83 surrounding the sidewalls of the gate 81; wherein the gate 81 is electrically connected to the word line WL; the semiconductor layer 83 can serve as the channel region and source / drain of the transistor T, and the two opposite outer walls of the semiconductor layer 83 in the X direction are electrically connected to the bit line BL and the first electrode of the capacitor C, respectively. The capacitor C also includes a dielectric layer covering the first electrode and a second electrode covering the dielectric layer. The word line WL can extend along a direction perpendicular to the substrate 1. The bit line BL can extend along the Y direction. Furthermore, the multiple memory cells can be arranged in a column at intervals along the Y direction.
[0198] For example, a column of memory cells shares the same bit line BL.
[0199] For example, two adjacent columns of memory cells are located on opposite sides of bit line BL and share the same bit line BL.
[0200] For example, please continue reading Figure 42 The memory also includes a common bit line CBL disposed on the same layer as the bit line BL; wherein each bit line BL can be selected by its corresponding selection transistor ( Figure 42 (Not shown in the image) is electrically connected to the common bit line CBL of the same layer. Here, "same layer" means that the two are at approximately the same height from the surface of substrate 1.
[0201] It should be added that, in some of the above embodiments, each conductive step in the stepped structure 4 can be the outer terminal of the corresponding common bit line CBL, and led out through the lead wire CT.
[0202] In some embodiments, please refer to Figure 43 and Figure 44 The target material layer 21 and transfer material layer 22 used to form each step in the stepped structure 4 can be formed by patterning etching after alternatingly stacking multiple initial target material layers 210 and multiple initial transfer material layers 220 along the direction perpendicular to the substrate 1.
[0203] For example, such as Figure 43 As shown, multiple initial target material layers 210 and multiple initial transfer material layers 220 are alternately stacked along a direction perpendicular to the substrate 1, for example, starting with the initial target material layer 210 and ending with the initial transfer material layer 220. Then, an etching protection layer 91 can be formed on the upper surface of the top initial transfer material layer 220, and a photoresist pattern 9 can be formed on the surface of the etching protection layer 91. Thus, each initial target material layer 210 and each initial transfer material layer 220 can be etched based on the photoresist pattern 9 to obtain, as shown... Figure 44The stacked structure shown includes the target material layer 21 and transfer material layer 22 mentioned in some of the foregoing embodiments, and can simultaneously form the required insulating and conductive patterns in the array region.
[0204] For example, the etch protection layer 91 can be a hard mask layer, such as a silicon nitride layer; or, the etch protection layer 91 can be an anti-reflection layer.
[0205] Fourthly, according to some embodiments, this disclosure also provides an electronic device, including: a memory as described in the third aspect of the embodiments of this application. It should be noted that the electronic device also possesses the technical advantages of the aforementioned semiconductor structure and its manufacturing method, as well as the memory. For parts that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated below.
[0206] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0207] The embodiments described above are merely examples of several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, and a stacked structure is formed on one side of the substrate; The stacked structure includes: a plurality of target material layers stacked along the direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers; The stacked structure is etched along the direction perpendicular to the substrate to form an etch trench extending along the first direction; A sacrificial material layer is formed within the etched trench; The sacrificial material layer is etched using an isotropic etching process, and the sidewalls of each target material layer exposed in the etching trench are simultaneously etched sequentially from top to bottom along a direction parallel to the substrate, so that the retained portion of each target material layer forms a first step, and multiple first steps are arranged along a second direction to form an initial stepped structure; wherein, the second direction intersects with the first direction; A first filling layer is formed in the etched trenches and the removal areas of each of the target material layers, and the material of the first filling layer is the same as the material of the transfer material layer; Using each of the first steps as a mask, the adjacent transfer material layers and the first filler layer are etched respectively, so that the retained portion of each transfer material layer forms a second step, thereby obtaining a stepped structure.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The etching selectivity ratio between the target material layer and the sacrificial material layer varies in different layers.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The thickness of the transfer material layer is positively correlated with the width of the second step formed by the adjacent transfer material layer below it.
4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The dimension of the etched groove in the second direction is negatively correlated with the step width difference between any two adjacent first steps.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method of etching the sacrificial material layer using an isotropic etching process, and simultaneously etching each of the target material layers sequentially from top to bottom along a direction parallel to the substrate to expose the sidewalls within the etching trench, includes: The target material layers are symmetrically etched on opposite sides of the etching trench in the second direction, exposing the sidewalls within the etching trench, to form the initial stepped structure symmetrically arranged with the etching trench as the center.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The sacrificial material layer includes a plurality of sub-selection regions that are spaced apart along the direction perpendicular to the substrate and correspond one-to-one with the target material layer; The etching selectivity ratios are different between the target material layer and the sacrificial material layers in different sub-selection regions.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the stacked structure on one side of the substrate, the manufacturing method further includes: An isolation barrier is formed on one side of the substrate; The layered structure is formed on one side of the isolation barrier, and the etched grooves expose the sidewall of the isolation barrier facing the layered structure.
8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The number of stacked target material layers is greater than a first threshold; the step of etching the sacrificial material layer using an isotropic etching process, and simultaneously etching the sidewalls of each target material layer exposed in the etching trench from top to bottom along the direction parallel to the substrate, further includes: The target material layer and the corresponding transfer material layer of the target number of layers are used as etching units; the target number of layers is less than or equal to a second threshold, and the second threshold is less than or equal to half of the first threshold; The sacrificial material layer corresponding to each etching unit is etched one by one from top to bottom. After etching the target material layer in the etching unit to form an initial first step and etching the transfer material layer in the etching unit to form an initial second step, the sacrificial material layer corresponding to the next etching unit is etched.
9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 8, characterized in that, The target material layer is an insulating material layer, and the transfer material layer is a conductive material layer; Alternatively, the target material layer may be a conductive material layer, and the transfer material layer may be an insulating material layer.
10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Also includes: After obtaining the stepped structure, a second filling layer is formed to cover the stepped structure and fill the etched trenches.
11. A semiconductor structure, characterized in that, include: Substrate; A stacked structure, located on one side of the substrate, includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers; the stacked structure has etching trenches; wherein, the target material layers are configured to: form a plurality of first steps arranged along a second direction after etching; the transfer material layers are configured to: form second steps after etching using adjacent first steps as masks, so that each first step and each second step constitutes a stepped structure; A first filling layer is located within the etched trench and in the removal area after the target material layer has been etched to form multiple first steps; the material of the first filling layer is the same as the material of the transfer material layer; wherein, the first filling layer is configured to be etched synchronously with the transfer material layer.
12. The semiconductor structure according to claim 11, characterized in that, Also includes: An isolation barrier is located on one side of the stacked structure along a direction parallel to the substrate; The first filling layer is located between the isolation barrier and the stacked structure.
13. A memory, characterized in that, include: At least one stepped structure; wherein, The stepped structure is obtained by etching the semiconductor structure as described in claim 11 or 12; The stepped structure includes: a plurality of first steps stacked along the direction perpendicular to the substrate, and a second step located between any two adjacent first steps.
14. An electronic device, characterized in that, include: The memory as described in claim 13.