Reverse conducting insulated gate bipolar transistor

Abstract

The invention provides a reverse conducting insulated gate bipolar transistor. The reverse conducting insulated gate bipolar transistor comprises a collector region, a drift region, an N well region, a P + region and a plurality of trench gates, the collector region, the drift region, the N well region and the P + region are sequentially stacked, the trench gates penetrate through the P + region and the N well region and extend to the drift region, a channel region and a non-channel region are defined by the trench gates, the P well region is arranged in the channel region and between the N well region and the P + region, and the P well region is arranged between the N well region and the P + region. In the non-channel region, the P + regions are located on the two sides of the N well region, and the portion, located between the P + regions, of the N well region is in Schottky contact with emitter metal. By introducing Schottky contact into a non-channel region, a PN junction between a P well region and an N well region of a channel region can be short-circuited, and the injection efficiency of IGBT cells is reduced, so that the reverse recovery loss of the reverse conducting IGBT is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a reverse-conducting insulated gate bipolar transistor. Background Art

[0002] The reverse-conducting insulated gate bipolar transistor (RC-IGBT) is a derivative device of IGBT developed to meet the needs of different application circuits. The RC-IGBT integrates the cell structure of a traditional insulated gate bipolar transistor (IGBT) and the cell structure of a fast recovery diode (FRD) on the same chip to provide a compact current discharge circuit. The dynamic performance adjustment of the RC-IGBT needs to consider both the IGBT region and the FRD region. For the IGBT, considering aspects such as on-state voltage drop and breakdown voltage, it is desirable that the doping concentration of the P-well region is as high as possible. From the perspective of the FRD, the lower the anode doping concentration, the smaller the reverse recovery loss. There is an obvious contradiction between the two, and it is difficult to make a compromise adjustment. Since the anode of the FRD region is generally formed by the P-well region of the IGBT, the anode concentration of the RC-IGBT is generally relatively large, resulting in a relatively low on-state voltage drop, a relatively large reverse peak current, a relatively large reverse recovery loss, and a relatively large reverse recovery loss will reduce the application performance of the device.

[0003] Therefore, the current reverse-conducting insulated gate bipolar transistor still needs to be improved. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, an object of the present invention is to provide a reverse-conducting insulated gate bipolar transistor to improve the problem of relatively large reverse recovery loss of the existing reverse-conducting insulated gate bipolar transistor.

[0005] In one aspect of the present invention, a reverse-conducting insulated gate bipolar transistor is provided. The reverse-conducting insulated gate bipolar transistor includes: a collector region, a drift region, an N-well region, a P+ region stacked in sequence, and a plurality of trench gates penetrating the P+ region, the N-well region and extending to the drift region. The trench gates define a channel region and a non-channel region. In the channel region, a P-well region is provided between the N-well region and the P+ region. In the non-channel region, the P+ regions are located on both sides of the N-well region, and the N-well region between the P+ regions forms a Schottky contact with the emitter metal.

[0006] Further, the trench gate includes a first trench gate, a second trench gate, and a third trench gate. The two first trench gates define the channel region, and the second trench gate and the first trench gate define the non-channel region. In the channel region, an N+ region is disposed between the first trench gate and the P+ region, and the N+ region is disposed on the same layer as the P+ region. A third trench gate is disposed between the two first trench gates, and the third trench gate is in contact with the emitter metal. The N+ region, the P+ region, and the P well region are located between the first trench gate and the third trench gate. The N well region is located between the P well region and the third trench gate, and between the P+ region and the third trench gate, and forms a Schottky contact with the emitter metal.

[0007] Further, the distance between the third trench gate and the two first trench gates is the same.

[0008] In another aspect of the present invention, the present invention provides a reverse-conducting insulated gate bipolar transistor. The reverse-conducting insulated gate bipolar transistor includes: a collector region, a drift region, an N well region, a P+ region, which are stacked in sequence, and a plurality of trench gates that penetrate the P+ region, the N well region, and extend to the drift region. The trench gate includes a first trench gate, a second trench gate, and a fourth trench gate. The two first trench gates define a channel region, and the second trench gate and the first trench gate define a non-channel region. In the channel region, a P well region is disposed between the N well region and the P+ region. Wherein, in the non-channel region, at least one fourth trench gate is disposed between the second trench gate and the first trench gate. The fourth trench gate is in contact with the emitter metal. The N well region is divided into a plurality of sub-N well regions by the fourth trench gate. The P+ regions are located on both sides of the sub-N well regions. The sub-N well region located between the P+ regions forms a Schottky contact with the emitter metal.

[0009] Further, the distance between adjacent trench gates in the non-channel region is the same as the distance between the two first trench gates in the channel region.

[0010] Further, a plurality of fourth trench gates arranged at equal intervals are disposed between the second trench gate and the first trench gate, and the distance between adjacent two trench gates in the non-channel region is 0.2 - 0.4 μm.

[0011] Further, in the channel region, an N+ region is provided between the first trench gate and the P+ region, and the N+ region is provided on the same layer as the P+ region. The trench gate further includes a third trench gate. The third trench gate is provided between the two first trench gates. The third trench gate is in contact with the emitter metal. The N+ region, the P+ region, and the P-well region are located between the first trench gate and the third trench gate. The N-well region is located between the P-well region and the third trench, and between the P+ region and the third trench gate, and forms a Schottky contact with the emitter metal.

[0012] Further, the distances between the third trench gate and the two first trench gates are the same.

[0013] In another aspect of the present invention, the present invention provides a reverse-conducting insulated gate bipolar transistor. The reverse-conducting insulated gate bipolar transistor includes: a collector region, a drift region, an N-well region, a P-well region, a P+ region, which are stacked in sequence, and a plurality of trench gates that penetrate the P+ region, the P-well region, the N-well region and extend to the drift region. The trench gates include a first trench gate and a third trench gate. The two first trench gates define a channel region. Wherein, in the channel region, an N+ region is provided between the first trench gate and the P+ region, and the N+ region is provided on the same layer as the P+ region. The third trench gate is provided between the two first trench gates. The third trench gate is in contact with the emitter metal. The N+ region, the P+ region, and the P-well region are located between the first trench gate and the third trench gate. The N-well region is located between the P-well region and the third trench, and between the P+ region and the third trench gate, and forms a Schottky contact with the emitter metal.

[0014] Further, the distances between the third trench gate and the two first trench gates are the same.

[0015] The reverse-conducting insulated gate bipolar transistor of the present invention has the following advantages:

[0016] 1. By introducing a Schottky diode structure in the non-channel region, the PN junction between the P-well region and the N-well region in the channel region can be short-circuited, reducing the hole injection efficiency on the front surface of the device, and reducing the reverse recovery loss of the device without affecting the forward operating characteristics of the device, thereby improving the overall performance of the device;

[0017] 2. By introducing a Schottky diode structure with a grounded trench gate in the non-channel region, the breakdown voltage of the Schottky diode can be increased, the leakage current can be reduced, and at the same time the reverse recovery loss of the device can be reduced;

[0018] 3. By introducing a Schottky diode structure with a grounded trench gate in the channel region, while reducing the reverse recovery loss of the device, the on-state voltage drop of the device is reduced, and the overall performance of the device is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 Shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor according to an embodiment of the present invention;

[0021] Figure 2 Shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor according to another embodiment of the present invention;

[0022] Figure 3 Shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor according to still another embodiment of the present invention;

[0023] Figure 4 Shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor according to still another embodiment of the present invention;

[0024] Figure 5 Shows a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor according to still another embodiment of the present invention.

[0025] Reference Signs:

[0026] 11: P+ collector region; 12: N+ collector region; 20: drift region; 30: N-well region; 40: P+ region; 51: first trench gate; 52: second trench gate; 53: third trench gate; 54: fourth trench gate; 60: P-well region; 70: emitter metal; 80: N+ region; 90: insulating layer; 100: buffer layer; 110: collector metal; 1: channel region; 2: non-channel region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The embodiments of the present invention will be described in detail below. The following described embodiments are exemplary and are only used to explain the present invention, and should not be construed as a limitation to the present invention. For those not specified in the embodiments, the techniques or conditions described in the literature in the field or according to the product specifications are followed.

[0028] In one aspect of the present invention, the present invention provides a reverse-conducting insulated gate bipolar transistor. In some embodiments of the present invention, refer to Figure 1, the reverse-conducting insulated gate bipolar transistor includes: a collector region (the P+ collector region 11 and the N+ collector region 12 shown in the figure), a drift region 20, an N-well region 30, a P+ region 40, and a plurality of trench gates (the first trench gate 51 and the second trench gate 52 shown in the figure). Among them, the collector region, the drift region 20, the N-well region 30, and the P+ region 40 are stacked in sequence. The trench gate penetrates through the P+ region 40 and the N-well region 30 and extends into the drift region 20. The trench gate defines a channel region 1 and a non-channel region 2. Specifically, two first trench gates 51 define the channel region 1, and the second trench gate 52 and the first trench gate 51 define the non-channel region 2. In the channel region 1, a P-well region 60 is provided between the N-well region 30 and the P+ region 40. In the non-channel region 2, the P+ region 40 is located on both sides of the N-well region 30. The N-well region 30 located between the P+ regions 40 forms a Schottky contact with the emitter metal 70. By introducing a Schottky contact in the non-channel region in the present invention, the on-state voltage drop of the Schottky contact is less than 0.7V, the PN junction between the P-well region and the N-well region in the channel region can be short-circuited, the injection efficiency of the IGBT cell can be reduced, and thus the reverse recovery loss of the reverse-conducting IGBT can be reduced. In addition, in the non-channel region, P+ regions are provided on both sides of the N-well region, which can reduce the leakage current generated by the edge peak electric field of the Schottky diode and improve the performance of the device.

[0029] In this embodiment, in the channel region 1, an N+ region 80 is provided between the first trench gate 51 and the P+ region 40, and the N+ region 80 is provided on the same layer as the P+ region 40. That is, in the channel region 1, the N+ region 80 is located on the side of the P-well region 60 away from the N-well region 30, and the P+ region 40 is located between the N+ regions 80 (as Figure 1 shown). An ohmic contact is provided between the N+ region 80 and the emitter metal 70, and an ohmic contact is provided between the P+ region 40 in the channel region and the non-channel region and the emitter metal 70. An insulating layer 90 is provided between the first trench gate 51 and the emitter metal 70 and between the second trench gate 52 and the emitter metal 70.

[0030] In other embodiments of the present invention, refer to Figure 2, in the non-channel region 2, a Schottky contact is formed between the N-well region 30 and the emitter metal 70. And in the channel region 1, a third trench gate 53 is disposed between two first trench gates 51, and the third trench gate 53 is in contact with the emitter metal 70, that is, the third trench gate 53 is a grounded trench gate. The N+ region 80, the P+ region 40, and the P-well region 60 are located between the first trench gate 51 and the third trench gate 53. That is to say, the N+ region 80, the P+ region 40, and the P-well region 60 are disposed on both sides of the third trench gate 53. The N-well region 30 is located between the P-well region 60 and the third trench gate 53 and between the P+ region 40 and the third trench gate 53 and forms a Schottky contact with the emitter metal 70. That is to say, in the channel region, the N-well region located below the P-well region extends between the P-well region and the third trench gate and between the P+ region and the third trench gate, realizing the contact between the N-well region and the emitter metal and forming a Schottky contact. The above structure can integrate the Schottky diode and the IGBT cell more closely. On the one hand, it further enhances the short-circuit effect of the Schottky contact and further reduces the reverse recovery loss of the device. On the other hand, the introduction of the third trench gate reduces the distance between the two first trench gates, improves the carrier storage effect of the device, and reduces the on-state voltage drop of the device. Setting a grounded trench gate between the two first trench gates can connect the two parts of the channel region divided by the grounded trench gate, ensuring the consistency of the two divided parts.

[0031] In some embodiments of the present invention, the distance between the third trench gate 53 and the two first trench gates 51 is the same, further optimizing the performance of the device and improving the stability of the device performance.

[0032] In the present invention, the emitter metal 70 forms a Schottky contact with the N-well region and an ohmic contact with the N+ region and the P+ region. The material constituting the emitter metal 70 may include aluminum, titanium, gold, silver, or platinum to meet the performance of forming Schottky contacts and ohmic contacts with different regions respectively.

[0033] Reference Figure 1 and Figure 2 , the collector region includes a P+ collector region 11 and an N+ collector region 12. In the direction along the arrangement of multiple trench gates, the P+ collector region 11 and the N+ collector region 12 are arranged continuously and alternately. The P+ collector region 11 serves as the anode of the IGBT, and the N+ collector region 12 serves as the cathode of the FRD. The side of the collector region away from the drift region 20 is connected to the collector metal 110. A buffer layer 100 is disposed between the collector region and the drift region 20 to block the expansion of the depletion layer when the IGBT is in forward blocking.

[0034] In another aspect of the present invention, the present invention proposes a reverse-conducting insulated gate bipolar transistor. In some embodiments of the present invention, reference Figure 3, the reverse-conducting insulated gate bipolar transistor includes: a collector region (the P+ collector region 11 and the N+ collector region 12 shown in the figure), a drift region 20, an N-well region 30, a P+ region 40, and a plurality of trench gates. Among them, the collector region, the drift region 20, the N-well region 30, and the P+ region 40 are stacked in sequence. The trench gates penetrate through the P+ region 40 and the N-well region 30 and extend into the drift region 20. The trench gates include a first trench gate 51, a second trench gate 52, and a fourth trench gate 54. Two first trench gates 51 define a channel region 1, and the second trench gate 52 and the first trench gate 51 define a non-channel region 2. In the channel region 1, a P-well region 60 is arranged between the N-well region 30 and the P+ region 40. In the non-channel region 2, at least one fourth trench gate 54 is arranged between the second trench gate 52 and the second trench gate 51. The fourth trench gate 54 is in contact with the emitter metal 70, that is, the fourth trench gate is a grounded trench gate. The N-well region 30 is divided into a plurality of sub-N-well regions by the fourth trench gate 54, and the P+ region 40 is located on both sides of the sub-N-well regions. That is to say, P+ regions are arranged on both sides of each sub-N-well region. The sub-N-well region located between the P+ regions forms a Schottky contact with the emitter metal 70. By reducing the width of the Schottky contact in the non-channel region, the doping concentration of the N-well region can be enhanced, the breakdown voltage of the Schottky diode region can be improved, the leakage current of the Schottky diode can be further reduced, and introducing a Schottky contact in the non-channel region can short-circuit the PN junction between the P-well region and the N-well region in the channel region, reduce the hole injection efficiency on the front side of the device, reduce the reverse recovery loss of the device, and improve the overall performance of the device. Arranging a grounded trench gate between the second trench gate and the first trench gate can connect the multiple parts of the non-channel region divided by the grounded trench gate and ensure the consistency between the multiple divided parts.

[0035] In this embodiment, in the channel region 1, an N+ region 80 is arranged between the first trench gate 51 and the P+ region 40, and the N+ region 80 is arranged on the same layer as the P+ region 40. That is, in the channel region 1, the N+ region 80 is located on the side of the P-well region 60 away from the N-well region 30, and the P+ region 40 is located between the N+ regions 80 (as Figure 3 shown). There is an ohmic contact between the N+ region 80 and the emitter metal 70, and there is an ohmic contact between the P+ region 40 in the channel region and the non-channel region and the emitter metal 70. Insulating layers 90 are arranged between the first trench gate 51 and the emitter metal 70 and between the second trench gate 52 and the emitter metal 70.

[0036] In some embodiments of the present invention, one fourth trench gate 54 can be arranged between the second trench gate 52 and the first trench gate 51, or a plurality of fourth trench gates 54 can be arranged between the second trench gate 52 and the first trench gate 51. The distance between adjacent trench gates in the non-channel region can be the same as the distance between the two first trench gates in the channel region.

[0037] Alternatively, according to some preferred embodiments of the present invention, a plurality of fourth trench gates 54 arranged at equal intervals are provided between the second trench gate 52 and the first trench gate 51. The distance between two adjacent trench gates in the non-channel region can be 0.2 - 0.4 μm, for example, 0.2 μm, 0.3 μm, 0.4 μm. This can effectively reduce the reverse recovery loss of the device and reduce the leakage current of the Schottky diode, further optimizing the overall performance of the device.

[0038] In some other embodiments of the present invention, referring to Figure 4 , in the non-channel region 2, a plurality of fourth trench gates 54 are provided between the second trench gate 52 and the first trench gate 51. The multiple sub-N well regions formed by being divided by the fourth trench gates 54 form Schottky contacts with the emitter metal 70. And in the channel region 1, a third trench gate 53 is provided between two first trench gates 51. The third trench gate 53 is in contact with the emitter metal 70, that is, the third trench gate 53 is a grounded trench gate. The N+ region 80, P+ region 40, and P well region 60 are located between the first trench gate 51 and the third trench gate 53. That is to say, both sides of the third trench gate 53 are provided with the N+ region 80, P+ region 40, and P well region 60. The N well region 30 is located between the P well region 60 and the third trench gate 53 and between the P+ region 40 and the third trench gate 53 and forms a Schottky contact with the emitter metal 70. That is to say, in the channel region, the N well region located below the P well region extends between the P well region and the third trench gate and between the P+ region and the third trench gate, realizing the contact between the N well region and the emitter metal and forming a Schottky contact. The above structure can further integrate the Schottky diode and the IGBT cell closely. On the one hand, it further enhances the short-circuit effect of the Schottky contact, further reducing the reverse recovery loss of the device. On the other hand, it further reduces the leakage current of the Schottky diode. On the third hand, by introducing the third trench gate, the distance between two first trench gates is reduced, improving the carrier storage effect of the device, reducing the on-state voltage drop of the device, and enhancing the overall performance of the device.

[0039] In some embodiments of the present invention, the distance between the third trench gate 53 and the two first trench gates 51 is the same, further optimizing the performance of the device and improving the stability of the device performance.

[0040] In the present invention, the emitter metal 70 forms a Schottky contact with the N well region and an ohmic contact with the N+ region and P+ region. The material constituting the emitter metal 70 can include aluminum, titanium, gold, silver, or platinum to meet the performance of forming Schottky contacts and ohmic contacts with different regions respectively.

[0041] Referring to Figure 3 and Figure 4, the collector region includes a P+ collector region 11 and an N+ collector region 12. In the direction along the arrangement of multiple trench gates, the P+ collector region 11 and the N+ collector region 12 are arranged continuously and alternately. The P+ collector region 11 serves as the anode of the IGBT, and the N+ collector region 12 serves as the cathode of the FRD. The side of the collector region far from the drift region 20 is connected to the collector metal 110. A buffer layer 100 is provided between the collector region and the drift region 20 to block the expansion of the depletion layer when the IGBT is in forward blocking.

[0042] In another aspect of the present invention, the present invention proposes a reverse-conducting insulated gate bipolar transistor. In some embodiments of the present invention, referring to Figure 5 , the reverse-conducting insulated gate bipolar transistor includes: a collector region (the P+ collector region 11 and the N+ collector region 12 shown in the figure), a drift region 20, an N-well region 30, a P-well region 60, a P+ region 40, and multiple trench gates. Among them, the collector region, the drift region 20, the N-well region 30, the P-well region 60, and the P+ region 40 are stacked in sequence. The trench gates penetrate through the P+ region 40, the P-well region 60, the N-well region 30 and extend into the drift region 20. The trench gates include a first trench gate 51, a second trench gate 52, and a third trench gate 53. Two first trench gates 51 define a channel region 1. The second trench gate 52 and the first trench gate 51 define a non-channel region 2. In the channel region 1, an N+ region 80 is provided between the first trench gate 51 and the P+ region 40, and the N+ region 80 is arranged on the same layer as the P+ region 40. A third trench gate 53 is provided between the two first trench gates 51. The third trench gate 53 is in contact with the emitter metal 70, that is, the third trench gate 53 is a grounded trench gate. The N+ region 80, the P+ region 40, and the P-well region 60 are located between the first trench gate 51 and the third trench gate 53. That is to say, both sides of the third trench gate 53 are provided with the N+ region 80, the P+ region 40, and the P-well region 60. The N-well region 30 is located between the P-well region 60 and the third trench gate 53 and between the P+ region 40 and the third trench gate 53 and forms a Schottky contact with the emitter metal 70. That is to say, in the channel region, the N-well region located below the P-well region extends between the P-well region and the third trench gate and between the P+ region and the third trench gate to achieve the contact between the N-well region and the emitter metal and form a Schottky contact. By introducing a Schottky contact in the channel region, the PN junction between the P-well region and the N-well region in the channel region can be short-circuited, reducing the injection efficiency of the IGBT cell, thereby reducing the reverse recovery loss of the reverse-conducting IGBT. And by introducing the third trench gate, the distance between the two first trench gates is reduced, improving the carrier storage effect of the device, reducing the on-state voltage drop of the device, and improving the overall performance of the device.

[0043] In some embodiments of the present invention, the distance between the third trench gate 53 and the two first trench gates 51 is the same, further optimizing the performance of the device and improving the stability of the device performance.

[0044] In this embodiment, the non-channel region may have a conventional structure. Specifically, referring to Figure 5 , in the non-channel region 2, the N-well region 30, the P-well region 60, and the P+ region 40 are stacked in sequence. There is an ohmic contact between the P+ region 40 and the emitter metal 70.

[0045] In this embodiment, in the channel region 1, there is an ohmic contact between the N+ region 80 and the emitter metal 70, and there is an ohmic contact between the P+ region 40 and the emitter metal 70. An insulating layer 90 is provided between the first trench gate 51 and the emitter metal 70 and between the second trench gate 52 and the emitter metal 70.

[0046] In the present invention, the emitter metal 70 forms a Schottky contact with the N-well region and ohmic contacts with the N+ region and the P+ region. The material constituting the emitter metal 70 may include aluminum, titanium, gold, silver, or platinum to meet the performance of forming Schottky contacts and ohmic contacts with different regions respectively.

[0047] Referring to Figure 5 , the collector region includes a P+ collector region 11 and an N+ collector region 12. In the direction along the arrangement of multiple trench gates, the P+ collector region 11 and the N+ collector region 12 are arranged continuously and alternately. The P+ collector region 11 serves as the anode of the IGBT, and the N+ collector region 12 serves as the cathode of the FRD. The side of the collector region away from the drift region 20 is connected to the collector metal 110. A buffer layer 100 is provided between the collector region and the drift region 20 to block the expansion of the depletion layer during forward blocking of the IGBT.

[0048] In the description of the present invention, the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third", and "fourth" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0049] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0050] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. An inverse-conductance insulated gate bipolar transistor, characterized in that, it includes: a collector region, a drift region, an N-well region, a P+ region which are stacked in sequence, and a plurality of trench gates that penetrate the P+ region, the N-well region and extend to the drift region, the trench gates define a channel region and a non-channel region, and in the channel region, a P-well region is arranged between the N-well region and the P+ region, wherein, in the non-channel region, the P+ regions are located on both sides of the N-well region, and the N-well region between the P+ regions forms a Schottky contact with the emitter metal.

2. The inverse-conductance insulated gate bipolar transistor according to claim 1, characterized in that, the trench gates include a first trench gate, a second trench gate and a third trench gate, two of the first trench gates define the channel region, and the second trench gate and the first trench gate define the non-channel region, in the channel region, an N+ region is arranged between the first trench gate and the P+ region, and the N+ region is arranged on the same layer as the P+ region, a third trench gate is arranged between the two first trench gates, the third trench gate is in contact with the emitter metal, the N+ region, the P+ region, the P-well region are located between the first trench gate and the third trench gate, and the N-well region is located between the P-well region and the third trench gate and between the P+ region and the third trench gate and forms a Schottky contact with the emitter metal.

3. The inverse-conductance insulated gate bipolar transistor according to claim 2, characterized in that, the distances between the third trench gate and the two first trench gates are the same.

4. An inverse-conductance insulated gate bipolar transistor, characterized in that, it includes: a collector region, a drift region, an N-well region, a P+ region which are stacked in sequence, and a plurality of trench gates that penetrate the P+ region, the N-well region and extend to the drift region, the trench gates include a first trench gate, a second trench gate and a fourth trench gate, two of the first trench gates define a channel region, and the second trench gate and the first trench gate define a non-channel region, and in the channel region, a P-well region is arranged between the N-well region and the P+ region, wherein, in the non-channel region, at least one of the fourth trench gates is arranged between the second trench gate and the first trench gate, the fourth trench gate is in contact with the emitter metal, the N-well region is divided into a plurality of sub-N-well regions by the fourth trench gate, the P+ regions are located on both sides of the sub-N-well regions, and the sub-N-well region between the P+ regions forms a Schottky contact with the emitter metal.

5. The inverse-conductance insulated gate bipolar transistor according to claim 4, characterized in that, the distance between adjacent trench gates in the non-channel region is the same as the distance between the two first trench gates in the channel region.

6. The inverse-conductance insulated gate bipolar transistor according to claim 4, characterized in that, a plurality of the fourth trench gates arranged at equal intervals are arranged between the second trench gate and the first trench gate, and the distance between adjacent two trench gates in the non-channel region is 0.2 - 0.4 μm.

7. The reverse-conducting insulated gate bipolar transistor according to claim 4, characterized in that, in the channel region, an N+ region is provided between the first trench gate and the P+ region, and the N+ region is arranged on the same layer as the P+ region. The trench gate further includes a third trench gate, and the third trench gate is provided between the two first trench gates. The third trench gate is in contact with the emitter metal. The N+ region, the P+ region, and the P-well region are located between the first trench gate and the third trench gate. The N-well region is located between the P-well region and the third trench, and between the P+ region and the third trench gate, and forms a Schottky contact with the emitter metal.

8. The reverse-conducting insulated gate bipolar transistor according to claim 7, characterized in that, the distances between the third trench gate and the two first trench gates are the same.

9. A reverse-conducting insulated gate bipolar transistor, characterized in that, comprising: a collector region, a drift region, an N-well region, a P-well region, a P+ region which are sequentially stacked, and a plurality of trench gates penetrating through the P+ region, the P-well region, the N-well region and extending to the drift region. The trench gates include a first trench gate and a third trench gate, and the two first trench gates define a channel region, wherein, in the channel region, an N+ region is provided between the first trench gate and the P+ region, and the N+ region is arranged on the same layer as the P+ region. The third trench gate is provided between the two first trench gates. The third trench gate is in contact with the emitter metal. The N+ region, the P+ region, and the P-well region are located between the first trench gate and the third trench gate. The N-well region is located between the P-well region and the third trench, and between the P+ region and the third trench gate, and forms a Schottky contact with the emitter metal.

10. The reverse-conducting insulated gate bipolar transistor according to claim 9, characterized in that, the distances between the third trench gate and the two first trench gates are the same.

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