Array substrate, preparation method thereof and flexible electronic paper display panel

Abstract

The application discloses an array substrate and a preparation method thereof and a flexible electronic paper display panel, and mainly relates to the technical field of display. The array substrate is used in the flexible electronic paper display panel, and the array substrate comprises a plurality of pixel unit regions. Each pixel unit region is divided into a thickened region and a normal region. The array substrate further comprises a substrate, a first metal electrode, a first insulating protective layer and a second electrode. The first metal electrode, the first insulating protective layer and the second electrode are sequentially arranged on the substrate. The projection of the first metal electrode and the second electrode in one pixel unit region on the substrate is overlapped. The thickened region covers the boundary of the first metal electrode. The thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the normal region. Through the above design, the problem of gray scale decline in the partial region of the flexible electronic paper display panel is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its preparation method, and a flexible electronic paper display panel. Background Technology

[0002] With the development of digital technology, more and more display devices are entering people's lives, such as electronic paper (EP) display panels. Because flexible electronic paper display panels can maintain their display for a long time when the power is off, and have advantages such as being lightweight, thin, having low power consumption, and being simple to manufacture, they are becoming increasingly popular.

[0003] Current flexible electronic paper display panels can be rolled up and folded arbitrarily by using flexible substrates made of polyimide film. However, during use, repeated bending will cause a decrease in grayscale in some areas. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and its fabrication method, as well as a flexible electronic paper display panel, which avoids the problem of grayscale degradation in some areas of the flexible electronic paper display panel.

[0005] This application discloses an array substrate used in a flexible electronic paper display panel. The array substrate includes multiple pixel unit regions, each pixel unit region being divided into a thickened region and a regular region. The array substrate also includes a substrate, a first metal electrode, a first insulating protective layer, and a second electrode. The first metal electrode, the first insulating protective layer, and the second electrode are sequentially disposed on the substrate, and the projections of the first metal electrode and the second electrode on the substrate within a pixel unit region overlap. The thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region.

[0006] Optionally, the first insulating protective layer includes a first elastic layer and a first insulating layer, the first elastic layer being located between the first metal electrode and the first insulating layer, and the first elastic layer being located only in the thickened region, such that the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region.

[0007] Optionally, the first metal electrode is a common electrode, the second electrode is a pixel electrode, and the array substrate further includes a PV insulating layer. The common electrode, the first insulating protective layer, the PV insulating layer, and the pixel electrode are sequentially disposed on the substrate.

[0008] Optionally, the first metal electrode is a common electrode, the second electrode is a pixel electrode, and the array substrate further includes a GI insulating layer. The GI insulating layer, the common electrode, the first insulating protective layer, and the pixel electrode are sequentially disposed on the substrate.

[0009] Optionally, the first metal electrode is an auxiliary pixel electrode, the second electrode is a common electrode, and the array substrate further includes a second insulating protective layer and a pixel electrode. The auxiliary pixel electrode, the first insulating protective layer, the common electrode, the second insulating protective layer, and the pixel electrode are sequentially disposed on the substrate. The second insulating protective layer includes a second elastic layer and a second insulating layer, the second elastic layer being located between the second electrode and the second insulating layer, and the second elastic layer being located only in the thickened region.

[0010] Optionally, the thickness of the first elastic layer is 8000um~10000um, and the thickness of the first insulating layer is 3500um~4000um.

[0011] Optionally, the array substrate further includes an active switch, which includes a gate, a semiconductor layer, a source, and a drain. The gate is disposed in the same layer as the first metal electrode, and the source and drain are disposed in the same layer as the second electrode. The semiconductor layer is located between the first insulating protective layer and the source and drain. The region where the active switch is located within each pixel unit region is defined as the switch region. The switch region includes overlapping regions and non-overlapping regions. The region where the switch region partially overlaps with the thickened region is defined as the overlapping region. In the overlapping region, the distance between the semiconductor layer and the gate is greater than the distance between the semiconductor layer and the gate in the non-overlapping region. The active switch has the same on-state current in the overlapping region and the same on-state current in the non-overlapping region.

[0012] This application also discloses a method for fabricating an array substrate, the array substrate comprising multiple pixel unit regions, each pixel unit region being divided into a thickened region and a regular region; the method for fabricating the array substrate includes the following steps: A first metal electrode is formed on the substrate; A first insulating protective layer is formed on the first metal electrode, and the thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region. A second electrode is formed on the first insulating protective layer.

[0013] Optionally, the step of forming a first insulating protective layer on the first metal electrode, and the thickened region covering the boundary of the first metal electrode; wherein the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region includes: A first elastic layer is formed on the first metal electrode; A first insulating layer is formed on the first elastic layer; The first elastic layer is located only in the thickened area.

[0014] This application also discloses a flexible electronic paper display panel, which includes an electrophoretic reflective layer and an array substrate. The array substrate is used to drive the electrophoretic reflective layer to reflect light for displaying an image.

[0015] Compared to existing array substrate solutions, this application provides a first insulating protective layer. The thickness of the first insulating protective layer in the thickened area is greater than that in the conventional area. Simply put, the first insulating protective layer is thickened at the boundary where it covers the first metal electrode. This prevents the edge of the first metal electrode from bending and scratching the first insulating protective layer when the flexible electronic paper display panel is repeatedly bent, and prevents the storage capacitance in the pixel unit area from decreasing, thus avoiding the problem of grayscale reduction in some areas of the flexible electronic paper display panel. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of a flexible electronic paper display panel according to an embodiment of this application; Figure 2 This is a planar schematic diagram of a pixel unit region according to the first embodiment of this application; Figure 3 This is a schematic diagram of a first array substrate according to the first embodiment of this application; Figure 4 This is a schematic diagram of the second type of array substrate according to the first embodiment of this application; Figure 5 This is a planar schematic diagram of an active switch according to the first embodiment of this application; Figure 6 This is a schematic diagram of a cross-section of a semiconductor layer according to the first embodiment of this application; Figure 7 This is a schematic diagram of a dual-gate active switch according to the first embodiment of this application; Figure 8 This is a schematic diagram of an array substrate according to a second embodiment of this application; Figure 9 This is a schematic diagram of an array substrate according to a third embodiment of this application; Figure 10 This is a schematic diagram of an array substrate according to the fourth embodiment of this application; Figure 11 This is a schematic flowchart of a method for fabricating a first array substrate according to an embodiment of this application; Figure 12 This is a schematic diagram of the fabrication process of a first array substrate according to an embodiment of this application.

[0017] Among them, 10 is a flexible electronic paper display panel; 20 is an electrophoretic reflective layer; 21 is a microcapsule; 22 is a common electrode layer; 30 is an array substrate; 40 is a pixel unit area; 41 is a thickened area; 42 is a regular area; 43 is a switching area; 44 is an overlapping area; 45 is a non-overlapping area; 100 is a substrate; 110 is a first metal layer; 120 is a GI insulating layer; 130 is a second metal layer; 140 is a PV insulating layer; 150 is a pixel electrode layer; 210 is a first metal electrode; 220 is a second electrode; and 310 is a first insulating protective layer. ; 311, First elastic layer; 312, First insulating layer; 320, Second insulating protective layer; 321, Second elastic layer; 322, Second insulating layer; 410, Common electrode; 420, Pixel electrode; 430, Auxiliary pixel electrode; 510, Active switch; 520, Gate; 521, First sub-gate; 522, Second sub-gate; 530, Semiconductor layer; 531, First sub-semiconductor layer; 532, Second sub-semiconductor layer; 540, Source; 550, Connecting electrode; 560, Drain; 610, Data line; 620, Scan line. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0020] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0023] Figure 1 This is a schematic diagram of a flexible electronic paper display panel according to an embodiment of this application, as shown below. Figure 1 As shown, this application discloses a flexible electronic paper display panel 10, which includes an electrophoretic reflective layer 20 and an array substrate 30. The array substrate 30 is used to drive the electrophoretic reflective layer 20 to reflect light for displaying an image.

[0024] The electrophoretic reflective layer 20 can vary depending on the type of flexible electronic paper display panel 10. For example, it can be a microcapsule 21 type electrophoretic reflective layer 20 or a microcup type electrophoretic reflective layer 20. The electrophoretic reflective layer 20 can use electrophoretic particles and electrophoretic ink to reflect and absorb external light.

[0025] For example, this application uses the electrophoretic reflective layer 20 as an example of microcapsule 21 for explanation and description. Moreover, depending on the needs, the microcapsule 21 may include black particles, white particles, red particles, green particles, and blue particles, etc.

[0026] The flexible electronic paper display panel 10 also includes a common electrode layer 22, and an electric field is formed between the common electrode layer 22 and the pixel electrode layer 150 to drive the electrophoretic reflective layer 20 to absorb or reflect external light, thereby realizing the display of the image.

[0027] This application also discloses an array substrate 30, which can be used in the flexible electronic paper display panel 10 described above. Regarding the array substrate 30, this application provides the following design, which is specifically described through several embodiments: First embodiment: Figure 2 This is a planar schematic diagram of a pixel unit region according to the first embodiment of this application. Figure 3 This is a schematic diagram of the first array substrate according to the first embodiment of this application, as shown below. Figures 2-3 As shown, this application also discloses an array substrate 30, which is used in a flexible electronic paper display panel 10. The array substrate 30 includes a plurality of pixel unit regions 40, each of the pixel unit regions 40 being divided into a thickened region 41 and a regular region 42. The array substrate 30 also includes a substrate 100, a first metal electrode 210, a first insulating protective layer 310, and a second electrode 220. The first metal electrode 210, the first insulating protective layer 310, and the second electrode 220 are sequentially disposed on the substrate 100, and the projections of the first metal electrode 210 and the second electrode 220 on the substrate 100 within one pixel unit region 40 overlap.

[0028] The thickened region 41 covers the boundary of the first metal electrode 210; the thickness of the first insulating protective layer 310 in the thickened region 41 is greater than the thickness of the first insulating protective layer 310 in the conventional region 42. In other words, the first insulating protective layer 310 is thickened at the location of the thickened region 41.

[0029] The first metal electrode 210 is made of a metal material, for example, copper, and the second electrode 220 can be made of a metal material or a metal oxide material.

[0030] A storage capacitor is formed between the first metal electrode 210 and the second electrode 220. For example, since the charging speed of the pixel electrode 420 of the array substrate 30 is much greater than the moving speed of the particles in the microcapsule 21, the first metal electrode 210 needs to be set relatively large in each pixel unit region 40, so that the storage capacitor formed between the first metal electrode 210 and the second electrode 220 is also relatively large. The existing first metal electrode is linear, while the first metal electrode 210 in this application is block-shaped.

[0031] It is understandable that the existing array substrate 30 has an insulating layer between the first metal electrode 210 and the second electrode 220. When the flexible electronic paper display panel 10 is repeatedly bent, each film layer will shift to the left and right relative to the substrate 100 around the center line. Since the area of ​​the first metal electrode 210 is large, and the first metal electrode 210 is usually disposed on the first metal layer 110 or the second metal layer 130, the offset of the first metal electrode 210 is large when it is bent, and even edge warping may occur. This causes scratches on the insulating layer originally disposed between the first metal electrode 210 and the second electrode 220, resulting in leakage of the storage capacitor between the first metal electrode 210 and the second electrode 220. Even worse, it can cause breakdown of the first metal electrode 210 and the second electrode 220, resulting in the inability to store capacitors between the first metal electrode 210 and the second electrode 220. As a result, when the flexible electronic paper display panel 10 is displayed, the grayscale of the scratched area decreases.

[0032] Compared to the existing array substrate 30 solution, this application provides a first insulating protective layer 310. The thickness of the first insulating protective layer 310 in the thickened region 41 is greater than the thickness of the first insulating protective layer 310 in the conventional region 42. Simply put, the first insulating protective layer 310 is thickened at the boundary position where it covers the first metal electrode 210. This prevents the edge of the first metal electrode 210 from bending and scratching the first insulating protective layer 310 when the flexible electronic paper display panel 10 is repeatedly bent, and prevents the storage capacitance in the pixel unit region 40 from decreasing, thereby avoiding the problem of grayscale reduction in some areas of the flexible electronic paper display panel 10.

[0033] Furthermore, it can prevent moisture intrusion, thus avoiding corrosion of the first metal electrode 210 and the resulting display abnormalities.

[0034] For example, the first metal electrode 210 is a common electrode 410, the second electrode 220 is a pixel electrode 420, and the array substrate 30 further includes a PV insulating layer 140. The common electrode 410, the first insulating protective layer 310, the PV insulating layer 140 and the pixel electrode 420 are sequentially disposed on the substrate 100.

[0035] The array substrate 30 further includes a data line 610, a scan line 620, and an active switch 510. In this embodiment, the data line 610, the scan line 620, and the active switch 510 are all disposed on the substrate 100. The scan line 620 is connected to the gate 520 of the active switch 510, the data line 610 is connected to the source 540 of the active switch 510, and the pixel electrode 420 is connected to the drain 560 of the active switch 510.

[0036] It should be understood that a first metal layer 110, a first insulating protective layer 310, a second metal layer 130, a PV insulating layer 140 and a pixel electrode layer 150 are sequentially defined on the substrate 100. In this embodiment, the first metal electrode 210 is in the first metal layer 110 and the second electrode 220 is in the pixel electrode layer 150.

[0037] The active switch 510 includes a top-gate active switch 510 and a bottom-gate active switch 510. For example, when the active switch 510 is a top-gate active switch 510, the gate 520 of the active switch 510 and the first metal electrode 210, i.e., the common electrode 410, are located within the first metal layer 110. The source 540 and drain 560 of the active switch 510 are located within the second metal layer 130. The semiconductor layer 530 of the active switch 510 is located between the first insulating protective layer 310 and the second metal layer 130.

[0038] The thickened region 41 covers the boundary of the first metal electrode 210. For example, the thickened region 41 covers the boundary of the first metal electrode 210 and extends inward by 8um-10um, and covers the boundary of the first metal electrode 210 and extends outward by 8um-10um, thereby ensuring that the first metal electrode 210 falls completely within the orthographic projection of the thickened region 41.

[0039] For example, the thickened region 41 can completely cover the boundary of the entire first metal electrode 210, or it can avoid the location of the active switch 510 and only cover part of the boundary of the first metal electrode 210.

[0040] The thickness of the first insulating protective layer 310 in the normal region 42 is defined as d1, and the thickness of the first insulating protective layer 310 in the thickened region 41 is defined as d2, where d2 is greater than d1. In order to avoid the problem that the surface of the second metal layer 130 on the top of the first insulating protective layer 310 is uneven after the first insulating protective layer 310 is thickened in the thickened region 41, in this application, d2 = d1 + d3, where d3 is the thickness of the second metal layer 130. That is, in this embodiment, the thickness of the source 540 of the active switch 510 is d1, and the thickness of the drain 560 of the active switch 510 is d3.

[0041] See Figure 3 This application can make the thickness of the first insulating protective layer 310 in the thickened region 41 greater than the thickness of the first insulating protective layer 310 in the conventional region 42 through a process. Specifically, when preparing the first insulating protective layer 310, the thickened region 41 and the conventional region 42 can be irradiated separately using a halftone process. The tone level of the thickened region 41 is 30%-50%, and the tone level of the conventional region 42 is 0%-10%. In this way, the thickness of the first insulating protective layer 310 in the thickened region 41 will be greater than the thickness of the first insulating protective layer 310 in the conventional region 42.

[0042] Figure 4 This is a schematic diagram of the second type of array substrate according to the first embodiment of this application, as shown below. Figure 4 As shown, by way of example, this application can also make the thickness of the first insulating protective layer 310 in the thickened region 41 greater than the thickness of the conventional region 42 by adding a first elastic layer 311, as follows: The first insulating protective layer 310 includes a first elastic layer 311 and a first insulating layer 312. The first elastic layer 311 is located between the first metal electrode 210 and the first insulating layer 312, and the first elastic layer 311 is only located in the thickened region 41, such that the thickness of the first insulating protective layer 310 in the thickened region 41 is greater than the thickness of the first insulating protective layer 310 in the normal region 42.

[0043] In other words, the first elastic layer 311 covers the boundary of the first metal electrode 210 layer. In this embodiment, the first elastic layer 311 covers the boundary of the common electrode 410. It should be understood that the thickness of the first insulating protective layer 310 is uniform, the thickness of the first elastic layer 311 is 8000um~10000um, and the thickness of the first insulating layer 312 is 3500um~4000um.

[0044] The first elastic layer 311 includes a PS spacer material (Polystyrene, abbreviated as PS). Because the PS spacer material is elastic, when the flexible electronic paper display panel 10 is bent, the first metal electrode 210 shifts, squeezing the PS spacer material at the edge. The PS spacer material deforms under pressure. Then, when the flexible electronic paper display panel 10 returns to flatness, the PS spacer material recovers its deformation and acts back on the first metal electrode 210. Firstly, this can prevent the first metal electrode 210 from shifting and failing to return to its original position under repeated bending of the flexible electronic paper display panel 10, which would reduce the overlap area between the first metal electrode 210 and the second electrode 220, resulting in a smaller storage capacitance in the pixel unit area 40. Secondly, because the PS spacer material is elastic, it can absorb the shift of the first metal electrode 210, thereby preventing damage to the upper first insulating protective layer 310.

[0045] When the active switch 510 is a bottom-gate active switch 510, and the gate 520 of the active switch 510 is on the first metal layer 110, and the source 540 and drain 560 of the active switch 510 are on the second metal layer 130, especially in the flexible electronic paper display panel 10, the area of ​​the first metal electrode 210 is relatively large. Therefore, the first insulating protective layer 310 is thickened at the edge position corresponding to the first metal electrode 210. This will cause part of the semiconductor layer 530, source 540 and drain 560 of the active switch 510 to be raised. As a result, the distance between the gate 520 and the semiconductor layer 530 at the position raised by the first insulating protective layer 310 is greater than the distance between the gate 520 and the semiconductor layer 530 at the position not raised by the first insulating protective layer 310, thereby reducing the charging capability of the active switch 510.

[0046] Therefore, this application also improves the active switch 510, as follows: Figure 5 This is a planar schematic diagram of an active switch according to the first embodiment of this application. Figure 6 This is a schematic diagram of a cross-section of a semiconductor layer according to the first embodiment of this application, as shown. Figures 5-6 As shown, the array substrate 30 further includes an active switch 510, which includes a gate 520, a semiconductor layer 530, a source 540, and a drain 560. The gate 520 is disposed in the same layer as the first metal electrode 210, and the source 540 and drain 560 are disposed in the same layer as the second electrode 220. The semiconductor layer 530 is located between the first insulating protective layer 310 and the source 540 and drain 560.

[0047] The region where the active switch 510 is located within each pixel unit region 40 is defined as the switch region 43. The switch region 43 includes an overlapping region 44 and a non-overlapping region 45. The region where the switch region 43 partially overlaps with the thickened region 41 is defined as the overlapping region 44. In the overlapping region 44, the distance between the semiconductor layer 530 and the gate 520 is greater than the distance between the semiconductor layer 530 and the gate 520 in the non-overlapping region 45.

[0048] The on-state current of the active switch 510 in the overlapping region 44 is the same as the on-state current of the active switch 510 in the non-overlapping region 45.

[0049] The on-state current refers to the conduction current between the source 540 and the drain 560 when the same gate voltage is applied to the gate 520. Simply put, the thickened region 41 of the first insulating protective layer 310 extends to the overlapping region 44 of the active switch 510, causing the semiconductor layer 530 in the overlapping region 44 of the active switch 510 to be raised. That is, the distance between the semiconductor layer 530 in the overlapping region 44 and the gate 520 is greater than the distance between the semiconductor layer 530 and the gate 520 in the non-overlapping region 45.

[0050] As the distance between the gate 520 and the semiconductor layer 530 increases, the required turn-on voltage for the active switch 510 is also greater. Therefore, this application makes the on-state current of the active switch 510 in the overlapping region 44 the same as the on-state current of the active switch 510 in the non-overlapping region 45. This avoids reducing the area of ​​the first metal electrode 210, thus preventing a decrease in the storage capacitance within a single pixel unit region 40; and it also avoids increasing the voltage of the scan line 620, thus preventing an increase in the load on the flexible electronic paper display panel 10.

[0051] For example, the channel length of the active switch 510 corresponding to the semiconductor layer 530 in the overlapping region 44 is less than the channel length of the active switch 510 corresponding to the semiconductor layer 530 in the non-overlapping region 45. For instance, the channel length of the active switch 510 corresponding to the semiconductor layer 530 in the overlapping region 44 is 4.5 μm, and the channel length of the active switch 510 corresponding to the semiconductor layer 530 in the non-overlapping region 45 is 6 μm. This compensates for the problem of reduced charging capability of the active switch 510 caused by the thickened region 41 of the first insulating protective layer 310 in the overlapping region 44. This makes the on-state current of the active switch 510 in the overlapping region 44 the same as the on-state current of the active switch 510 in the non-overlapping region 45, and does not require additional processing steps.

[0052] For example, the molar ratio of Ca2+ doping in the semiconductor layer 530 of the active switch 510 in the overlapping region 44 is greater than the molar ratio of Ca2+ doping in the semiconductor layer 530 of the active switch 510 in the non-overlapping region 45. By doping the semiconductor layer 530 of the active switch 510 in the overlapping region 44 with Ca2+, the driving capability of the TFT active switch 510 in that region is improved. For example, the active switch 510 is doped with 3% molar ratio of Ca2+ in the semiconductor layer 530 of the overlapping region 44 and with 0.5% molar ratio of Ca2+ in the semiconductor layer 530 of the non-overlapping region 45. This makes the driving capability of the active switch 510 in the overlapping region 44 and the non-overlapping region 45 comparable, and the on-state current of the active switch 510 in the overlapping region 44 is the same as that in the non-overlapping region 45.

[0053] For example, the semiconductor layer 530 includes an active layer and an ohmic doped layer. The thickness of the active layer of the active switch 510 in the overlapping region 44 is greater than the thickness of the active layer of the active switch 510 in the non-overlapping region 45. For example, defining the original film thickness as 1800 Å to 2100 Å, the active switch 510 has the strongest driving capability when it is 35% to 40% of the original film thickness. The thickness of the active layer of the active switch 510 in the overlapping region 44 is 630 Å to 840 Å, and the thickness of the active layer of the active switch 510 in the non-overlapping region 45 is 540 Å to 630 Å. This allows the on-state current of the active switch 510 in the overlapping region 44 to be the same as the on-state current of the active switch 510 in the non-overlapping region 45.

[0054] Figure 7 This is a schematic diagram of a dual-gate active switch according to the first embodiment of this application, as shown below. Figure 7 As shown, the array substrate 30 further includes an active switch 510, which includes a gate 520, a semiconductor layer 530, a source 540, a connection electrode 550, and a drain 560. The gate 520 includes a first sub-gate 521 and a second sub-gate 522, and the semiconductor layer 530 includes a first sub-semiconductor layer 531 and a second sub-semiconductor layer 532. The first sub-gate 521 and the second sub-gate 522 are disposed in the same layer as the first metal electrode 210, and the source 540, the connection electrode 550, and the drain 560 are disposed in the same layer as the second electrode 220. The first sub-semiconductor layer 531 is located between the first insulating protective layer 310 and the source 540 and the connection electrode 550; the second sub-semiconductor layer 532 is located between the first insulating protective layer 310 and the connection electrode 550 and the drain 560.

[0055] The region where the active switch 510 is located within each pixel unit region 40 is defined as the switch region 43. The switch region 43 includes an overlapping region 44 and a non-overlapping region 45. The region where the switch region 43 partially overlaps with the thickened region 41 is defined as the overlapping region 44. In the overlapping region 44, the distance between the semiconductor layer 530 and the gate 520 is greater than the distance between the semiconductor layer 530 and the gate 520 in the non-overlapping region 45.

[0056] The on-state current of the active switch 510 in the overlapping region 44 is the same as the on-state current of the active switch 510 in the non-overlapping region 45.

[0057] In simple terms, for the flexible electronic paper display panel 10 with a dual-gate 520 structure, the active switch 510 occupies a larger area. Therefore, without reducing the area of ​​the first metal electrode 210, the overlapping area 44 of the flexible electronic paper display panel 10 with a dual-gate 520 structure will also be larger, which will have a greater impact on the charging capability of the active switch 510.

[0058] Therefore, by making the electron mobility of the active switch 510 in the overlapping region 44 semiconductor layer 530 greater than that in the non-overlapping region 45 semiconductor layer 530, it is not necessary to reduce the area of ​​the first metal electrode 210, thus avoiding a decrease in the storage capacitance within a single pixel unit region 40; nor is it necessary to increase the voltage of the scan line 620, thus avoiding an increase in the load on the flexible electronic paper display panel 10.

[0059] Example 2: Figure 8 This is a schematic diagram of an array substrate according to a second embodiment of this application, as shown below. Figure 8 As shown, unlike the first embodiment, this embodiment includes an auxiliary pixel electrode 430. Specifically, the array substrate 30 further includes an auxiliary pixel electrode 430, which is disposed between the first insulating protective layer 310 and the PV insulating layer 140, that is, the auxiliary pixel electrode 430 is located within the second metal layer 130, and the auxiliary pixel electrode 430 is connected to the second electrode 420.

[0060] One possibility is that the auxiliary pixel electrode 430 is directly connected to the second electrode 420 through a via. Another possibility is that the auxiliary pixel electrode 430 is connected to the drain 560 of the active switch 510. Since the second electrode 420 is also connected to the drain 560 of the active switch 510, the auxiliary pixel electrode 430 is connected to the second electrode 420 through the drain 560 of the active switch 510.

[0061] Compared to the solution in the first embodiment, this embodiment adds an auxiliary pixel electrode 430 in the second metal layer 130, which increases the storage capacitance between the sub-pixel electrode 420 and the first metal electrode 210, thereby increasing the size of the storage capacitance in the pixel unit region 40.

[0062] Example 3: Figure 9 This is a schematic diagram of an array substrate according to a third embodiment of this application, as shown below. Figure 9 As shown, unlike the first embodiment, the first metal electrode 210 is located within the second metal layer 130. Specifically, the first metal electrode 210 is a common electrode 410, the second electrode 220 is a pixel electrode 420, and the array substrate 30 further includes a GI insulating layer 120. The GI insulating layer 120, the common electrode 410, the first insulating protective layer 310, and the pixel electrode 420 are sequentially disposed on the substrate 100.

[0063] Compared to the solution in the first embodiment, this embodiment reduces the distance between the first metal electrode 210 and the second electrode 220 by placing the first metal electrode 210 inside the second metal layer 130, thereby increasing the storage capacitance in the pixel unit region 40.

[0064] Moreover, at this time, the first insulating protective layer 310 is located above the first metal electrode 210, and correspondingly above the semiconductor layer 530, source 540 and drain 560 of the active switch 510. Therefore, the semiconductor layer 530, source 540 and drain 560 of the active switch 510 will not be raised, and there is no need to reduce the area of ​​the first metal electrode 210. This will not cause the storage capacitance to become smaller, and there is no need to improve the active switch 510, thus saving process time and reducing manufacturing difficulty.

[0065] Example 4: Figure 10 This is a schematic diagram of an array substrate according to the fourth embodiment of this application, as shown below. Figure 10 As shown, unlike the first embodiment, the first metal electrode 210 is an auxiliary pixel electrode 430, the second electrode 220 is a common electrode 410, and the array substrate 30 further includes a second insulating protective layer 320 and a pixel electrode 420. The auxiliary pixel electrode 430, the first insulating protective layer 310, the common electrode 410, the second insulating protective layer 322, and the pixel electrode 420 are sequentially disposed on the substrate 100.

[0066] The second insulating protective layer 320 includes a second elastic layer 321 and a second insulating layer 322. The second elastic layer 321 is located between the second electrode 220 and the second insulating layer 322, and the second elastic layer 321 is only located in the thickened region 41. That is, the second elastic layer 321 covers the boundary of the second electrode 220. In this embodiment, the second elastic layer 321 covers the boundary of the common electrode 410.

[0067] Compared to the solution in the third embodiment, in this embodiment, a storage capacitor is formed between the first metal electrode 210 and the second electrode 220, and a capacitor is formed between the second electrode 220 and the pixel electrode 420, thereby increasing the storage capacitor size within a pixel unit region 40.

[0068] The second elastic layer 321 covers the boundary of the first metal electrode 210 layer. In this embodiment, the second elastic layer 321 covers the boundary of the auxiliary pixel electrode 430. It should be understood that the thickness of the second insulating protective layer 320 is uniform, the thickness of the second elastic layer 321 is 8000um~10000um, and the thickness of the second insulating layer 322 is 3500um~4000um.

[0069] The second elastic layer 321 includes a PS spacer material (Polystyrene, abbreviated as PS). Because the PS spacer material is elastic, when the flexible electronic paper display panel 10 is bent, the second electrode 220 shifts, squeezing the PS spacer material at the edge. The PS spacer material deforms under pressure. Then, when the flexible electronic paper display panel 10 returns to flatness, the PS spacer material recovers its deformation and acts back on the second electrode 220. Firstly, this can prevent the second electrode 220 from shifting and failing to return to its original position under repeated bending of the flexible electronic paper display panel 10, which would reduce the overlap area between the first metal electrode 210 and the second electrode 220, resulting in a smaller storage capacitance in the pixel unit region 40. Secondly, because the PS spacer material is elastic, it can absorb the shift of the second electrode 220, thereby preventing damage to the upper second insulating protective layer 320.

[0070] Figure 11 This is a schematic flowchart of a first method for fabricating an array substrate according to an embodiment of this application. Figure 12 This is a schematic diagram of the fabrication process of the first array substrate according to an embodiment of this application, as shown below. Figures 11-12 As shown, this application discloses a method for fabricating an array substrate 30, wherein the array substrate 30 includes a plurality of pixel unit regions 40, each pixel unit region 40 being divided into a thickened region 41 and a regular region 42; the method for fabricating the array substrate 30 includes the following steps: S1: Form a first metal electrode on the substrate; S2: A first insulating protective layer is formed on the first metal electrode, and the thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region; S3: A second electrode is formed on the first insulating protective layer.

[0071] Compared to the existing array substrate 30 solution, this application provides a first insulating protective layer 310. The thickness of the first insulating protective layer 310 in the thickened region 41 is greater than the thickness of the first insulating protective layer 310 in the conventional region 42. Simply put, the first insulating protective layer 310 is thickened at the boundary position where it covers the first metal electrode 210. This prevents the edge of the first metal electrode 210 from bending and scratching the first insulating protective layer 310 when the flexible electronic paper display panel 10 is repeatedly bent, and prevents the storage capacitance in the pixel unit region 40 from decreasing, thereby avoiding the problem of grayscale reduction in some areas of the flexible electronic paper display panel 10.

[0072] Furthermore, it can prevent moisture intrusion, thus avoiding corrosion of the first metal electrode 210 and the resulting display abnormalities.

[0073] S2: The step of forming a first insulating protective layer on the first metal electrode, wherein the thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region includes: S211: A first insulating protective layer of a first thickness is formed on the first metal layer; S212: The thickened area and the normal area are illuminated separately using a halftone process, wherein the tonal range of the thickened area is 0%-10% and the tonal range of the normal area is 40%-60%; S213: The first insulating protective layer is formed by etching to create a thickened region with a thickness greater than that of the conventional region.

[0074] The thickened area 41 of the first insulating protective layer 310 is thickened by using a halftone process, eliminating the need for two layers to add an extra process.

[0075] Of course, the thickness of the first insulating protective layer 310 in the thickened region 41 can also be increased by adding a first elastic layer 311, specifically as follows: S2: Forming a first insulating protective layer on the first metal electrode, and the thickened region covering the boundary of the first metal electrode; the step of the first insulating protective layer having a thickness greater in the thickened region than in the conventional region includes: S221: A first elastic layer is formed on the first metal electrode; S222: A first insulating layer is formed on the first elastic layer; The first elastic layer 311 is located only in the thickened region 41.

[0076] The first elastic layer 311 includes a PS spacer material (Polystyrene, abbreviated as PS). Because the PS spacer material is elastic, when the flexible electronic paper display panel 10 is bent, the first metal electrode 210 shifts, squeezing the PS spacer material at the edge. The PS spacer material deforms under pressure. Then, when the flexible electronic paper display panel 10 returns to flatness, the PS spacer material recovers its deformation and acts back on the first metal electrode 210. Firstly, this can prevent the first metal electrode 210 from shifting and failing to return to its original position under repeated bending of the flexible electronic paper display panel 10, which would reduce the overlap area between the first metal electrode 210 and the second electrode 220, resulting in a smaller storage capacitance in the pixel unit area 40. Secondly, because the PS spacer material is elastic, it can absorb the shift of the first metal electrode 210, thereby preventing damage to the upper first insulating protective layer 310.

[0077] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0078] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0079] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate, characterized in that, The array substrate is used in a flexible electronic paper display panel. The array substrate includes multiple pixel unit regions. Each pixel unit region is divided into a thickened region and a regular region. The array substrate also includes a substrate, a first metal electrode, a first insulating protective layer and a second electrode. The first metal electrode, the first insulating protective layer and the second electrode are sequentially disposed on the substrate, and the projections of the first metal electrode and the second electrode on the substrate in one pixel unit region overlap. The thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region; The array substrate further includes an active switch, which includes a gate, a semiconductor layer, a source, and a drain. The gate is disposed in the same layer as the first metal electrode, and the source and drain are disposed in the same layer as the second electrode. The semiconductor layer is located between the first insulating protective layer and the source and drain. The region where the active switch is located within each pixel unit region is defined as the switch region. The switch region includes overlapping regions and non-overlapping regions. The region where the switch region partially overlaps with the thickened region is defined as the overlapping region. In the overlapping region, the distance between the semiconductor layer and the gate is greater than the distance between the semiconductor layer and the gate in the non-overlapping region. The active switch has the same on-state current in the overlapping region and the same on-state current in the non-overlapping region.

2. The array substrate according to claim 1, characterized in that, The first insulating protective layer includes a first elastic layer and a first insulating layer. The first elastic layer is located between the first metal electrode and the first insulating layer, and the first elastic layer is only located in the thickened region, such that the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region.

3. The array substrate according to any one of claims 1 and 2, characterized in that, The first metal electrode is a common electrode, the second electrode is a pixel electrode, and the array substrate further includes a PV insulating layer. The common electrode, the first insulating protective layer, the PV insulating layer and the pixel electrode are sequentially disposed on the substrate.

4. The array substrate according to any one of claims 1 and 2, characterized in that, The first metal electrode is a common electrode, the second electrode is a pixel electrode, and the array substrate further includes a GI insulating layer. The GI insulating layer, the common electrode, the first insulating protective layer, and the pixel electrode are sequentially disposed on the substrate.

5. The array substrate according to any one of claims 1 and 2, characterized in that, The first metal electrode is an auxiliary pixel electrode, the second electrode is a common electrode, and the array substrate further includes a second insulating protective layer and a pixel electrode. The auxiliary pixel electrode, the first insulating protective layer, the common electrode, the second insulating protective layer and the pixel electrode are sequentially disposed on the substrate. The second insulating protective layer includes a second elastic layer and a second insulating layer, the second elastic layer being located between the second electrode and the second insulating layer, and the second elastic layer being located only in the thickened region.

6. The array substrate according to claim 2, characterized in that, The thickness of the first elastic layer is 8000um~10000um, and the thickness of the first insulating layer is 3500um~4000um.

7. A method for fabricating an array substrate, characterized in that, The array substrate includes multiple pixel unit regions, each pixel unit region being divided into a thickened region and a regular region; the method for fabricating the array substrate includes the following steps: A first metal electrode is formed on the substrate; A first insulating protective layer is formed on the first metal electrode, and the thickened region covers the boundary of the first metal electrode; the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region. A second electrode is formed on the first insulating protective layer.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The step of forming a first insulating protective layer on a first metal electrode, wherein the thickened region covers the boundary of the first metal electrode, and the thickness of the first insulating protective layer in the thickened region is greater than the thickness of the first insulating protective layer in the conventional region includes: A first elastic layer is formed on the first metal electrode; A first insulating layer is formed on the first elastic layer; The first elastic layer is located only in the thickened area.

9. A flexible electronic paper display panel, characterized in that, The flexible electronic paper display panel includes an electrophoretic reflective layer and an array substrate as described in any one of claims 1-6, wherein the array substrate is used to drive the electrophoretic reflective layer to reflect light for displaying an image.

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