Display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise a display area and a non-display area; in the display area, the display panel comprises pixel driving circuits arranged in an array and a plurality of data signal lines, and at least part of the pixel driving circuits in the same column are electrically connected with the same data signal line; in the non-display area, the display panel comprises an isolation compensation module; the isolation compensation module is electrically connected with each data signal line, and the isolation compensation module receives a first control signal and data signals of each data signal line; the isolation compensation module is used for controlling signal transmission paths of each data signal to corresponding data signal lines according to the first control signal; one data refresh period of the display panel comprises a data writing frame and a holding frame; in the holding frame, the first control signal comprises a non-enabled level, so that the transmission paths of each data signal to corresponding data signal lines are in an off state, the leakage current of the pixel driving circuit is effectively reduced, and the display uniformity is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, short videos, games, and other trending applications are widely popular. To meet the high-quality display requirements of short videos and games, high-frequency driving is used to make the display device's refresh rate higher. This results in the display device consuming more and more power and having a shorter battery life.

[0003] To ensure the battery life of display devices, a low-frequency driving method is used to reduce the refresh rate of the display device in certain application scenarios. For example, when the display panel displays static images, a lower refresh rate can be used to reduce power consumption.

[0004] When driven at low frequency, the data voltage needs to be maintained for a long time during a single data voltage write. Due to leakage issues in the display panel, the data voltage will change significantly, resulting in a large difference between the actual output brightness of the pixel and the preset output brightness. This will cause noticeable screen flickering or shaking during screen refresh, affecting the display effect and user experience of the display device. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve the low-frequency flicker problem of the display panel and enhance the display effect of the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a display area and a non-display area;

[0007] In the display area, the display panel includes: an array of pixel driving circuits and multiple data signal lines, wherein at least some of the pixel driving circuits located in the same column are electrically connected to the same data signal line;

[0008] In the non-display area, the display panel includes: an isolation compensation module; the isolation compensation module is electrically connected to each of the data signal lines, and the isolation compensation module receives a first control signal and data signals from each data signal line; the isolation compensation module is used to control the signal transmission path of each data signal to its corresponding data signal line according to the first control signal;

[0009] A data refresh cycle of the display panel includes a data write frame and a hold frame; in the hold frame, the first control signal includes a de-enabled level, such that the signal transmission path of each data signal to the corresponding data signal line is turned off.

[0010] According to another aspect of the present invention, a display device is provided, comprising: the display panel described above.

[0011] The display panel provided by this invention, by setting at least a portion of the pixel driving circuits located in the same column in the display area to be electrically connected to the same data signal line, allows each data signal line to provide data signals to at least a portion of the pixel driving circuits located in the same column. By setting an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives a first control signal and the data signals of each data signal line. The isolation compensation module can control the signal transmission path of each data signal to the corresponding data signal line according to the first control signal. During the hold frame of each data refresh cycle, the first control signal is controlled to include a non-enable level, so that the signal transmission path of each data signal to the corresponding data signal line is in a turned-off state. This allows the data signal line to maintain the preset data voltage written in the data write frame during the hold frame, which can effectively reduce the leakage current of the pixel driving circuit, make the voltage of the data signal output by the pixel driving circuit more stable, effectively improve the display uniformity, and improve the user experience of the display panel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art;

[0015] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 3 This is a driving timing diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0018] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0019] Figure 6This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 8 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0022] Figure 9 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0023] Figure 10 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0025] Figure 12 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0026] Figure 13 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0028] Figure 15 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0029] Figure 16 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0030] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0032] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art, such as... Figure 1 As shown, in the display panel, the pixel driving circuit 10' is electrically connected to the data signal line DL', and provides a data voltage Vdata' to the pixel driving circuit 10' through the data signal line DL'. During the data writing phase, the pixel driving circuit 10' is turned on, causing the data voltage Vdata' to be written into the pixel driving circuit 10' and stored, enabling the corresponding pixel to emit light. During the holding phase, the pixel driving circuit 10' is turned off and the data voltage Vdata' transmitted on the data signal line DL' is set to zero. The pixel driving circuit 10' continues to control the pixel to emit light through the stored data voltage Vdata'. At this time, the voltage difference between the end of the pixel driving circuit 10′ electrically connected to the pixel and the end electrically connected to the data signal line DL′ is large, causing the pixel driving circuit 10′ to continuously leak current. Furthermore, due to the long duration of the holding phase during low-frequency driving, the leakage current of the pixel circuit 10′ lasts for a long time, resulting in a large voltage change in the data voltage Vdata′. This leads to a large difference between the actual output brightness of the pixel and the preset output brightness, causing obvious screen flickering or shaking during screen refresh. This affects the display effect of the display device during low-frequency driving, thus affecting the user experience.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a display area and a non-display area; in the display area, the display panel includes: an array of pixel driving circuits and multiple data signal lines, wherein at least some of the pixel driving circuits located in the same column are electrically connected to the same data signal line; in the non-display area, the display panel includes: an isolation compensation module; the isolation compensation module is electrically connected to each data signal line, and the isolation compensation module receives a first control signal and data signals from each data signal line; the isolation compensation module is used to control the signal transmission path of each data signal to its corresponding data signal line according to the first control signal; a data refresh cycle of the display panel includes a data write frame and a hold frame; in the hold frame, the first control signal includes a de-enabled level, such that the transmission path of each data signal to its corresponding data signal line is in a turned-off state.

[0037] By adopting the above technical solution, at least some pixel driving circuits located in the same column in the display area are electrically connected to the same data signal line, so that each data signal line can provide data signals to at least some pixel driving circuits located in the same column. By setting an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives the first control signal and the data signals of each data signal line. The isolation compensation module can control the signal transmission path of each data signal to the corresponding data signal line according to the first control signal. During the holding frame of each data refresh cycle, the first control signal is controlled to include a non-enable level so that the signal transmission path of each data signal to the corresponding data signal line is in a turned-off state. This allows the data signal line to maintain the voltage corresponding to the data signal written in the data write frame during the holding frame, which can effectively reduce the leakage current of the pixel driving circuit, make the voltage of the data signal output by the pixel driving circuit more stable, effectively improve the display uniformity, and improve the user experience of the display panel.

[0038] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 2 As shown, the display panel 100 includes: a display area A1 and a non-display area A2; in the display area A1, the display panel 100 includes: an array of pixel driving circuits 10 and multiple data signal lines DL, at least some of the pixel driving circuits 10 located in the same column are electrically connected to the same data signal line DL; in the non-display area A2, the display panel 100 includes: an isolation compensation module 20; the isolation compensation module 20 is electrically connected to each data signal line DL, and the isolation compensation module 20 receives a first control signal VCT and data signals Vdata of each data signal line DL; the isolation compensation module 20 is used to control the signal transmission path of each data signal Vdata to the corresponding data signal line DL according to the first control signal VCT.

[0039] Specifically, an array of pixel driving circuits 10 is arranged in the display area A1 so that the display area A1 can realize the display function through the pixel driving circuits 10. In the display area A1, at least some of the pixel driving circuits 10 located in the same column can be electrically connected to the same data signal line DL, so that each data signal line DL can provide data signals to at least some of the pixel driving circuits 10 located in the same column. In a feasible embodiment, each pixel driving circuit 10 located in the same column can be electrically connected to the same data signal line DL. In this case, each data signal line DL can provide data signals to all the pixel driving circuits 10 located in the same column.

[0040] In the non-display area A2, an isolation compensation module 20 can be installed. The isolation compensation module 20 may include a control terminal, input terminals corresponding one-to-one with each data signal line DL, and output terminals corresponding one-to-one with each data signal line DL. The control terminal of the isolation compensation module 20 receives a first control signal VCT. Each input terminal of the isolation compensation module 20 receives the data signal Vdata to be transmitted to each data signal line DL, and each output terminal of the isolation compensation module 20 is electrically connected to its corresponding data signal line DL. The isolation compensation module 20 can be turned on or off under the control of the first control signal VCT. When on, it enables the signal transmission path of each data signal Vdata to its corresponding data signal line DL to be open, thus transmitting the data signal Vdata to the corresponding data signal line DL. When the isolation compensation module 20 is turned off, it disconnects the signal transmission path of each data signal Vdata to its corresponding data signal line DL, preventing the data signal Vdata from being transmitted to the corresponding data signal line DL.

[0041] For example, assuming the display panel includes N data signal lines DL, then along the arrangement direction of each data signal line DL, the data signal Vdata received by each data signal line DL can be a first data signal Vdata1, a second data signal Vdata2, a third data signal Vdata3, ..., an (N-1)th data signal VdataN-1, and an Nth data signal VdataN. The data signal Vdata provided to each data signal line DL can be set according to display requirements, and can be the same or different; this embodiment of the invention does not specifically limit this.

[0042] Figure 3 This is a driving timing diagram of a pixel driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 and Figure 3A data refresh cycle T of the display panel 100 includes a data write frame T1 and a hold frame T2; in the hold frame T2, the first control signal VCT includes a disabled level so that the signal transmission path of each data signal Vdata to the corresponding data signal line DL is turned off.

[0043] Specifically, the data write frame T1 can be a stage in which the pixel driving circuit 10 remains on, so that the data signal Vdata on the data signal line DL can be written to the pixel driving circuit 10 and stored. In the data write frame T1, the first control signal VCT can be at an enabled level for at least a portion of the time, so that the isolation compensation module 20 is turned on, so that each data signal Vdata can be written to the corresponding data signal line DL when the isolation compensation module 20 is turned on, so that each data signal line DL can transmit the data signal Vdata to the electrically connected pixel driving circuit 10. During this stage, the pixel driving circuit 10 can be controlled to be turned on at the same time, so that the pixel driving circuit 10 can drive the pixel to emit light according to the data signal Vdata and store the data signal Vdata.

[0044] After entering the hold frame T2, the data signals Vdata received by the isolation compensation module 20 can be set to zero to reduce the charging time to the data signal line DL. At the same time, the pixel driving circuit 10 can be turned off. At this time, the pixel driving circuit 10 drives the pixel to continue emitting light according to the stored data signal Vdata, which can reduce power consumption while ensuring the display of the image.

[0045] It is understood that for non-self-emissive liquid crystal display panels, the pixel driving circuit 10 can drive the liquid crystal molecules to deflect according to the data signal Vdata. Different data signals Vdata result in different deflection angles of the liquid crystal molecules in the corresponding pixels, thus causing different light emission brightness of the pixels. Therefore, pixels have different light emission brightness under the control of different data signals Vdata. For self-emissive display panels including light-emitting elements, the pixel driving circuit can generate a driving current for driving the light-emitting elements to emit light according to the data signal Vdata. The light-emitting elements in the pixels emit light according to the driving current. Different data signals Vdata result in different driving currents generated by the pixel driving circuit, thus causing different light emission brightness of the light-emitting elements in the pixels. This embodiment of the invention does not specifically limit the type of display panel. For ease of understanding, this embodiment of the invention only exemplifies the technical solution of the invention using a non-self-emissive liquid crystal display panel as an example.

[0046] For example, Figure 4 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention, specifically a schematic diagram of a pixel driving circuit in a liquid crystal display panel, as shown below. Figure 4As shown, the pixel driving circuit 10 includes a driving transistor T0 and a pixel capacitor C0; the gate of the driving transistor T0 receives the scan signal Gout, the first terminal of the driving transistor T0 is electrically connected to the data signal line DL, and the second terminal of the driving transistor T0 is electrically connected to the pixel capacitor C0.

[0047] Specifically, the voltage value of the pixel capacitor C0 is the pixel voltage value. The driving transistor T0 can be turned on or off under the control of the scan signal. When on, it transmits the data signal Vdata received at its first electrode to its second electrode, thus writing the data signal Vdata into the pixel capacitor C0 for storage, allowing the pixel to emit light based on this data signal Vdata. After the data signal Vdata is written into the pixel capacitor C0, the driving transistor T0 can be turned off, allowing the pixel to continue emitting light based on the data signal Vdata stored in the pixel capacitor C0, thus allowing the current display image to continue. If the data signal Vdata on the data signal line DL is set to zero at this time, the voltage difference between the first and second electrodes of the driving transistor T0 will be large, causing leakage current in the driving transistor T0. For example, if the data signal Vdata written to the pixel capacitor C0 is 2.7V, then if the data signal Vdata on the data signal line DL is set to zero, the high voltage at the second terminal of the driving transistor T0 will gradually leak to the low potential at the first terminal, thereby causing the voltage of the pixel capacitor C0 to gradually decrease and the brightness of the pixel to gradually decrease. Alternatively, if the data signal Vdata written to the pixel capacitor C0 is -2.7V, then if the data signal Vdata on the data signal line DL is set to zero, the high voltage at the first terminal of the driving transistor T0 will gradually leak to the low potential at the second terminal, thereby causing the voltage of the pixel capacitor C0 to gradually increase and the brightness of the pixel to gradually decrease. Furthermore, the longer hold frame T2 in low-frequency drive mode results in a longer leakage time, causing a significant difference between the voltage at the second electrode of the drive transistor T0 (i.e., the voltage of the pixel capacitor C0) and the voltage of the data signal Vdata written in the data write frame T1. This leads to a substantial reduction in the pixel's output brightness. Consequently, the pixel's output brightness is significantly reduced in the initial and final stages within the same data refresh cycle T. When the same display screen is refreshed multiple times, the pixel's output brightness will also change abruptly when the data signal Vdata is rewritten in the data write frame T1, resulting in noticeable screen flickering or shaking, which affects the user experience.

[0048] Based on the above issues, in holding frame T2, the first control signal VCT may include a disabled level to control the isolation compensation module 20 to be turned off. Then, the zero potential of each data signal Vdata will not be transmitted to each data signal line DL, so that the data signal line DL can be maintained as the data signal Vdata written in data writing frame T1. Assuming that the data signal Vdata provided to the data signal line DL in data write frame T1 is a preset data voltage Vd0, then in hold frame T2, both the output data signal Vdata and the received data signal Vdata of the pixel driving circuit 10 are kept at the preset data voltage Vd0. That is, the first and second terminals of the driving transistor T0 are both at the preset data voltage Vd0, which effectively reduces the voltage difference across the driving transistor T0 in the pixel driving circuit 10, thereby effectively reducing the leakage current of the driving transistor T0 in the pixel driving circuit 10. This makes the voltage of the pixel capacitor C0 in the pixel driving circuit 10 more stable, thereby effectively reducing the difference between the brightness of the pixel at the end of hold frame T2 and the brightness of the pixel at the end of data write frame T1. This effectively improves the screen flickering or jittering phenomenon during screen refresh, effectively improves the display uniformity, especially effectively improves the display uniformity of the display device when driven at low frequency, which is beneficial to improving the user experience.

[0049] For example, in conjunction with reference Figure 2 , Figure 3 and Figure 4 The moment when the first control signal VCT changes from an enabled level to an disabled level is the first moment t1; the first moment t1 is the same moment as the moment when the data signal Vdata is set to zero, t2. In this way, the isolation compensation module 20 can be turned off simultaneously when the data signal Vdata is set to zero, which can prevent the zero potential of the data signal Vdata from being written to the data signal line DL. This can prevent the voltage difference across the pixel driving circuit 10 from being too large and causing leakage, that is, it can prevent the voltage difference between the first and second terminals of the driving transistor T0 from being too large, which can prevent screen shaking or flickering during low-frequency driving and improve the uniformity of display during low-frequency driving.

[0050] or, Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 2 , Figure 3 and Figure 5 The moment when the first control signal VCT transitions from an enabled level to an disabled level is the first time t1, which is before the time t2 when the data signal Vdata is set to zero. This ensures that the isolation compensation module 20 is turned off before the data signal Vdata is set to zero, thus preventing the zero potential of the data signal Vdata from being written to the data signal line DL. This avoids screen flickering or jitter during low-frequency driving and improves the uniformity of the display during low-frequency driving.

[0051] For example, the first terminal of the driving transistor T0 can be set to the drain, the second terminal to the source, and the control terminal to the gate. Furthermore, the driving transistor T0 can be either a P-type MOS transistor or an N-type MOS transistor; this embodiment of the invention does not specifically limit this. When the driving transistor T0 is a P-type MOS transistor, its enable level is low and its disable level is high; that is, when the scan signal Gout is low, the driving transistor T0 is turned on, and when the scan signal Gout is high, the driving transistor T0 is turned off. When the driving transistor T0 is an N-type MOS transistor, its enable level is high and its disable level is low; that is, when the scan signal Gout is high, the driving transistor T0 is turned on, and when the scan signal Gout is low, the driving transistor T0 is turned off. Unless otherwise specified, the following embodiments use an N-type MOS transistor as the driving transistor T0 to explain the technical solution of the present invention.

[0052] For example, refer to Figure 2 In the display area A1, the display panel 100 also includes a scan signal line SCAN; at least some of the pixel driving circuits 10 located in the same row are electrically connected to the same scan signal line SCAN. This enables line-by-line scanning of each pixel driving circuit 10 in the display area A1, allowing each pixel driving circuit 10 to refresh data line by line. Furthermore, a shift register circuit (not shown in the figure) can be provided in the non-display area A2, through which a sequentially shifted scan signal Gout is output to each scan signal line SCAN to achieve line-by-line scanning of each pixel driving circuit 10.

[0053] The display panel provided in this embodiment of the invention, by setting at least a portion of the pixel driving circuits located in the same column in the display area to be electrically connected to the same data signal line, allows each data signal line to provide data signals to at least a portion of the pixel driving circuits located in the same column. By setting an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives a first control signal and the data signals of each data signal line. The isolation compensation module can control the signal transmission path of each data signal to the corresponding data signal line according to the first control signal. During the holding frame of each data refresh cycle, the first control signal is controlled to include a non-enable level, so that the signal transmission path of each data signal to the corresponding data signal line is in a turned-off state. This allows the data signal line to maintain the preset data voltage written in the data write frame during the holding frame, which can effectively reduce the leakage current of the pixel driving circuit, make the voltage of the data signal output by the pixel driving circuit more stable, effectively improve the display uniformity, and improve the user experience of the display panel.

[0054] For example, refer to Figure 3In two adjacent data refresh cycles T, the polarity of the data signal Vdata provided to the data signal line DL can be different, so that when the pixel includes a liquid crystal layer, flexible control of the liquid crystal molecules in the liquid crystal layer can be guaranteed.

[0055] Optional, Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 6 As shown, the isolation compensation module 20 includes a switch unit 21 corresponding to each data signal line DL; the control terminal of the switch unit 21 receives a first control signal VCT, the first terminal of the switch unit 21 receives a data signal Vdata, and the second terminal of the switch unit 21 is electrically connected to the corresponding data signal line DL.

[0056] Specifically, each data signal line DL can be equipped with a corresponding switch unit 21, so that each data signal Vdata can be transmitted to the corresponding data signal line DL through a separate channel, thus avoiding signal crosstalk. The first control signal VCT can be transmitted through the control signal line L0, and the control terminal of each switch unit 21 is electrically connected to the control signal line L0. Therefore, the first control signal VCT transmitted through the control signal line L0 can control the switching unit 21 to be turned on or off.

[0057] Optional, Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 7 As shown, the switching unit 21 includes a switching transistor T1; the first terminal of the switching transistor T1 receives a data signal Vdata, the second terminal of the switching transistor T1 is electrically connected to the corresponding data signal line DL, and the gate of the switching transistor T1 receives a first control signal VCT.

[0058] Specifically, the gates of the switching transistors T1 in each switching unit 21 are electrically connected to the control signal line L0, and can be turned on or off under the control of the first control signal VCT transmitted through the control signal line L0. Taking one of the switching transistors T1 as an example, when the first control signal VCT controls the switching transistor T1 to turn on, the data signal Vdata received by its first electrode can be transmitted to the data signal line DL electrically connected to its second electrode. When the first control signal VCT controls the switching transistor T1 to turn off, the data signal Vdata received by its first electrode cannot be transmitted to the data signal line DL electrically connected to its second electrode.

[0059] Optional, see reference Figure 3 or Figure 5During the phase when the first control signal VCT remains at an inactive level, each data signal Vdata includes a first voltage V1. The first voltage V1 is the initial voltage of the data signal Vdata. In a preferred embodiment, the first voltage can be 0V, meaning that during the phase when the first control signal VCT remains at an inactive level, the data signal Vdata can be set to zero. This reduces the time that the data signal Vdata output by the driver IC remains at a high voltage, thereby effectively reducing power consumption.

[0060] Optional, Figure 8 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 , Figure 4 and Figure 8 During hold frame T2, the first control signal VCT includes an active pulse EP; between two adjacent active pulses EP, the first control signal VCT is at a disabled level; during the active pulse phase of the first control signal VCT, each data signal Vdata is a compensation voltage Vd1 corresponding to each data signal line DL.

[0061] Specifically, in the display panel 100, the data signal line DL may have parasitic capacitance with other signal lines or components. When the driving transistor T0 in the pixel driving circuit 10 of the holding frame T2 is turned off, and the switching units 21 in the isolation compensation module 20 are turned off, the voltage stored on the data signal line DL may leak through the parasitic capacitance, causing a change in the data signal Vdata on the data signal line DL. This also causes an imbalance in the voltage between the first and second terminals of the driving transistor T0 in the pixel driving circuit 10, resulting in leakage and affecting the accuracy of pixel light output. Therefore, in the holding frame T2, the first control signal VCT can be controlled to output a valid pulse EP. During the period when the first control signal VCT outputs a valid pulse EP, the compensation voltage Vd1 for each data signal Vdata can be controlled. The compensation voltage Vd1 is related to the data signal Vdata during the data writing stage, so that the voltage compensation for the data signal Vdata on each data signal line DL meets the display requirements of the corresponding pixel. This further reduces the leakage current of the driving transistor T0, thereby further improving screen flicker and dizziness.

[0062] Optional, Figure 9 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 , Figure 4 and Figure 9 In data writing frame T1, the data signal Vdata is the preset data voltage Vd0; the absolute value of the compensation voltage Vd1 is greater than the absolute value of the preset data voltage Vd0.

[0063] Specifically, the displayed image has corresponding grayscale data, which is represented by the data voltage of the data signal Vdata. Data write frame T1 provides a preset data voltage Vd0 to each corresponding pixel based on the grayscale data of the current displayed image, so that each pixel emits light according to the received preset data voltage Vd0, enabling accurate image display. In hold frame T2, since the driving transistor T0 is in the off state, to avoid leakage current from the driving transistor T0 affecting the accuracy of light emission, voltage compensation can be performed on the pixel capacitor C0. To perform voltage compensation on the pixel capacitor C0 electrically connected to the second terminal of the driving transistor T0 to ensure accurate light emission, the absolute value of the compensation voltage Vd1 provided to the first terminal of the driving transistor T0 can be greater than the absolute value of the preset data voltage Vd0 provided by data write frame T1 to the data signal line DL, i.e., |Vd1| > |Vd0|. In this way, it is possible to prevent leakage current caused by excessive voltage difference between the first and second terminals of the driving transistor T0, so that the voltage between the first and second terminals of the driving transistor T0 gradually balances, thereby achieving voltage compensation for the pixel capacitor C0 and ensuring accurate light output from the pixel.

[0064] Optional, Figure 10 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 , Figure 4 and Figure 10 The absolute value of the compensation voltage Vd1 is less than the absolute value of the pulse voltage VEP of the first control signal.

[0065] Specifically, during frame T2, the pulse voltage VEP when the first control signal VCT outputs a valid pulse EP can be greater than the compensation voltage Vd1. This larger pulse voltage VEP ensures that each switching transistor T1 in the isolation compensation module 20 is fully turned on quickly, thereby increasing the charging speed of the compensation voltage Vd1 onto the data signal line DL. This allows the voltage on the data signal line DL to quickly reach the voltage value corresponding to the compensation voltage Vd1, thus enabling timely voltage compensation of the pixel capacitor C0 in the pixel driving circuit 10 and effectively ensuring accurate light output from the pixel.

[0066] Optional, Figure 11 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, for reference. Figures 8-11 In any of the attached figures, during hold frame T2, the first control signal VCT includes N1 valid pulses EP, where N1 ≥ 1 and N1 is an integer.

[0067] in, Figures 8-10 This shows that when N1=1, meaning the first control signal VCT in hold frame T2 includes one valid pulse, voltage compensation can be performed on the pixel once in hold frame T2 to improve the accuracy of pixel light output. (Reference) Figure 11 Alternatively, N1 can be set to be greater than 1, meaning that the first control signal VCT in the hold frame T2 includes multiple valid pulses. In this way, the data signal line DL can be provided with multiple compensation voltages Vd1 in the hold frame T2, thereby enabling multiple voltage compensations for the pixels. This further ensures the accuracy of pixel light output when the hold frame T2 lasts for a long time.

[0068] Understandable, Figure 11 An example is shown where N1 = 3, that is, the first control signal VCT in hold frame T2 includes 3 valid pulses. It is understood that in other feasible embodiments of the present invention, N1 can also be set to 2 or N1 > 3, so that the number of valid pulses EP of the first control signal VCT in hold frame T2 is 2 or more than 3. The specific value of N1 can be determined according to the duration of hold frame T2 and the pulse width of the first control signal VCT. The embodiments of the present invention do not specifically limit this.

[0069] Optional, Figure 12 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, for reference. Figure 12 ,refer to Figure 3 , Figure 5 and Figures 8-12 In any of the attached figures, in the data write frame T1, the first control signal VCT includes N2 valid pulses, where N2≥1 and N1 is an integer.

[0070] Specifically, Figure 3 , Figure 5 and Figures 8-11 The diagram shows that N2=1, which means that the first control signal VCT of the data writing frame T1 includes one valid pulse. In this case, the pulse width of the valid pulse can be large so that the conduction time of each switching transistor T1 in the isolation compensation module 20 is longer, thereby ensuring that each data signal Vdata is fully written into the corresponding data signal line DL during the conduction phase of the switching transistor T1.

[0071] For example, refer to Figure 3 and Figures 8-11 In any of the attached figures, N2 = 1; during data writing frame T1, the pulse width of the first control signal VCT is equal to the duration of data writing frame T1. This further ensures that each data signal Vdata is fully written to the corresponding data signal line DL during the period when the switching transistor T1 is turned on, thereby further guaranteeing the accuracy of pixel light output.

[0072] Or, refer to Figure 12Furthermore, N2 can be set to >1, ensuring that the first control signal VCT in the data write frame T1 includes multiple valid pulses. In this case, since the data signal Vdata remains at the preset data voltage Vd0 in the data write frame T1, when the first control signal VCT includes multiple valid pulses in the data write frame T1, the switching transistors T1 in the isolation compensation module 20 can be turned on multiple times. This allows the data signal Vdata of the first electrode to be transmitted to the corresponding data signal line DL each time it is turned on. Thus, through multiple turns, the voltage on the data signal line DL can reach the preset data voltage Vd0, and through multiple charging operations, the voltage of the pixel capacitor C0 can reach the preset data voltage Vd0, thereby driving the pixel to accurately emit light.

[0073] For example, when the first control signal VCT includes multiple valid pulses in the data write frame T1, since the driving transistor T0 is in the on state, the pulse voltage of the first control signal VCT in the data write frame T1 can be less than the pulse voltage in the hold frame T1. After the voltage of the data signal line DL reaches the preset data voltage Vd0 through multiple charging, the preset data voltage Vd0 can be written to the pixel capacitor C0 through the driving transistor T0. Alternatively, Figure 13 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, for reference. Figure 13 The pulse voltage of the first control signal VCT in the data write frame T1 can be equal to the pulse voltage in the hold frame T1, so as to drive the switching transistor T1 to turn on completely at a faster speed, thereby increasing the charging speed of the data signal Vdata to the data signal line DL.

[0074] Optional, Figure 14 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 14 As shown, N1≥2 and N2≥2; the pulse width of the first control signal VCT in holding frame T2 is greater than the pulse width in data writing frame T1.

[0075] Specifically, compared to the situation where the data signal Vdata in the data write frame T1 is continuously maintained at the preset data voltage Vd0, and the voltage of the data signal line DL can reach the preset data voltage Vd0 by controlling the switching transistor T1 to be turned on multiple times, the data signal Vdata in the hold frame T2 can only jump from zero voltage to compensation voltage Vd1 when the switching transistor T1 is turned on. At this time, the data signal Vdata has a charging process from zero voltage to compensation voltage Vd1. Therefore, setting the pulse width of the first control signal VCT in the hold frame T2 to be greater than the pulse width in the data write frame T1 can ensure that each switching transistor T1 in the isolation switching module 20 in the hold frame T2 fully writes the received compensation voltage Vd1 to the data signal line DL, thereby ensuring that the compensation voltage Vd1 received by the data signal line DL can effectively compensate the voltage of the pixel.

[0076] For example, refer to Figure 12 or Figure 13 When N1 = 1 and N2 ≥ 2, the pulse width of the first control signal VCT in the holding frame T2 can be greater than the pulse width in the data writing frame T1. This also ensures that each switching transistor T1 in the isolation switch module 20 in the holding frame T2 fully writes the received compensation voltage Vd1 to the data signal line DL, thus ensuring voltage compensation for the pixel.

[0077] Optional, Figure 15 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, such as... Figure 15 As shown, N1≥2; in the same holding frame T2, when the first control signal VCT outputs each valid pulse EP, the compensation voltage Vd1 received by the same data signal line DL is different.

[0078] Specifically, due to signal interference from other signal lines or components, the leakage current of the data signal line Vdata varies at different stages of the holding frame T2, and the preset data voltage Vd0 written by each data signal line DL in the data writing frame T1 may also be different. Therefore, when the first control signal VCT outputs multiple valid pulses EP, the compensation voltage Vd1 provided to the data signal line DL can be set to be different, so that the compensation voltage Vd1 received by the data signal line DL can compensate the voltage of the pixel capacitor C0 to the preset data voltage Vd0, thereby ensuring the accuracy of pixel light output. The compensation voltage Vd1 provided to the data signal line DL each time can be calibrated according to the leakage current of the data signal line Vdata at different stages of the holding frame T2 and the preset data voltage Vd0 written in the data writing frame T1. This embodiment of the invention does not specifically limit this.

[0079] Optional, Figure 16 This is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present invention, for reference. Figures 8 to 16In any of the attached figures, during hold frame T2, the data signal Vdata further includes N3 compensation voltages Vd1, where N3 ≥ 1 and N3 is an integer; the data signal Vdata between two adjacent compensation voltages Vd1 is the first voltage; when the data signal Vdata is the compensation voltage Vd1, the first control signal VCT includes N4 valid pulses, where N4 ≥ 1 and N4 is an integer; the first control signal VCT between two adjacent valid pulses is at the disabled level.

[0080] For details, please refer to the following: Figures 8-15 In any of the attached figures, during the stage when the data signal Vdata of frame T2 is held at the compensation voltage Vd1, the first control signal VCT may include one effective pulse EP, i.e., N4=1. When the effective pulse EP of the first control signal VCT controls the switching transistors T1 in the isolation compensation module 20 to be turned on, the compensation voltage Vd1 can be transmitted to the corresponding data signal line DL through the turned-on switching transistors T1.

[0081] Or refer to Figure 16 During the hold frame T2 data signal Vdata being held at the compensation voltage Vd1 for a period of time (ta), the first control signal VCT can include multiple valid pulses EP, i.e., N4 > 1. This allows the switching transistors T1 in the isolation compensation module 20 to be turned on multiple times, providing the compensation voltage Vd1 to the data signal line DL multiple times. This avoids large voltage fluctuations on the data signal line DL due to leakage current, thereby preventing leakage current from the driving transistor T0 in the pixel driving circuit 10 and ensuring the accuracy of pixel light output. Furthermore, during the hold frame T2 data signal Vdata being held at the compensation voltage Vd1 for a period of time (ta), when N4 > 1, the holding time of the compensation voltage Vd1 can be longer. This reduces the number of transitions in the hold frame T2 data signal Vdata from the first voltage V1 to the compensation voltage Vd1, reducing the number of times the driving IC charges the data signal Vdata, thus further reducing power consumption.

[0082] Optional, Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 17 As shown, in the non-display area A2, the display panel also includes a binding area A21; the binding area A21 is electrically connected to the isolation compensation module 20 and is used at least to output a first control signal VCT to the isolation compensation module 20 and to output data signals Vdata of each data signal line DL to the isolation compensation module 20.

[0083] Specifically, bonding pads can be set in bonding area A21, which are electrically connected to the isolation compensation module 20. In addition, bonding pads can be set to be electrically connected to the driver IC, so that the data signals Vdata and the first control signal VCT provided by the driver IC can be transmitted to the isolation transmission module 20 through the bonding pads.

[0084] For example, the driver IC can be disposed on the glass step area of ​​the display panel, that is, the driver IC can be disposed in the form of COG (Chip on Glass), or the driver IC can be disposed on the FPC (Flexible Printed Circuit), that is, the driver IC can be disposed in the form of COF (Chip on FPC). The embodiments of the present invention do not specifically limit this.

[0085] Optional, see reference Figure 17 The non-display area A2 also includes a fan-out area A22; the fan-out area A22 includes fan-out traces L1 that correspond one-to-one with each data signal line DL; the bonding area A21 is located on the side of the fan-out area A22 away from the display area A1. By setting the fan-out traces L1, the area of ​​the bonding area A21 can be reduced, which helps to reduce the space occupied by the bonding pads on the display panel 100, facilitates the narrow bezel design of the display panel 100, and enables the accurate transmission of each data signal Vdata, the first control signal VCT, and other signals.

[0086] For example, the isolation compensation module 20 can be located in the non-display area A2 adjacent to the display area A1. Optionally, refer to... Figure 17 The isolation compensation module 20 is located between the fan-out area A22 and the display area A1; the binding area A21 is electrically connected to the isolation compensation module 20 through each fan-out trace L1. Thus, the binding area A21 can be electrically connected to each corresponding switching transistor T1 in the isolation compensation module 20 through each fan-out trace L1. Furthermore, when the isolation compensation module 20 is located between the fan-out area A22 and the display area A1, a fan-out trace L1 corresponding to the control signal line L0 can also be provided in the fan-out area A22, so that the control signal line L0 used to transmit the first control signal VCT in the isolation compensation module 20 is electrically connected to the binding area A21 through the fan-out trace.

[0087] Optional, Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 18 As shown, the isolation drive module 20 is located between the bonding area A21 and the fan-out area A22; the isolation drive module 20 is electrically connected to each data signal line DL through each fan-out trace L1. In this way, the space occupied by the isolation compensation module 20 and the bonding area A21 can be reduced, which can further realize the narrow bezel of the display panel 100.

[0088] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided in any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0089] For example, Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 19 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0090] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Display area and non-display area; In the display area, the display panel includes: an array of pixel driving circuits and multiple data signal lines, wherein at least some of the pixel driving circuits located in the same column are electrically connected to the same data signal line; In the non-display area, the display panel includes: an isolation compensation module and a bonding area; the isolation compensation module is electrically connected to each of the data signal lines, and the isolation compensation module receives a first control signal and data signals from each data signal line; the isolation compensation module is used to control the signal transmission path of each data signal to its corresponding data signal line according to the first control signal. The binding area is electrically connected to the isolation compensation module and is used at least to output a first control signal to the isolation compensation module and to output data signals of each of the data signal lines to the isolation compensation module. A data refresh cycle of the display panel includes a data write frame and a hold frame; in the hold frame, the first control signal includes a de-enabled level, such that the signal transmission path of each data signal to the corresponding data signal line is turned off.

2. The display panel according to claim 1, characterized in that, The isolation compensation module includes a switching unit that corresponds one-to-one with each of the data signal lines; The control terminal of the switching unit receives the first control signal, the first terminal of the switching unit receives the data signal, and the second terminal of the switching unit is electrically connected to the corresponding data signal line.

3. The display panel according to claim 2, characterized in that, The switching unit includes a switching transistor; The first terminal of the switching transistor receives the data signal, the second terminal of the switching transistor is electrically connected to the corresponding data signal line, and the gate of the switching transistor receives the first control signal.

4. The display panel according to claim 1, characterized in that, The moment when the first control signal changes from the enable level to the disable level is the first moment; The first moment is the same moment as the zeroing moment of the data signal, or the first moment is before the zeroing moment of the data signal.

5. The display panel according to claim 1, characterized in that, During the hold frame, in the phase when the first control signal is held at an inactive level, each of the data signals includes a first voltage.

6. The display panel according to claim 1, characterized in that, In the hold frame, the first control signal includes a valid pulse; the first control signal between two adjacent valid pulses is the disabled level; During the phase when the first control signal is a valid pulse, each of the data signals is a compensation voltage corresponding to each of the data signal lines.

7. The display panel according to claim 6, characterized in that, In the data writing frame, the data signal is a preset data voltage; The absolute value of the compensation voltage is greater than the absolute value of the preset data voltage.

8. The display panel according to claim 6, characterized in that, The absolute value of the compensation voltage is less than the absolute value of the pulse voltage of the first control signal.

9. The display panel according to claim 1, characterized in that, In the hold frame, the first control signal includes N1 valid pulses, where N1 ≥ 1 and N1 is an integer.

10. The display panel according to claim 9, characterized in that, In the data writing frame, the first control signal includes N2 valid pulses, where N2 ≥ 1 and N1 is an integer.

11. The display panel according to claim 10, characterized in that, N1≥2 and N2≥2; The pulse width of the first control signal in the holding frame is greater than the pulse width in the data writing frame.

12. The display panel according to claim 10, characterized in that, N2=1； In the data write frame, the pulse width of the first control signal is equal to the duration of the data write frame.

13. The display panel according to claim 6, characterized in that, The hold frame, wherein the first control signal includes N1 valid pulses, where N1 ≥ 2 and N1 is an integer; During the same holding frame, when the first control signal outputs each valid pulse, the same data signal line receives different compensation voltages.

14. The display panel according to claim 5, characterized in that, In the holding frame, the data signal further includes N3 compensation voltages, where N3 ≥ 1 and N3 is an integer; the data signal between two adjacent compensation voltages is a first voltage; When the data signal is the compensation voltage, the first control signal includes N4 valid pulses, where N4 ≥ 1 and N4 is an integer; the first control signal between two adjacent valid pulses is the disabled level.

15. The display panel according to claim 1, characterized in that, The pixel driving circuit includes a driving transistor and a pixel capacitor; The gate of the driving transistor receives the scan signal, the first terminal of the driving transistor is electrically connected to the data signal line, and the second terminal of the driving transistor is electrically connected to the pixel capacitor.

16. The display panel according to claim 1, characterized in that, In the display area, the display panel further includes scan signal lines; At least some of the pixel driving circuits located in the same row are electrically connected to the same scan signal line.

17. The display panel according to claim 1, characterized in that, The non-display area also includes a fan-out area; the fan-out area includes fan-out traces that correspond one-to-one with each of the data signal lines; The binding area is located on the side of the fan-out area away from the display area.

18. The display panel according to claim 17, characterized in that, The isolation compensation module is located between the fan-out area and the display area; The binding area is electrically connected to the isolation compensation module through each of the fan-out cables.

19. The display panel according to claim 17, characterized in that, The isolation compensation module is located between the binding area and the fan-out area; The isolation compensation module is electrically connected to each of the data signal lines via each of the fan-out traces.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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