LLC four-way interleaved parallel circuit structure and control method

Abstract

The present application relates to a kind of wide power range four-way staggered LLC control method, comprising: after loop current sampling, loop output pointer is obtained after processing and according to pointer inquiry switching frequency and full-bridge phase shift, generate four-way complementary phase-shift PWM switching signal.Wherein, four-way PWM moves to signal respectively acts on four-way switch tube of four-way full-bridge Q1, Q2, Q3, Q4.The inquiry mechanism of the present application is optimized according to LLC gain change rate, so that LLC is more simplified in full range static regulation.The present application reaches the purpose of stabilizing input current by series double-loop control through output current control, and by the way of pointer inquiry, reaches rectifier circuit soft switch and full-bridge change soft switch compatible under the working different gain and load of LLC.By pointer plus phase shift, the function of full-range four-way parallel current is achieved.Through four-way branch and feedback, the converter is made to work in the maximum demand state of the converter in real time.

Description

Technical Field

[0001] This invention pertains to the field of digital switching power supply technology, specifically relating to an LLC four-channel interleaved parallel circuit structure and control method. Background Technology

[0002] LLC resonant converters are widely used due to their high power density and ease of soft switching. In high-power applications, a single LLC branch requires large inductors, capacitors, and transformers, while parallel LLC branches can solve this problem. Since the battery stack has requirements for waveform quality, interleaved control can effectively reduce circuit ripple. Current four-way interleaved parallel LLC control methods have the following drawbacks: first, if one branch fails during application, the other branches cannot work; second, the voltage gain of the LLC resonant converter is quite sensitive to the parameters of the resonant devices. In practical applications, due to factors such as manufacturing processes and the natural environment, it is difficult to keep the parameters of the resonant devices in each module consistent, leading to differences in the output load current of each parallel branch, which seriously affects the reliability and lifespan of the LLC resonant converter. In existing technologies, current sharing uses a phase-shifting control method through the main LLC control; if the main circuit fails, current sharing in other branches fails. There are also control methods that achieve parallel current sharing of LLC resonant converters through virtual impedance, but these require separate control of the four loops, increasing the microcontroller's load rate. While this method shows good adjustment performance under heavy loads, the differences are significant under light loads. In new energy fuel cell power supplies, the input stack range varies considerably, and the output voltage range is also quite large. Therefore, a wide gain range is required for the switching power supply. For stack safety, the current needs to be controlled evenly across all charging stages. Summary of the Invention

[0003] In view of this, the first aspect of the present invention provides a four-channel LLC interleaved parallel circuit structure, which aims to reduce the output current waveform ripple and control the stability of the input current.

[0004] An LLC four-way interleaved parallel circuit structure includes: Parallel first LLC branch, parallel second LLC branch, parallel third LLC branch, parallel fourth LLC branch, sampling module, DSP, and driving module corresponding to each LLC branch; Among them, the first LLC branch in parallel is the basic branch, the second LLC branch in parallel is 45 degrees ahead of the first LLC branch in parallel, the third LLC branch in parallel is 45 degrees ahead of the second LLC branch in parallel, and the fourth LLC branch in parallel is 45 degrees ahead of the third LLC branch in parallel. Each LLC branch includes: an IGBT full-bridge converter unit, an LLC resonant circuit, an isolation transformer circuit, and a diode full-bridge rectifier unit connected in sequence. The IGBT full-bridge converter unit includes a first switch, a second switch, a third switch, and a fourth switch. In this configuration, the source of the first switching transistor is connected to the drain of the second switching transistor, the source of the third switching transistor is connected to the drain of the fourth switching transistor, the drain of the first switching transistor is connected to the drain of the third switching transistor, and the source of the second switching transistor is connected to the source of the fourth switching transistor. The first and second switches form the lagging arm of the full bridge, and the third and fourth switches form the leading arm of the full bridge. The sampling module is used to collect the output current of four LLC channels; The DSP is configured as a main loop control module, a current sharing loop control module, a lookup table and interleaving control module; The main loop control module acquires the output sampling current and obtains a lookup table pointer through the processing circuit. The current sharing loop control module acquires the output sampling current and obtains four-channel output current sharing compensation phase shift through the processing circuit. The lookup table and interleaving control module obtains the lookup table pointer and the four-channel output current sharing compensation phase shift, and obtains four-channel drive signals through the processing circuit.

[0005] Specifically, the degree of lead of the leading arm to the lagging arm in each LLC branch is used as phase shift control, and the switching frequencies of the leading arm and the lagging arm are the same. The first and second switches of each LLC branch hysteresis arm are driven complementaryly, with a first dead time set during which the rising edge of the first dead time is valid and acts on the first and second switches respectively. The third and fourth switches of the leading arm of each LLC branch are driven complementaryly, with a first dead time set during this period. The rising edge of the first dead time is valid and acts on the first and second switches respectively. The first switch of the lagging arm and the fourth switch of the leading arm of each LLC branch are driven complementaryly, with the first switch turning on after the fourth switch, and the lag time serving as the loop adjustment phase. The second switch of the lagging arm and the third switch of the leading arm are driven complementaryly, with the second switch turning on after the third switch, and the lag time serving as the loop adjustment phase.

[0006] Specifically, the resonant circuit includes a resonant inductor, a resonant capacitor, and a parallel inductor; One end of the resonant inductor is connected to the midpoint of the hysteresis arm, and the other end is connected to the resonant capacitor; The other end of the resonant capacitor is connected to the primary side of the parallel inductor and the isolation transformer circuit, and the other end of the parallel inductor and the isolation transformer circuit is connected to the midpoint of the forearm. The primary side of the isolation transformer circuit is connected in parallel with the parallel inductor, and the two ends of the secondary side are respectively connected to the two midpoints of the diode rectifier bridge.

[0007] Specifically, the processing circuit of the main loop control module includes: a first adder, a second adder, a third adder, a first comparator, a second comparator, a first PI regulator, a second PI regulator, a third PI regulator, a first limiter, a second limiter, a first multiplier, a first divider, and a second divider. The first adder processes the first output sampling current and the second output sampling current to obtain the first adder output signal; The second adder processes the output signal of the first adder and the third output sampling current to obtain the output signal of the second adder; The third adder processes the output signal of the second adder and the sampling current of the fourth output to obtain the total output current; The first comparator processes the input reference current and the input sampled current to obtain a first error signal; The first PI regulator processes the first error signal and obtains the input current loop output; The first multiplier processes the input current loop output and the input voltage; The first divider processes the signal and output voltage processed by the first multiplier and obtains the output current loop reference signal. The second divider processes the input voltage and the output voltage to obtain the gain signal; The second comparator processes the output current loop reference signal and the total output current to obtain the second error signal; The second PI regulator and the second limiter process the second error signal sequentially and obtain the output current loop output; The third PI regulator processes the gain signal and obtains the maximum pointer limit signal; The second limiter processes the maximum pointer limit signal and the output current loop output to obtain the lookup table pointer.

[0008] Specifically, the processing circuit of the current sharing loop control module includes: a fourth adder, a fifth adder, a sixth adder, a third divider, and a four-channel output current sharing compensation phase shift circuit; The fourth adder processes the first output sampling current and the second output sampling current to obtain the fourth adder output signal; The fifth adder processes the output signal of the fourth adder and the sampling current of the third output to obtain the output signal of the fifth adder; The sixth adder processes the output signal of the fifth adder and the sampling current of the fourth output to obtain the total output current; The third divider processes the total output current to obtain a quarter current-sharing signal. The four-channel output current sharing compensation phase shift circuit includes a comparator, a PI regulator, and a limiter; the four output sampling currents and a quarter current sharing signal are processed sequentially by the comparator, PI regulator, and limiter to obtain the current sharing compensation phase shift signal for each output.

[0009] Specifically, the processing circuit of the lookup table and interleaving control module includes a lookup table module, a first PWM module, a second PWM module, a third PWM module, and a fourth PWM module; The lookup module processes the lookup pointer and obtains the periodic signal and the phase signal; The first PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 0-degree signal of the first branch output and obtains the drive signals of the four switching transistors of the first branch; The second PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 45-degree signal output from the second branch and obtains the drive signals for the four switching transistors of the second branch. The third PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 90-degree signal output from the third branch and obtains the drive signals for the four switching transistors of the third branch. The fourth PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 135-degree signal output from the fourth branch and obtains the drive signals for the four switching transistors of the fourth branch.

[0010] Specifically, the lookup module queries a two-dimensional data table, where each element contains two elements: frequency and phase, which control the driving frequency and the first phase shift, respectively.

[0011] Secondly, based on the circuit structure of the above scheme, a wide-range four-way interleaved parallel LLC control method is proposed, including main loop control, current sharing loop control, table lookup and interleaving control: The main loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the input reference current, input sampled current, input voltage, and output voltage to obtain the output current loop reference signal; Process the input voltage and output voltage and obtain the gain signal; Process the gain signal and obtain the maximum pointer limit signal; Process the output current loop reference signal, output the total current, and obtain the output current loop output; Process the maximum pointer limit signal and the output current loop output to obtain the lookup table pointer; The current sharing loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the total output current and obtain a quarter current sharing signal; Process the sampling current of four output channels and a quarter current sharing signal to obtain the current sharing compensation phase shift signal of each output channel; The table lookup and interleaving control include the following steps: Process the lookup pointer and obtain the periodic signal and phase signal; Process the current sharing compensation phase shift signal, period signal, phase signal, and interleaved signal of each output and obtain the drive signal of each of the four switching transistors; The interleaved control signals are: 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

[0012] Based on the above scheme, the method for generating the maximum pointer limit signal is as follows: S1: Obtain the maximum gain and minimum gain, and divide the gain into several segments according to linear rules; S2: For each gain in S1, select the operating point at its maximum allowable power. S3: Find the pointer of the point obtained in S2 in the lookup table. If the working point is outside the lookup table range, expand the table according to the lookup table rules and use the working point obtained in S2 as a pointer to map to the expanded table. S4: Linearly fit the pointer obtained in S3 to obtain a linear function of the maximum pointer limit and gain; S5: Adjust the gain parameter according to the fitted linear function to finally obtain the loop output maximum pointer limit signal.

[0013] Based on the above scheme, the operating switching frequency fw of the switching transistor satisfies the condition that the voltage gain Gw at this frequency is greater than the actual required voltage gain Gr. The relationship between the voltage gain Gw and the operating switching frequency fw is as follows: ; in: ; k is the ratio of resonant inductance Lr to magnetizing inductance Lm, fn is the ratio of operating switching frequency fw to resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance from the secondary load to the primary side of the transformer, Cr is the resonant capacitance, m is the transformer turns ratio, Ro is the actual resistance of the secondary load of the transformer, and Q is the quality factor. The actual required voltage gain Gr is: .

[0014] The beneficial effects of this invention are: This invention employs four LLCs in parallel to achieve high-power control, reducing the size of the magnetic field, increasing power density, and simultaneously reducing current ripple. The parallel interleaved loop method used in this invention effectively balances the dynamic and static regulation of the LLCs. This invention also effectively balances the operating current of each branch through current sharing control. Attached Figure Description

[0015] The present invention includes the following figures: Figure 1 Overall structure diagram; Figure 2 Main power topology diagram; Figure 3 Main loop control circuit flowchart; Figure 4 Flowchart of current sharing loop control; Figure 5 Lookup table and interleaved control flowchart; Figure 6 Waveform diagram of single-channel LLC four-channel drive; Figure 7 Interleaved drive diagram; Figure 8 Psr_Max is a linear function of the gain. Detailed Implementation

[0016] To make the objectives, advantages and features of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] like Figure 1As shown, an LLC four-way interleaved parallel circuit structure includes a DSP, multiple PI regulators, multiple PWM control units, and a parallel full-bridge LLC resonant converter composed of multiple LLC branches connected in parallel. The primary side of each LLC branch includes switching transistors Sn1, Sn2, Sn3, Sn4 (n = 1, 2, 3, 4), resonant capacitors Crn (n = 1, 2, 3, 4), resonant inductors Lrn (n = 1, 2, 3, 4), and magnetizing inductors Lmn (n = 1, 2, 3, 4). The resonant capacitors Crn (n = 1, 2, 3, 4), resonant inductors Lrn, and magnetizing inductors Lmn together form a resonant cavity. The switching transistors Sn1, Sn2, Sn3, Sn4 (n = ... 1, 2, 3, 4) form a full bridge. Each switching transistor has a diode and a capacitor connected in parallel. One end of the resonant inductor Lrn is connected in series with one end of the resonant capacitor Crn. The other end of the resonant inductor Lrn is connected to the midpoint An of the left arm of the primary side full bridge. The other end of the resonant capacitor Crn is connected to one end of the primary winding of transformer Tn (n = 1, 2, 3, 4). The other end of the primary winding of transformer Tn is connected to the midpoint Bn (n = 1, 2, 3, 4) of the right arm of the full bridge. The magnetizing inductor Lmn is connected in parallel across the primary winding of transformer Tn. The secondary side of the converter module includes diodes Dn1, Dn2, Dn3, Dn4 (n = 1, 2, 3, 4). Diodes Dn1, Dn2, Dn3, Dn4 form a diode rectifier bridge. One end of the secondary winding of transformer Tn is connected to the midpoint Cn (n = 1, 2, 3, 4) of the left arm of the diode rectifier bridge. Connect the first end to the second end (1, 2, 3, 4), and connect the second end to the midpoint Dn (n = 1, 2, 3, 4) of the right arm of the diode rectifier bridge. Connect a filter capacitor Con (n = 1, 2, 3, 4) in parallel to the output of the diode rectifier bridge. Connect the load resistor RLoad in parallel with the filter capacitor Con.

[0018] The PI controller consists of a proportional element and an integral element, mathematically expressed as P + I / S. Here, P is the proportional gain, I is the integral gain, and S is the integrator. The error signal is linearly combined with the proportional and integral elements to form the control quantity. The outer loop uses this control quantity and the given input to control the controlled object, while the inner loop uses this control quantity to query and obtain the control quantity to control the controlled object. The control quantity consists of the frequency of the drive signals of the switching transistors Sn1, Sn2, Sn3, and Sn4 (n = 1, 2, 3, 4) and the phases of the switching transistors Sn3 and Sn4. By changing the frequencies of the switching transistors Sn1, Sn2, Sn3, and Sn4, as well as the phases of the switching transistors Sn3 and Sn4, the controlled object is controlled.

[0019] The frequency Fw and phase Pwcn (n = 1, 2, 3, 4) are sent to the PWM control unit. The PWM control unit generates four drive signals gsn1 and gsn3 (n = 1, 2, 3, 4) with a switching period of 1 / Fw according to the working switching frequency Fw.

[0020] Preferably, in the PWM control unit, the duty cycle of drive signals gsn1 and gsn3 is set to 0.5, and the phase shift of gsn3 is (n-1). After 45+Pwcn (n= 1, 2, 3, 4), the complementary module of the PWM control unit generates a drive signal gsn4 that is complementary to the drive signal gsn2, thus realizing constant current and loop control of four interleaved 180+ parallel LLCs with current sharing.

[0021] like Figure 2 As shown in the main power topology diagram: GS11, GS12, GS13, and GS14 are the drive signals for the first branch, where GS11 and GS12 are lagging arm drives, with complementary outputs; GS13 and GS14 are leading arm drives, with complementary outputs; when the LLC branch is working, GS11 and GS14 output simultaneously or with phase shift, and GS12 and GS13 output simultaneously or with phase shift. GS21, GS22, GS23, and GS24 are the drive signals for the second branch, where GS21 and GS22 are lagging arm drives, with complementary outputs; GS23 and GS24 are leading arm drives, with complementary outputs; when the LLC branch is working, GS21 and GS24 output simultaneously or with phase shift, and GS22 and GS23 output simultaneously or with phase shift. GS31, GS32, GS33, and GS34 are the drive signals for the third branch. GS31 and GS32 are for the lagging arm drive, and their outputs are complementary. GS33 and GS34 are for the leading arm drive, and their outputs are complementary. When the LLC branch is working, GS31 and GS34 output simultaneously or with a phase shift, and GS32 and GS33 output simultaneously or with a phase shift. GS41, GS42, GS43, and GS44 are the drive signals for the third branch. GS41 and GS42 are for the lagging arm drive, and their outputs are complementary. GS43 and GS44 are for the leading arm drive, and their outputs are complementary. When the LLC branch is working, GS41 and GS44 output simultaneously or with a phase shift, and GS42 and GS43 output simultaneously or with a phase shift.

[0022] like Figure 3As shown in the main loop control circuit flowchart: Iref is the voltage setpoint, Iin is the input current sampling, and PIin is the current loop PI processing module. Error is the input current loop error signal, Error = Iref – Iin. Error is processed by PIin to obtain the Lout signal, which is the current loop output signal. Lout is boundary-limited to obtain L1out. L1out is multiplied by Vin by multiplier MULT1, and then divided by the output voltage Vout by divider DIVD1 to obtain Iref_out, i.e., Iref_out = L1out. Vin / Vout; Iref_out serves as the reference signal for the output current loop.

[0023] Iout is the total output current, which is obtained by summing the currents of its four branches through adders SUMP1, SUMP2, and SUMP3. Iref_out and Iout are subtracted by comparator COMPout to obtain the output current loop error signal Error2. Error2 is processed by the PI of the PLout module to obtain L2out. L2out is bounded to obtain L3out. L3out is bounded by Psr_Max to obtain the output polling pointer Psr.

[0024] Psr_Max is the gain limit pointer, which is obtained by processing the gain signal Gain through the PI of the G2Psr module. The gain is obtained by dividing the output voltage and the input voltage by the divider DIVD2, i.e., Gain = Vo / Vin.

[0025] like Figure 4As shown in the current sharing loop control flowchart: Is1, Is2, Is3, and Is4 are the output current sampling signals of the four LLC branches. The four currents and the constant 4Const are passed through adders SUMP4, SUMP6 and multiplier DIDV3 to obtain the average signal Varage, which serves as the reference input for the current sharing loop. Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 are the outputs of the current sharing loop. Is1, Is2, Is3, and Is4 are compared by comparators COM1, COM2, COM3, and COM4, ​​respectively. Then, the outputs are adjusted by their respective PI modules PI1, PI2, PI3, and PI4, and finally obtained after boundary constraints. Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 serve as the compensation phases for the phases obtained from the pointer lookup table. Specifically, Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 are added to Phase to serve as the phase inputs for PWM1, PWM2, PWM3, and PWM4, respectively. Phase and PWM1, PWM2, PWM3, and PWM4 represent the phase signals for the lookup table and the interleaved flowchart, respectively, and are also part of the PWM modulation module.

[0026] like Figure 5 As shown in the table lookup and interleaving flowchart: The lookup pointer Psr queries the two-dimensional data table PPHBOX to obtain the basic period and phase of the PWM modulation. The loop compensation signals Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 obtained from current sharing are added to Phase to obtain Phase1, Phase2, Phase3, and Phase4 respectively. Phase1, Phase2, Phase3, and Phase4 are used as the modulation inputs of PWM1, PWM2, PWM3, and PWM4 respectively. Together with Period and the interleaved phases of each PWM modulation module (0 degrees, 45 degrees, 90 degrees, and 135 degrees), they produce the drive signals for the four branches. Period determines the period of all drives, Phase1, Phase2, Phase3, and Phase4 determine the phase time between the leading and lagging arms of each branch, and the interleaved inputs determine the interleaved phases between each branch.

[0027] like Figure 6As shown in the waveform diagram of a single-channel LLC with four drive channels: Phase_Delta represents Phase_Delta1, Phase_Delta2, Phase_Delta3, and Phase_Delta4, respectively, i.e., n = 1, 2, 3, and 4. Similarly, n in gsn1, gsn2, gsn3, and gsn4 are also 1, 2, 3, and 4, respectively. When n=1, it drives the first branch LLC; when n=2, it drives the second branch LLC; when n=3, it drives the third branch LLC; and when n=4, it drives the fourth branch LLC. For a single-channel LLC, there is a lead-lag relationship between its two bridge arms due to the influence of the phase. For the nth (n=1, 2, 3, 4) LLC, the upper and lower transistors of its leading arm are driven by gsn1 and gsn2 respectively, and the upper and lower transistors of its lagging arm are driven by gsn3 and gsn4 respectively. The LLC works by phase shifting the driving signals of gsn1 and gsn4, phase shifting the driving signals of gsn2 and gsn3, and the driving signals of gsn1 and gsn2 are complementary, as are the driving signals of gsn3 and gsn4. This achieves the adjustment of the LLC by looking up the table, frequency modulation, and phase shifting.

[0028] like Figure 7 As shown in the diagram of the interleaved drive, the nth (n=1,2,3,4) switches of the 1st, 2nd, 3rd, and 4th branches have the same waveform frequency and the same duty cycle, and are interleaved at 45 degrees to achieve the purpose of interleaved parallel connection.

[0029] Furthermore, the rules for creating PSR lookup tables (PPHBOX) are as follows: When the input is 300V to 600V and the output is 200V to 1000V, the maximum gain Gmax = 1000V / 300V, and the minimum gain gmin = 200V / 600V. Gain simulation range planning objective: 600V 200 300V 200 300 1000 Based on the maximum permissible operating power at the operating point, find the operating point and construct an initial simplified table: Step 1: Find the operating point of the LLC corresponding to a 600V input and 200V output. This point includes the period and phase. Step 2: Find the operating point with an output of 200V and an input that drops from 600V to 300V. All points include the period and phase. The input changes linearly from 600V to 300V. In case of special circumstances, add a query operating point. Step 3: Find the operating point with an input of 300V and an output between 200V and 1000V. All points include period and phase. The output changes linearly from 200V to 1000V. In case of special circumstances, add a query operating point. Based on the above plan, N working points are ultimately obtained, as shown in the simplified table below. ; Step 4: Expand into the final two-dimensional table according to the rules: Extended examples are as follows: Extension from working point 0 to working point 1: According to the LLC property that P0 <= P1, in order to maintain gain consistency, the simplified table guarantees that PH0 >= PH1. There are three cases for table expansion: 1) P0 = P1, PH0 > PH1 2) P0<P1,PH0 => PH 1 3) P0<P1,PH0> PH 1 In the first case, the extension is as follows: ; The second scenario involves expansion: ; In the third case, the extension ; In another embodiment, a wide-range four-way interleaved parallel LLC control method is proposed based on the above circuit structure, including main loop control, current sharing loop control, table lookup and interleaving control: The main loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the input reference current, input sampled current, input voltage, and output voltage to obtain the output current loop reference signal; Process the input voltage and output voltage and obtain the gain signal; Process the gain signal and obtain the maximum pointer limit signal; Process the output current loop reference signal, output the total current, and obtain the output current loop output; Process the maximum pointer limit signal and the output current loop output to obtain the lookup table pointer; The current sharing loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the total output current and obtain a quarter current sharing signal; Process the sampling current of four output channels and a quarter current sharing signal to obtain the current sharing compensation phase shift signal of each output channel; The table lookup and interleaving control include the following steps: Process the lookup pointer and obtain the periodic signal and phase signal; Process the current sharing compensation phase shift signal, period signal, phase signal, and interleaved signal of each output and obtain the drive signal of each of the four switching transistors; The interleaved control signals are: 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

[0030] Furthermore, the rule for converting G2Psr gain to the maximum pointer is as follows: Step 1: Given the maximum gain Gmax and the minimum gain gmin, divide the gain from gmin to gmax into N segments according to a linear rule; Step 2: For each gain in Step 1, select the operating point at 120% of its maximum allowable power. Step 3: Locate the pointer of the point obtained in step 2 in the PPHBOX table. If the working point is outside the range of PPHBOX, expand the PPHBOX table according to the rules of PPHBOX and map the working pointer obtained in step 2 to the expanded PPHBOX table. Step 4: Linearly fit the pointer obtained in Step 3 to obtain a linear function of Psr_Max and Gain; (e.g.) Figure 8 (As shown) Step 5: Adjust the G2Psr parameters according to the fitted linear function to finally obtain the loop output maximum pointer limit Psr_Max.

[0031] Furthermore, the operating switching frequency fw of the switching transistor satisfies the condition that the voltage gain Gw at that frequency is greater than the actual required voltage gain Gr. The relationship between the voltage gain Gw and the operating switching frequency fw is as follows: ; in: ; k is the ratio of resonant inductance Lr to magnetizing inductance Lm, fn is the ratio of operating switching frequency fw to resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance from the secondary load to the primary side of the transformer, Cr is the resonant capacitance, m is the transformer turns ratio, Ro is the actual resistance of the secondary load of the transformer, and Q is the quality factor. The actual required voltage gain Gr is: .

[0032] It should be noted that any process or method description in the embodiments can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which the embodiments of the invention pertain.

[0033] It should be noted that the logic and / or steps in the embodiments, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0034] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0035] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0036] Furthermore, in the embodiments of the present invention, the functional modules can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0037] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0038] The above embodiments have provided a detailed description of the technical solution of the present invention. Obviously, the present invention is not limited to the described embodiments. Based on the embodiments of the present invention, those skilled in the art can make various modifications, but any modifications that are equivalent to or similar to the present invention fall within the scope of protection of the present invention.

[0039] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A four-way interleaved parallel circuit structure for LLC, characterized in that, include: Parallel first LLC branch, parallel second LLC branch, parallel third LLC branch, parallel fourth LLC branch, sampling module, DSP, and driving module corresponding to each LLC branch; Among them, the first LLC branch in parallel is the basic branch, the second LLC branch in parallel is 45 degrees ahead of the first LLC branch in parallel, the third LLC branch in parallel is 45 degrees ahead of the second LLC branch in parallel, and the fourth LLC branch in parallel is 45 degrees ahead of the third LLC branch in parallel. Each LLC branch includes: an IGBT full-bridge converter unit, an LLC resonant circuit, an isolation transformer circuit, and a diode full-bridge rectifier unit connected in sequence. The IGBT full-bridge converter unit includes a first switch, a second switch, a third switch, and a fourth switch. In this configuration, the source of the first switch is connected to the drain of the second switch, the source of the third switch is connected to the drain of the fourth switch, the drain of the first switch is connected to the drain of the third switch, and the source of the second switch is connected to the source of the fourth switch; the first switch and the second switch form the lagging arm of the full bridge, and the third switch and the fourth switch form the leading arm of the full bridge. The sampling module is used to collect the output current of four LLC channels; The DSP is configured as a main loop control module, a current sharing loop control module, a lookup table and interleaving control module; The main loop control module acquires the output sampling current and obtains a lookup table pointer through the processing circuit. The current sharing loop control module acquires the output sampling current and obtains four-channel output current sharing compensation phase shift through the processing circuit. The lookup table and interleaving control module obtains the lookup table pointer and the four-channel output current sharing compensation phase shift, and obtains four-channel drive signals through the processing circuit. The processing circuit of the main loop control module includes: a first adder, a second adder, a third adder, a first comparator, a second comparator, a first PI regulator, a second PI regulator, a third PI regulator, a first limiter, a second limiter, a first multiplier, a first divider, and a second divider. The first adder processes the first output sampling current and the second output sampling current to obtain the first adder output signal; The second adder processes the output signal of the first adder and the third output sampling current to obtain the output signal of the second adder; The third adder processes the output signal of the second adder and the sampling current of the fourth output to obtain the total output current; The first comparator processes the input reference current and the input sampled current to obtain a first error signal; The first PI regulator processes the first error signal and obtains the input current loop output; The first multiplier processes the input current loop output and the input voltage; The first divider processes the signal and output voltage processed by the first multiplier and obtains the output current loop reference signal. The second divider processes the input voltage and the output voltage to obtain the gain signal; The second comparator processes the output current loop reference signal and the total output current to obtain the second error signal; The second PI regulator and the second limiter process the second error signal sequentially and obtain the output current loop output; The third PI regulator processes the gain signal and obtains the maximum pointer limit signal; The second limiter processes the maximum pointer limit signal and the output current loop output to obtain the lookup table pointer.

2. The circuit structure according to claim 1, characterized in that, The degree of lead of the leading arm to the lagging arm in each LLC branch is used as the phase shift control, and the switching frequencies of the leading arm and the lagging arm are the same. The first and second switches of each LLC branch hysteresis arm are driven complementaryly, during which a first dead time is set, and the rising edge of the first dead time is valid, acting on the first and second switches respectively. The third and fourth switches of the leading arm of each LLC branch are driven complementaryly, with a first dead time set during this period. The rising edge of the first dead time is valid and acts on the first and second switches respectively. The first switch of the lagging arm and the fourth switch of the leading arm of each LLC branch are driven complementaryly, with the first switch turning on after the fourth switch, and the lag time serving as the loop adjustment phase. The second switch of the lagging arm and the third switch of the leading arm are driven complementaryly, with the second switch turning on after the third switch, and the lag time serving as the loop adjustment phase.

3. The circuit structure according to claim 1, characterized in that, The resonant circuit includes a resonant inductor, a resonant capacitor, and a parallel inductor; One end of the resonant inductor is connected to the midpoint of the hysteresis arm, and the other end is connected to the resonant capacitor; The other end of the resonant capacitor is connected to the primary side of the parallel inductor and the isolation transformer circuit, and the other end of the parallel inductor and the isolation transformer circuit is connected to the midpoint of the forearm. The primary side of the isolation transformer circuit is connected in parallel with the parallel inductor, and the two ends of the secondary side are respectively connected to the two midpoints of the diode rectifier bridge.

4. The circuit structure according to claim 1, characterized in that, The processing circuit of the current sharing loop control module includes: a fourth adder, a fifth adder, a sixth adder, a third divider, and a four-channel output current sharing compensation phase shift circuit; The fourth adder processes the first output sampling current and the second output sampling current to obtain the fourth adder output signal; The fifth adder processes the output signal of the fourth adder and the sampling current of the third output to obtain the output signal of the fifth adder; The sixth adder processes the output signal of the fifth adder and the sampling current of the fourth output to obtain the total output current; The third divider processes the total output current to obtain a quarter current-sharing signal. The four-channel output current sharing compensation phase shift circuit includes a comparator, a PI regulator, and a limiter; the four output sampling currents and a quarter current sharing signal are processed sequentially by the comparator, PI regulator, and limiter to obtain the current sharing compensation phase shift signal for each output.

5. The circuit structure according to claim 1, characterized in that, The processing circuit of the lookup table and interleaving control module includes a lookup table module, a first PWM module, a second PWM module, a third PWM module, and a fourth PWM module; The lookup module processes the lookup pointer and obtains the periodic signal and the phase signal; The first PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 0-degree signal of the first branch output and obtains the drive signals of the four switching transistors of the first branch; The second PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 45-degree signal output from the second branch and obtains the drive signals for the four switching transistors of the second branch. The third PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 90-degree signal output from the third branch and obtains the drive signals for the four switching transistors of the third branch. The fourth PWM module processes the current sharing compensation phase shift signal, period signal, phase signal, and 135-degree signal output from the fourth branch and obtains the drive signals for the four switching transistors of the fourth branch.

6. The circuit structure according to claim 5, characterized in that, The lookup module queries a two-dimensional data table. Each element contains two elements: frequency and phase, which control the driving frequency and the first phase shift, respectively.

7. A control method for a wide-range four-way interleaved parallel LLC, characterized in that, Based on the circuit structure described in any one of claims 1-6, including main loop control, current sharing loop control, lookup table, and interleaving control: The main loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the input reference current, input sampled current, input voltage, and output voltage to obtain the output current loop reference signal; Process the input voltage and output voltage and obtain the gain signal; Process the gain signal and obtain the maximum pointer limit signal; Process the output current loop reference signal, output the total current, and obtain the output current loop output; Process the maximum pointer limit signal and the output current loop output to obtain the lookup table pointer; The current sharing loop control includes the following steps: Process the sampling current of the four output channels and obtain the total output current; Process the total output current and obtain a quarter current sharing signal; Process the sampling current of four output channels and a quarter current sharing signal to obtain the current sharing compensation phase shift signal of each output channel; The table lookup and interleaving control include the following steps: Process the lookup pointer and obtain the periodic signal and phase signal; Process the current sharing compensation phase shift signal, period signal, phase signal, and interleaved signal of each output and obtain the drive signal of each of the four switching transistors; The interleaved control signals are: 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

8. The control method according to claim 7, characterized in that, The method for generating the maximum pointer limit signal is as follows: S1: Obtain the maximum gain and minimum gain, and divide the gain into several segments according to linear rules; S2: For each gain in S1, select the operating point at its maximum allowable power. S3: Find the pointer of the point obtained in S2 in the lookup table. If the working point is outside the lookup table range, expand the table according to the lookup table rules and use the working point obtained in S2 as a pointer to map to the expanded table. S4: Linearly fit the pointer obtained in S3 to obtain a linear function of the maximum pointer limit and gain; S5: Adjust the gain parameter according to the fitted linear function to finally obtain the loop output maximum pointer limit signal.

9. The control method according to claim 7, characterized in that, The operating switching frequency fw of the switching transistor satisfies the condition that the voltage gain Gw at that frequency is greater than the actual required voltage gain Gr. The relationship between the voltage gain Gw and the operating switching frequency fw is as follows: ; in: ; k is the ratio of resonant inductance Lr to magnetizing inductance Lm, fn is the ratio of operating switching frequency fw to resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance from the secondary load to the primary side of the transformer, Cr is the resonant capacitance, m is the transformer turns ratio, Ro is the actual resistance of the secondary load of the transformer, and Q is the quality factor. The actual required voltage gain Gr is: 。

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