Semiconductor devices, memory and their manufacturing methods, electronic devices

Abstract

A semiconductor device, a memory, a method for manufacturing the same, and an electronic device are disclosed, belonging to the field of semiconductor device design and manufacturing. The semiconductor device includes: a substrate and at least one memory cell disposed on the substrate. The memory cell includes: a read transistor comprising a first gate electrode, a second gate electrode, and a first semiconductor layer; the first gate electrode is connected to a read word line; one end of the first semiconductor layer is connected to a first bit line, and the other end is connected to a second bit line; a write transistor comprising a third gate electrode and a second semiconductor layer; one end of the second semiconductor layer is electrically connected to the second gate electrode, and the other end is connected to the second bit line; the third gate electrode is connected to a write word line; wherein the read transistor and the write transistor are stacked along a direction perpendicular to the substrate. The semiconductor device of this application has a simple structure and occupies a small area.

Description

Technical Field

[0001] The embodiments of this application relate to, but are not limited to, the design and manufacture of semiconductor devices, and particularly to a semiconductor device, a memory and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device, a memory and its manufacturing method, and an electronic device. The semiconductor device has a simple structure, is easy to manufacture, and occupies a small area.

[0006] This application provides a semiconductor device, the semiconductor device including a substrate and at least one memory cell disposed on the substrate, the memory cell including:

[0007] The read transistor includes a first gate electrode, a second gate electrode, and a first semiconductor layer; the first gate electrode is connected to a read word line; one end of the first semiconductor layer is connected to a first bit line, and the other end is connected to a second bit line;

[0008] The write transistor includes a third gate electrode and a second semiconductor layer; one end of the second semiconductor layer is electrically connected to the second gate electrode, and the other end is connected to a second bit line; the third gate electrode is connected to the write word line.

[0009] The read transistor and the write transistor are stacked in a direction perpendicular to the substrate.

[0010] For example, the first semiconductor layer extends in a direction perpendicular to the substrate, and a first gate electrode is disposed on one side of the first semiconductor layer, and a second gate electrode is disposed on the other side of the first semiconductor layer.

[0011] For example, the second semiconductor layer extends in a direction perpendicular to the substrate, and the third gate electrode is disposed on one side of the second semiconductor layer, and the second semiconductor layer is connected to the first semiconductor layer.

[0012] For example, the semiconductor device may further include a semiconductor layer, the semiconductor layer comprising a first semiconductor layer and a second semiconductor layer sequentially distributed along a direction perpendicular to the substrate;

[0013] A gate insulating layer is provided between the semiconductor layer and the first gate electrode, between the semiconductor layer and the second gate electrode, and between the semiconductor layer and the third gate electrode.

[0014] For example, the semiconductor device may further include a through-hole extending through the read transistor and the write transistor;

[0015] The semiconductor layer is located at least on the sidewall of the via and is annular. The semiconductor layer, the gate insulating layer between the semiconductor layer and the second gate electrode, and the second gate electrode are sequentially distributed in the via along a direction away from the sidewall of the via.

[0016] For example, both the read line and the write line extend along a first direction parallel to the substrate, the first gate electrode is part of the read line, and the third gate electrode is part of the write line.

[0017] For example, both the first bit line and the second bit line extend along a second direction parallel to the substrate, and the first direction intersects the second direction.

[0018] Exemplarily, the write transistor may further include a fourth gate electrode;

[0019] The semiconductor device includes a conductive layer, the conductive layer including the fourth gate electrode and the second gate electrode sequentially distributed along a direction perpendicular to the substrate;

[0020] The second semiconductor layer at least partially surrounds the fourth gate electrode, and a gate insulating layer is present between the second semiconductor layer and the fourth gate electrode.

[0021] For example, the semiconductor device may further include a memory node connected to the fourth gate electrode and the second gate electrode;

[0022] The memory node is part of the conductive layer, and a gate insulating layer is provided between the second semiconductor layer and the memory node. The second semiconductor layer and the memory node are electrically connected through a fourth conductive layer; or, the memory node is connected to the fourth gate electrode and is located in different film layers, and the second semiconductor layer is connected to the memory node.

[0023] For example, the read transistor is located between the substrate and the write transistor;

[0024] The reading line is located between the substrate and the writing line;

[0025] The first bit line is located between the substrate and the second bit line.

[0026] For example, the write transistor is located between the read transistor and the substrate;

[0027] The writing line is located between the substrate and the reading line;

[0028] The second bit line is located between the substrate and the first bit line.

[0029] This application also provides a memory, which includes at least one semiconductor device as provided in the above embodiments of this application.

[0030] This application also provides a method for manufacturing a memory, the method comprising:

[0031] Provide substrate;

[0032] A first bit line, a second bit line, a dummy read line, and a dummy write line are formed on the substrate, spaced apart and insulated from each other along a direction perpendicular to the substrate;

[0033] A through-hole is formed by etching, which at least penetrates the second bit line, the dummy read line, and the dummy write line;

[0034] A semiconductor layer, a gate insulating layer, and a conductive layer are sequentially deposited within the via.

[0035] The dummy character lines are etched away to form character lines;

[0036] The dummy writing line is removed by etching to form a writing line.

[0037] For example, forming a first bit line, a second bit line, a dummy read line, and a dummy write line spaced apart and insulatedly distributed along a direction perpendicular to the substrate on the substrate may include:

[0038] Along a direction perpendicular to the substrate, a first bit line, a dummy read line, a second bit line, and a dummy write line are sequentially formed on the substrate. The dummy read line and the dummy write line both extend along a first direction parallel to the substrate, and the first bit line and the second bit line both extend along a second direction parallel to the substrate. The first direction and the second direction intersect. The first bit line, the dummy read line, the second bit line, and the dummy write line are insulated from each other by an insulating layer.

[0039] Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes:

[0040] A through-hole is formed by etching, penetrating the second bit line, the dummy read line, and the dummy write line, and the through-hole exposes the first bit line.

[0041] For example, etching away the dummy writing line to form a writing line may include:

[0042] The insulating layer between each via is patterned and etched along the direction toward the substrate to expose the dummy writing lines;

[0043] The exposed dummy writing lines are etched laterally to remove the dummy writing lines and expose the semiconductor layer that was originally surrounded by the dummy writing lines.

[0044] A gate insulating layer and a writing line layer are deposited on the exposed area of ​​the semiconductor layer, and the writing line layer is etched back to obtain writing lines extending along the first direction.

[0045] For example, etching away the dummy reading lines to form reading lines may include:

[0046] The insulating layer between the writing line and the dummy reading line is etched to expose the dummy reading line;

[0047] The dummy read lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy read lines;

[0048] The exposed area of ​​the semiconductor layer and the gate insulating layer and read line layer of the writing line are deposited sequentially;

[0049] The reading line layer is etched back to obtain reading lines extending along the first direction.

[0050] For example, forming a first bit line, a second bit line, a dummy read line, and a dummy write line spaced apart and insulatedly distributed along a direction perpendicular to the substrate on the substrate may include:

[0051] Along a direction perpendicular to the substrate, a memory node, a dummy write line, a second bit line, a dummy read line, and a first bit line are sequentially formed on the substrate. A plurality of memory nodes are arrayed on the substrate along a first direction and a second direction parallel to the substrate. The dummy read line and the dummy write line both extend along the first direction, and the first bit line and the second bit line both extend along the second direction. The first direction and the second direction intersect. The memory node, the dummy write line, the second bit line, the dummy read line, and the first bit line are insulated from each other by an insulating layer.

[0052] Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes:

[0053] Through-holes are formed by etching, penetrating the first bit line, the second bit line, the dummy read line, and the dummy write line, and the through-holes are made to expose the memory node.

[0054] For example, etching away the dummy reading lines to form reading lines may include:

[0055] The insulating layer between each of the vias is patterned and etched along the direction toward the substrate to expose the dummy character lines;

[0056] The exposed dummy read lines are etched to remove them, revealing the semiconductor layer that was originally surrounded by the dummy read lines.

[0057] A gate insulating layer and a readout line layer are deposited on the exposed area of ​​the semiconductor layer, and the readout line layer is etched back to obtain readout lines extending along the first direction.

[0058] For example, etching away the dummy writing line to form a writing line may include:

[0059] The insulating layer between the reading line and the dummy writing line is etched to expose the dummy writing line;

[0060] The dummy writing lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy writing lines;

[0061] Sequentially deposit the exposed area covering the semiconductor layer and the gate insulating layer and the write line layer covering the read line;

[0062] The writing line layer is etched back to obtain writing lines extending along the first direction.

[0063] This application also provides an electronic device, which includes the memory provided in the above embodiments of this application.

[0064] The semiconductor device and memory of this application embodiment stack the read transistor and write transistor, which helps to reduce the area of ​​the memory cell of the semiconductor device and thus increase the storage density of the device. Moreover, since the read transistor of the semiconductor device of this application embodiment can form a diode connection under the control of the write transistor, thereby compensating for the threshold voltage of the read transistor during the data writing stage, the accuracy of data reading can be improved.

[0065] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0066] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0067] Figure 1A A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of this application;

[0068] Figure 1B A logic circuit diagram of another semiconductor device provided for an exemplary embodiment of this application;

[0069] Figure 2A A schematic cross-sectional view parallel to the substrate of a memory device including an embodiment of the present application, provided for an exemplary embodiment of the present application;

[0070] Figure 2B for Figure 2A The edge of the memory shown Figure 2A A schematic diagram of a cross-section perpendicular to the substrate, taken from line AA in the middle;

[0071] Figure 3A A schematic cross-sectional view parallel to the substrate of another memory, including a semiconductor device according to an embodiment of this application, provided for exemplary embodiments of this application;

[0072] Figure 3B for Figure 3A The edge of the memory shown Figure 3A A schematic diagram of a cross-section perpendicular to the substrate, taken from line AA in the middle;

[0073] Figure 4 Current-voltage curves of the read transistor of a semiconductor device, which are exemplary embodiments of this application, during data readout;

[0074] Figure 5 A timing diagram of a semiconductor device as an exemplary embodiment of this application;

[0075] Figure 6 Another timing diagram of a semiconductor device as an exemplary embodiment of this application;

[0076] Figure 7 Another timing diagram of a semiconductor device as an exemplary embodiment of this application;

[0077] Figure 8A process flow diagram of a method for manufacturing a memory provided for an exemplary embodiment of this application;

[0078] Figure 9A A schematic cross-sectional view parallel to the substrate after the formation of the first line, provided as an exemplary embodiment of this application, of a method for manufacturing a memory.

[0079] Figure 9B for Figure 9A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0080] Figure 10A A schematic cross-sectional view of a memory manufacturing method provided for an exemplary embodiment of this application, after forming dummy write lines, parallel to the substrate;

[0081] Figure 10B for Figure 10A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0082] Figure 11A A schematic cross-sectional view parallel to the substrate after forming a via in a method for manufacturing a memory according to an exemplary embodiment of this application;

[0083] Figure 11B for Figure 10A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0084] Figure 12A A schematic cross-sectional view parallel to the substrate after the formation of a third conductive layer, provided as an exemplary embodiment of this application;

[0085] Figure 12B for Figure 12A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0086] Figure 13A A schematic cross-sectional view parallel to the substrate of a method for manufacturing a memory provided in an exemplary embodiment of this application, after disconnecting the semiconductor layer, gate insulating layer and third conductive layer between each via;

[0087] Figure 13B for Figure 13A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0088] Figure 14A A schematic cross-sectional view parallel to the substrate after the formation of a fourth conductive layer, provided as an exemplary embodiment of this application, of a method for manufacturing a memory.

[0089] Figure 14B for Figure 14AThe diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0090] Figure 15A A schematic cross-sectional view parallel to the substrate after forming a patterned writing line layer, provided as an exemplary embodiment of this application, of a method for manufacturing a memory.

[0091] Figure 15B for Figure 15A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0092] Figure 16A A schematic cross-sectional view of a memory manufacturing method provided in an exemplary embodiment of this application, after removing dummy read lines, parallel to the substrate;

[0093] Figure 16B for Figure 16A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0094] Figure 17A A schematic cross-sectional view parallel to the substrate after forming a read word line layer, provided as an exemplary embodiment of this application, of another method for manufacturing a memory.

[0095] Figure 17B for Figure 17A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0096] Figure 18A A schematic cross-sectional view parallel to the substrate after forming a memory node, provided as an exemplary embodiment of this application;

[0097] Figure 18B for Figure 18A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0098] Figure 19A A schematic cross-sectional view parallel to the substrate after the formation of the first line, provided as an exemplary embodiment of this application, of another method for manufacturing a memory.

[0099] Figure 19B for Figure 19A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0100] Figure 20A A schematic cross-sectional view parallel to the substrate after forming a via in another method for manufacturing a memory provided in an exemplary embodiment of this application;

[0101] Figure 20B for Figure 20A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0102] Figure 21A A schematic cross-sectional view parallel to the substrate after filling a via with a third conductive layer, provided as an exemplary embodiment of this application, of another method for manufacturing a memory.

[0103] Figure 21B for Figure 21A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate.

[0104] Figure 22A A schematic cross-sectional view parallel to the substrate after deposition of a read line layer, provided as an exemplary embodiment of this application, of another method for manufacturing a memory.

[0105] Figure 22B for Figure 22A The diagram shows a cross-section of the device taken along line AA, perpendicular to the substrate. Detailed Implementation

[0106] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0107] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values ​​shown in the drawings.

[0108] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0109] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0110] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0111] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.

[0112] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this application, unless otherwise specified, the "source electrode" and "drain electrode" can be interchanged.

[0113] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0114] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0115] In some embodiments of this application, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0116] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0117] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0118] This application provides a novel memory cell circuit design and driving method. In at least some embodiments of this application, the read transistor simultaneously participates in pre-charging and writing data during the data writing phase, and is used for reading data during the read phase. A threshold voltage V for the read transistor is implemented during the writing phase. th Compensation.

[0119] Figure 1A A logic circuit diagram of a semiconductor device provided for an exemplary embodiment of this application; Figure 1B A logic circuit diagram of another semiconductor device provided for an exemplary embodiment of this application; Figure 2A A schematic cross-sectional view parallel to the substrate of a memory device including an embodiment of the present application, provided for an exemplary embodiment of the present application; Figure 2B for Figure 2A The edge of the memory shown Figure 2A A schematic diagram of a cross-section perpendicular to the substrate, taken from line AA in the middle; Figure 3A A schematic cross-sectional view parallel to the substrate of another memory, including a semiconductor device according to an embodiment of this application, provided for exemplary embodiments of this application; Figure 3B for Figure 3A The edge of the memory shown Figure 3A A schematic diagram of a cross-section perpendicular to the substrate, taken from line AA in the middle.

[0120] like Figures 1A to 3B As shown, the semiconductor device includes a substrate 01 and at least one memory cell disposed on the substrate 01. The memory cell can be a 2TOC structure, that is, it includes a read transistor Tr_r and a write transistor Tr_w.

[0121] The read transistor Tr_r includes a first gate electrode 51, a second gate electrode 52, and a first semiconductor layer 31; the first gate electrode 51 is connected to the read word line R_WL; one end of the first semiconductor layer 31 is connected to the first bit line BL1, and the other end is connected to the second bit line BL2;

[0122] The write transistor Tr_w includes a third gate electrode 53 and a second semiconductor layer 32; one end of the second semiconductor layer 32 is electrically connected to the second gate electrode 52, and the other end is connected to the second bit line BL2; the third gate electrode 53 is connected to the write word line W_WL.

[0123] The read transistor Tr_r and the write transistor Tr_w are stacked along a direction perpendicular to the substrate.

[0124] The first line BL1 is configured to provide a data voltage, such as the voltage corresponding to writing data "1" or "0".

[0125] The second bit line BL2 is configured to provide a pre-charge voltage to the memory node SN, for example, a high voltage greater than V for an n-type transistor. data"1” +V th .

[0126] The semiconductor device of this application embodiment stacks read transistors and write transistors (e.g., stacked in a direction perpendicular to the substrate), which helps to reduce the area of ​​the memory cells of the semiconductor device and thus increase the storage density of the device. Moreover, due to the above-described circuit connection arrangement, the read transistor of the semiconductor device of this application embodiment can form a diode connection under the control of the write transistor, thereby compensating for the threshold voltage of the read transistor during the data writing stage and improving the accuracy of data reading.

[0127] In describing the operation of a semiconductor device, the following embodiments of this application use n-type transistors as an example where both the write transistor and the read transistor are read transistors.

[0128] Figure 4 The current-voltage curve of the read transistor of the semiconductor device, which is an exemplary embodiment of this application, during data readout; wherein, the "0" state represents the current-voltage curve when reading data "0", and the "1" state represents the current-voltage curve when reading data "1"; the horizontal axis V GS The vertical axis represents the voltage applied to the read line R_WL. D This indicates the magnitude of the current flowing through the read transistor Tr_r; V R This represents the set voltage value applied to the read word line R_WL during the data reading phase, and w / o current represents the current flowing through the read transistor Tr_r corresponding to this set voltage value. Figure 4 It can be seen that, when the set voltage value V RUnder the same conditions, the current of the transistor Tr_r is greater when reading data "1" than when reading data "0".

[0129] Figure 5 A timing diagram of a semiconductor device as an exemplary embodiment of this application; Figure 6 Another timing diagram of a semiconductor device as an exemplary embodiment of this application; Figure 7 This is yet another timing diagram of a semiconductor device that is an exemplary embodiment of this application.

[0130] The data write operation is as follows: Before the data write operation, a high voltage is provided to the write word line, the write transistor is turned on, a high voltage is provided to the second bit line BL2, and the memory node SN is pre-charged. This is to achieve V during the write operation. th With compensation, a high voltage is supplied to the read word line, the read transistor is turned on, and the first bit line BL1 is supplied with the data voltage V. data The data voltage passes through the source and drain electrodes of the read transistor, bypasses the current transistor, and is ultimately written into the memory node SN. During this process, the read transistor is connected as a diode, and the voltage at memory node SN is V. data +V th Therefore, read the V of the transistor. th They were compensated.

[0131] The data reading operation is as follows:

[0132] Provide low voltage V to the second bit line BL2 low (For example, grounding voltage);

[0133] A high voltage is supplied to the read word line R_WL. At this time, the voltage difference V between the storage gate of the read transistor Tr_r, i.e., the storage node SN and the source of the read transistor Tr_r, is increased. GS =V data +V th -V low V GS -V th =V data -V low For the data "1", V GS -V th If the value is >0, the transistor Tr_r will be turned on; however, for the case of data "0", V GS -V th If the value is less than 0, the transistor Tr_r remains in the "off" state.

[0134] In order to improve V th For compensation and data writing, the lower the coupling between the storage node SN and the first bit line BL1 and the second bit line BL2, the better.

[0135] in, Figures 5 to 7 The timing diagram shows that the voltage change time from high to low on the read word line R_WL differs during the data write phase. Figure 5 In this process, the high voltage supply to the read word line R_WL is stopped first, then the data on BL1 is turned off, and finally the high voltage supply to the write word line W_WL is stopped. This operating mode can reduce the impact of BL1 signal transitions on the storage node SN.

[0136] Figure 6 and Figure 7 Under normal circumstances Figure 5 Other implementation schemes can also reduce the impact of BL1 signal transitions on the storage node SN. Among them, Figure 6 First, stop supplying high voltage to the write line W_WL, then stop supplying high voltage to the read line R_WL; Figure 7 It is to synchronously stop providing high voltage to the write line W_WL and the read line R_WL.

[0137] For example, such as Figure 2B and Figure 3B As shown, the first semiconductor layer 31 extends in a direction perpendicular to the substrate, a first gate electrode 51 is provided on one side of the first semiconductor layer 31, and a second gate electrode 52 is provided on the other side of the first semiconductor layer 31.

[0138] For example, such as Figure 2B and Figure 3B As shown, the second semiconductor layer 32 extends in a direction perpendicular to the substrate, and a third gate electrode 53 is provided on one side of the second semiconductor layer 32. The second semiconductor layer 32 is connected to the first semiconductor layer 31.

[0139] The above configuration facilitates the simultaneous formation of the second semiconductor layer and the first semiconductor layer.

[0140] For example, such as Figures 2A to 3B As shown, the semiconductor device may further include a semiconductor layer 30, which includes a first semiconductor layer 31 and a second semiconductor layer 32 sequentially distributed along a direction perpendicular to the substrate.

[0141] A gate insulating layer 40 is provided between the semiconductor layer 30 and the first gate electrode 51, between the semiconductor layer 30 and the second gate electrode 52, and between the semiconductor layer 30 and the third gate electrode 53.

[0142] For example, such as Figures 2A to 3B As shown, the semiconductor device may further include a through-hole K through the read transistor Tr_r and the write transistor Tr_w;

[0143] The semiconductor layer 30 is located at least on the sidewall of the via K and is annular. The semiconductor layer 30, the gate insulating layer 40 between the semiconductor layer 30 and the second gate electrode 52, and the second gate electrode 52 are sequentially distributed in the via K along the direction away from the sidewall of the via K.

[0144] For example, such as Figures 2A to 3B As shown, both the first semiconductor layer 31 and the second semiconductor layer 32 are connected to the second bit line BL2, and the first semiconductor layer 31 is also connected to the first bit line BL1.

[0145] For example, both the read line R_WL and the write line W_WL extend along a first direction parallel to the substrate, the first gate electrode 51 is a part of the read line R_WL, and the third gate electrode 53 is a part of the write line W_WL.

[0146] For example, the first bit line BL1 and the second bit line BL2 both extend along a second direction parallel to the substrate, and the first direction intersects the second direction.

[0147] For example, the first direction can be as follows: Figure 2A The X direction shown can be the second direction as follows: Figure 2A The Y direction is shown; the first direction and the second direction can be perpendicular to each other.

[0148] For example, such as Figure 2B and Figure 3B As shown, the write transistor Tr_w may also include a fourth gate electrode 54; the fourth gate electrode 54 can increase the capacitance of the storage node and improve the storage capacity of the storage node.

[0149] The semiconductor device further includes a conductive layer (e.g., it can be a conductive layer). Figure 2B or Figure 3B The third conductive layer 11 shown in the figure includes a fourth gate electrode 54 and a second gate electrode 52 distributed sequentially along a direction perpendicular to the substrate.

[0150] The second semiconductor layer 32 at least partially surrounds the fourth gate electrode 54, and a gate insulating layer 40 is provided between the second semiconductor layer 32 and the fourth gate electrode 54.

[0151] For example, such as Figure 2B and Figure 3B As shown, the semiconductor device may further include a storage node SN, which is connected to the fourth gate electrode 54 and the second gate electrode 52.

[0152] like Figure 2BAs shown, the storage node SN can be part of the conductive layer, and a gate insulating layer 40 is provided between the second semiconductor layer 32 and the storage node SN; the second semiconductor layer 32 and the storage node SN are electrically connected through the fourth conductive layer 12.

[0153] like Figure 3B As shown, the storage node SN and the fourth gate electrode 54 can be connected and are located in different film layers. For example, the fourth gate electrode 54 is part of the conductive layer, but the conductive layer does not include the storage node SN. The second semiconductor layer 32 is connected to the storage node SN.

[0154] For example, such as Figure 2B As shown, the read transistor Tr_r can be located between the substrate and the write transistor Tr_w.

[0155] For example, such as Figure 2B As shown, the read line R_WL can be located between the substrate and the write line W_WL.

[0156] For example, such as Figure 2B As shown, the first bit line BL1 can be located between the substrate and the second bit line BL2.

[0157] For example, such as Figure 3B As shown, the write transistor Tr_w can be located between the read transistor Tr_r and the substrate.

[0158] For example, such as Figure 3B As shown, the writing line W_WL can be located between the substrate and the reading line R_WL.

[0159] For example, such as Figure 3B As shown, the second bit line BL2 can be located between the substrate and the first bit line BL1.

[0160] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0161] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0162] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0163] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0164] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0165] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A to 10 -18 A. This can improve the performance of dynamic memory.

[0166] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0167] For example, the materials of the first bit line and the second bit line can each be independently selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The first bit line and the second bit line can each be independently a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0168] For example, the materials of the first gate electrode, the second gate electrode, the third gate electrode, the fourth gate electrode, the writing line, and the reading line can each be independently selected from any one or more of the following materials:

[0169] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0170] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0171] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0172] Exemplarily, the material of the gate insulating layer may independently comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The features of the first gate insulating layer and the second gate insulating layer of this application will be described exemplarily below.

[0173] Low-K materials, such as silicon oxide.

[0174] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0175] This application also provides a memory, which includes at least one semiconductor device as provided in the above embodiments of this application.

[0176] For example, the memory also includes a first bit line BL1, a second bit line BL2, a read word line R_WL, and a write word line W_WL.

[0177] For example, the read word line R_WL and the write word line W_WL may both extend along the first direction and be connected to the memory cells of a plurality of semiconductor devices that are spaced apart on the substrate along the first direction.

[0178] For example, the first bit line BL1 and the second bit line BL2 may both extend along the second direction and be connected to the memory cells of a plurality of semiconductor devices that are spaced apart on the substrate along the second direction.

[0179] For example, the memory can be a 3D memory, such as 3D DRAM. The 3D memory can be a 2TOC structure.

[0180] This application also provides a method for manufacturing a memory.

[0181] Figure 8 A process flow diagram of a method for manufacturing a memory provided as an exemplary embodiment of this application. (See diagram for details.) Figure 8 As shown, the manufacturing method includes:

[0182] A substrate is provided on which first bit lines, second bit lines, dummy read lines and dummy write lines are formed at intervals and insulatedly distributed along a direction perpendicular to the substrate;

[0183] A through-hole is formed by etching, which at least penetrates the second bit line, the dummy read line, and the dummy write line;

[0184] A semiconductor layer, a gate insulating layer, and a conductive layer are sequentially deposited within the via.

[0185] The dummy character lines are etched away to form character lines;

[0186] The dummy writing line is removed by etching to form a writing line.

[0187] For example, forming a first bit line, a second bit line, a dummy read line, and a dummy write line spaced apart and insulatedly distributed along a direction perpendicular to the substrate on the substrate may include:

[0188] Along a direction perpendicular to the substrate, a first bit line, a dummy read line, a second bit line, and a dummy write line are sequentially formed on the substrate. The dummy read line and the dummy write line both extend along a first direction parallel to the substrate, and the first bit line and the second bit line both extend along a second direction parallel to the substrate. The first direction and the second direction intersect. The first bit line, the dummy read line, the second bit line, and the dummy write line are insulated from each other by an insulating layer.

[0189] Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes:

[0190] A through-hole is formed by etching, penetrating the second bit line, the dummy read line, and the dummy write line, and the through-hole exposes the first bit line.

[0191] For example, etching away the dummy writing line to form a writing line may include:

[0192] The insulating layer between each via is patterned and etched along the direction toward the substrate to expose the dummy writing lines;

[0193] The exposed dummy writing lines are etched laterally to remove the dummy writing lines and expose the semiconductor layer that was originally surrounded by the dummy writing lines.

[0194] A gate insulating layer and a writing line layer are deposited on the exposed area of ​​the semiconductor layer, and the writing line layer is etched back to obtain writing lines extending along the first direction.

[0195] For example, etching away the dummy reading lines to form reading lines may include:

[0196] The insulating layer between the writing line and the dummy reading line is etched to expose the dummy reading line;

[0197] The dummy read lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy read lines;

[0198] The exposed area of ​​the semiconductor layer and the gate insulating layer and read line layer of the writing line are deposited sequentially;

[0199] The reading line layer is etched back to obtain reading lines extending along the first direction.

[0200] For example, forming a first bit line, a second bit line, a dummy read line, and a dummy write line spaced apart and insulatedly distributed along a direction perpendicular to the substrate on a substrate may include:

[0201] Along a direction perpendicular to the substrate, a memory node, a dummy write line, a second bit line, a dummy read line, and a first bit line are sequentially formed on the substrate. A plurality of memory nodes are arrayed on the substrate along a first direction and a second direction parallel to the substrate. The dummy read line and the dummy write line both extend along the first direction, and the first bit line and the second bit line both extend along the second direction. The first direction and the second direction intersect. The memory node, the dummy write line, the second bit line, the dummy read line, and the first bit line are insulated from each other by an insulating layer.

[0202] Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes:

[0203] Through-holes are formed by etching, penetrating the first bit line, the second bit line, the dummy read line, and the dummy write line, and the through-holes are made to expose the memory node.

[0204] For example, etching away the dummy reading lines to form reading lines may include:

[0205] The insulating layer between each of the vias is patterned and etched along the direction toward the substrate to expose the dummy character lines;

[0206] The exposed dummy read lines are etched to remove them, revealing the semiconductor layer that was originally surrounded by the dummy read lines.

[0207] A gate insulating layer and a readout line layer are deposited on the exposed area of ​​the semiconductor layer, and the readout line layer is etched back to obtain readout lines extending along the first direction.

[0208] For example, etching away the dummy writing line to form a writing line may include:

[0209] The insulating layer between the reading line and the dummy writing line is etched to expose the dummy writing line;

[0210] The dummy writing lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy writing lines;

[0211] Sequentially deposit the exposed area covering the semiconductor layer and the gate insulating layer and the write line layer covering the read line;

[0212] The writing line layer is etched back to obtain writing lines extending along the first direction.

[0213] The technical solutions of the embodiments of this application are further illustrated below through an exemplary embodiment of the memory manufacturing process. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0214] Figures 9A to 17B and Figures 2A to 2B This is a schematic diagram illustrating intermediate steps and the structure of the final device obtained in a method for manufacturing a memory, provided as an exemplary embodiment of this application. Figure 2A , Figure 2B and Figures 9A to 17B As shown, in an exemplary embodiment, the method of manufacturing the memory may include the following processes.

[0215] S10: An insulating layer 10 is deposited on the substrate 01, a first conductive layer is deposited on the insulating layer 10, and the first conductive layer is patterned. The patterned first conductive layer includes a plurality of first first lines BL1, which are spaced apart in a first direction and extend along a second direction, such as... Figure 9A and Figure 9B As shown, where, Figure 9A The cross section parallel to the substrate passes through the first line BL1.

[0216] For example, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may intersect, for example, they may be perpendicular to each other. For example, the first direction may be as follows: Figure 9A The X direction shown can be the second direction as follows: Figure 9A Y direction shown.

[0217] For example, the material forming the insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0218] S20: A dummy read line 21, a second bit line BL2, and a dummy write line 22 are deposited on the patterned surface of the first conductive layer, such as... Figure 10A and Figure 10B As shown, where, Figure 10A The cross section parallel to the substrate passes through the dummy writing line.

[0219] For example, step S20 may include:

[0220] S21: Deposit an insulating layer 10 on the patterned surface of the first conductive layer and planarize it;

[0221] S22: A dummy readout line layer is deposited on the substrate surface obtained in step S21, and the dummy readout line layer is patterned. The patterned dummy readout line layer includes a plurality of dummy readout lines 21 that extend along the first direction and are spaced apart in the second direction.

[0222] S23: Deposit an insulating layer 10 on the surface of the patterned dummy reading line layer and flatten it;

[0223] S24: A second conductive layer is deposited on the surface of the structure obtained in step S23, and the second conductive layer is patterned. The patterned second conductive layer includes a plurality of second bit lines BL2, each second bit line BL2 extending along the second direction, and the plurality of second bit lines BL2 are spaced apart in the first direction.

[0224] S25: Deposit an insulating layer 10 on the patterned surface of the second conductive layer and planarize it;

[0225] S26: A dummy writing line layer is deposited on the structural surface obtained in step S25, and the dummy writing line layer is patterned. The patterned dummy writing line layer includes a plurality of dummy writing lines 22 that extend along the first direction and are spaced apart in the second direction.

[0226] S30: Etch the patterned dummy read line layer, the second conductive layer, and the dummy write line layer to form a via K that penetrates the patterned dummy read line layer, the second conductive layer, and the dummy write line layer, and make one via K pass through one dummy read line 21 and one dummy write line 22, such as... Figure 11A and Figure 11B As shown, where, Figure 11A The cross section parallel to the substrate passes through the first line BL1.

[0227] like Figure 11A and Figure 11B As shown, the orthogonal projection of the via K on the substrate falls completely within the range of the orthogonal projection of the second bit line BL2 that the via K penetrates on the substrate, that is, the sidewall of the via K exposes the second bit line BL2.

[0228] For example, each via K may extend into each first line BL1 but not through the first line BL1; the via K may extend in a direction perpendicular to the substrate.

[0229] S40: A semiconductor layer 30 and a gate insulating layer 40 are sequentially deposited on the inner wall (including the sidewall and bottom wall) of the via K, and a third conductive layer 11 is filled inside the via K, as shown. Figure 12A and Figure 12B As shown, where, Figure 12A The cross section parallel to the substrate passes through the second bit line BL2.

[0230] For example, the semiconductor layer 30, the gate insulating layer 40, and the third conductive layer 11 may also cover the area between each via K.

[0231] S50: Isolate each storage unit.

[0232] For example, step S50 may include:

[0233] S51: Disconnect the semiconductor layer 30, gate insulating layer 40, and third conductive layer 11 located between each via K, exposing the semiconductor layer 30, gate insulating layer 40, the third conductive layer 11 filled in the via K, and the area between each via K, such as... Figure 13A and Figure 13B As shown;

[0234] S52: A fourth conductive layer 12 is deposited on the exposed area between each via K, and the fourth conductive layer 12 is patterned and etched. The patterned fourth conductive layer 12 surrounds the opening of the via K and is connected to the semiconductor layer 30 and the third conductive layer 11 in each via K, but the patterned fourth conductive layer 12 is disconnected between each via K.

[0235] S53: An insulating layer 10 is deposited on the substrate obtained in step S52 to cover the exposed areas between each via K, such as... Figure 14A and Figure 14B As shown, where, Figure 14A The cross section parallel to the substrate penetrates the fourth conductive layer and the via.

[0236] S60: Etch away the dummy writing lines 22 to form a writing line layer 13, and perform patterned etching on the writing line layer 13 to expose the patterned fourth conductive layer 12. A hard mask 14 is then formed on the patterned fourth conductive layer 12. Figure 15A and Figure 15B As shown, where, Figure 15A The cross section parallel to the substrate penetrates the writing line layer and the hard mask.

[0237] For example, step S60 may include:

[0238] S61: Pattern the insulating layer 10 between each via K along the direction toward the substrate to expose the dummy writing line 22;

[0239] S62: Perform lateral etching on the exposed dummy writing line 22. For example, wet etching can be used to perform lateral etching to remove the dummy writing line 22 and expose the semiconductor layer 30 that was originally surrounded by the dummy writing line 22.

[0240] S63: Deposit a gate insulating layer 40 and a word line layer 13 on the exposed area of ​​the semiconductor layer 30, and perform patterned etching on the word line layer 13 to expose a patterned fourth conductive layer 12, and form a hard mask 14 on the patterned fourth conductive layer 12.

[0241] S70: Form the writing line W_WL and etch away the dummy reading line, such as Figure 16A and Figure 16B As shown, where, Figure 16A The cross section parallel to the substrate runs through the writing line.

[0242] For example, step S70 may include:

[0243] S71: Re-engraving the writing line layer 13 to form the writing line W_WL;

[0244] S72: Selectively etch the insulating layer 10 to expose the dummy read lines, and etch away the dummy read lines. For example, wet etching can be used to remove the dummy read lines and expose the semiconductor layer 30 that was originally surrounded by the dummy read lines.

[0245] S80: Divide the word line layer into multiple spaced word lines R_WL, such as Figure 2A and Figure 2B As shown, where, Figure 2A The cross section parallel to the substrate runs through the reading line.

[0246] For example, step S80 may include:

[0247] S81: On the structure obtained in step S70, a gate insulating layer 40 and a read word line layer are sequentially deposited. The gate insulating layer 40 and the read word line layer cover the exposed area of ​​the semiconductor layer 30 and the write word line W_WL, as shown. Figure 17A and Figure 17B As shown;

[0248] S82: Re-etch the reading line layer that covers the writing line W_WL, and retain the reading line layer located at the original virtual reading line position, thus obtaining multiple spaced reading lines R_WL;

[0249] S83: An insulating layer 10 is deposited on the structure obtained in step S82, covering the writing lines W_WL and the reading lines R_WL, to obtain the structure as shown in step S82. Figure 2A and Figure 2B The memory shown.

[0250] Figures 18A to 22B and Figures 3A to 3B This is a schematic diagram illustrating the intermediate process and the structure of the final device obtained in another method for manufacturing a memory provided as an exemplary embodiment of this application. Figure 3A , Figure 3B and Figures 18A to 22B As shown, in an exemplary embodiment, the method of manufacturing the memory may include the following processes.

[0251] S100: An insulating layer 10 is deposited on a substrate, and a fifth conductive layer is deposited on the insulating layer 10; the fifth conductive layer is patterned, and the patterned fifth conductive layer includes a plurality of memory nodes SN arranged in an array along a first direction (e.g., the X direction as shown in 18A) and a second direction (e.g., the Y direction as shown in 18A), such as... Figure 18A and Figure 18B As shown, where, Figure 18A The cross section parallel to the substrate penetrates the storage node SN.

[0252] S200: Dummy write line 22, second bit line BL2, dummy read line 21, and first bit line BL1 are deposited on the patterned surface of the fifth conductive layer, such as... Figure 19A and Figure 19B As shown, where, Figure 19A The cross section parallel to the substrate passes through the first line BL1.

[0253] For example, step S20 may include:

[0254] S201: An insulating layer 10 is deposited on the patterned surface of the fifth conductive layer and then planarized;

[0255] S202: A dummy writing line layer is deposited on the structural surface obtained in step S201. The dummy writing line layer is patterned. The patterned dummy writing line layer includes a plurality of dummy writing lines 22 that extend along the first direction and are spaced apart in the second direction.

[0256] S203: Deposit an insulating layer 10 on the surface of the patterned virtual writing line layer and planarize it;

[0257] S204: A second conductive layer is deposited on the substrate surface obtained in step S203, and the second conductive layer is patterned. The patterned second conductive layer includes a plurality of second bit lines BL2, each second bit line BL2 extending along the second direction, and the plurality of second bit lines BL2 are spaced apart in the first direction.

[0258] S205: Deposit an insulating layer 10 on the patterned surface of the second conductive layer and planarize it;

[0259] S206: A dummy readout line layer is deposited on the substrate surface obtained in step S205, and the dummy readout line layer is patterned. The patterned dummy readout line layer includes a plurality of dummy readout lines 21 that extend along the first direction and are spaced apart in the second direction.

[0260] S207: Deposit an insulating layer 10 on the surface of the patterned dummy reading line layer and planarize it;

[0261] S208: A first conductive layer is deposited on the surface of the structure obtained in step S207, and the first conductive layer is patterned. The patterned first conductive layer includes a plurality of first first lines BL1, each first first line BL1 extending along the second direction, and the plurality of first first lines BL1 are spaced apart in the first direction, such as... Figure 19A and Figure 19B As shown, where, Figure 19A The cross section parallel to the substrate passes through the first line BL1.

[0262] S300: Etch the patterned first conductive layer, dummy read line layer, second conductive layer, and dummy write line layer to form a via K that penetrates the patterned first conductive layer, dummy read line layer, second conductive layer, and dummy write line layer, and make one via K pass through one dummy read line 21 and one dummy write line 22, such as... Figure 20A and Figure 20B As shown, where, Figure 20A The cross section parallel to the substrate passes through the first line BL1.

[0263] like Figure 20A and Figure 20B As shown, the orthogonal projection of the via K onto the substrate falls completely within the range of the orthogonal projections of the first line BL1 and the second line BL2 that the via K penetrates onto the substrate, that is, the sidewall of the via K exposes the first line BL1 and the second line BL2.

[0264] For example, each via K may extend into each memory node SN but not through the memory node SN; the via K may extend in a direction perpendicular to the substrate.

[0265] S400: A semiconductor layer 30 and a gate insulating layer 40 are sequentially deposited on the inner wall of the via K, and a third conductive layer 11 is filled inside the via K.

[0266] For example, step S400 may include:

[0267] S401: The semiconductor layer 30 and the gate insulating layer 40 are sequentially deposited on the structural surface obtained in step S300, covering the inner wall (including the side wall and bottom wall) of the via K and the exposed area between each via K;

[0268] S402: Etch away the semiconductor layer 30 and gate insulating layer 40 on the bottom wall of the via K to expose each memory node SN;

[0269] S403: A third conductive layer 11 is filled in the via K, wherein the third conductive layer 11 in each via K is connected to each storage node SN.

[0270] S404: Deposit a third conductive layer 11 covering the via K and an insulating layer 10 covering the exposed areas between the vias K on the structure obtained in step S403, such as Figure 21A and Figure 21B As shown, where, Figure 21A The cross section parallel to the substrate passes through the second bit line BL2.

[0271] S500: Etching removes dummy character lines, depositing 15 character line layers, such as... Figure 22A and Figure 22B As shown, where, Figure 22A The cross section parallel to the substrate penetrates the hard mask.

[0272] For example, step S500 may include:

[0273] S501: Pattern the semiconductor layer 30, gate insulating layer 40 and insulating layer 10 between each via K along the direction toward the substrate to expose the dummy read line 21;

[0274] S502: Etching to remove the dummy read line 21. For example, wet etching can be used to remove the dummy read line 21, exposing the semiconductor layer 30 that was originally surrounded by the dummy read line 21.

[0275] S503: A gate insulating layer 40 and a read word line layer 15 are deposited on the exposed area of ​​the semiconductor layer 30, and the read word line layer 15 is patterned and etched to expose the insulating layer 10 covering the via K, and a hard mask 14 is formed on the insulating layer 10 covering the via K.

[0276] S600: Etch away the dummy writing line 22 to form the writing line W_WL.

[0277] For example, step S600 may include:

[0278] S601: The patterned read line layer 15 and insulating layer 10 between each via K are etched along the direction toward the substrate to expose the dummy write line 22. At the same time, the patterned read line layer 15 between each via K is broken to obtain multiple spaced read lines R_WL.

[0279] S602: Etching removes the dummy write lines 22, exposing the semiconductor layer 30 that was originally surrounded by the dummy write lines 22;

[0280] S603: On the structure obtained in step S602, a gate insulating layer 40 and a write word line layer are deposited sequentially. The gate insulating layer 40 and the write word line layer cover the exposed area of ​​the semiconductor layer 30 and the read word line R_WL.

[0281] 604: Re-etch the writing line layer that covers the reading line R_WL, and retain the writing line layer located at the original virtual writing line position, thus obtaining multiple spaced writing lines W_WL;

[0282] S605: An insulating layer 10 covering the write line W_WL and the read line R_WL is deposited on the substrate obtained in step S604, resulting in... Figure 3A and Figure 3B The memory shown.

[0283] This application also provides an electronic device, which includes the memory provided in the above embodiments of this application.

[0284] For example, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0285] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, Includes a substrate and at least one memory cell disposed on the substrate, the memory cell comprising: The read transistor includes a first gate electrode, a second gate electrode, and a first semiconductor layer; the first gate electrode is directly connected to the read word line; one end of the first semiconductor layer is connected to the first bit line, and the other end is connected to the second bit line; The write transistor includes a third gate electrode and a second semiconductor layer; one end of the second semiconductor layer is electrically connected to the second gate electrode, and the other end is connected to a second bit line; the third gate electrode is connected to the write word line. The read transistor and the write transistor are stacked in a direction perpendicular to the substrate.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor layer extends in a direction perpendicular to the substrate, and a first gate electrode is disposed on one side of the first semiconductor layer, and a second gate electrode is disposed on the other side of the first semiconductor layer.

3. The semiconductor device according to claim 1, characterized in that, The second semiconductor layer extends in a direction perpendicular to the substrate, and the third gate electrode is disposed on one side of the second semiconductor layer. The second semiconductor layer is connected to the first semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, Includes a semiconductor layer, the semiconductor layer comprising a first semiconductor layer and a second semiconductor layer sequentially distributed along a direction perpendicular to the substrate; A gate insulating layer is provided between the semiconductor layer and the first gate electrode, between the semiconductor layer and the second gate electrode, and between the semiconductor layer and the third gate electrode.

5. The semiconductor device according to claim 4, characterized in that, It also includes a through-hole that extends through the read transistor and the write transistor; The semiconductor layer is located at least on the sidewall of the via and is annular. The semiconductor layer, the gate insulating layer between the semiconductor layer and the second gate electrode, and the second gate electrode are sequentially distributed in the via along a direction away from the sidewall of the via.

6. The semiconductor device according to claim 4, characterized in that, Both the read line and the write line extend along a first direction parallel to the substrate, the first gate electrode is a part of the read line, and the third gate electrode is a part of the write line; and / or, Both the first bit line and the second bit line extend along a second direction parallel to the substrate, and the first direction intersects the second direction.

7. The semiconductor device according to claim 1, characterized in that, The write transistor further includes a fourth gate electrode; The semiconductor device further includes a conductive layer, the conductive layer comprising the fourth gate electrode and the second gate electrode sequentially distributed along a direction perpendicular to the substrate; The second semiconductor layer at least partially surrounds the fourth gate electrode, and a gate insulating layer is present between the second semiconductor layer and the fourth gate electrode.

8. The semiconductor device according to claim 7, characterized in that, It also includes a storage node, which is connected to the fourth gate electrode and the second gate electrode; The memory node is part of the conductive layer, and a gate insulating layer is provided between the second semiconductor layer and the memory node. The second semiconductor layer and the memory node are electrically connected through a fourth conductive layer; or, the memory node is connected to the fourth gate electrode and is located in different film layers, and the second semiconductor layer is connected to the memory node.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The read transistor is located between the substrate and the write transistor; The reading line is located between the substrate and the writing line; The first bit line is located between the substrate and the second bit line.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The write transistor is located between the read transistor and the substrate; The writing line is located between the substrate and the reading line; The second bit line is located between the substrate and the first bit line.

11. A memory, characterized in that, It includes at least one semiconductor device according to any one of claims 1 to 10.

12. A method for manufacturing a memory, characterized in that, include: Provide substrate; A first bit line, a second bit line, a dummy read line, and a dummy write line are formed on the substrate, spaced apart and insulated from each other along a direction perpendicular to the substrate; A through-hole is formed by etching, which at least penetrates the second bit line, the dummy read line, and the dummy write line; A semiconductor layer, a gate insulating layer, and a conductive layer are sequentially deposited within the via. The conductive layer includes a second gate electrode of a readout transistor; The dummy read lines are etched away to form read lines; the read lines include the first gate electrode of the read transistor. The dummy writing line is removed by etching to form a writing line.

13. The manufacturing method according to claim 12, characterized in that, A first bit line, a second bit line, a dummy read line, and a dummy write line are formed on the substrate, spaced apart and insulated from each other along a direction perpendicular to the substrate, including: Along a direction perpendicular to the substrate, a first bit line, a dummy read line, a second bit line, and a dummy write line are sequentially formed on the substrate. The dummy read line and the dummy write line both extend along a first direction parallel to the substrate, and the first bit line and the second bit line both extend along a second direction parallel to the substrate. The first direction and the second direction intersect. The first bit line, the dummy read line, the second bit line, and the dummy write line are insulated from each other by an insulating layer. Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes: A through-hole is formed by etching, penetrating the second bit line, the dummy read line, and the dummy write line, and the through-hole exposes the first bit line.

14. The manufacturing method according to claim 13, characterized in that, Etching removes the dummy writing line to form a writing line, including: The insulating layer between each via is patterned and etched along the direction toward the substrate to expose the dummy writing lines; The exposed dummy writing lines are etched laterally to remove the dummy writing lines and expose the semiconductor layer that was originally surrounded by the dummy writing lines. A gate insulating layer and a writing line layer are deposited on the exposed area of ​​the semiconductor layer, and the writing line layer is etched back to obtain writing lines extending along the first direction.

15. The manufacturing method according to claim 14, characterized in that, Etching removes the dummy character lines to form character lines, including: The insulating layer between the writing line and the dummy reading line is etched to expose the dummy reading line; The dummy read lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy read lines; The exposed area of ​​the semiconductor layer and the gate insulating layer and read line layer of the writing line are deposited sequentially; The reading line layer is etched back to obtain reading lines extending along the first direction.

16. The manufacturing method according to claim 12, characterized in that, A first bit line, a second bit line, a dummy read line, and a dummy write line are formed on the substrate, spaced apart and insulated from each other along a direction perpendicular to the substrate, including: Along a direction perpendicular to the substrate, a memory node, a dummy write line, a second bit line, a dummy read line, and a first bit line are sequentially formed on the substrate. A plurality of memory nodes are arrayed on the substrate along a first direction and a second direction parallel to the substrate. The dummy read line and the dummy write line both extend along the first direction, and the first bit line and the second bit line both extend along the second direction. The first direction and the second direction intersect. The memory node, the dummy write line, the second bit line, the dummy read line, and the first bit line are insulated from each other by an insulating layer. Forming a through-hole by etching that at least penetrates the second bit line, the dummy read line, and the dummy write line includes: Through-holes are formed by etching, penetrating the first bit line, the second bit line, the dummy read line, and the dummy write line, and the through-holes are made to expose the memory node.

17. The manufacturing method according to claim 16, characterized in that, Etching removes the dummy character lines to form character lines, including: The insulating layer between each of the vias is patterned and etched along the direction toward the substrate to expose the dummy character lines; The exposed dummy read lines are etched to remove them, revealing the semiconductor layer that was originally surrounded by the dummy read lines. A gate insulating layer and a readout line layer are deposited on the exposed area of ​​the semiconductor layer, and the readout line layer is etched back to obtain readout lines extending along the first direction.

18. The manufacturing method according to claim 17, characterized in that, Etching removes the dummy writing line to form a writing line, including: The insulating layer between the reading line and the dummy writing line is etched to expose the dummy writing line; The dummy writing lines are etched away to expose the semiconductor layer that was originally surrounded by the dummy writing lines; Sequentially deposit the exposed area covering the semiconductor layer and the gate insulating layer and the write line layer covering the read line; The writing line layer is etched back to obtain writing lines extending along the first direction.

19. An electronic device, characterized in that, Includes the memory according to claim 11.

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