Array substrate and display device

Abstract

This invention discloses an array substrate and a display device. The array substrate includes a substrate, a pixel circuit on the substrate, and a first trace. The pixel circuit includes a driving transistor, a storage capacitor, at least one first capacitor, and at least one preset transistor. The storage capacitor includes a first electrode plate and a second electrode plate stacked along the thickness direction of the substrate. The first electrode plate is connected to the gate of the driving transistor. In at least a portion of the first capacitors, the second electrode plate is reused as an electrode plate of the first capacitor. The first capacitor also includes a third electrode plate, and the preset transistor is connected to the third electrode plate. The first trace is located on the side of the third electrode plate of at least a portion of the first capacitors away from the second electrode plate. At least a portion of the first trace is reused as an electrode plate of the first capacitor. The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate to form a portion of the first capacitor. This solution is beneficial for improving display effect and increasing layout utilization.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the performance of display panels.

[0003] Currently, existing display panels suffer from poor display quality. Summary of the Invention

[0004] This invention provides an array substrate and a display device to improve display performance.

[0005] According to one aspect of the present invention, an array substrate is provided, comprising:

[0006] Base;

[0007] A pixel circuit is located on a substrate. The pixel circuit includes a driving transistor, a storage capacitor, at least one first capacitor, and at least one preset transistor. The storage capacitor includes a first electrode plate and a second electrode plate stacked along the thickness direction of the substrate. The first electrode plate of the storage capacitor is connected to the gate of the driving transistor. In at least a portion of the first capacitors, the second electrode plate is reused as an electrode plate of the first capacitor. The first capacitor also includes a third electrode plate located on the side of the second electrode plate away from the first electrode plate. The preset transistor is connected to the third electrode plate.

[0008] The first trace is located on the side of the third plate of at least a portion of the first capacitors away from the second plate. At least a portion of the first trace is multiplexed as a plate of the first capacitor. The orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the third plate on the substrate to form a portion of the first capacitor.

[0009] The first insulating layer is located between the first electrode plate and the second electrode plate;

[0010] The second insulating layer is located between the second electrode plate and the third electrode plate;

[0011] The third insulating layer is located between the third electrode plate and the first trace.

[0012] Optionally, in at least a portion of the first capacitors, the overlapping area of ​​the orthographic projection of the first plate on the substrate and the orthographic projection of the second plate on the substrate overlaps with the orthographic projection of the third plate on the substrate.

[0013] Optionally, in at least a portion of the first capacitors, the orthographic projection of the second plate on the substrate overlaps with the orthographic projection of the third plate on the substrate to form a first sub-capacitor of the first capacitor, and the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the third plate on the substrate to form a second sub-capacitor of the first capacitor.

[0014] Optionally, the second electrode plate is electrically connected to the first trace;

[0015] Optionally, the first sub-capacitor and the second sub-capacitor are connected in parallel;

[0016] Optionally, the first electrode is located between the substrate and the second electrode;

[0017] Optionally, the first plate of the storage capacitor is reused as the gate of the driving transistor;

[0018] Optionally, the array substrate further includes data lines, with the first trace extending along a first direction and the data lines disposed on the same layer.

[0019] Optionally, the orthographic projection of the third electrode plate onto the substrate lies within the orthographic projection of the first trace onto the substrate;

[0020] Optionally, the second electrode plate and the first trace are connected to a power supply voltage or DC potential.

[0021] Optionally, in at least a portion of the first capacitors, the overlapping area of ​​the orthographic projection of the first plate on the substrate and the orthographic projection of the second plate on the substrate, the overlapping area of ​​the orthographic projection of the third plate on the substrate, overlaps with the orthographic projection of the first trace on the substrate.

[0022] Optionally, in at least a portion of the first capacitors, the area of ​​the overlapping region between the orthographic projection of the second plate on the substrate and the orthographic projection of the third plate on the substrate is smaller than the area of ​​the overlapping region between the orthographic projection of the third plate on the substrate and the orthographic projection of the first trace on the substrate.

[0023] Optionally, in at least a portion of the first capacitors, the area of ​​the overlapping region of the orthographic projection of the first plate on the substrate and the orthographic projection of the second plate on the substrate, and the area of ​​the overlapping region of the orthographic projection of the third plate on the substrate, are smaller than the area of ​​the overlapping region of the orthographic projection of the third plate on the substrate and the orthographic projection of the first trace on the substrate.

[0024] Optionally, it further includes: a second trace connected to the gate of the driving transistor, at least a portion of the second trace being multiplexed as a plate of a storage capacitor, at least a portion of the first trace being multiplexed as a plate of a storage capacitor, and the orthographic projection of the second trace on the substrate overlapping with the orthographic projection of the first trace on the substrate to form a portion of the storage capacitor.

[0025] Optionally, the orthographic projection of the second trace on the substrate and the orthographic projection of the third electrode plate on the substrate are spaced apart;

[0026] Optionally, the second trace is installed on the same layer as the third electrode plate;

[0027] Optionally, the second trace extends along the first trace in the first direction;

[0028] Optionally, the orthographic projection of the second trace on the substrate lies within the orthographic projection of the first trace on the substrate.

[0029] Optionally, the pixel circuit further includes at least one auxiliary transistor, the preset electrode of the auxiliary transistor is connected to the third plate, and the preset transistor is connected between the preset electrode of the auxiliary transistor and the driving transistor.

[0030] Optionally, at least one preset transistor includes a first transistor, at least one auxiliary transistor includes a second transistor, the first terminal of the first transistor is connected to the gate of the driving transistor, the second terminal of the first transistor and the first terminal of the second transistor are connected to a third plate, and the second terminal of the second transistor is connected to the first terminal of the driving transistor.

[0031] Optionally, at least one preset transistor includes a third transistor, at least one auxiliary transistor includes a fourth transistor, the first terminal of the third transistor is connected to the gate of the driving transistor, the second terminal of the third transistor and the first terminal of the fourth transistor are connected to a third plate, and the second terminal of the fourth transistor is connected to an initialization signal line.

[0032] Optionally, at least one preset transistor includes a fifth transistor, at least one auxiliary transistor includes a sixth transistor, and the pixel circuit further includes a seventh transistor. The first terminal of the fifth transistor is connected to the gate of the driving transistor, the second terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor are connected to the third plate, the second terminal of the sixth transistor is connected to the first terminal of the driving transistor, and the second terminal of the seventh transistor is connected to the initialization signal line.

[0033] Optionally, at least one preset transistor includes an eighth transistor, the first terminal of the eighth transistor and the second terminal of the driving transistor are connected to the third plate, and the second terminal of the eighth transistor is connected to the data line.

[0034] At least one preset transistor includes an eighth transistor, at least one auxiliary transistor includes a ninth transistor, the first terminal of the eighth transistor is connected to the second terminal of the driving transistor, the second terminal of the eighth transistor and the first terminal of the ninth transistor are connected to a third plate, and the second terminal of the ninth transistor is connected to a data line.

[0035] Optionally, at least one preset transistor includes a first transistor and a tenth transistor, and at least one auxiliary transistor includes a second transistor and an eleventh transistor;

[0036] The first terminal of the tenth transistor is connected to the gate of the driving transistor, the second terminal of the tenth transistor is connected to the first terminal of the eleventh transistor, the first terminal of the first transistor is connected to the second terminal of the eleventh transistor, the first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the driving transistor.

[0037] In the same pixel circuit, there is one first capacitor and one third plate; or, there are at least two first capacitors and at least two third plates, the second terminal of the first transistor and the first terminal of the second transistor are connected to the third plate, and / or, the first terminal of the first transistor and the second terminal of the eleventh transistor are connected to the third plate, and / or, the first terminal of the eleventh transistor and the second terminal of the tenth transistor are connected to the third plate.

[0038] Optionally, in the same pixel circuit, there are at least two third plates, and the at least two third plates are arranged at intervals.

[0039] The orthographic projection of the third plate of each first capacitor onto the substrate overlaps with the orthographic projection of the first trace onto the substrate, and the orthographic projection of the third plate of each first capacitor onto the substrate overlaps with the orthographic projection of the second plate onto the substrate.

[0040] Alternatively, the orthographic projection of the third plate of each first capacitor onto the substrate overlaps with the orthographic projection of the first trace onto the substrate; the orthographic projection of the third plate of a portion of the first capacitors onto the substrate overlaps with the orthographic projection of the second plate onto the substrate; and the orthographic projection of the third plate of a portion of the first capacitors onto the substrate does not overlap with the orthographic projection of the second plate onto the substrate.

[0041] Optionally, the ratio of the capacitance of the storage capacitor to that of the first capacitor is greater than or equal to 1:4 and less than or equal to 4:1; Optionally, the second insulating layer is an inorganic insulating layer and the third insulating layer is an inorganic insulating layer; Optionally, the thickness of the second insulating layer is greater than or equal to 2000 angstroms and less than or equal to 2500 angstroms; Optionally, the thickness of the third insulating layer is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

[0042] Optionally, the array substrate further includes a multilayer conductive layer stacked on one side of the substrate, comprising a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked on one side of the substrate, wherein a first electrode plate is located on the first conductive layer, a second electrode plate is located on the second conductive layer, a third electrode plate and a second trace are located on the third conductive layer, and a first trace is located on the fourth conductive layer.

[0043] Optionally, the array substrate further includes an active layer and a fourth insulating layer, wherein the active layer is located between the first conductive layer and the substrate, the fourth insulating layer is located between the active layer and the first conductive layer, the first insulating layer is located between the first conductive layer and the second conductive layer, the second insulating layer is located between the second conductive layer and the third conductive layer, and the third insulating layer is located between the third conductive layer and the fourth conductive layer.

[0044] Optionally, at the intersection of the first trace and the second electrode plate, the first trace is connected to the second electrode plate via a first via.

[0045] Optionally, the gate of the driving transistor is connected to the second trace via a second via, and the active layer is connected to the second trace via a third via; the active layer includes the active portion of a preset transistor, and the active portion of the preset transistor is connected to the third electrode via a fourth via.

[0046] Optionally, the first via penetrates the third insulating layer and the second insulating layer, the second via penetrates the second insulating layer and the first insulating layer, the third via penetrates the second insulating layer, the first insulating layer and the fourth insulating layer, and the fourth via penetrates the second insulating layer, the first insulating layer and the fourth insulating layer.

[0047] Optionally, the array substrate further includes a second trace connected to the gate of the driving transistor, wherein the second trace is disposed in a different layer from the third electrode plate;

[0048] Optionally, the array substrate further includes a multilayer conductive layer stacked on one side of the substrate, comprising a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the multilayer conductive layer, wherein a first electrode plate is located on the first conductive layer, a second electrode plate is located on the second conductive layer, a third electrode plate is located on the third conductive layer, and a first trace and a second trace are located on the fourth conductive layer.

[0049] Optionally, the array substrate further includes an active layer and a fourth insulating layer, wherein the active layer is located between the first conductive layer and the substrate, the fourth insulating layer is located between the active layer and the first conductive layer, the first insulating layer is located between the first conductive layer and the second conductive layer, the second insulating layer is located between the second conductive layer and the third conductive layer, and the third insulating layer is located between the third conductive layer and the fourth conductive layer.

[0050] Optionally, at the intersection of the first trace and the second electrode plate, the first trace is connected to the second electrode plate via a first via.

[0051] Optionally, the gate of the driving transistor is connected to the second trace via a second via, and the active layer is connected to the second trace via a third via; the active layer includes the active portion of a preset transistor, and the active portion of the preset transistor is connected to the third electrode via a fourth via.

[0052] Optionally, the first via penetrates the third insulating layer and the second insulating layer, the second via penetrates the third insulating layer, the second insulating layer and the first insulating layer, the third via penetrates the third insulating layer, the second insulating layer, the first insulating layer and the fourth insulating layer, and the fourth via penetrates the second insulating layer, the first insulating layer and the fourth insulating layer.

[0053] Optionally, the array substrate further includes a data line, with the second trace extending along the first direction and the data line on the same layer as the first trace; optionally, the data line is connected to the active layer through a fifth via, the fifth via penetrating the third insulating layer, the second insulating layer, the first insulating layer, and the fourth insulating layer; or, the array substrate further includes a transition portion, the film layer of which the transition portion is located between the film layer of the data line and the active layer, the data line being connected to the transition portion through a sixth via, and the active layer being connected to the transition portion through a seventh via; optionally, the transition portion and the third electrode plate are on the same layer. Layer configuration; and / or, the adapter and the second trace are configured on the same layer; optionally, the sixth via penetrates the third insulating layer; the seventh via penetrates the second insulating layer, the first insulating layer, and the fourth insulating layer; optionally, the orthographic projection of the adapter on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate, and the orthographic projection of the adapter on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate; optionally, the overlapping area of ​​the orthographic projection of the data line on the substrate and the orthographic projection of the active layer on the substrate overlaps with the orthographic projection of the adapter on the substrate.

[0054] The array substrate further includes a first scan line, a second scan line, and an active layer, corresponding to the same pixel circuit. The orthographic projection of the second scan line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first scan line on the substrate. The first scan line overlaps with the active layer to form the tenth transistor, the eleventh transistor, and the first transistor, respectively, and the second scan line overlaps with the active layer to form the second transistor. Optionally, the pixel circuit further includes a data writing transistor, which is formed by the second scan line overlapping with the active layer and is connected between the data line and the second electrode of the driving transistor. Optionally, the pixel circuit further includes a data writing transistor, which is formed by the second scan line overlapping with the active layer and is connected between the data line and the second electrode of the driving transistor. Optionally, the third scan line and the fourth scan line are disposed on the same layer, and the third scan line and the initialization signal line are disposed on different layers. Optionally, the third scan line and the fourth scan line are disposed on the same layer as the gate or the first electrode of the driving transistor, and the initialization signal line is disposed on the same layer as the second electrode.

[0055] Optionally, the pixel circuit further includes a bias transistor, and the array substrate further includes a bias voltage signal line. The fourth scan line overlaps with the active layer to form a bias transistor. The bias transistor is connected between the bias voltage signal line and the first terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the first terminal of the driving transistor; or, the bias transistor is connected between the bias voltage signal line and the second terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the second terminal of the driving transistor.

[0056] Optionally, the bias voltage signal line is disposed on the same layer as the second plate or the initialization signal line;

[0057] Optionally, for the same pixel circuit, the orthographic projection of the bias voltage signal line on the substrate is located between the orthographic projection of the third scan line on the substrate and the orthographic projection of the fourth scan line connected to the bias transistor on the substrate.

[0058] Optionally, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, and the array substrate further includes a light-emitting control signal line. The light-emitting control signal line overlaps with the active layer to form the first light-emitting control transistor and the second light-emitting control transistor. The first electrode of the first light-emitting control transistor is connected to the first trace, the second electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor, and the second light-emitting control transistor is connected between the first electrode of the driving transistor and the first electrode of the light-emitting element.

[0059] Optionally, the light emission control signal line is disposed on the same layer as the gate or first plate of the driving transistor;

[0060] Optionally, for the same pixel circuit, the orthographic projection of the third scan line on the substrate is located on the side where the orthographic projection of the first scan line on the substrate is far away from the orthographic projection of the gate of the driving transistor on the substrate.

[0061] Optionally, corresponding to the same pixel circuit, the orthographic projection of the fourth scan line connected to the bias transistor on the substrate is located on the side of the orthographic projection of the third scan line on the substrate away from the orthographic projection of the gate of the driving transistor on the substrate; Optionally, corresponding to the same pixel circuit, the orthographic projection of the initialization signal line adjacent to the bias transistor on the substrate is located on the side of the orthographic projection of the fourth scan line connected to the bias transistor on the substrate away from the orthographic projection of the bias voltage signal line on the substrate; Optionally, corresponding to the same pixel circuit, the orthographic projection of the light emission control signal line on the substrate is located on the side of the orthographic projection of the gate of the driving transistor on the substrate away from the orthographic projection of the second scan line on the substrate; Optionally, the orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the first scan line on the substrate; Optionally, the orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the third scan line. The orthographic projections on the substrate overlap; optionally, the array substrate further includes a connecting line, which connects between the initialization signal line and the second initialization transistor, and the orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the fourth scan line on the substrate; the orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the first trace on the substrate; optionally, the orthographic projection of the connecting line on the substrate is located within the orthographic projection of the first trace on the substrate; optionally, the connecting line is disposed on the same layer as the third electrode plate; optionally, the array substrate further includes a connecting portion, through which the first trace is connected to the first electrode of the first light-emitting control transistor; optionally, the connecting portion is disposed on the same layer as the third electrode plate; optionally, in two adjacent rows of pixel circuits, the bias transistor in the current row of pixel circuits and the second initialization transistor in the previous row of pixel circuits are formed by overlapping with the active layer through the same fourth scan line.

[0062] Optionally, the operation of the pixel circuit includes a write frame and a hold frame. Within the write frame, the first scan signal transmitted on the first scan line, the second scan signal transmitted on the second scan line, the third scan signal transmitted on the third scan line, and the fourth scan signal transmitted on the fourth scan line each include at least two pulses. The start time of the first pulse of the first scan signal is after the end time of the first pulse of the third scan signal, and the first pulse of the first scan signal at least partially overlaps with the second pulse of the third scan signal. The start time of the first pulse of the second scan signal is after the end time of the first pulse of the first scan signal, and the first pulse of the second scan signal at least partially overlaps with the second pulse of the first scan signal. The start time of the first pulse of the fourth scan signal is after the end time of the second pulse of the second scan signal. Within the hold frame, the first, second, and third scan signals maintain a fixed level, and the fourth scan signal includes at least two pulses.

[0063] According to another aspect of the present invention, an array substrate is provided, comprising:

[0064] Base;

[0065] An active layer and a multilayer conductive layer are stacked together to form a pixel circuit. The multilayer conductive layer is located on the side of the active layer away from the substrate. The pixel circuit includes a driving transistor, a first initialization transistor, a second initialization transistor, and a bias transistor.

[0066] The system comprises a third scan line, a fourth scan line, an initialization signal line, and a bias voltage signal line. The third scan line overlaps with the active layer to form a first initialization transistor, and the fourth scan line overlaps with the active layer to form a second initialization transistor and a bias transistor. The first initialization transistor is connected to the initialization signal line and is used to transmit the initialization voltage on the initialization signal line to the gate of the driving transistor. The second initialization transistor is connected between the initialization signal line and the first electrode of the light-emitting element and is used to transmit the initialization voltage to the first electrode of the light-emitting element. The bias transistor is connected between the bias voltage signal line and the first electrode of the driving transistor and is used to transmit the bias voltage on the bias voltage signal line to the first electrode of the driving transistor. Alternatively, the bias transistor is connected between the bias voltage signal line and the second electrode of the driving transistor and is used to transmit the bias voltage on the bias voltage signal line to the second electrode of the driving transistor.

[0067] For the same pixel circuit, the orthographic projection of the third scan line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the fourth scan line connected to the bias transistor on the substrate.

[0068] And / or, corresponding to the same pixel circuit, the orthographic projection of the bias voltage signal line on the substrate is located between the orthographic projection of the third scan line on the substrate and the orthographic projection of the fourth scan line connected to the bias transistor on the substrate.

[0069] And / or, corresponding to the same pixel circuit, the orthographic projection of the initialization signal line adjacent to the bias transistor on the substrate is located on the side of the orthographic projection of the fourth scan line connected to the bias transistor on the substrate that is far from the orthographic projection of the bias voltage signal line on the substrate.

[0070] According to another aspect of the present invention, a display device is provided, the display device comprising an array substrate provided in any embodiment of the present invention.

[0071] The technical solution provided by this invention uses a first electrode plate and a second electrode plate as the upper and lower electrodes of a storage capacitor, and reuses the second electrode plate as an electrode plate of the first capacitor. The second electrode plate overlaps with the third electrode plate to form the first sub-capacitor of the first capacitor. The first capacitor and the storage capacitor are stacked on top of each other, thereby reducing the layout space occupied by the two capacitors and improving the layout space utilization. In addition, by reusing at least a portion of the first trace located on the side of the third electrode plate away from the second electrode plate as an electrode plate of the first capacitor, and the first trace overlapping with the third electrode plate to form the second sub-capacitor of the first capacitor, it is beneficial to improve the stability of the node potential and / or reduce leakage current, thereby improving the display effect.

[0072] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 This is a partial structural diagram of a pixel circuit provided in an embodiment of the present invention;

[0075] Figure 2A This is a top view of an array substrate provided in an embodiment of the present invention;

[0076] Figure 2B This is a top view of another array substrate provided in an embodiment of the present invention;

[0077] Figure 2C This is a top view of another array substrate provided in an embodiment of the present invention;

[0078] Figure 3A This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0079] Figure 3B A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0080] Figure 4 This is a top view of another array substrate provided in an embodiment of the present invention;

[0081] Figure 5 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0082] Figure 6 This is a top view of another array substrate provided in an embodiment of the present invention;

[0083] Figure 7 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0084] Figure 8A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0085] Figure 8B This is a top view of another array substrate provided in an embodiment of the present invention;

[0086] Figure 9A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0087] Figure 9B This is a top view of another array substrate provided in an embodiment of the present invention;

[0088] Figure 9C This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0089] Figure 9D This is a top view of another array substrate provided in an embodiment of the present invention;

[0090] Figure 10A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0091] Figure 10B This is a top view of another array substrate provided in an embodiment of the present invention;

[0092] Figure 10C This is a top view of another array substrate provided in an embodiment of the present invention;

[0093] Figure 11A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0094] Figure 11B This is a top view of another array substrate provided in an embodiment of the present invention;

[0095] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0096] Figure 13A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0097] Figure 13BThis is a top view of another array substrate provided in an embodiment of the present invention;

[0098] Figure 13C This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0099] Figure 13D This is a top view of another array substrate provided in an embodiment of the present invention;

[0100] Figure 14A This is a top view of another array substrate provided in an embodiment of the present invention;

[0101] Figure 14B This is a top view of another array substrate provided in an embodiment of the present invention;

[0102] Figure 14C This is a top view of another array substrate provided in an embodiment of the present invention;

[0103] Figure 15 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0104] Figure 16 This is a top view of another array substrate provided in an embodiment of the present invention;

[0105] Figure 17 This is a top view of another array substrate provided in an embodiment of the present invention;

[0106] Figure 18 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0107] Figure 19 This is a top view of another array substrate provided in an embodiment of the present invention;

[0108] Figure 20 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0109] Figure 21 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0110] Figure 22 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0111] Figure 23A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0112] Figure 23B This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0113] Figure 24 This is a top view of another array substrate provided in an embodiment of the present invention;

[0114] Figure 25 This is a top view of another array substrate provided in an embodiment of the present invention;

[0115] Figure 26 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0116] Figure 27 A cross-sectional structural diagram of another array substrate provided in an embodiment of the present invention;

[0117] Figure 28 This is a top view of another array substrate provided in an embodiment of the present invention;

[0118] Figure 29 A schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0119] Figure 30 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0120] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0121] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Connections may include direct or indirect connections.

[0122] The display panels of related technologies suffer from poor display quality. The inventors' research revealed the following reasons for this problem: The display panel includes pixel circuits, which in turn include multiple thin-film transistors (TFTs). These TFTs include driving transistors and switching transistors. Due to the inherent characteristics of TFTs and other factors, TFTs may not be completely turned off, leading to a leakage path between the gate of the driving transistor and its connected switching transistor. This causes instability in the gate voltage of the driving transistor, resulting in a decrease in display brightness. Related technologies typically reduce gate leakage by adding voltage-stabilizing capacitors at the nodes of the leakage path of the driving transistor. However, this results in two large capacitors in the pixel circuit, increasing the complexity of the pixel circuit layout and affecting the layout space of the original storage capacitor. This reduces the capacity of the storage capacitor, which is detrimental to the stability of the driving transistor's gate voltage, thus affecting the display quality.

[0123] To address the aforementioned problems, embodiments of the present invention provide an array substrate that improves display performance by optimizing the layout of pixel circuits. Figure 1 This is a partial structural diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2A This is a top view of an array substrate provided in an embodiment of the present invention. Figure 2B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 2C This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 3A This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention, specifically... Figure 2C The cross-sectional structure of the array substrate obtained along the section line AA' is referenced. Figure 1 As shown in Figures 1-3, the array substrate provided in this embodiment includes:

[0124] Base 10;

[0125] A pixel circuit is located on a substrate 10. The pixel circuit includes a driving transistor QT, a storage capacitor Cst, at least one first capacitor C1, and at least one preset transistor Tx. The storage capacitor Cst includes a first electrode 21 and a second electrode 22 stacked along the thickness direction Z of the substrate 10. The first electrode 21 of the storage capacitor Cst is connected to the gate of the driving transistor QT. In at least a portion of the first capacitors C1, the second electrode 22 is reused as an electrode of the first capacitor C1. The first capacitor C1 also includes a third electrode 31, which is located on the side of the second electrode 33 away from the first electrode 21. The orthographic projection of the second electrode 22 on the substrate 10 overlaps with the orthographic projection of the third electrode 31 on the substrate 10 to form a portion of the first capacitor C1 (e.g., a first sub-capacitor C01). The preset transistor Tx is connected to the third electrode 31.

[0126] A first trace 42 is located on the side of the third plate 31 of at least a portion of the first capacitors C1 away from the second plate 22. At least a portion of the first trace 42 is multiplexed as a plate of the first capacitor C1. The orthographic projection of the first trace 42 on the substrate 10 overlaps with the orthographic projection of the third plate 31 on the substrate 10 to form a portion of the first capacitor C1 (e.g., a second sub-capacitor C02). The first sub-capacitor C01 and the second sub-capacitor C02 can be connected in series or in parallel. The second plate 22 is electrically connected to the first trace 42, i.e., the first sub-capacitor C01 and the second sub-capacitor C02 are connected in parallel. Alternatively, the second plate 22 and the first trace 42 are connected to a power supply voltage or DC potential, for example, the second plate 22 and the first trace 42 are connected to the same voltage or different voltages. Alternatively, the second plate 22 is insulated from the first trace 42, for example, not electrically connected, for example, connected to different signal or power supply voltages or DC potentials, i.e., the first sub-capacitor C01 and the second sub-capacitor C02 are connected in series. The DC potential may include the initialization voltage Vref, the first power supply voltage VDD, the second power supply voltage VSS, or the bias voltage Vcom.

[0127] Specifically, the substrate 10 can provide protection and support for the array substrate. The substrate 10 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate made of materials such as glass. Multiple insulating layers are disposed on one side of the substrate 10 to isolate the capacitor plates. For example, a first insulating layer 11 is disposed between the first plate 21 and the second plate 22, a second insulating layer 12 is disposed between the second plate 22 and the third plate 31, and a third insulating layer 13 is disposed between the third plate 31 and the first trace 42.

[0128] Multiple pixel circuits are formed on the array substrate to generate driving current to drive the light-emitting element D1 connected to the pixel circuit to emit light. Each pixel circuit includes at least a thin-film transistor (TFT) and a capacitor. The TFT includes at least a driving transistor QT and at least one preset transistor Tx. The capacitor includes a storage capacitor Cst and a first capacitor C1. The storage capacitor Cst stores the gate voltage of the driving transistor QT, and the first capacitor C1 is a voltage regulator used to stabilize the voltage at the node connected to the preset transistor Tx in the pixel circuit (e.g., ...). Figure 1 The voltage of the first node N1 in the preset transistor is reduced to decrease the voltage difference across the preset transistor Tx during a preset time period (e.g., the light emission period or the holding frame), thereby reducing the leakage current of the pixel circuit.

[0129] The first plate 21 and the second plate 22 together form the two plates of the storage capacitor Cst, and the third plate 31 and the second plate 22 together form the two plates of the first capacitor C1.

[0130] In this embodiment, a first trace 42 is also provided. The orthographic projection of the first trace 42 on the substrate 10 at least partially overlaps with the orthographic projection of the third electrode plate 31 on the substrate 10. That is, the first trace 42 and the third electrode plate 31 are located in different film layers, and the overlapping part forms part of the first capacitor C1. Since the first trace 42 is connected to the second electrode plate 22 of the storage capacitor Cst (for example, the first trace 42 and the second electrode plate 22 are connected through a first via K1, which penetrates the third insulating layer 13 and the second insulating layer 12), the capacitor formed by the overlap of the first trace 42 and the third electrode plate 31 can be connected in parallel with the first capacitor C1 as an additional capacitor. Together, they form a larger capacitor, which is equivalent to increasing the first capacitor C1 and can better stabilize the node potential.

[0131] The technical solution provided in this embodiment of the invention uses the first electrode plate 21 and the second electrode plate 22 as the upper and lower electrodes of the storage capacitor Cst, and reuses the second electrode plate 22 as the electrode of the first capacitor C1. The second electrode plate 22 overlaps with the third electrode plate 31 to form a portion of the first capacitor C1 (e.g., the first sub-capacitor C01). Since the second electrode plate 22 of the storage capacitor Cst is reused as the electrode of the first capacitor C1, the orthographic projection of the second electrode plate 22 of the storage capacitor Cst on the substrate 10 overlaps at least with the orthographic projection of the third electrode plate 31 of the first capacitor C1 on the substrate 10. Therefore, the first capacitor C1 and the storage capacitor Cst are stacked on each other, thereby reducing the layout space occupied by the two capacitors and improving the layout space utilization rate. Furthermore, by reusing at least a portion of the first trace 42 located on the side of the third electrode plate 31 away from the second electrode plate 22 as the electrode plate of the first capacitor C1, the first trace 42 and the third electrode plate 31 overlap to form the second sub-capacitor CO2 of the first capacitor C1, which helps to improve the stability of the node potential, reduce leakage current, and thus improve the display effect.

[0132] Optionally, in at least a portion of the first capacitors C1, the overlapping area of ​​the orthographic projection of the first plate 21 on the substrate 10 and the orthographic projection of the second plate 22 on the substrate overlaps with the orthographic projection of the third plate 31 on the substrate 10, which can cause the storage capacitor Cst to overlap with the first capacitor C1 over a large area, further compressing the layout space and improving the layout space utilization.

[0133] Optionally, in at least a portion of the first capacitors C1, the orthographic projection of the second electrode 22 on the substrate 10 overlaps with the orthographic projection of the third electrode 31 on the substrate 10 to form a first sub-capacitor C01 of the first capacitor C1, and the orthographic projection of the first trace 42 on the substrate 10 overlaps with the orthographic projection of the third electrode 31 on the substrate 10 to form a second sub-capacitor C02 of the first capacitor C1.

[0134] Optionally, the first sub-capacitor C01 and the second sub-capacitor C02 are connected in parallel.

[0135] In this embodiment, the first electrode 21 is located between the substrate 10 and the second electrode 22. In other embodiments, the first electrode 21 is located on the side of the second electrode 22 away from the substrate 10.

[0136] For example, the first plate 21 of the storage capacitor Cst can be reused as the gate of the driving transistor QT.

[0137] In this embodiment, the first trace 42 can extend along the first direction Y, which intersects with the second direction X, for example, perpendicularly, and both the first direction Y and the second direction X are perpendicular to the thickness direction Z of the array substrate. The first trace 42 overlaps with the third electrode 31 over a large area to form the first capacitor C1. The orthographic projection of the first trace 42 on the substrate 10 covers the orthographic projection of the third electrode 31 on the substrate 10. According to the capacitance calculation formula C = εS / d, when the dielectric constant ε and the electrode spacing d remain constant, by maximizing the overlap area of ​​the two electrodes, the capacitance value of the first capacitor C1 can be maximized within the limited layout space, thereby improving the retention effect on the node voltage and further improving the layout utilization.

[0138] Optionally, the array substrate also includes data lines, with the first trace 42 extending along the first direction Y. For example, the first trace 42 and the data lines are disposed on the same layer.

[0139] For example, the orthographic projection of the third electrode plate 31 on the substrate 10 is located within the orthographic projection of the first trace 42 on the substrate 10. For example, the width of the first trace 42 along the second direction X is relatively large, which is beneficial to reduce the line voltage drop of the signal on the first trace 42.

[0140] Optionally, in at least a portion of the first capacitors C1, the overlapping area of ​​the orthographic projection of the first electrode 21 on the substrate 10 and the orthographic projection of the second electrode 22 on the substrate 10, the overlapping area of ​​the orthographic projection of the third electrode 31 on the substrate 10, and the overlapping area of ​​the orthographic projection of the first trace 42 on the substrate 10, further compress the layout space and improve the layout space utilization.

[0141] For example, in at least a portion of the first capacitors C1, the area of ​​the overlapping region between the orthographic projection of the second electrode 22 on the substrate 10 and the orthographic projection of the third electrode 31 on the substrate 10 can be smaller than the area of ​​the overlapping region between the orthographic projection of the third electrode 31 on the substrate 10 and the orthographic projection of the first trace 42 on the substrate 10. This increases the size of the third electrode 31, increases the overlapping area between the third electrode 31 and the first trace 42, and increases the capacitance of the second sub-capacitor C02. For example, when the dielectric constants and film thicknesses of the second insulating layer 12 and the third insulating layer 13 are the same, the capacitance of the first capacitor C1 formed by the third electrode 31 and the first trace 42 is greater than the capacitance of the first capacitor formed by the second electrode 22 and the third electrode 31.

[0142] Optionally, in at least a portion of the first capacitors C1, the area of ​​the overlapping region of the orthographic projection of the first electrode 21 on the substrate 10 and the orthographic projection of the second electrode 22 on the substrate 10, and the area of ​​the overlapping region of the orthographic projection of the third electrode 31 on the substrate 10, is smaller than the area of ​​the overlapping region of the orthographic projection of the third electrode 31 on the substrate 10 and the orthographic projection of the first trace 42 on the substrate 10.

[0143] In this embodiment, the capacitance of the first capacitor C1 can be effectively increased by the large-area overlap between the third electrode plate 31 and the first trace 42. At the same time, the first trace 42 also has a wide linewidth, which can effectively reduce the line voltage drop (IR drop) of the first trace 42, thereby improving the uniformity of the signal transmitted by the first trace 42.

[0144] Figure 3B This is a cross-sectional view of another array substrate provided in an embodiment of the present invention. Optionally, the array substrate further includes an overlap portion 32, where the first trace 41 is connected to the overlap portion 32 via a first sub-via K1-1, and the overlap portion 32 is connected to the second electrode plate 22 via a second sub-via K1-2. The first sub-via K1-1 can penetrate the third insulating layer 13, and the second sub-via K1-2 can penetrate the second insulating layer 12.

[0145] Figure 4 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 5 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 4 The cross-sectional structure of the array substrate shown is obtained along the section line BB', for reference. Figure 4 and Figure 5Based on the above embodiments, optionally, the array substrate further includes a second trace 41, which is connected to the gate of the driving transistor QT. At least a portion of the second trace 41 is multiplexed as the electrode of the storage capacitor Cst, and at least a portion of the first trace 42 is multiplexed as the electrode of the storage capacitor Cst. The orthographic projection of the second trace 41 on the substrate 10 overlaps with the orthographic projection of the first trace 42 on the substrate 10 to form a portion of the storage capacitor Cst (e.g., a fourth sub-capacitor CO4). That is, while the first trace 42 overlaps with the second trace 41 to form the fourth sub-capacitor CO4 of the storage capacitor Cst, the first trace 42 also overlaps with the third electrode 31 of the first capacitor C1 to form the second sub-capacitor CO2 of the first capacitor C1.

[0146] Specifically, the first electrode 21 and the second electrode 22 form the upper and lower electrodes of the storage capacitor Cst. The orthographic projections of the first electrode 21 and the second electrode 22 onto the substrate 10 overlap to form the third sub-capacitor CO3 of the storage capacitor Cst. The overlapping portion of the second trace 41 and the first trace 42 forms the fourth sub-capacitor CO4 of the storage capacitor Cst. Since the second trace 41 is connected to the first electrode 21 of the storage capacitor Cst, and the first trace 42 is connected to the second electrode 22 of the storage capacitor Cst, the fourth sub-capacitor CO4 formed by the overlapping portion of the second trace 41 and the first trace 42 can be connected in parallel with the third sub-capacitor CO3 of the storage capacitor Cst as an additional capacitor to increase the capacitance value of the storage capacitor Cst. The orthographic projection of the first trace 42 onto the substrate 10 can cover the orthographic projection of the second trace 42 onto the substrate 10 to maximize the overlap, thereby maximizing the capacitance value of the first additional capacitor.

[0147] Optionally, the orthographic projection of the second trace 41 on the substrate 10 can be spaced apart from the orthographic projection of the third electrode 31 on the substrate 10. For example, the second trace 41 can be disposed in the same layer as the third electrode 31 to reduce the number of film layers. Multiple structures disposed in the same layer can be obtained by patterning the same film layer to simplify the process.

[0148] Optionally, the orthographic projection of the second trace 41 on the substrate 10 and the orthographic projection of the third electrode 31 on the substrate 10 can be arranged along the second direction X. Optionally, for the same pixel circuit, the orthographic projection of the second trace 41 on the substrate 10 is located between the orthographic projection of the data line on the substrate 10 and the orthographic projection of the third electrode 31 on the substrate 10. Alternatively, for the same pixel circuit, the orthographic projection of the third electrode 31 on the substrate 10 is located between the orthographic projection of the data line on the substrate 10 and the orthographic projection of the second trace 41 on the substrate 10.

[0149] The technical solution provided in this embodiment of the invention allows the storage capacitor Cst to include a third sub-capacitor C03 and a fourth sub-capacitor C04. The storage capacitor Cst can be formed by two parts of the capacitor. For example, the first electrode 21 and the second electrode 22 form part of the storage capacitor Cst, which is the third sub-capacitor C03, and the second trace 41 overlaps with the first trace 42 to form the other part of the storage capacitor Cst, which is the fourth sub-capacitor C03. The first capacitor C1 can include a first sub-capacitor C01 and a second sub-capacitor C02. The first capacitor C1 can be formed by two parts of the capacitor. For example, the third electrode 31 and the first trace 42 overlap to form part of the first capacitor C1, which is the second sub-capacitor C02, and the third electrode 31 overlaps with the second electrode 22 of the storage capacitor Cst to form the other part of the first capacitor C1, which is the first sub-capacitor C01. This solution improves layout space utilization by sharing part of the film structure between the storage capacitor Cst and the first capacitor C1. At the same time, by adjusting the space ratio between the second trace 41 and the third electrode plate 31, the capacitance values ​​of the storage capacitor Cst and the first capacitor C1 can be flexibly adjusted. For large capacitance requirements, this solution can greatly increase the capacitance values ​​of the storage capacitor Cst and the first capacitor C1 within a limited layout space, thereby improving the holding effect of the gate voltage or node voltage of the driving transistor Q1, which in turn helps to improve the display effect.

[0150] Continue to refer to Figure 4 and Figure 5 In this embodiment, the orthographic projection of the second trace 41 on the substrate 10 and the orthographic projection of the third electrode plate 31 on the substrate 10 are spaced apart, that is, the orthographic projection of the second trace 41 on the substrate 10 and the orthographic projection of the third electrode plate 31 on the substrate 10 are separated. In other words, the second trace 41 and the third electrode plate 31 are independent of each other. By adjusting the size of the second trace 41 and the third electrode plate 31, the overlap area between the two and the first trace 42 can be adjusted, thereby flexibly adjusting the capacitance value of the first capacitor C1 and the capacitance value of the storage capacitor Cst.

[0151] Optionally, in this embodiment, the first trace 42 can be a power trace, used to transmit power supply voltage. For example, the first trace 42 can be a first power line, used to transmit the first power supply voltage VDD to the pixel circuit, and the second plate 22 of the storage capacitor Cst is connected to the first power supply voltage VDD through the first trace 42.

[0152] In this embodiment, both the second trace 41 and the first trace 42 extend along the first direction Y. For example, the orthographic projection of the first trace 42 on the substrate 10 lies within the orthographic projection of the first trace 42 on the substrate 10. The linewidth of the first trace 42 can be greater than the linewidth of the second trace 41. For example, the linewidth of the first trace 42 along the second direction X can be greater than the linewidth of the second trace 41 along the second direction X. Since the first trace 42 is used to transmit the first power supply voltage VDD, designing the first trace 42 with a larger linewidth enables the first trace 42 to have stronger conductivity, effectively reducing IR drop on the first trace 42. This allows high-brightness display to be supported without increasing the film thickness of the first trace 42, avoiding the color shift problem caused by the film thickness of the first trace 42.

[0153] Optionally, the thickness of the first trace 42 is greater than or equal to 900 angstroms and less than or equal to 1100 angstroms. For example, the thickness of the first trace 42 can be 900 angstroms, 950 angstroms, 1000 angstroms, 1050 angstroms or 1100 angstroms.

[0154] Figure 6 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 7 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention. Figure 7 Specifically Figure 6 The cross-sectional structure of the array substrate shown is obtained along section line II', with reference to... Figure 6 and Figure 7 Based on the above embodiments, optionally, the orthographic projection of the second trace 41 on the substrate 10 overlaps with the orthographic projection of the second electrode 22 of the storage capacitor Cst on the substrate 10. The overlapping portion of the second trace 41 and the second electrode 22 of the storage capacitor Cst forms a portion of the storage capacitor Cst, namely the fifth sub-capacitor C05. Combined with the portion of the storage capacitor Cst formed by the second trace 41 and the first trace 42 (i.e., the fourth sub-capacitor C04), and the portion of the storage capacitor Cst formed by the first electrode 21 and the second electrode 22 (i.e., the third sub-capacitor C03), the storage capacitor Cst is formed by a total of three parts, which can further increase the capacitance value of the storage capacitor Cst.

[0155] Based on the above embodiments, optionally, the pixel circuit further includes at least one auxiliary transistor Ty, the preset terminal of the auxiliary transistor Ty (which may be connected to the first terminal or the second terminal) is connected to the third plate 31, and the preset transistor Tx is connected between the preset terminal of the auxiliary transistor Ty and the driving transistor QT.

[0156] In one optional implementation of this embodiment, both the preset transistor Tx and the auxiliary transistor Ty can be compensation transistors. Figure 8AThis is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 8B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 8A and Figure 8B Based on the above embodiments, optionally, at least one preset transistor Tx includes a first transistor Q1, and at least one auxiliary transistor Ty includes a second transistor Q2. The first terminal of the first transistor Q1 is connected to the gate of the driving transistor QT, and the second terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are connected to the third plate 31. That is, the active portion of the first transistor Q1 and the active portion of the second transistor Q2 are connected to the third plate 31 through a via. The second terminal of the second transistor Q2 is connected to the first terminal of the driving transistor QT. Here, the first transistor Q1 is a first compensation transistor, and the second transistor Q2 is a second compensation transistor. The first transistor Q1 and the second transistor Q2 are respectively connected to the same scan signal (in other embodiments, the first transistor Q1 and the second transistor Q2 may also be connected to different scan signals). The first transistor Q1 and the second transistor Q2 are used to transmit a voltage related to the data voltage Vdata and the threshold voltage of the driving transistor QT to the gate of the driving transistor QT. Here, the first transistor Q1 and the second transistor Q2 can together form a horizontal dual-gate transistor, or they can be two transistors connected in series.

[0157] In another optional implementation provided in this embodiment, both the preset transistor Tx and the auxiliary transistor Ty can be initialization transistors. Figure 9A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 9B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 9A and Figure 9B Based on the above embodiments, optionally, at least one preset transistor Tx includes a third transistor Q3, and at least one auxiliary transistor Ty includes a fourth transistor Q4. The first terminal of the third transistor Q3 is connected to the gate of the driving transistor QT, and the second terminals of the third transistor Q3 and the first terminals of the fourth transistor Q4 are connected to the third plate 31. That is, the active portions of the third transistor Q3 and the fourth transistor Q4 are connected to the third plate 31 through a via. The second terminal of the fourth transistor Q4 is connected to the initialization signal line. The third transistor Q3 and the fourth transistor Q4 are used to transmit the initialization voltage Vref on the initialization signal line to the gate of the driving transistor QT to initialize the gate of the driving transistor QT. Here, the third transistor Q3 and the fourth transistor Q4 can together form a horizontal dual-gate transistor, or they can be two transistors connected in series.

[0158] Figure 9CThis is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 9D This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 9C and Figure 9D At least one preset transistor Tx includes a first transistor Q1 and a third transistor Q3, and at least one auxiliary transistor Ty includes a second transistor Q2 and a fourth transistor Q4. There are two first capacitors C1, namely first capacitor C1-1 and first capacitor C1-2. The active portions of the first transistor Q1 and the second transistor Q2 are connected to the third electrode plate 31-1 via hole K4-1. The active portions of the third transistor Q3 and the fourth transistor Q4 are connected to the third electrode plate 31-2 via hole K4-2. The third electrode plates 31-1 and 31-2 are spaced apart and insulated from each other. For example, the third electrode plates 31-1 and 31-2 are located on opposite sides of the second trace 41.

[0159] In another optional implementation provided in this embodiment, the preset transistor Tx can be a leakage current suppression transistor, and the auxiliary transistor Ty can be a compensation transistor. Figure 10A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 10B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 10B The film layer corresponding to the first trace is not shown in the diagram. Figure 10C This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 10A , Figure 10B and Figure 10C Based on the above embodiments, optionally, at least one preset transistor Tx includes a fifth transistor Q5, at least one auxiliary transistor Ty includes a sixth transistor Q6, and the pixel circuit further includes a seventh transistor Q7. The first terminal of the fifth transistor Q5 is connected to the gate of the driving transistor QT, and the second terminals of the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are connected to the third electrode plate 31. That is, the active portions of the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are connected to the third electrode plate 31 through vias. The second terminal of the sixth transistor Q6 is connected to the first terminal of the driving transistor QT, and the second terminal of the seventh transistor Q7 is connected to the initialization signal line. The fifth transistor Q5 is a leakage current suppression transistor used to suppress gate leakage current of the driving transistor QT; the sixth transistor Q6 is a compensation transistor used to transmit a voltage related to the data voltage and the threshold voltage of the driving transistor QT to the gate of the driving transistor QT; and the seventh transistor Q7 is an initialization transistor.

[0160] In another optional implementation provided in this embodiment, the preset transistor Tx can be a data write transistor. Figure 11A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 11B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 11A and Figure 11B Based on the above embodiments, optionally, at least one preset transistor Tx includes an eighth transistor Q8. The first terminal of the eighth transistor Q8 and the second terminal of the driving transistor QT are connected to the third plate 31. That is, the active portions of the eighth transistor Q8 and the active portions of the driving transistor QT are connected to the third plate 31 through vias. The second terminal of the eighth transistor Q8 is connected to the data line. The eighth transistor Q8 is a data writing transistor used to transmit the data voltage Vdata on the data line 201 to the second terminal of the driving transistor QT. By setting a first capacitor C1, the writing effect of the data voltage can be improved.

[0161] In another optional implementation provided in this embodiment, the preset transistor Tx and the auxiliary transistor Ty can be data writing transistors. Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 12 Based on the above embodiments, optionally, at least one preset transistor Tx includes an eighth transistor Q8, and at least one auxiliary transistor Ty includes a ninth transistor Q9. The first terminal of the eighth transistor Q8 is connected to the second terminal of the driving transistor QT. The second terminals of the eighth transistor Q8 and the first terminals of the ninth transistor Q9 are connected to the third electrode plate 31, and the second terminal of the ninth transistor Q9 is connected to the data line. The specific connection relationship of the third electrode plate 31 on the layout can be found in [reference needed]. Figure 11B .

[0162] In another optional implementation provided in this embodiment, Figure 13A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 13B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 13C This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 13D This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figures 13A-13DBased on the above embodiments, optionally, at least one preset transistor Tx includes a first transistor Q1 and a tenth transistor Q10, and at least one auxiliary transistor Ty includes a second transistor Q2 and an eleventh transistor Q11; the first terminal of the tenth transistor Q10 is connected to the gate of the driving transistor QT, the second terminal of the tenth transistor Q10 is connected to the first terminal of the eleventh transistor Q11, the first terminal of the first transistor Q1 is connected to the second terminal of the eleventh transistor Q11, the first terminal of the second transistor Q2 is connected to the second terminal of the first transistor Q1, and the second terminal of the second transistor Q2 is connected to the first terminal of the driving transistor QT. Wherein, the first transistor Q1 is a first compensation transistor, the second transistor Q2 is a second compensation transistor, the tenth transistor Q10 is a first leakage current suppression transistor (the same as the fifth transistor Q5 in the above embodiments), and the eleventh transistor Q11 is a second leakage current suppression transistor. For example, in the same pixel circuit, the first capacitor C1 may be one or more, or at least two, and the third plate 31 may be one or more, or the first capacitor C1 may be one, and the third plate 31 may be one; or the first capacitor C1 may be at least two, and the third plate 31 may be at least two. The second terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are connected to the third plate 31-3, for example, the second terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are connected to the first capacitor C1-3. And / or, the first terminal of the first transistor Q1 and the second terminal of the eleventh transistor Q11 are connected to the third plate 31-2, for example, the first terminal of the first transistor Q1 and the second terminal of the eleventh transistor Q11 are connected to the first capacitor C1-2. And / or, the first terminal of the eleventh transistor Q11 and the second terminal of the tenth transistor Q10 are connected to the third plate 31-1, for example, the first terminal of the eleventh transistor Q11 and the second terminal of the tenth transistor Q10 are connected to the first capacitor C1-1. For example, a pixel circuit may include one or at least two of a first capacitor C1-1, a first capacitor C1-2, and a first capacitor C1-3.

[0163] Figure 14A This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 14ABased on the above embodiments, optionally, when there are at least two third electrode plates 31 in the same pixel circuit, the at least two third electrode plates 31 are arranged at intervals. The orthographic projection of the third electrode plate 31 of each first capacitor C1 on the substrate 10 overlaps with the orthographic projection of the first trace 42 on the substrate 10, and the orthographic projection of the third electrode plate 31 of each first capacitor C1 on the substrate 10 overlaps with the orthographic projection of the second electrode plate 22 on the substrate 10. For example, the multiple third electrode plates 31 are insulated from each other, for example, not electrically connected. For example, referring to FIG3, the multiple third electrode plates 31 can share the same first trace 42 to form the second sub-capacitors CO2 of the multiple first capacitors C1 respectively. For example, the multiple third electrode plates 31 can share the same second electrode plate to form the first sub-capacitors CO1 of the multiple first capacitors C1 respectively (e.g., Figure 14A (As shown).

[0164] In some embodiments, Figure 14B This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 14C This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 14B and Figure 14C The orthographic projection of the third plate 31 of each first capacitor C1 onto the substrate 10 overlaps with the orthographic projection of the first trace 42 onto the substrate 10. The orthographic projections of the third plates 31 of a portion of the first capacitors C1 (e.g., third plate 31-1) onto the substrate 10 overlap with the orthographic projection of the second plate 22 onto the substrate 10; the orthographic projections of the third plates 31 of a portion of the first capacitors C1 (e.g., third plate 31-5) onto the substrate 10 do not overlap with the orthographic projection of the second plate 22 onto the substrate 10. For example, combined with... Figure 14B At least one third electrode plate 31 (e.g., third electrode plate 31-1) has its orthographic projection on the substrate 10 overlapping with the orthographic projection of the second electrode plate 22 on the substrate 10; at least one third electrode plate 31 (e.g., third electrode plate 31-5) has its orthographic projection on the substrate 10 not overlapping with the orthographic projection of the second electrode plate 22 on the substrate 10 (e.g., ...). Figure 14B and Figure 14C (As shown). At least one first capacitor C1 includes a first sub-capacitor C01 and a second sub-capacitor C02, and at least one first capacitor C1 includes only the second sub-capacitor C02.

[0165] Figure 15 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 16 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 17 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figures 15 to 17Based on the above embodiments, optionally, the array substrate further includes a multilayer conductive layer stacked on one side of the substrate 10. The multilayer conductive layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4 stacked on one side. The first electrode 21 is located in the first conductive layer M1, the second electrode 22 is located in the second conductive layer M2, the third electrode 31 and the second trace 41 are located in the third conductive layer M3, and the first trace 42 is located in the fourth conductive layer M4.

[0166] Figure 18 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 17 The cross-sectional structure of the array substrate shown is obtained along the section line CC', for reference. Figures 15 to 18 The array substrate further includes an active layer 101 and a fourth insulating layer 14. The active layer 101 is located between the first conductive layer M1 and the substrate 10. The fourth insulating layer 14 is located between the active layer 101 and the first conductive layer M1. The first insulating layer 11 is located between the first conductive layer M1 and the second conductive layer M2. The second insulating layer 12 is located between the second conductive layer M2 and the third conductive layer M3. The third insulating layer 13 is located between the third conductive layer M3 and the fourth conductive layer M4. The first conductive layer M1 may include a metal layer. The second conductive layer M2 may include a metal layer or an indium tin oxide layer. The third conductive layer M3 may include a metal layer or an indium tin oxide layer. For example, the third conductive layer M3 may include molybdenum. The fourth conductive layer M4 may include a metal layer or an indium tin oxide layer. For example, the fourth conductive layer M4 includes a titanium layer, an aluminum layer, and a titanium layer sequentially stacked along the thickness direction Z of the substrate. The thickness D4 of the third conductive layer M3 may be less than the thickness D5 of the fourth conductive layer.

[0167] Optionally, the ratio of the capacitance of the storage capacitor Cst to that of the first capacitor C1, Cst / C1, is greater than or equal to 1:4 and less than or equal to 4:1. For example, the ratio Cst / C1 can be 1:4, 1:3, 1:2, 1:1, 2:1, 2:3, 3:2, 4:1, etc. By adjusting the area ratio of the third plate 31 to the second trace 41, the sizes of the storage capacitor Cst and the first capacitor C1 can be flexibly adjusted to meet different performance requirements. (Referring to Figure 3 and...) Figure 5 The storage capacitor Cst may include a third sub-capacitor C03 and a fourth sub-capacitor C04 connected in parallel. The first capacitor C1 may include a first sub-capacitor C01 and a second sub-capacitor C02 connected in parallel.

[0168] Optionally, in this embodiment, the thickness D2 of the second insulating layer 12 is less than the thickness D1 of the first insulating layer 11, and / or the thickness D3 of the third insulating layer 13 is less than the thickness D2 of the second insulating layer 12.

[0169] Specifically, the first insulating layer 11 is the capacitor dielectric layer between the first electrode 21 and the second electrode 22, the second insulating layer 12 is the capacitor dielectric layer between the second electrode 22 and the third electrode 31, and the third insulating layer 13 is the capacitor dielectric layer between the third electrode 31 and the first trace 42. By reducing the thickness of the second insulating layer 12 and the third insulating layer 13, a larger first capacitor C1 can be designed.

[0170] For example, the second insulating layer 12 is an inorganic insulating layer, the third insulating layer 13 is an inorganic insulating layer, and the first insulating layer 11 is an inorganic insulating layer.

[0171] For example, the thickness D2 of the second insulating layer 12 is greater than or equal to 2000 angstroms and less than or equal to 2500 angstroms; the thickness D3 of the third insulating layer 13 is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms. For example, the thickness D2 of the second insulating layer 12 is 2000 angstroms, 2100 angstroms, 2200 angstroms, 2300 angstroms, 2400 angstroms or 2500 angstroms, and the thickness D3 of the third insulating layer 13 is 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms or 1500 angstroms. The sum of the thicknesses of the second insulating layer 12 and the third insulating layer 13 is relatively small, so the etching depth is smaller when etching the second insulating layer 12 and the third insulating layer 13, which is beneficial for the etching of the hole.

[0172] Furthermore, since the third insulating layer 13 is relatively thin, in order to avoid adverse effects on the third electrode plate 31 during the etching process of the first trace 42, the technical solution provided in this embodiment can place the third electrode plate 31 within the orthographic projection of the first trace 42 on the substrate 10, thereby reducing the situation where the third electrode plate 31 is not covered by the first trace 42.

[0173] Combination Figure 1 , Figure 3A and Figure 17 As shown, in this embodiment, at the intersection of the first trace 42 and the second electrode plate 22, the first trace 42 is connected to the second electrode plate 22 via the first via K1.

[0174] refer to Figure 5 , Figure 16 and Figure 17 The gate of the driving transistor QT is connected to the second trace 41 via the second via K2, and the active layer 101 is connected to the second trace 41 via the third via K3. The active layer 101 includes the active part of the preset transistor Tx, and the active part of the preset transistor Tx is connected to the third plate 31 via the fourth via K4.

[0175] Specifically, in combination Figure 15The preset transistor Tx includes a first transistor Q1 and a tenth transistor Q10. The gate of the driving transistor QT (here, the first electrode 21 is reused as the gate of the driving transistor QT) is connected to the second trace 41 (e.g., the first end of the second trace 41) via the second via K2. The first electrode of the eleventh transistor Q11 is connected to the second trace 41 (e.g., the second end of the second trace 41) via the third via K3. That is, the active part of the eleventh transistor Q11 and the gate of the driving transistor QT are bridged through the second trace 41, and the second trace 41 can also be reused as the electrode of the storage capacitor Cst.

[0176] The second terminal of the tenth transistor Q10 (which may be a preset transistor Tx) is connected to the third plate 31 via a fourth via. The first terminal of the eleventh transistor Q11 (which may be an auxiliary transistor Ty) is connected to the third plate 31 via a fourth via. The first terminal of the eleventh transistor Q11 may be one of the source and drain regions of its active portion, and the second terminal of the eleventh transistor Q11 may be the other of the source and drain regions of its active portion. Here, the first via K1 penetrates the third insulating layer 13 and the second insulating layer 12, the second via K2 penetrates the second insulating layer 12 and the first insulating layer 11, the third via K3 penetrates the second insulating layer 12, the first insulating layer 11, and the fourth insulating layer 14, and the fourth via K4 penetrates the second insulating layer 12, the first insulating layer 11, and the fourth insulating layer 14.

[0177] Figure 17 The third electrode plate 31 and the second trace 41 are disposed on the same layer; in other embodiments, they can also be disposed on different layers. For example, Figure 19 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 20 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 19 The cross-sectional structure of the array substrate shown is obtained along the section line EE', with reference to... Figure 19 and Figure 20 The second trace 41 is connected to the gate of the driving transistor QT, and the second trace 41 is disposed on a different layer from the third electrode plate 31. For example, the first trace 42 and the second trace 41 are disposed on the same layer. The first trace 42 and the second trace 41 are located in the fourth conductive layer M4.

[0178] Combination Figure 3A At the intersection of the first trace 42 and the second electrode plate 22, the first trace 42 is connected to the second electrode plate 22 through the first via K1.

[0179] Combination Figure 5 , Figure 19 and Figure 20The gate of the driving transistor QT is connected to the second trace 41 via the second via K2, and the active layer 101 is connected to the second trace 41 via the third via K3. The active layer 101 includes the active portion of the preset transistor Tx, and the active portion of the preset transistor (e.g., the tenth transistor Q10) is connected to the third electrode plate 31 via the fourth via K4. The first via K1 penetrates the third insulating layer 13 and the second insulating layer 12, the second via K2 penetrates the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11, the third via K3 penetrates the third insulating layer 13, the second insulating layer 12, the first insulating layer 11 and the fourth insulating layer 14, and the fourth via K4 penetrates the second insulating layer 12, the first insulating layer 11 and the fourth insulating layer 14.

[0180] exist Figure 19 In the array substrate shown, the first trace 42 and the second trace 41 are both located in the fourth conductive layer M4, and the orthographic projections of the first trace 42 and the second trace 41 on the substrate 10 do not overlap.

[0181] Continue to refer to Figure 17 or Figure 19 The array substrate also includes a data line 201, a second trace 41 extending along the first direction Y, and a first trace 42 disposed on the same layer as the data line 201. The data line 201 may be located in the fourth conductive layer M4. The data line 201 is used to transmit data voltage to the driving transistor QT via a data writing transistor (e.g., the eighth transistor Q8).

[0182] Figure 21 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 17 The cross-sectional structure of the array substrate shown is obtained along the cutting line DD', for reference. Figure 17 and Figure 21 The array substrate also includes a transition section 301. The film layer containing the transition section 301 is located between the film layer containing the data line 201 and the active layer 101. The data line 201 is connected to the transition section 301 via a sixth via K6, and the active layer 101 is connected to the transition section 301 via a seventh via K7. In other words, the data line 201 and the active layer of the eighth transistor Q8 are connected via a via 301, which avoids deep hole etching and helps to ensure the integrity of each insulating layer.

[0183] The adapter 301 can be disposed on the same layer as the third electrode plate 31, and / or, the adapter 301 can be disposed on the same layer as the second trace 41. For example, the adapter 301 is located in the third conductive layer M3. Specifically, when the third electrode plate 31 and the second trace 41 are disposed on the same layer, the adapter 301 can be disposed on the same layer as both the third electrode plate 31 and the second trace 41. When the third electrode plate 31 and the second trace 41 are disposed on different layers, the adapter 301 can be disposed on either the same layer as the third electrode plate 31 or the same layer as the second trace 41.

[0184] For example, the adapter 301 is located in the third conductive layer M3. Taking the adapter 301 and the third electrode plate 31 as being in the same layer as an example, the sixth via K6 penetrates the third insulating layer 13, and the seventh via K7 penetrates the second insulating layer 12, the first insulating layer 11 and the fourth insulating layer 14.

[0185] Optionally, the orthographic projection of the adapter 301 on the substrate 10 at least partially overlaps with the orthographic projection of the data line 201 on the substrate 10, and the orthographic projection of the adapter 301 on the substrate 10 at least partially overlaps with the orthographic projection of the active layer 101 on the substrate 10. Here, the overlapping area of ​​the orthographic projections of the data line 201 and the active layer 101 on the substrate 10, and the overlapping area of ​​the orthographic projection of the adapter 301 on the substrate 10, facilitates the formation of vias for the sixth via K6 and the seventh via K7, which helps to reduce the space occupied by the sixth via K6 and the seventh via K7.

[0186] Figure 22 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention, and... Figure 21 The array substrate shown is different in that... Figure 22 In the structure shown, data line 201 is connected to active layer 101 through fifth via K5, which penetrates third insulating layer 13, second insulating layer 12, first insulating layer 11, and fourth insulating layer 14. That is, data line 201 is directly connected to the active layer of the eighth transistor Q8 using a single via, which helps save via space and allows the space to be allocated to the capacitor plates to increase capacitance.

[0187] Figure 21 In the process, the data line 201 is connected to the active layer 101 through the sixth via K6, the adapter 301 and the seventh via K7. The seventh via K7 and the fourth via K4 are fabricated simultaneously. The etching depth required to fabricate the sixth via K6 is relatively small, which can save fabrication time and improve process efficiency. Figure 22 In the process, data line 201 is connected to active layer 101 through the fifth via K5. The fourth via K4 and the fifth via K5 are fabricated in steps. The etching depth required to fabricate the fifth via K5 is larger, and the etching time is longer than that required to fabricate the sixth via K6. Figure 21 The adapter 301 occupies space, which will reduce the size of the third electrode plate 31, etc., therefore Figure 22 This allows for an increase in the size of the third plate 31 and the size of the first capacitor C1. (Continue to refer to...) Figure 17The array substrate also includes a first scan line 111 extending along the second direction X, which overlaps with the active layer 101 to form a tenth transistor Q10. One end of a second trace 41 is connected to the active layer 101 of the tenth transistor Q10, and the other end of the second trace 41 is connected to the first plate 21 of the storage capacitor Cst (i.e., the gate of the driving transistor QT). When the tenth transistor Q10 is turned on, the third plate 31 of the first capacitor C1 and the first plate 21 of the storage capacitor Cst have the same potential. When the tenth transistor Q10 changes from being turned on to being turned off, the parasitic capacitance between the gate of the tenth transistor Q10 and the gate of the driving transistor QT couples, coupling the gate voltage of the driving transistor QT so that the gate potential of the driving transistor QT is close to the potential of the first electrode of the tenth transistor Q10, thereby reducing the voltage difference between the first and second electrodes of the tenth transistor Q10, which helps to reduce the leakage current of the tenth transistor Q10 and thus maintain the stability of the gate potential of the driving transistor QT. In other words, by setting the first capacitor C1 to store the node voltage, the voltage difference between the driving transistor QT and the node, as well as the voltage difference across the tenth transistor Q10, can be reduced, thereby reducing the leakage current of the tenth transistor Q10 and thus reducing the leakage phenomenon of the driving transistor QT, which is beneficial to improving the display effect.

[0188] The first scan line 11 overlaps with the active layer 101 to form the eleventh transistor Q11 and the first transistor Q1. The second trace 41 can be directly drilled to the active layer 101 of the tenth transistor Q10 and the gate of the driving transistor QT below, so as to connect with the tenth transistor Q10 and the driving transistor QT.

[0189] The array substrate also includes a second scan line 112, which overlaps with the active layer 101 to form a second transistor Q2. The second trace 41 is connected to the first terminal of the driving transistor QT via the tenth transistor Q10, the eleventh transistor Q11, the first transistor Q1, and the second transistor Q2 in sequence.

[0190] Continue to refer to Figure 16 and Figure 17 The pixel circuit also includes a data writing transistor (eighth transistor Q8). The second scan line 112 overlaps with the active layer 101 to form the data writing transistor, which is connected between the data line 201 and the second terminal of the driving transistor QT.

[0191] Optionally, both the first scan line 111 and the second scan line 112 are located in the first conductive layer M1, for example, corresponding to the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X). The orthogonal projection of the second scan line 112 on the substrate 10 is located between the orthogonal projection of the gate of the driving transistor QT on the substrate 10 and the orthogonal projection of the first scan line 111 on the substrate 10. The second scan line 112 may extend along the second direction X.

[0192] Figure 23A This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 23B This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 24 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 25 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 24 and Figure 25 Specifically Figure 23A For the corresponding map structure, please refer to Figures 23A to 25 Optionally, the pixel circuit PX further includes a first initialization transistor (which may be the seventh transistor Q7) and a second initialization transistor Q12. The array substrate further includes a third scan line 113, a fourth scan line 114, and an initialization signal line 116. The third scan line 113 overlaps with the active layer 101 to form the first initialization transistor, and the fourth scan line 114 overlaps with the active layer 101 to form the second initialization transistor Q12. The first initialization transistor Q7 is connected to the initialization signal line 116 and is used to transmit the initialization voltage Vref on the initialization signal line 116 to the gate of the driving transistor QT. When the first initialization transistor, the tenth transistor Q10, and the eleventh transistor Q11 are turned on, they transmit the initialization voltage Vref on the initialization signal line 116 to the gate of the driving transistor QT.

[0193] The second initialization transistor Q12 is connected between the initialization signal line 116 and the first terminal of the light-emitting element D1. The second initialization transistor Q12 is used to transmit the initialization voltage Vref to the first terminal of the light-emitting element D1. For example, the third scan line 113, the fourth scan line 114 and the initialization signal line 116 extend along the second direction X and are arranged along the first direction Y.

[0194] For example, the first initialization transistor Q7 and the second initialization transistor Q12 are connected to the same initialization signal line, that is, they are connected to the same voltage; or, the first initialization transistor Q7 and the second initialization transistor Q12 are connected to different initialization signal lines, that is, they are connected to different voltages.

[0195] Optionally, the third scan line 113 and the fourth scan line 114 are disposed on the same layer, and the third scan line 113 and the fourth scan line 114 may be located in the first conductive layer M1. The third scan line 113 and the initialization signal line 116 are disposed on different layers. The fourth scan line 114 and the initialization signal line 116 are disposed on different layers. For example, the third scan line 113 and the fourth scan line 114 are disposed on the same layer as the gate or the first electrode 21 of the driving transistor QT, and the initialization signal line 116 is disposed on the same layer as the second electrode 22. The initialization signal line 116 may be located in the second conductive layer M2.

[0196] Figure 26 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 25 The cross-sectional structure of the array substrate shown is obtained along the section line GG', with reference to... Figure 25 and Figure 26 The array substrate also includes a connection line 510, which connects the initialization signal line 116 and the second initialization transistor Q12. The orthographic projection of the connection line 510 on the substrate 10 overlaps with the orthographic projection of the fourth scan line 114 on the substrate 10. The connection line 510 is located in the third conductive layer M3. The initialization signal line 116, located in the second conductive layer M2, is connected to one end of the connection line 510 via an eighth via K8. The first electrode of the second initialization transistor Q12 is connected to the other end of the connection line 510 via a ninth via K9. The eighth via K8 penetrates the second insulating layer 12, and the ninth via K9 penetrates the second insulating layer 12, the first insulating layer 11, and the fourth insulating layer 14. The connection line 510 can be disposed on the same layer as the third electrode plate 31.

[0197] Optionally, the first trace 42 can be widened so that the orthographic projection of the connecting line 510 on the substrate 10 overlaps with the orthographic projection of the first trace 42 on the substrate 10, which helps to reduce the line impedance voltage drop of the first trace 42. The orthographic projection of the connecting line 510 on the substrate 10 is located within the orthographic projection of the first trace 42 on the substrate 10.

[0198] Optionally, for the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the third scan line 113 on the substrate 10 is located on the side where the orthogonal projection of the first scan line 111 on the substrate 10 is away from the orthogonal projection of the gate of the driving transistor QT on the substrate 10. Each row of pixel circuits includes a plurality of pixel circuits arranged along the second direction X.

[0199] The length of each first trace 42 along the first direction Y can be greater than the length of a pixel circuit along the first direction Y. The orthographic projection of each first trace 42 on the substrate 10 overlaps with the orthographic projection of multiple pixel circuits arranged along the first direction Y on the substrate 10. Each column of pixel circuits can correspond to one first trace 42. Each column of pixel circuits includes multiple pixel circuits arranged along the first direction Y. Multiple first traces 42 extend along the first direction Y and are arranged along a second direction.

[0200] Figure 27 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 25 The cross-sectional structure of the array substrate shown is obtained along the section line HH', for reference. Figure 25 and Figure 27 The array substrate further includes a light-emitting control signal line 115, which may be located in the first conductive layer M1. The light-emitting control signal line 115 overlaps with the active layer 101 to form a first light-emitting control transistor Q14 and a second light-emitting control transistor Q15. The second terminal of the driving transistor QT is connected to the first trace 42 via the first light-emitting control transistor Q14, and the first trace 42 is connected to the first power supply voltage VDD. The first terminal of the first light-emitting control transistor Q14 is connected to the first trace, and the second terminal of the first light-emitting control transistor Q14 is connected to the second terminal of the driving transistor QT. The light-emitting control signal line 115 is disposed on the same layer as the gate or first electrode 21 of the driving transistor QT. The light-emitting control signal line 115 can transmit light-emitting control signals. The light-emitting control signal line 115 may extend along the second direction X.

[0201] Optionally, the array substrate further includes a connection portion 520, through which the first trace 42 is connected to the first electrode of the first light-emitting control transistor Q14; the connection portion 520 is disposed on the same layer as the third electrode plate 31. The first trace 42 is connected to the active layer 101 using a double-hole configuration to ensure that the first trace 42 located on the fourth conductive layer M4 is used only as a power line, thereby ensuring that the first trace 42 can have a very wide linewidth. Specifically, the third conductive layer M3 is used as a transition layer. The first trace 42 located on the fourth conductive layer M4 is first drilled to the third conductive layer M3 and connected to the connection portion 520 in the third conductive layer M3. Then, it is drilled from the third conductive layer M3 to the active layer 101, connecting the connection portion 520 to the active layer 101, thereby realizing the connection between the first trace 42 and the active layer 101. The first trace 42 is connected to the connection portion 520 via the tenth via K10, and the connection portion 520 is connected to the first electrode of the first light-emitting control transistor Q14 via the eleventh via K11. The tenth via K10 can penetrate the third insulating layer. The eleventh via K11 can penetrate the second, first, and fourth insulating layers.

[0202] Optionally, the light emission control signal line 115 is disposed on the same layer as the gate or first plate 21 of the driving transistor QT.

[0203] The first terminal of the driving transistor QT is also connected to the light-emitting element D1 via the second light-emitting control transistor Q15, which is connected between the first terminal of the driving transistor QT and the first terminal of the light-emitting element. Here, vias can still be used to connect the active layer 101 of the second light-emitting control transistor Q15 to the light-emitting element D1. The second terminal (e.g., cathode) of the light-emitting element D1 is connected to the second power supply line (which can transmit the second power supply voltage VSS).

[0204] Optionally, for the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the light emission control signal line 115 on the substrate 10 is located on the side where the orthogonal projection of the gate of the driving transistor Q1 on the substrate 10 is far away from the orthogonal projection of the second scan line 112 on the substrate 10.

[0205] Optionally, continue to refer to Figure 24 and Figure 25 The array substrate also includes a bias voltage signal line 117. A fourth scan line 114 overlaps with the active layer 101 to form a bias transistor Q13. The bias transistor Q13 is connected between the bias voltage signal line 117 and the first or second terminal of the driving transistor QT, and is used to transmit the bias voltage Vcom on the bias voltage signal line 117 to the first or second terminal of the driving transistor QT. For example, as... Figure 23B As shown, bias transistor Q13 is connected between bias voltage signal line 117 and the first terminal of driving transistor QT, used to transmit the bias voltage Vcom on bias voltage signal line 117 to the first terminal of driving transistor QT. For example, as... Figure 23A As shown, bias transistor Q13 is connected between bias voltage signal line 117 and the second terminal of driving transistor QT, and is used to transmit the bias voltage Vcom on bias voltage signal line 117 to the second terminal of driving transistor QT. Bias voltage signal line 117 can extend along the second direction X.

[0206] For example, in two adjacent rows of pixel circuits, the bias transistor Q13 in one row and the second initialization transistor Q12 in the other row overlap with the active layer 101 via the same fourth scan line 114. Alternatively, in two adjacent rows of pixel circuits, the bias transistor Q13 in the current row and the second initialization transistor Q12 in the previous row overlap with the active layer 101 via the same fourth scan line 114. In this case, the second initialization transistor Q12 and the bias transistor Q13, formed by the overlap of the same fourth scan line 114 with the active layer 101, belong to pixel circuits in different rows. The bias transistor Q13 in the current row can share the same bias voltage signal line 117 with the second initialization transistor Q12 in the previous row.

[0207] The bias voltage signal line 117 can be located on the second conductive layer M2. Here, the bias voltage signal line 117 and the bias transistor Q13 can also be connected by a connector to optimize the layout and reduce signal interference.

[0208] For example, for the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the fourth scan line 114 connected to the bias transistor Q13 on the substrate 10 is located on the side of the orthogonal projection of the third scan line 113 on the substrate 10 that is far away from the orthogonal projection of the gate of the driving transistor QT on the substrate 10, so as to optimize the layout.

[0209] For example, the bias voltage signal line 117 is disposed on the same layer as the second electrode or the initialization signal line; for example, the bias voltage signal line 117 is located in the second conductive layer.

[0210] For example, for the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the bias voltage signal line 117 on the substrate 10 is located between the orthogonal projection of the third scan line 113 on the substrate 10 and the orthogonal projection of the fourth scan line 114 connected to the bias transistor Q13 on the substrate 10.

[0211] Figure 28 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 28 Based on the above embodiments, optionally, the orthographic projection of the third electrode plate 31 on the substrate 10 overlaps with the orthographic projection of the first scan line 11 on the substrate 10.

[0212] Furthermore, the orthographic projection of the third electrode plate 31 on the substrate 10 overlaps with the orthographic projection of the third scan line 113 on the substrate 10.

[0213] The technical solution provided in this embodiment, by setting the orthogonal projection of the third electrode plate 31 on the substrate 10 to overlap with the orthogonal projection of the first scan line 11 on the substrate 10, or simultaneously overlapping with the orthogonal projections of the first scan line 11 and the third scan line 113 on the substrate 10, can increase the overlap area between the third electrode plate 31 and the first trace 42 when the third electrode plate 31 and the second trace 41 are set on the same layer, thereby increasing the first capacitor C1 and improving the layout space utilization.

[0214] Optionally, the driving transistor QT, the first initialization transistor (seventh transistor Q7), the second initialization transistor Q12, and the bias transistor Q13 can be P-type transistors. Optionally, the driving transistor QT, the first initialization transistor (seventh transistor Q7), the second initialization transistor Q12, and the bias transistor Q13 can be polysilicon transistors.

[0215] For example, for the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the initialization signal line 116 adjacent to the bias transistor Q13 on the substrate 10 is located on the side where the orthogonal projection of the fourth scan line 114 connected to the bias transistor Q13 on the substrate 10 is far away from the orthogonal projection of the bias voltage signal line 117 on the substrate 10.

[0216] For example, corresponding to the same pixel circuit or the same row of pixel circuits (the row direction is parallel to the second direction X), the orthogonal projection of the initialization signal line 116 adjacent to the second initialization transistor Q12 on the substrate 10 is located on the side where the orthogonal projection of the fourth scan line 114 connected to the second initialization transistor Q12 on the substrate 10 is far away from the orthogonal projection of the light emission control signal line 115 on the substrate 10.

[0217] In some embodiments, within the same pixel circuit, there may be three or more first capacitors and three or more third plates. For example... Figure 23B The pixel circuit in it can also be combined with Figure 9C , Figure 11A , Figure 12 One or more of these components can be combined to create more first capacitors and third plates, which will not be elaborated here.

[0218] Each trace or signal line may extend in one or more combinations of straight lines, curves, broken lines, or irregular shapes (such as tree branches) along its own extension direction.

[0219] Figure 29 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, which can be applied to the pixel circuit shown in Figure 23. (Refer to...) Figure 23A and Figure 29Within a display cycle, there are write frames and hold frames. In the write frame, the first scan signal S1 transmitted on the first scan line 111, the second scan signal S2 transmitted on the second scan line 112, the third scan signal S3 transmitted on the third scan line 113, and the fourth scan signal S4 transmitted on the fourth scan line 114 each include at least two pulses (i.e., turn-on pulses). The start time of the first pulse of the first scan signal S1 is after the end time of the first pulse of the third scan signal S3, and the first pulse of the first scan signal S1 at least partially overlaps with the second pulse of the third scan signal S2. The start time of the first pulse of the second scan signal S2 is after the end time of the first pulse of the first scan signal S1, and the first pulse of the second scan signal S2 at least partially overlaps with the second pulse of the first scan signal S1. The start time of the first pulse of the fourth scan signal S4 is after the end time of the second pulse of the second scan signal S2. For example, the start time of the first pulse of the fourth scan signal S4 is after the end time of the last pulse of the second scan signal S2.

[0220] Within the hold frame, the first scan signal S1, the second scan signal S2, and the third scan signal S3 remain at a fixed level (e.g., off level), and / or the fourth scan signal S4 includes at least two pulses.

[0221] Taking a P-type transistor as an example, the write frame includes a first initialization stage T1, a data writing and compensation stage T2, a second initialization stage T3, and a light emission stage T4.

[0222] In the first initialization phase T1, the first scan signal S1 is at an on level (e.g., low), the second scan signal S2 is at an off level (e.g., high), the third scan signal S3 is at an on level (e.g., low), the fourth scan signal S4 is at an off level (e.g., high), and the light emission control signal EM is at an off level (e.g., high). Therefore, the first leakage current suppression transistor (tenth transistor Q10), the second leakage current suppression transistor (eleventh transistor Q11), the first compensation transistor (first transistor Q1), and the first initialization transistor (seventh transistor Q7) are turned on, while the second compensation transistor (second transistor Q2), the data writing transistor (eighth transistor Q8), the second initialization transistor Q12, the bias transistor Q13, the first light emission control transistor Q14, and the second light emission control transistor Q15 are turned off. The initialization voltage Vref on the initialization signal line is transmitted to the gate of the driving transistor QT via the seventh transistor Q7, the eleventh transistor Q11, and the tenth transistor Q10, initializing the gate of the driving transistor QT and simultaneously turning on the driving transistor QT.

[0223] During the data writing and compensation phase T2, the first scan signal S1 is at an on level (e.g., low), the second scan signal S2 is at an on level (e.g., low), the third scan signal S3 is at an off level (e.g., high), the fourth scan signal S4 is at an off level (e.g., high), and the light emission control signal EM is at an off level (e.g., high). Therefore, the tenth transistor Q10, the eleventh transistor Q11, the first transistor Q1, the second transistor Q2, and the eighth transistor Q8 are on, while the seventh transistor Q7, the second initialization transistor Q12, the bias transistor Q13, the first light emission control transistor Q14, and the second light emission control transistor Q15 are off. The data voltage Vdata on the data line is written to the gate of the driving transistor QT via the eighth transistor Q8, the driving transistor QT, the second transistor Q2, the first transistor Q1, the eleventh transistor Q11, and the tenth transistor Q10. When the gate voltage of the driving transistor QT reaches Vdata + Vth1, the driving transistor QT is turned off, thus achieving data writing and threshold voltage compensation. The gate voltages are stored on the storage capacitor Cst. Where Vth1 is the threshold voltage of the driving transistor QT.

[0224] When the first scan signal S1 transitions from a low level to a high level, the tenth transistor Q10 changes from being on to being off. Under the coupling effect of the parasitic capacitance of the gate of the driving transistor QT, the gate voltage of the driving transistor QT is pulled up to be close to the voltage stored on the first capacitor C1. Therefore, the voltage difference between the first and second terminals of the tenth transistor Q10 is small, which makes the leakage current of the tenth transistor Q3 small, thereby maintaining the stability of the gate voltage of the driving transistor QT.

[0225] In the second initialization phase T3, the first scan signal S1 is at a shutdown level (e.g., high level), the second scan signal S2 is at a shutdown level (e.g., high level), the third scan signal S3 is at a shutdown level (e.g., high level), the fourth scan signal S4 is at a conduction level (e.g., low level), and the light emission control signal EM is at a shutdown level (e.g., high level). Therefore, the second initialization transistor Q12 is turned on, and the tenth transistor Q10, the eleventh transistor Q11, the first transistor Q1, the seventh transistor Q7, the second transistor Q2, the eighth transistor Q6, the first light emission control transistor Q14, and the second light emission control transistor Q15 are turned off. The initialization voltage Vref is transmitted to the first electrode (anode) of the light-emitting element D1 via the second initialization transistor Q12 to initialize the first electrode of the light-emitting element D1, thereby reducing the impact of residual charge on the display effect.

[0226] The operation of this pixel circuit also includes a biasing stage, during which bias transistor Q13 is turned on. Bias transistor Q13 transmits the bias voltage Vcom to the second terminal of the driving transistor QT, biasing QT to reduce the difference in bias state between the driving transistor QT in the write frame and the hold frame. This ensures that the first terminal of the driving transistor QT has the same voltage value under the same grayscale conditions, guaranteeing that the first and second terminals of the driving transistor QT maintain the same potential in both the write and hold frames. The bias voltage Vcom can be set according to the actual screen adjustment effect.

[0227] In this embodiment, in two adjacent rows of pixel circuits, the biasing phase of the current row of pixel circuits is performed simultaneously with the second initialization phase T3 of the previous row of pixel circuits.

[0228] Of course, in other embodiments, the bias transistor Q13 can also transmit the bias voltage Vcom to the first terminal of the driving transistor QT, which can also change the bias state of the driving transistor QT and has the same beneficial effect.

[0229] During the light-emitting phase T4, the first scan signal S1 is at a shutdown level (e.g., high), the second scan signal S2 is at a shutdown level (e.g., high), the third scan signal S3 is at a shutdown level (e.g., high), the fourth scan signal S4 is at a shutdown level (e.g., high), and the light-emitting control signal EM is at a conduction level (e.g., low). Therefore, the first light-emitting control transistor Q14 and the second light-emitting control transistor Q15 are turned on, while the tenth transistor Q10, the eleventh transistor Q11, the first transistor Q1, the seventh transistor Q7, the second transistor Q2, the eighth transistor Q8, the second initialization transistor Q12, and the bias transistor Q13 are turned off. The driving transistor QT generates a driving current, driving the light-emitting element D1 to emit light. Because the gate voltage of the driving transistor QT can remain stable for a long time, the uniformity of the driving current can be guaranteed, improving the ghosting problem of the displayed image.

[0230] The process of maintaining the frame is as follows:

[0231] Phase T5 is the initialization and voltage biasing phase. The specific working process is the same as the second initialization phase T3, which can be referred to in the above description.

[0232] Stage T6 is the light-emitting stage, and its specific working process is the same as that of stage T4. Please refer to the above description.

[0233] The technical solution provided in this embodiment, by setting a holding frame and including T5 and T6 stages within the holding frame, effectively increases the number of times the light-emitting element D1 emits light in one display cycle. This converts low-frequency brightness components, which are easily perceived by the human eye, into high-frequency brightness components that are not easily perceived, thereby improving the flickering phenomenon of the display screen. Furthermore, the storage capacitor Cst in the pixel circuit can have a large capacitance value, which is beneficial to improving the stability of the gate potential of the driving transistor QT, thereby further improving the flickering phenomenon of the display screen. And through the corresponding via design, the first trace 42 can be guaranteed to have a wide linewidth, so as to improve the display effect while meeting the high brightness display requirements.

[0234] Optionally, the present invention also provides an array substrate, referring to Figures 23 to 24. Figure 25 The array substrate includes:

[0235] Base;

[0236] An active layer 101 and a multilayer conductive layer stacked together form a pixel circuit. The multilayer conductive layer is located on the side of the active layer 101 away from the substrate. The pixel circuit includes a driving transistor QT, a first initialization transistor (seventh transistor Q7), a second initialization transistor Q12, and a bias transistor Q13.

[0237] The system comprises a third scan line 113, a fourth scan line 114, an initialization signal line 116, and a bias voltage signal line 117. The third scan line 113 overlaps with the active layer 101 to form a first initialization transistor. The fourth scan line 114 overlaps with the active layer 101 to form a second initialization transistor Q12 and a bias transistor Q13. The first initialization transistor is connected to the initialization signal line 116 and is used to transmit the initialization voltage Vref on the initialization signal line 116 to the gate of the driving transistor QT. The second initialization transistor Q12 is connected between the initialization signal line 116 and the first terminal of the light-emitting element D1 and is used to transmit the initialization voltage Vref on the initialization signal line 116 to the first terminal of the light-emitting element D1. The bias transistor Q13 is connected between the bias voltage signal line 117 and the first or second terminal of the driving transistor QT and is used to transmit the bias voltage Vcom on the bias voltage signal line 117 to the first or second terminal of the driving transistor QT. Bias transistor Q13 is connected between bias voltage signal line 117 and the first terminal of driving transistor QT. Bias transistor Q13 is used to transmit the bias voltage Vcom on bias voltage signal line 117 to the first terminal of driving transistor QT. Alternatively, bias transistor Q13 is connected between bias voltage signal line 117 and the second terminal of driving transistor QT. Bias transistor Q13 is used to transmit the bias voltage Vcom on bias voltage signal line 117 to the second terminal of driving transistor QT.

[0238] For the same pixel circuit, the orthographic projection of the third scan line 113 on the substrate is located between the orthographic projection of the gate of the driving transistor QT on the substrate and the orthographic projection of the fourth scan line 114 connected to the bias transistor on the substrate.

[0239] For the same pixel circuit, the orthographic projection of the bias voltage signal line 117 on the substrate is located between the orthographic projection of the third scan line 113 on the substrate and the orthographic projection of the fourth scan line 114 connected to the bias transistor on the substrate.

[0240] For the same pixel circuit, the orthogonal projection of the initialization signal line 116 on the substrate is located on the side where the orthogonal projection of the fourth scan line 114 connected to the bias transistor on the substrate is far away from the orthogonal projection of the bias voltage signal line 117 on the substrate.

[0241] The specific structure of the array substrate provided in the embodiments of the present invention can be referred to the array substrate described in any of the above embodiments, and has the same beneficial effects, so it will not be described again.

[0242] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0243] Optionally, embodiments of the present invention also provide a display device, which includes the array substrate provided in any embodiment of the present invention. Therefore, the display device also possesses the beneficial effects described in any of the above embodiments. The array substrate can be a display panel. The array substrate can be a flexible substrate or a rigid substrate. By using the array substrate provided in any of the above embodiments to form a display device, the display effect of AOD (Always On Display) can be effectively improved. Figure 30 This is a schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 is a mobile phone, but it can also be any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on these.

[0244] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0245] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized by, include: Base; A pixel circuit is located on the substrate. The pixel circuit includes a driving transistor, a storage capacitor, at least one first capacitor, and at least one preset transistor. The storage capacitor includes a first electrode plate and a second electrode plate stacked along the thickness direction of the substrate. The first electrode plate of the storage capacitor is connected to the gate of the driving transistor. In at least a portion of the first capacitors, the second electrode plate is reused as an electrode plate of the first capacitor. The first capacitor also includes a third electrode plate located on the side of the second electrode plate away from the first electrode plate. The preset transistor is connected to the third electrode plate. A first trace is located on the side of the third plate of at least a portion of the first capacitors away from the second plate, at least a portion of the first trace is multiplexed as a plate of the first capacitor, and the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the third plate on the substrate to form a portion of the first capacitor. A first insulating layer is located between the first electrode plate and the second electrode plate; The second insulating layer is located between the second electrode plate and the third electrode plate; The third insulating layer is located between the third electrode plate and the first trace.

2. The array substrate according to claim 1, characterized in that, In at least a portion of the first capacitors, the overlapping area of ​​the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate.

3. The array substrate of claim 1, wherein, In at least a portion of the first capacitors, the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate to form a first sub-capacitor of the first capacitor, and the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the third electrode plate on the substrate to form a second sub-capacitor of the first capacitor.

4. The array substrate of claim 3, wherein, The first sub-capacitor and the second sub-capacitor are connected in parallel.

5. The array substrate of claim 1, wherein, The second electrode plate is electrically connected to the first trace.

6. The array substrate of claim 1, wherein, The first electrode is located between the substrate and the second electrode.

7. The array substrate of claim 1, wherein, The first plate of the storage capacitor is reused as the gate of the driving transistor.

8. The array substrate of claim 1, wherein, The array substrate also includes a data line, the first trace extends along a first direction with the data line, and the first trace and the data line are disposed on the same layer.

9. The array substrate of claim 1, wherein, The orthographic projection of the third electrode plate on the substrate lies within the orthographic projection of the first trace on the substrate.

10. The array substrate of claim 1, wherein, The second electrode plate and the first trace are connected to the power supply voltage or DC potential.

11. The array substrate according to claim 1, characterized in that, In at least a portion of the first capacitors, the overlapping area of ​​the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate, the overlapping area of ​​the orthographic projection of the third electrode plate on the substrate, overlaps with the orthographic projection of the first trace on the substrate.

12. The array substrate of claim 1, wherein, In at least a portion of the first capacitors, the area of ​​the overlapping region between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate is smaller than the area of ​​the overlapping region between the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the first trace on the substrate.

13. The array substrate of claim 1, wherein, In at least a portion of the first capacitors, the area of ​​the overlapping region of the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate, and the area of ​​the overlapping region of the orthographic projection of the third electrode plate on the substrate, is smaller than the area of ​​the overlapping region of the orthographic projection of the third electrode plate on the substrate and the orthographic projection of the first trace on the substrate.

14. The array substrate of claim 1, wherein, Also includes: The second trace is connected to the gate of the driving transistor. At least a portion of the second trace is multiplexed as a plate of the storage capacitor. At least a portion of the first trace is multiplexed as a plate of the storage capacitor. The orthographic projection of the second trace on the substrate overlaps with the orthographic projection of the first trace on the substrate to form a portion of the storage capacitor.

15. The array substrate of claim 14, wherein, The orthographic projection of the second trace on the substrate and the orthographic projection of the third electrode plate on the substrate are spaced apart.

16. The array substrate of claim 14, wherein, The second trace is disposed on the same layer as the third electrode plate.

17. The array substrate of claim 14, wherein, The second trace extends along the first trace in the first direction.

18. The array substrate of claim 14, wherein, The orthographic projection of the second trace on the substrate lies within the orthographic projection of the first trace on the substrate.

19. The array substrate of claim 1, wherein, The pixel circuit further includes at least one auxiliary transistor, the preset electrode of the auxiliary transistor is connected to the third electrode plate, and the preset transistor is connected between the preset electrode of the auxiliary transistor and the driving transistor.

20. The array substrate of claim 19, wherein, The at least one preset transistor includes a first transistor, the at least one auxiliary transistor includes a second transistor, the first terminal of the first transistor is connected to the gate of the driving transistor, the second terminals of the first transistor and the first terminals of the second transistor are connected to the third plate, and the second terminal of the second transistor is connected to the first terminal of the driving transistor.

21. The array substrate of claim 19, wherein, The at least one preset transistor includes a third transistor, the at least one auxiliary transistor includes a fourth transistor, the first terminal of the third transistor is connected to the gate of the driving transistor, the second terminal of the third transistor and the first terminal of the fourth transistor are connected to the third plate, and the second terminal of the fourth transistor is connected to the initialization signal line.

22. The array substrate of claim 19, wherein, The at least one preset transistor includes a fifth transistor, the at least one auxiliary transistor includes a sixth transistor, the pixel circuit further includes a seventh transistor, the first terminal of the fifth transistor is connected to the gate of the driving transistor, the second terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor are connected to the third electrode plate, the second terminal of the sixth transistor is connected to the first terminal of the driving transistor, and the second terminal of the seventh transistor is connected to the initialization signal line.

23. The array substrate of claim 1, wherein, The at least one preset transistor includes an eighth transistor, the first terminal of the eighth transistor and the second terminal of the driving transistor are connected to the third plate, and the second terminal of the eighth transistor is connected to the data line.

24. The array substrate of claim 19, wherein, The at least one preset transistor includes an eighth transistor, the at least one auxiliary transistor includes a ninth transistor, the first terminal of the eighth transistor is connected to the second terminal of the driving transistor, the second terminal of the eighth transistor and the first terminal of the ninth transistor are connected to the third plate, and the second terminal of the ninth transistor is connected to the data line.

25. The array substrate of claim 19, wherein, The at least one preset transistor includes a first transistor and a tenth transistor, and the at least one auxiliary transistor includes a second transistor and an eleventh transistor; The first terminal of the tenth transistor is connected to the gate of the driving transistor, the second terminal of the tenth transistor is connected to the first terminal of the eleventh transistor, the first terminal of the first transistor is connected to the second terminal of the eleventh transistor, the first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the driving transistor. In the same pixel circuit, there may be one first capacitor and one third electrode plate, or there may be at least two first capacitors and at least two third electrodes. The second terminal of the first transistor and the first terminal of the second transistor are connected to the third plate, and / or the first terminal of the first transistor and the second terminal of the eleventh transistor are connected to the third plate, and / or the first terminal of the eleventh transistor and the second terminal of the tenth transistor are connected to the third plate.

26. The array substrate of claim 25, wherein, In the same pixel circuit, there are at least two third electrodes, and the at least two third electrodes are arranged at intervals. The orthographic projection of the third plate of each first capacitor on the substrate overlaps with the orthographic projection of the first trace on the substrate, and the orthographic projection of the third plate of each first capacitor on the substrate overlaps with the orthographic projection of the second plate on the substrate. Alternatively, the orthographic projection of the third plate of each of the first capacitors onto the substrate overlaps with the orthographic projection of the first trace onto the substrate, and the orthographic projection of the third plate of a portion of the first capacitors onto the substrate overlaps with the orthographic projection of the second plate onto the substrate. The orthographic projection of the third plate of a portion of the first capacitor onto the substrate does not overlap with the orthographic projection of the second plate onto the substrate.

27. The array substrate of claim 1, wherein, The ratio of the capacitance of the storage capacitor to that of the first capacitor is greater than or equal to 1:4 and less than or equal to 4:

1.

28. The array substrate of claim 1, wherein, The second insulating layer is an inorganic insulating layer, and the third insulating layer is an inorganic insulating layer.

29. The array substrate of claim 1, wherein, The thickness of the second insulating layer is greater than or equal to 2000 angstroms and less than or equal to 2500 angstroms.

30. The array substrate of claim 1, wherein, The thickness of the third insulating layer is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.

31. The array substrate of claim 14, wherein, The array substrate further includes multiple conductive layers stacked on one side of the substrate. The multiple conductive layers are a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on one side. The first electrode is located on the first conductive layer, the second electrode is located on the second conductive layer, the third electrode and the second trace are located on the third conductive layer, and the first trace is located on the fourth conductive layer.

32. The array substrate of claim 31, wherein, The array substrate further includes an active layer and a fourth insulating layer. The active layer is located between the first conductive layer and the substrate. The fourth insulating layer is located between the active layer and the first conductive layer. The first insulating layer is located between the first conductive layer and the second conductive layer. The second insulating layer is located between the second conductive layer and the third conductive layer. The third insulating layer is located between the third conductive layer and the fourth conductive layer.

33. The array substrate of claim 32, wherein, At the intersection of the first trace and the second electrode plate, the first trace is connected to the second electrode plate via a first via.

34. The array substrate of claim 33, wherein, The gate of the driving transistor is connected to the second trace via a second via, and the active layer is connected to the second trace via a third via; the active layer includes the active portion of the preset transistor, and the active portion of the preset transistor is connected to the third plate via a fourth via.

35. The array substrate of claim 34, wherein, The first via penetrates the third insulating layer and the second insulating layer, the second via penetrates the second insulating layer and the first insulating layer, and the third via penetrates the second insulating layer, the first insulating layer and the fourth insulating layer; The fourth via penetrates the second insulating layer, the first insulating layer, and the fourth insulating layer.

36. The array substrate of claim 1, wherein, The array substrate further includes a second trace, which is connected to the gate of the driving transistor, wherein the second trace is disposed on a different layer from the third electrode plate.

37. The array substrate of claim 36, wherein, The array substrate further includes multiple conductive layers stacked on one side of the substrate. The multiple conductive layers are a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on one side. The first electrode is located on the first conductive layer, the second electrode is located on the second conductive layer, the third electrode is located on the third conductive layer, and the first trace and the second trace are located on the fourth conductive layer.

38. The array substrate of claim 37, wherein, The array substrate further includes an active layer and a fourth insulating layer. The active layer is located between the first conductive layer and the substrate. The fourth insulating layer is located between the active layer and the first conductive layer. The first insulating layer is located between the first conductive layer and the second conductive layer. The second insulating layer is located between the second conductive layer and the third conductive layer. The third insulating layer is located between the third conductive layer and the fourth conductive layer.

39. The array substrate of claim 38, wherein, At the intersection of the first trace and the second electrode plate, the first trace is connected to the second electrode plate via a first via.

40. The array substrate of claim 39, wherein, The gate of the driving transistor is connected to the second trace via a second via, and the active layer is connected to the second trace via a third via; the active layer includes the active portion of the preset transistor, and the active portion of the preset transistor is connected to the third plate via a fourth via.

41. The array substrate of claim 40, wherein, The first via penetrates the third insulating layer and the second insulating layer; the second via penetrates the third insulating layer, the second insulating layer and the first insulating layer; the third via penetrates the third insulating layer, the second insulating layer, the first insulating layer and the fourth insulating layer; and the fourth via penetrates the second insulating layer, the first insulating layer and the fourth insulating layer.

42. The array substrate of claim 32 or 38, wherein, The array substrate also includes a data line, the second trace extends along a first direction with the data line, and the first trace is disposed on the same layer as the data line.

43. The array substrate of claim 42, wherein, The data line is connected to the active layer through a fifth via, and the fifth via penetrates the third insulating layer, the second insulating layer, the first insulating layer and the fourth insulating layer; Alternatively, the array substrate may further include a transition section, wherein the film layer containing the transition section is located between the film layer containing the data line and the active layer, the data line is connected to the transition section via a sixth via, and the active layer is connected to the transition section via a seventh via.

44. The array substrate of claim 43, wherein, The adapter is disposed on the same layer as the third electrode plate; and / or, the adapter is disposed on the same layer as the second trace.

45. The array substrate of claim 43, wherein, The sixth via penetrates the third insulating layer; the seventh via penetrates the second insulating layer, the first insulating layer, and the fourth insulating layer.

46. The array substrate of claim 43, wherein, The orthographic projection of the adapter on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate, and the orthographic projection of the adapter on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

47. The array substrate of claim 43, wherein, The overlapping area of ​​the orthographic projection of the data line on the substrate and the orthographic projection of the active layer on the substrate overlaps with the orthographic projection of the transition part on the substrate.

48. The array substrate of claim 25, wherein, The array substrate further includes a first scan line, a second scan line, and an active layer; For the same pixel circuit, the orthographic projection of the second scan line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first scan line on the substrate. The first scan line overlaps with the active layer to form the tenth transistor, the eleventh transistor, and the first transistor, respectively, and the second scan line overlaps with the active layer to form the second transistor.

49. The array substrate of claim 48, wherein, The pixel circuit further includes a data writing transistor, which is formed by the overlap of the second scan line and the active layer. The data writing transistor is connected between the data line and the second electrode of the driving transistor.

50. The array substrate of claim 48, wherein, The pixel circuit further includes a first initialization transistor and a second initialization transistor. The array substrate further includes a third scan line, a fourth scan line and an initialization signal line. The third scan line overlaps with the active layer to form the first initialization transistor, and the fourth scan line overlaps with the active layer to form the second initialization transistor. The first initialization transistor is connected to the initialization signal line, and the first initialization transistor is used to transmit the initialization voltage on the initialization signal line to the gate of the driving transistor; The second initialization transistor is connected between the initialization signal line and the first electrode of the light-emitting element, and the second initialization transistor is used to transmit the initialization voltage on the initialization signal line to the first electrode of the light-emitting element.

51. The array substrate of claim 50, wherein, The third scan line and the fourth scan line are arranged on the same layer, and the third scan line and the initialization signal line are arranged on different layers.

52. The array substrate of claim 50, wherein, The third scan line and the fourth scan line are disposed on the same layer as the gate of the driving transistor or the first electrode plate, and the initialization signal line is disposed on the same layer as the second electrode plate.

53. The array substrate of claim 50, wherein, The pixel circuit further includes a bias transistor, and the array substrate further includes a bias voltage signal line. The fourth scan line overlaps with the active layer to form the bias transistor. The bias transistor is connected between the bias voltage signal line and the first terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the first terminal of the driving transistor; or, the bias transistor is connected between the bias voltage signal line and the second terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the second terminal of the driving transistor.

54. The array substrate of claim 53, wherein, The bias voltage signal line is disposed on the same layer as the second electrode plate or the initialization signal line.

55. The array substrate of claim 53, wherein, For the same pixel circuit, the orthogonal projection of the bias voltage signal line on the substrate is located between the orthogonal projection of the third scan line on the substrate and the orthogonal projection of the fourth scan line connected to the bias transistor on the substrate.

56. The array substrate of claim 50, wherein, The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The array substrate further includes a light-emitting control signal line. The light-emitting control signal line overlaps with the active layer to form the first light-emitting control transistor and the second light-emitting control transistor. The first electrode of the first light-emitting control transistor is connected to the first trace. The second electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor. The second light-emitting control transistor is connected between the first electrode of the driving transistor and the first electrode of the light-emitting element.

57. The array substrate of claim 56, wherein, The light emission control signal line is disposed on the same layer as the gate of the driving transistor or the first electrode plate.

58. The array substrate of claim 50, wherein, For the same pixel circuit, the orthogonal projection of the third scan line on the substrate is located on the side where the orthogonal projection of the first scan line on the substrate is away from the orthogonal projection of the gate of the driving transistor on the substrate.

59. The array substrate of claim 53, wherein, Corresponding to the same pixel circuit, the orthogonal projection of the fourth scan line connected to the bias transistor on the substrate is located on the side where the orthogonal projection of the third scan line on the substrate is away from the orthogonal projection of the gate of the driving transistor on the substrate.

60. The array substrate of claim 53, wherein, For the same pixel circuit, the orthogonal projection of the initialization signal line adjacent to the bias transistor on the substrate is located on the side where the orthogonal projection of the fourth scan line connected to the bias transistor on the substrate is far from the orthogonal projection of the bias voltage signal line on the substrate.

61. The array substrate of claim 56, wherein, Corresponding to the same pixel circuit, the orthogonal projection of the light emission control signal line on the substrate is located on the side where the orthogonal projection of the gate of the driving transistor on the substrate is far from the orthogonal projection of the second scan line on the substrate.

62. The array substrate of claim 48, wherein, The orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the first scan line on the substrate.

63. The array substrate of claim 50, wherein, The orthographic projection of the third electrode plate on the substrate overlaps with the orthographic projection of the third scan line on the substrate.

64. The array substrate of claim 50, wherein, The array substrate further includes a connecting line, which connects the initialization signal line and the second initialization transistor. The orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the fourth scan line on the substrate. The orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the first trace on the substrate.

65. The array substrate of claim 64, wherein, The orthographic projection of the connecting line on the substrate lies within the orthographic projection of the first trace on the substrate.

66. The array substrate of claim 64, wherein, The connecting line is disposed on the same layer as the third electrode plate.

67. The array substrate of claim 56, wherein, The array substrate further includes a connection portion, through which the first trace is connected to the first electrode of the first light-emitting control transistor.

68. The array substrate of claim 67, wherein, The connecting part is disposed on the same layer as the third electrode plate.

69. The array substrate of claim 53, wherein, In the pixel circuits of two adjacent rows, the bias transistor in the pixel circuit of this row and the second initialization transistor in the pixel circuit of the previous row are formed by overlapping with the active layer through the same fourth scan line.

70. The array substrate of claim 50, wherein, The operation of the pixel circuit includes writing frames and holding frames; Within the write frame, the first scan signal transmitted on the first scan line, the second scan signal transmitted on the second scan line, the third scan signal transmitted on the third scan line, and the fourth scan signal transmitted on the fourth scan line each include at least two pulses. The start time of the first pulse of the first scan signal is after the end time of the first pulse of the third scan signal, and the first pulse of the first scan signal and the second pulse of the third scan signal at least partially overlap. The start time of the first pulse of the second scan signal is after the end time of the first pulse of the first scan signal, and the first pulse of the second scan signal and the second pulse of the first scan signal at least partially overlap. The start time of the first pulse of the fourth scan signal is after the end time of the second pulse of the second scan signal. Within the hold frame, the first scan signal, the second scan signal, and the third scan signal remain at a fixed level, and the fourth scan signal includes at least two pulses.

71. An array substrate, comprising: include: Base; An active layer and a multilayer conductive layer are stacked together, wherein the active layer and the multilayer conductive layer form a pixel circuit, wherein the multilayer conductive layer is located on the side of the active layer away from the substrate, and the pixel circuit includes a driving transistor, a first initialization transistor, a second initialization transistor, and a bias transistor; The system comprises a third scan line, a fourth scan line, an initialization signal line, and a bias voltage signal line. The third scan line overlaps with the active layer to form the first initialization transistor. The fourth scan line overlaps with the active layer to form the second initialization transistor and the bias transistor. The first initialization transistor is connected to the initialization signal line and is used to transmit the initialization voltage on the initialization signal line to the gate of the driving transistor. The second initialization transistor is connected between the initialization signal line on the initialization signal line and the first terminal of the light-emitting element, and the second initialization transistor is used to transmit the initialization voltage to the first terminal of the light-emitting element. The bias transistor is connected between the bias voltage signal line and the first terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the first terminal of the driving transistor; or, the bias transistor is connected between the bias voltage signal line and the second terminal of the driving transistor, and the bias transistor is used to transmit the bias voltage on the bias voltage signal line to the second terminal of the driving transistor. For the same pixel circuit, the orthographic projection of the third scan line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the fourth scan line connected to the bias transistor on the substrate. And / or, corresponding to the same pixel circuit, the orthographic projection of the bias voltage signal line on the substrate is located between the orthographic projection of the third scan line on the substrate and the orthographic projection of the fourth scan line connected to the bias transistor on the substrate; And / or, corresponding to the same pixel circuit, the orthogonal projection of the initialization signal line adjacent to the bias transistor on the substrate is located on the side where the orthogonal projection of the fourth scan line connected to the bias transistor on the substrate is far from the orthogonal projection of the bias voltage signal line on the substrate.

72. A display device, comprising: Includes the array substrate described in any one of claims 1-71.

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