Semiconductor device

Abstract

In order to achieve excellent performance and economic efficiency, it is desirable to improve the integration level of a semiconductor device. According to the semiconductor device provided by the present invention, in a semiconductor device including a vertical channel transistor, a bit line is configured into two layers to reduce contact resistance with respect to a channel layer, and thus electrical characteristics and product performance of the semiconductor device can be improved.

Description

BACKGROUND OF THE INVENTION

[0001] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical channel transistor.

[0002] To achieve excellent performance and economic efficiency, it is desirable to increase the integration degree of semiconductor devices. In particular, the integration degree of memory devices is an important factor determining the economic feasibility of products. Since the integration degree of two-dimensional memory devices is mainly determined by the area occupied by a unit memory cell, the technical level for forming fine patterns is a decisive factor. However, since expensive devices are required to form fine patterns and the area of chip dies is limited, although the integration degree of two-dimensional memory devices is increasing, it is still limited. SUMMARY OF THE INVENTION

[0003] The inventive concept provides a semiconductor device having improved electrical characteristics and improved product performance.

[0004] The objects to be solved and improved by the inventive concept are not limited to the above objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to some aspects of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate and including a lower conductive layer and an upper conductive layer; a channel layer penetrating a part of the bit line in the bit line and having an inner wall and an outer wall; a gate insulating layer on one side of the inner wall of the channel layer; a word line on the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; and a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer, the channel layer includes an oxide semiconductor material containing indium (In), the upper conductive layer includes a conductive material containing In, and the outer wall of the channel layer contacts the upper conductive layer, but does not contact the lower conductive layer.

[0006] According to some aspects of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate and including a central conductive layer and a U-shaped conductive layer; a channel layer passing through a part of the bit line in the bit line and having sidewalls and a bottom; a gate insulating layer on one side of the sidewalls of the channel layer; a word line on the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; and a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer, the bottom of the channel layer contacts the U-shaped conductive layer, but does not contact the central conductive layer, and the U-shaped conductive layer extends conformally along the bottom of the channel layer.

[0007] According to some aspects of the inventive concept, there is provided a semiconductor device including: bit lines extending in a first horizontal direction on a substrate and including a first conductive layer containing a metal or a metal nitride and a second conductive layer containing In; a molding layer covering the bit lines on the substrate and defining mold openings; a channel layer on inner walls of the mold openings, having a bottom penetrating the bottom of the bit lines and sidewalls extending in a vertical direction on the inner walls of the mold openings, and including an oxide semiconductor material containing In; a gate insulating layer on the channel layer within the mold openings and including a high-k dielectric material; a word line within the mold openings and on the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer; and a capacitor structure on the contact layer, wherein a bottom of the channel layer contacts the second conductive layer but does not contact the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A layout of a semiconductor device according to some example embodiments is shown.

[0010] Figure 2 Shown Figure 1 An enlarged layout of a part of a cell array region.

[0011] Figure 3 Is a cross-sectional view taken along line A1-A1' in Figure 2 Therein.

[0012] Figure 4 And Figure 5 Are cross-sectional views illustrating a semiconductor device according to some example embodiments.

[0013] Figures 6 to 16 Is a cross-sectional view showing a method of manufacturing a semiconductor device according to a process sequence according to some example embodiments.

[0014] Figure 17 Is a structural diagram showing a system including a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0015] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 A layout of a semiconductor device according to some example embodiments is shown. Figure 2 Shown Figure 1 An enlarged layout of a part of a cell array region. Figure 3 Is along Figure 2A cross-sectional view taken along line A1 - A1' in

[0017] Referring together to Figures 1 to 3 , the semiconductor device 100 may include a substrate 110, and the substrate 110 includes a cell array region MCA and a peripheral circuit region PCA.

[0018] In some example embodiments, the cell array region MCA may be a memory cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors (not shown) that transmit signals and / or power to the memory cell array included in the cell array region MCA.

[0019] In some example embodiments, the peripheral circuit transistors (not shown) may form various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and / or a data input / output circuit.

[0020] In the cell array region MCA of the substrate 110, a plurality of bit lines BL extending in a first horizontal direction X and a plurality of word lines WL extending in a second horizontal direction Y intersecting the first horizontal direction X may be arranged. A plurality of cell transistors CTR may be provided at intersections between the plurality of bit lines BL and the plurality of word lines WL. A plurality of cell capacitors CAP may be respectively provided on the plurality of cell transistors CTR.

[0021] The plurality of word lines WL may include a first word line WL1 and a second word line WL2 alternately arranged in the first horizontal direction X, and the plurality of cell transistors CTR may include a first cell transistor CTR1 and a second cell transistor CTR2 alternately arranged in the first horizontal direction X. That is, the first cell transistor CTR1 may be provided on the first word line WL1, and the second cell transistor CTR2 may be provided on the second word line WL2.

[0022] The first cell transistor CTR1 and the second cell transistor CTR2 may have a mirror-symmetric structure with respect to each other. For example, the first cell transistor CTR1 and the second cell transistor CTR2 may have a mirror-symmetric structure with respect to a center line extending in the second horizontal direction Y.

[0023] In some example embodiments, the width of the plurality of bit lines BL may be 1F, and the pitch (e.g., the sum of the width and the spacing) of the plurality of bit lines BL may be 2F, where F is a non-zero distance. Additionally, the width of the plurality of word lines WL may be 1F, and the pitch of the plurality of word lines WL may be 2F. Thus, the unit area for forming one cell transistor CTR may be 4F 2Therefore, the unit transistor CTR can have a cross-point type that requires a relatively small unit area, which may be advantageous for improving the integration of the semiconductor device 100.

[0024] The lower insulating layer 112 may be disposed on the substrate 110. In some example embodiments, the substrate 110 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some example embodiments, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. Additionally, the lower insulating layer 112 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0025] The bit line BL extending in the first horizontal direction X may be disposed on the lower insulating layer 112. In some example embodiments, the bit line BL may have a stacked structure including a lower conductive layer 120 and an upper conductive layer 122 disposed on the lower conductive layer 120. Here, the lower conductive layer 120 may be referred to as the first conductive layer, and the upper conductive layer 122 may be referred to as the second conductive layer.

[0026] In the semiconductor device 100 according to some example embodiments, the lower conductive layer 120 may include, for example, a metal such as tungsten (W), ruthenium (Ru), or molybdenum (Mo); or a metal nitride such as tungsten nitride (WN) and titanium nitride (TiN); or a combination thereof. However, the example embodiments are not limited thereto. Additionally, the upper conductive layer 122 may include a conductive material containing indium (In), for example, indium tin oxide (ITO) and indium oxide (InO x ) or any one of them, but not limited thereto.

[0027] In some example embodiments, the bit line BL may include a lower conduction blocking layer 124L disposed on the lower surface of the lower conductive layer 120 and an upper conduction blocking layer 124U disposed on the upper surface of the upper conductive layer 124.

[0028] In some example embodiments, the thickness of the upper conductive layer 122 in the vertical direction Z may be configured to be less than the thickness of the lower conductive layer 120 in the vertical direction Z.

[0029] In some exemplary embodiments, the upper conductive layer 122 may be disposed on the upper surface of the lower conductive layer 120, and the lower conduction blocking layer 124L may be disposed on the lower surface of the lower conductive layer 120, and both the upper surface and the lower surface of the lower conductive layer 120 may be formed in a flat shape. Additionally, the upper conduction blocking layer 124U may be disposed on a part of the upper surface of the upper conductive layer 122, and the lower conductive layer 120 may be disposed on the lower surface of the upper conductive layer 122, and the upper surface of the upper conductive layer 122 may have an uneven shape, and the lower surface of the upper conductive layer 122 may be formed in a flat shape.

[0030] That is to say, the bit line BL may include a groove region and a flat region surrounding the groove region, and a channel layer 140 described later may be disposed by penetrating the bit line BL in the groove region. Here, the groove region of the bit line BL may be formed in the upper conduction blocking layer 124U and the upper conductive layer 122.

[0031] A bit line insulating layer (not shown) extending in the first horizontal direction X may be disposed on the sidewalls of the bit line BL. For example, the bit line insulating layer may fill the space between two adjacent bit lines BL and may be at the same height as the bit line BL.

[0032] The mold layer 130 may be disposed on the bit line BL and the bit line insulating layer. The mold layer 130 may include a plurality of mold openings 130H. Here, each mold opening 130H may have a first sidewall 130H1 and a second sidewall 130H2 facing each other. Additionally, each mold opening 130H may have a rounded lower wall 130H3 exposing the upper conductive layer 122 of the bit line BL. The groove region may be formed in the bit line BL through the rounded lower wall 130H3 of each mold opening 130H. Additionally, the mold layer 130 may be disposed to cover the flat region surrounding the groove region of the bit line BL. For example, the mold layer 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0033] A plurality of channel layers 140 may be disposed on the inner walls of the plurality of mold openings 130H. Each of the plurality of channel layers 140 may include a first portion 140P1 extending in the first horizontal direction X from the rounded lower wall 130H3 of the plurality of mold openings 130H and a second portion 140P2 connected to the first portion 140P1 and disposed on the first sidewall 130H1 and the second sidewall 130H2 of the plurality of mold openings 130H.

[0034] In some example embodiments, each of the plurality of channel layers 140 may have a U-shaped vertical cross-section that penetrates the bit line BL. A first portion 140P1 of the plurality of channel layers 140 may have a rounded corner. A second portion 140P2 of the plurality of channel layers 140 may include a first sidewall 140S1 and a second sidewall 140S2 that face each other, and the second sidewall 140S2 may be in contact with the mold layer 130.

[0035] In addition, the first portion 140P1 and the second portion 140P2 of the plurality of channel layers 140 may be in contact with the bit line BL. The first portion 140P1 of the plurality of channel layers 140 may be in contact with the upper conductive layer 122, and a portion of the second portion 140P2 of the plurality of channel layers 140 may be in contact with the upper conduction blocking layer 124U. However, the plurality of channel layers 140 may not be in contact with the lower conductive layer 120 and the lower conduction blocking layer 124L.

[0036] In some example embodiments, the plurality of channel layers 140 may include an oxide semiconductor material. In some example embodiments, the oxide semiconductor material may include In, such as InGaZnO x (IGZO), Sn-doped InGaZnO x (IGZO), W-doped InGaZnO x (IGZO) and IZO (InZnO x ).

[0037] The gate insulating layer 150 and the word line WL may be sequentially disposed on the first sidewall 140S1 of the plurality of channel layers 140. For example, the gate insulating layer 150 may be conformally disposed on the upper surface of the first portion 140P1 of the plurality of channel layers 140 and the first sidewall 140S1 of the second portion 140P2.

[0038] The word line WL may be disposed on the upper surface of the first portion 140P1 of the plurality of channel layers 140 and the first sidewall 140S1 of the second portion 140P2, and the gate insulating layer 150 may be disposed between the word line WL and the channel layer 140. Here, the gate insulating layer 150 may include an outer wall facing the first sidewall 140S1 of the plurality of channel layers 140 and an inner wall facing the word line WL.

[0039] The channel layer 140 having a U-shaped vertical cross-section may be disposed within a mold opening 130H, and two word lines WL may be disposed separately from each other on the channel layer 140 within the mold opening 130H. Here, one word line WL may be disposed to face a second portion 140P2 of the channel layer 140, and the other word line WL may be disposed to face another second portion 140P2 of the channel layer 140. A word line WL, a second portion 140P2 of the channel layer 140, and the gate insulating layer 150 may constitute a first unit transistor CTR1. Additionally, the other word line WL, another second portion 140P2 of the channel layer 140, and the gate insulating layer 150 may constitute a second unit transistor CTR2. Thus, the first unit transistor CTR1 and the second unit transistor CTR2 may be disposed mirror-symmetrically with respect to each other within a mold opening 130H.

[0040] In some example embodiments, the gate insulating layer 150 may include a high-k dielectric material having a higher dielectric constant than silicon oxide. In some example embodiments, the gate insulating layer 150 may have a dielectric constant of about or exactly 10 to about or exactly 25. For example, the gate insulating layer 150 may include HfO2, Al2O3, HfAlO3, Ta2O3, TiO2, or a combination thereof, but is not limited thereto.

[0041] In some example embodiments, the word line WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0042] The contact layer 170 may be disposed on the upper surface of the channel layer 140 and the upper surface of the gate insulating layer 150. The contact layer 170 may cover the channel layer 140 and the gate insulating layer 150, and may extend onto the mold layer 130. The contact layer 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0043] The insulating spacer 182A and the first insulating layer 182B may be disposed between two word lines WL within each of the plurality of mold openings 130H, and the second insulating layer 184 may be disposed on the two word lines WL. Additionally, the third insulating layer 186 may be disposed on two sidewalls of the contact layer 170. For example, the insulating spacer 182A may include silicon nitride, and the first insulating layer 182B may include silicon oxide. Additionally, the second insulating layer 184 and the third insulating layer 186 may include silicon nitride.

[0044] The etch stop layer 188 may be disposed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 may include an opening 188H, and the upper surface of the contact layer 170 may be exposed through the opening 188H.

[0045] The capacitor structure 190 may be disposed on the etch stop layer 188. The capacitor structure 190 may include a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196. Sidewalls at the bottom of the lower electrode 192 may be disposed within the opening 188H of the etch stop layer 188, and the lower electrode 192 may extend in the vertical direction Z. The capacitor dielectric layer 194 may be disposed on the sidewalls of the lower electrode 192, and the upper electrode 196 may cover the capacitor dielectric layer 194 on the lower electrode 192.

[0046] To achieve excellent performance and economic efficiency, it is necessary to increase the integration degree of semiconductor devices. In particular, the integration degree of memory devices is an important factor determining the economic feasibility of products. Since the integration degree of two-dimensional memory devices is mainly determined by the area occupied by a unit memory cell, the technical level for forming fine patterns is a decisive factor. However, due to the need for expensive devices to form fine patterns and the limited area of chip dies, although the integration degree of two-dimensional memory devices is increasing, it is still limited. Therefore, the demand for semiconductor devices including vertical channel transistors (VCTs) is increasing.

[0047] Generally, in semiconductor devices using an oxide semiconductor material containing In as the channel layer constituting the vertical channel transistor, due to the significant difference in properties between the material constituting the channel layer (oxide semiconductor material) and the material constituting the bit line (metal or metal nitride), the contact resistance increases, and electrical characteristics such as on-current may deteriorate. Therefore, problems such as a reduction in product reliability may occur in semiconductor devices.

[0048] To solve problems such as those described above, in the semiconductor device 100 according to the inventive concept, the bit line BL may be formed in a stacked structure, and in particular, a conductive material containing In, which is the material constituting the channel layer 140, may be used to form the upper conductive layer 122 so as to first reduce the contact resistance on the contact surface between the channel layer 140 and the upper conductive layer 122, and second reduce the contact resistance on the contact surface between the upper conductive layer 122 and the lower conductive layer 120. Therefore, the total resistance of the bit line BL can be reduced, and electrical characteristics such as on-current can be improved.

[0049] Ultimately, a semiconductor device 100 having improved electrical characteristics and product performance can be provided by forming the bit line BL in a stacked structure including the lower conductive layer 120 and the upper conductive layer 122 made of different conductive materials.

[0050] Figure 4 and Figure 5 is a cross-sectional view showing a semiconductor device according to some example embodiments.

[0051] Most of the components that make up semiconductor devices 100A and 100B below and the materials forming the components are substantially the same as or similar to those described in the previous reference Figures 1 to 3 described. Therefore, for ease of description, the description will focus on the differences from the above semiconductor device 100.

[0052] Reference Figure 4 , the semiconductor device 100A may include a bit line BL, a word line WL, a channel layer 140, a gate insulating layer 150, a contact layer 170, and a capacitor structure 190. The bit line BL includes a central conductive layer 120A and a U-shaped conductive layer 122A.

[0053] In the semiconductor device 100A according to some example embodiments, the bit line BL extending in the first horizontal direction X may be disposed on the lower insulating layer 112. In some example embodiments, the bit line BL may include a central conductive layer 120A and a U-shaped conductive layer 122A disposed on a part of the central conductive layer 120A. The central conductive layer 120A may include a groove region, and the U-shaped conductive layer 122A may be conformally disposed in contact with the inner wall of the groove region of the central conductive layer 120A. Here, the central conductive layer 120A may be referred to as the first conductive layer, and the U-shaped conductive layer 122A may be referred to as the second conductive layer.

[0054] In the semiconductor device 100A according to some example embodiments, the central conductive layer 120A may comprise, for example, a metal such as tungsten (W), ruthenium (Ru), or molybdenum (Mo); or a metal nitride such as tungsten nitride (WN) and titanium nitride (TiN); or a combination thereof. However, the example embodiments are not limited thereto. Additionally, the U-shaped conductive layer 122A may include a conductive material containing In, for example, any one of indium tin oxide (ITO) and indium oxide (InO x ), but not limited thereto.

[0055] In some example embodiments, the bit line BL may include a lower conduction blocking layer 124L disposed on the lower surface of the central conductive layer 120A and an upper conduction blocking layer 124U disposed on a part of the upper surface of the central conductive layer 120A. Here, the uppermost surface of the U-shaped conductive layer 122A may be disposed in contact with the lowermost surface of the upper conduction blocking layer 124U.

[0056] In some example embodiments, each of the plurality of channel layers 140 may have a U-shaped vertical cross-section that penetrates the bit line BL. A first portion 140P1 of the plurality of channel layers 140 may have a rounded corner. The U-shaped conductive layer 122A may be conformally disposed along the rounded shape of the first portion 140P1 of the plurality of channel layers 140. A second portion 140P2 of the plurality of channel layers 140 may include a first sidewall 140S1 and a second sidewall 140S2 that face each other, and the second sidewall 140S2 may contact the mold layer 130.

[0057] In addition, the first portion 140P1 and the second portion 140P2 of the plurality of channel layers 140 may contact the bit line BL. The first portion 140P1 of the plurality of channel layers 140 may contact the U-shaped conductive layer 122A, and a portion of the second portion 140P2 of the plurality of channel layers 140 may contact the upper conduction barrier layer 124U. However, the plurality of channel layers 140 may not contact the lower conduction barrier layer 124L. In other words, the U-shaped conductive layer 122A may be disposed along the interface between the plurality of channel layers 140 and the central conductive layer 120A.

[0058] Reference Figure 5 , the semiconductor device 100B may include a bit line BL, a word line WL, a channel layer 140, a gate insulating layer 150, a contact layer 170, and a capacitor structure 190, and the bit line BL includes a central conductive layer 120B and a U-shaped conductive layer 122B.

[0059] In the semiconductor device 100B according to some example embodiments, the bit line BL extending in the first horizontal direction X may be disposed on the lower insulating layer 112. In some example embodiments, the bit line BL may include a central conductive layer 120B and a U-shaped conductive layer 122B disposed on a portion of the central conductive layer 120B. The central conductive layer 120B may include a groove region, and the U-shaped conductive layer 122B may be conformally disposed to contact the inner wall of the groove region of the central conductive layer 120B. Here, the central conductive layer 120B may be referred to as a first conductive layer, and the U-shaped conductive layer 122B may be referred to as a second conductive layer.

[0060] In the semiconductor device 100B according to some example embodiments, the central conductive layer 120B may include (for example) a metal such as tungsten (W), ruthenium (Ru), or molybdenum (Mo); or a metal nitride such as tungsten nitride (WN) and titanium nitride (TiN); or a combination thereof. However, the example embodiments are not limited thereto. In addition, the U-shaped conductive layer 122B may include a conductive material containing In, for example, indium tin oxide (ITO) and indium oxide (InO x ) any one of, but not limited thereto.

[0061] In some example embodiments, the bit line BL may include a lower conduction blocking layer 124L disposed on the lower surface of the central conductive layer 120B and an upper conduction blocking layer 124U disposed on a part of the upper surface of the central conductive layer 120B. Here, the sidewalls of the U-shaped conductive layer 122B may be disposed in contact with the sidewalls of the upper conduction blocking layer 124U.

[0062] In some example embodiments, each of the plurality of channel layers 140 may have a U-shaped vertical cross-section that penetrates the bit line BL. A first portion 140P1 of the plurality of channel layers 140 may have a rounded corner. The U-shaped conductive layer 122B may be conformally disposed along the rounded shape of the first portion 140P1 of the plurality of channel layers 140. A second portion 140P2 of the plurality of channel layers 140 may include a first sidewall 140S1 and a second sidewall 140S2 that face each other, and the second sidewall 140S2 may be in contact with the mold layer 130. However, due to the U-shaped conductive layer 122B, a step may be formed at the connection portion between the first portion 140P1 and the second portion 140P2 of the plurality of channel layers 140.

[0063] In addition, the first portion 140P1 and the second portion 140P2 of the plurality of channel layers 140 may be in contact with the bit line BL. The first portion 140P1 of the plurality of channel layers 140 may be in contact with the U-shaped conductive layer 122B, and a part of the second portion 140P2 of the plurality of channel layers 140 may be in contact with the upper conduction blocking layer 124U. In some exemplary embodiments, as Figure 5 shown, the U-shaped conductive layer 122B may be completely between the second portion 140P2 and the upper conduction blocking layer 124U. However, in some exemplary embodiments, the U-shaped conductive layer 122B may not extend completely between the second portion 140P2 and the upper conduction blocking layer 124U, such that a part of the second portion 140P2 of the plurality of channel layers 140 may be in contact with the upper conduction blocking layer 124U. However, the plurality of channel layers 140 may not be in contact with the lower conduction blocking layer 124L. In other words, the U-shaped conductive layer 122B may be disposed along the interface between the plurality of channel layers 140 and the central conductive layer 120B.

[0064] Figures 6 to 16 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a process sequence according to some exemplary embodiments.

[0065] Referring Figure 6 , a lower insulating layer 112 may be formed on the substrate 110.

[0066] Next, a plurality of bit lines BL extending in a first horizontal direction X may be formed on the lower insulating layer 112 and a bit line insulating layer (not shown) filling the space between the plurality of bit lines BL may be formed.

[0067] In some example embodiments, each of the plurality of bit lines BL may have a stacked structure including a lower conduction blocking layer 124L, a lower conductive layer 120, an upper conductive layer 122, and an upper conduction blocking layer 124U that are sequentially arranged. For example, a bit line insulating layer may be formed on the lower insulating layer 112, and a bit line formation space (not shown) may be formed by patterning the bit line insulating layer using a mask pattern (not shown). The lower conduction blocking layer 124L, the lower conductive layer 120, the upper conductive layer 122, and the upper conduction blocking layer 124U may be sequentially formed in the bit line formation space.

[0068] Next, the plurality of bit lines BL may be formed by removing upper portions of the lower conduction blocking layer 124L, the lower conductive layer 120, the upper conductive layer 122, and the upper conduction blocking layer 124U such that the upper surface of the bit line insulating layer is exposed.

[0069] The lower conductive layer 120 may include, for example, a metal such as tungsten (W), ruthenium (Ru), or molybdenum (Mo), or a metal nitride such as tungsten nitride (WN) or titanium nitride (TiN); or a combination thereof. Additionally, the upper conductive layer 122 may include a conductive material containing In, for example, indium tin oxide (ITO) and indium oxide (InO x ) or any one of them.

[0070] Reference Figure 7 , a mold layer 130 including a mold opening 130H may be formed on the plurality of bit lines BL and the bit line insulating layer.

[0071] The mold layer 130 may be formed using at least one of silicon oxide, silicon nitride, and silicon oxynitride, and has a relatively large height in the vertical direction Z.

[0072] Next, a mask pattern (not shown) may be formed on the mold layer 130, and the plurality of mold openings 130H may be formed using the mask pattern as an etch mask. Each mold opening 130H may have a first sidewall 130H1 and a second sidewall 130H2 facing each other.

[0073] Reference Figure 8 , the upper conduction blocking layer 124U and the upper conductive layer 122 of the bit line BL exposed through the mold opening 130H may be etched to form a rounded lower wall 130H3.

[0074] A groove region may be formed in the bit line BL through the rounded lower wall 130H3 of each mold opening 130H. The bit line BL may include a groove region and a flat region surrounding the groove region. Here, the groove region of the bit line BL may be formed only in the upper conduction blocking layer 124U and the upper conductive layer 122.

[0075] Reference Figure 9, a preliminary channel layer 140L can be formed on the mold layer 130 to conformally cover the inner wall of the mold opening 130H.

[0076] The preliminary channel layer 140L can be formed using an oxide semiconductor material. The oxide semiconductor material can include In, such as InGaZnO x (IGZO), Sn-doped InGaZnO x (IGZO), W-doped InGaZnO x (IGZO), and InZnO x (IZO).

[0077] In some example embodiments, at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD process, a plasma-enhanced CVD process, a metalorganic CVD (MOCVD) process, and / or an atomic layer deposition process can be used to form the preliminary channel layer 140L.

[0078] Reference Figure 10 , the gate insulating layer 150 and the gate electrode layer 160L can be sequentially formed on the preliminary channel layer 140L.

[0079] The gate insulating layer 150 can include a high-k dielectric material having a higher dielectric constant than silicon oxide. In some example embodiments, the gate electrode layer 160L can be formed using Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0080] Reference Figure 11 , an anisotropic etching process can be performed on the gate electrode layer 160L to remove a portion of the gate electrode layer 160L disposed on the bottom of the mold opening 130H, and the gate electrode layer 160L can remain on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H.

[0081] Meanwhile, a portion of the gate electrode layer 160L disposed on the upper surface of the mold layer 130 can be removed by the anisotropic etching process.

[0082] For example, the gate electrode layer 160L can be divided into two word lines WL respectively disposed on the first sidewall 130H1 and the second sidewall 130H2 of a plurality of mold openings 130H.

[0083] Meanwhile, a part of the gate insulating layer 150 provided on the bottom of the mold opening 130H can be removed through an anisotropic etching process. As a result, the upper surface of the preliminary channel layer 140L can be exposed on the bottom of the mold opening 130H. Additionally, through the anisotropic etching process, a part of the gate insulating layer 150 provided on the upper surface of the mold layer 130 can be removed, and the upper surface of the preliminary channel layer 140L can be exposed.

[0084] Reference Figure 12 , an insulating spacer 182A and a first insulating layer 182B can be formed inside the mold opening 130H.

[0085] The insulating spacer 182A and the first insulating layer 182B can be provided between two adjacent word lines WL, and the insulating spacer 182A can be provided on the upper surface of the preliminary channel layer 140L.

[0086] Reference Figure 13 , the insulating spacer 182A and a part of the preliminary channel layer 140L provided on the upper surface of the mold layer 130 can be removed through an etch-back process or a planarization process to form a channel layer 140 inside the mold opening 130H.

[0087] A channel layer 140 having a U-shaped vertical cross-section can be formed inside the mold opening 130H through an etch-back process or a planarization process. Additionally, when a part of the preliminary channel layer 140L provided on the upper surface of the mold layer 130 is removed, the upper surface of the mold layer 130 can be exposed.

[0088] In some exemplary embodiments, the channel layer 140 can include a first portion 140P1 extending in a first horizontal direction X and second portions 140P2 connected to both ends of the first portion 140P1 and extending in a vertical direction Z. A first sidewall 140S1 of the second portion 140P2 can be surrounded by the gate insulating layer 150, and a second sidewall 140S2 of the second portion 140P2 can be surrounded by the mold layer 130. Additionally, the upper surface of the channel layer 140 can be at the same vertical level as the upper surface of the mold layer 130.

[0089] Next, an upper portion of the word line WL provided inside the mold opening 130H can be removed through an etch-back process. In the etch-back process, an upper portion of the insulating spacer 182A and an upper portion of the first insulating layer 182B can be removed together.

[0090] Next, a second insulating layer 184 can be formed to fill the entrance of the mold opening 130H. The second insulating layer 184 can have a flat bottom surface provided on the upper surfaces of the word line WL, the insulating spacer 182A, and the first insulating layer 182B.

[0091] Accordingly, the first unit transistor CTR1 and the second unit transistor CTR2 can be formed within the mold opening 130H. The first unit transistor CTR1 and the second unit transistor CTR2 can be arranged mirror-symmetrically with respect to each other.

[0092] Reference Figure 14 , the contact conductive layer 170L can be formed on the mold layer 130 and the second insulating layer 184.

[0093] In some example embodiments, the contact conductive layer 170L can include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0094] Reference Figure 15 , a mask pattern (not shown) can be formed on the contact conductive layer 170L (see Figure 14 ), and a portion of the contact conductive layer 170L, a portion of the mold layer 130, and a portion of the second insulating layer 184 can be removed using the mask pattern to form the contact layer 170, and a third insulating layer 186 can be formed in the region where the contact conductive layer 170L has been removed.

[0095] In some example embodiments, the third insulating layer 186 can be formed using silicon nitride. Additionally, the sidewalls of the contact layer 170 can be surrounded by the third insulating layer 186, and the bottom surface of the contact layer 170 can cover the upper surface of the channel layer 140 and the upper surface of the gate insulating layer 150 to extend onto the mold layer 130.

[0096] Reference Figure 16 , an etch stop layer 188 can be formed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 can include an opening 188H, and the upper surface of the contact layer 170 can be exposed through the opening 188H.

[0097] Next, the lower electrode 192, the capacitor dielectric layer 194, and the upper electrode 196 can be sequentially formed on the etch stop layer 188.

[0098] By performing the above manufacturing process, the semiconductor device 100 according to the inventive concept can be manufactured.

[0099] Figure 17 is a structural diagram showing a system including a semiconductor device according to some example embodiments.

[0100] Reference Figure 17 , the system 1000 includes a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050.

[0101] System 1000 can be a mobile system or a system that sends or receives information. In some example embodiments, the mobile system can be a portable computer, a network tablet, a mobile phone, a digital music player, or a memory card.

[0102] The controller 1010 is used to control the execution programs in the system 1000 and can include a microprocessor, a digital signal processor, a microcontroller, or similar devices.

[0103] The input / output device 1020 can be used to input or output data of the system 1000. The system 1000 can use the input / output device 1020 to connect to external devices, such as a personal computer or a network, and can exchange data with the external devices. The input / output device 1020 can be, for example, a touch screen, a touchpad, a keyboard, or a display.

[0104] The storage device 1030 can store data for the operation of the controller 1010 or store data processed by the controller 1010. The storage device 1030 can include any one of the semiconductor devices 100, 100A, and 100B according to the above inventive concept.

[0105] The interface 1040 can be a data transmission path between the system 1000 and external devices. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other via the bus 1050.

[0106] When the terms “about” or “substantially” are used in this specification in combination with a numerical value, it is intended that the associated numerical value include manufacturing or operating tolerances around the stated numerical value (e.g., ±10%). Further, when the words “substantially” and “about” are used in combination with a geometric shape, it is intended that no precision of the geometric shape is required, but rather that a tolerance of the shape is within the scope of the present disclosure. Further, whether the numerical value or the shape is modified with “about” or “substantially”, it should be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances around the stated numerical value or shape (e.g., ±10%).

[0107] As described herein, any electronic device and / or part thereof according to any example embodiment may include one or more instances of a processing circuit (such as hardware including logic circuits), may be included in one or more instances of a processing circuit (such as hardware including logic circuits), and / or may be implemented by one or more instances of a processing circuit (such as hardware including logic circuits); a hardware / software combination, such as a processor that executes software; or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., a memory) that stores an instruction program, such as a DRAM device, and a processor (e.g., a CPU), which is configured to execute the instruction program to implement the functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or part thereof according to any example embodiment, and / or any part thereof.

[0108] Although the inventive concept has been specifically shown and described with reference to example embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept defined by the appended claims. Therefore, the example embodiments should be considered in a descriptive sense only and not for purposes of limitation.

[0109] Although the inventive concept has been specifically shown and described with reference to example embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0110] Cross-reference to related applications

[0111] This application claims priority based on Korean Patent Application No. 10-2023-0187514, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A bit line extending in a first horizontal direction on the substrate and comprising a lower conductive layer and an upper conductive layer; a channel layer, in the bit line, penetrating a portion of the bit line and having an inner wall and an outer wall; a gate insulating layer on one side of the inner wall of the channel layer; a word line extending on the gate insulating layer and in a second horizontal direction intersecting the first horizontal direction; as well as a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer, The channel layer includes an oxide semiconductor material containing indium (In), The upper conductive layer includes a conductive material containing In, and The outer wall of the channel layer contacts the upper conductive layer but does not contact the lower conductive layer.

2. The semiconductor device according to claim 1, wherein The channel layer includes InGaZnO x (IGZO) and InZnO x One of the (IZO) The upper conductive layer includes indium tin oxide (ITO) and indium oxide (InO x ), and The lower conductive layer includes metal or metal nitride.

3. The semiconductor device according to claim 1, wherein The upper surface of the upper conductive layer has a concavoconvex shape, The lower surface of the upper conductive layer has a flat shape, and Both the upper surface and the lower surface of the lower conductive layer are flat. 4 . The semiconductor device according to claim 3 , wherein a thickness of the upper conductive layer in a vertical direction is smaller than a thickness of the lower conductive layer in the vertical direction.

5. The semiconductor device according to claim 4, wherein The channel layer has a U-shape penetrating a portion of the upper conductive layer, and A portion of the outer wall of the channel layer contacting the upper conductive layer has a rounded corner.

6. The semiconductor device according to claim 1, wherein The bit line further includes a lower conductive barrier layer on a lower surface of the lower conductive layer and an upper conductive barrier layer on an upper surface of the upper conductive layer, and The outer wall of the channel layer contacts a sidewall of the upper conductive barrier layer and the upper conductive layer, but does not contact the lower conductive layer and the lower conductive barrier layer.

7. The semiconductor device according to claim 6, wherein The bit line includes a groove area and a flat area surrounding the groove area, The semiconductor device further includes a mold layer covering the planar region of the bit line, and The outer wall of the channel layer contacts a sidewall of the mold layer and the recessed region of the bit line. 8 . The semiconductor device according to claim 7 , wherein the recess region of the bit line is formed in the upper conductive barrier layer and the upper conductive layer.

9. A semiconductor device comprising: A bit line extending along a first horizontal direction on the substrate and comprising a central conductive layer and a U-shaped conductive layer; a channel layer, in the bit line, penetrating a portion of the bit line and having a sidewall and a bottom; a gate insulating layer on one side of the sidewall of the channel layer; a word line extending on the gate insulating layer and in a second horizontal direction intersecting the first horizontal direction; as well as a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer, The bottom of the channel layer contacts the U-shaped conductive layer but does not contact the central conductive layer, and The U-shaped conductive layer conforms along the bottom of the channel layer.

10. The semiconductor device according to claim 9, wherein The channel layer includes an oxide semiconductor material containing indium (In), and The U-shaped conductive layer includes a conductive material containing In.

11. The semiconductor device according to claim 10, wherein The channel layer includes InGaZnO x (IGZO) and InZnO x (IZO), and The U-shaped conductive layer includes indium tin oxide (ITO) and indium oxide (InO x ) 12. The semiconductor device according to claim 9, wherein The central conductive layer defines a recessed area, The U-shaped conductive layer contacts the groove region of the central conductive layer, and The U-shaped conductive layer is along an interface between the channel layer and the central conductive layer.

13. The semiconductor device according to claim 9, wherein The bottom of the channel layer has rounded corners, and The U-shaped conductive layer conforms to the rounded shape of the channel layer.

14. The semiconductor device according to claim 13, wherein The bit line further includes a lower conductive barrier layer on a lower surface of the central conductive layer and an upper conductive barrier layer on an upper surface of the central conductive layer, and The uppermost surface of the U-shaped conductive layer contacts the lowermost surface of the upper conductive barrier layer.

15. The semiconductor device according to claim 13, wherein The bit line further includes a lower conductive barrier layer on a lower surface of the central conductive layer and an upper conductive barrier layer on an upper surface of the central conductive layer, and A sidewall of the U-shaped conductive layer contacts a sidewall of the upper conductive barrier layer.

16. A semiconductor device comprising: a bit line extending in a first horizontal direction on the substrate and comprising a first conductive layer containing a metal or a metal nitride and a second conductive layer containing indium (In); a mold layer covering the bit lines on the substrate and defining a mold opening; a channel layer, on an inner wall of the mold opening, having a bottom portion penetrating the bit line and a side wall extending in a vertical direction on the inner wall of the mold opening, and comprising an oxide semiconductor material containing In; a gate insulating layer on the channel layer within the die opening and comprising a high-k dielectric material; a word line within the mold opening and on the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; a contact layer extending on an upper surface of the channel layer and an upper surface of the gate insulating layer; as well as a capacitor structure on the contact layer, The bottom of the channel layer contacts the second conductive layer but does not contact the first conductive layer.

17. The semiconductor device according to claim 16, wherein The first conductive layer includes any one of tungsten (W), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN) and titanium nitride (TiN), The second conductive layer includes indium tin oxide (ITO) and indium oxide (InO x ), and The channel layer includes InGaZnO x (IGZO) and InZnO x One of the (IZO).

18. The semiconductor device according to claim 16, wherein The upper surface and the lower surface of the first conductive layer are flat, The upper surface of the second conductive layer has a concavo-convex shape, and the lower surface of the second conductive layer has a flat shape, and A thickness of the first conductive layer in a vertical direction is greater than a thickness of the second conductive layer in the vertical direction.

19. The semiconductor device according to claim 16, wherein The bottom of the channel layer has rounded corners, and The second conductive layer has a U-shape conforming to the rounded shape of the channel layer.

20. The semiconductor device according to claim 16, wherein The bit line defines a recessed region, and The bottom of the channel layer fills the recessed region of the bit line.

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