Microelectronic devices including contact structures, and related electronic systems and methods

Abstract

The invention relates to microelectronic devices including contact structures, and related electronic systems and methods. A microelectronic device includes a stacked structure including alternating conductive structures and insulating structures arranged in layers, each of the layers including, respectively, a conductive structure and an insulating structure; a memory cell string extending vertically through the stack structure, the memory cell string including a channel material extending vertically through the stack structure; another stack structure vertically overlying the stack structure and including alternating levels of other conductive structures and other insulating structures, the another stack structure including pillars vertically overlying the strings of memory cells, each pillar comprising another channel material in electrical communication with the channel material of the memory cell string; and a conductive contact structure vertically overlying the other stack structure.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is a patent application for invention with the application date of May 17, 2021, the invention name of "Microelectronic Devices Including Contact Structures, and Related Electronic Systems and Methods", and the application number of 202110534322.4.

[0003] Priority claim

[0004] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 877,233, filed on May 18, 2020, "MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS". TECHNICAL FIELD

[0005] In various embodiments, the present disclosure generally relates to the field of microelectronic device design and manufacturing. More specifically, the present disclosure relates to microelectronic devices and apparatuses including self-aligned contact structures having enlarged regions, and to related electronic systems and methods for forming microelectronic devices. BACKGROUND ART

[0006] An ongoing goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices (e.g., non-volatile memory devices (e.g., NAND flash memory devices)). One way to increase the memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings that extend through openings in a stack of conductive structures (e.g., word lines) and dielectric materials at each interface between the vertical memory strings and the conductive structures. Compared to structures with a conventional planar (e.g., two-dimensional) arrangement of transistors, this configuration allows a greater number of switching devices (e.g., transistors) to be positioned per die area (i.e., the length and width of the active surface consumed) by building the array upward (e.g., longitudinally, vertically) on the die.

[0007] A conventional vertical memory array includes an electrical connection between a conductive structure and an access line (e.g., a word line) such that a memory cell in the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such an electrical connection includes forming a so-called - at least one "step" (or "step step") structure at an edge (e.g., a horizontal end) of a conductive structure layer. The step structure includes individual "steps" that provide a contact region for the conductive structure, and a conductive contact structure can be positioned on the contact region to provide an electrical path to the conductive structure.

[0008] As vertical memory array technology has advanced, additional memory density has been provided by forming a stacked vertical memory array that includes additional conductive structure layers and thus additional step structures and / or additional steps in the individual step structures associated therewith. As the number of layers of conductive structures increases, the processing conditions for forming alignment contacts with various components of a microelectronic device become increasingly difficult. Additionally, other techniques for increasing memory density have reduced the spacing between adjacent vertical memory strings. However, reducing the spacing between adjacent vertical memory strings can increase the difficulty of forming individual electrical connections to the vertical memory strings without shorting to adjacent vertical memory strings. SUMMARY OF THE INVENTION

[0009] In some embodiments, a microelectronic device includes a stacked structure that includes alternating conductive and insulating structures arranged in layers, each of the layers individually including a conductive structure and an insulating structure; a memory cell string that extends vertically through the stacked structure, the memory cell string including a channel material that extends vertically through the stacked structure; another stacked structure that vertically overlies the stacked structure and includes alternating layers of other conductive and other insulating structures, the other stacked structure including a pillar that vertically overlies the memory cell string, each pillar including another channel material that is in electrical communication with the channel material of the memory cell string; and a conductive contact structure that vertically overlies the other stacked structure, each conductive contact structure including a conductive contact that at least partially extends into the pillar and a portion that extends outside the pillar and has a larger cross-sectional area than the pillar.

[0010] In other embodiments, a method of forming a microelectronic device includes: forming a first stack structure including alternating layers of an insulating structure and other insulating structures; forming a first pillar including channel material extending through the first stack structure; forming a second stack structure on the first stack structure, the second stack structure including alternating layers of additional insulating structures and sacrificial structures; forming a second pillar through the second stack structure, the second pillar including additional channel material extending vertically through the second pillar and in electrical communication with the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0011] In further embodiments, a microelectronic device includes: a stack structure including layers of alternating conductive and insulating structures; a memory cell string extending through the stack structure, the memory cell string including at least dielectric material and channel material extending vertically through the stack structure; and a conductive contact structure in electrical communication with the channel material of a string of the memory cell string, the conductive contact structure having a larger cross-sectional area than the at least one dielectric material and the channel material of the string.

[0012] In other embodiments, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device structure. The at least one microelectronic device structure includes: a memory cell string extending through alternating layers of an insulating structure and a conductive structure; a pillar within the stack structure including alternating layers of an insulating structure and a conductive structure, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a larger lateral dimension than the memory cell string. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1A to 1N is a simplified cross-sectional view showing a method of forming a microelectronic device structure according to an embodiment of the present disclosure ( Figure 1A , Figure 1C , Figure 1D , Figure 1F , Figure 1G , Figure 1I , Figure 1K , Figure 1L , Figure 1M and Figure 1N ) and a top view ( Figure 1B , Figure 1E , Figure 1H andFigure 1J )

[0014] Figure 1O and Figure 1P is a simplified cross-sectional view of a memory cell according to an embodiment of the present disclosure;

[0015] Figure 2 is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0016] Figure 3 is a block diagram of an electronic system according to an embodiment of the present disclosure; and

[0017] Figure 4 is a processor-based system according to an embodiment of the present disclosure. Detailed Description

[0018] The illustrations included herein are not meant to be actual views of any particular system, microelectronic architecture, microelectronic device, or integrated circuit thereof, but are merely idealized representations for describing embodiments herein. Common elements and features between the figures may retain the same numerical markings, except that for ease of the following description, the reference numerals start from the number of the figure that first introduces or most fully describes the element.

[0019] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a thorough description of the embodiments described herein. However, one of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without using these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques employed in the semiconductor industry. Additionally, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device (e.g., a DRAM memory device)), apparatus, or electronic system, or a complete microelectronic device, apparatus, or electronic system that includes a self-aligned contact structure that has a relatively large lateral dimension (e.g., area, cross-sectional area) relative to a vertical memory string or pillar associated with the contact structure. The structures described below do not form a complete microelectronic device, apparatus, or electronic system. Only those process actions and structures necessary for understanding the embodiments described herein are detailed below. Additional actions for forming a complete microelectronic device, apparatus, or electronic system from these structures may be performed by conventional techniques.

[0020] The materials described herein can be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in-situ. Those of ordinary skill in the art can select the techniques for depositing or growing the materials according to the specific materials to be formed. The removal of materials can be achieved by any suitable technique, including but not limited to etching, polishing planarization (e.g., chemical mechanical planarization), or other known methods, unless otherwise indicated by the context.

[0021] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are with respect to the major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) on or in which one or more structures and / or features are formed and need not be defined by the earth's gravitational field. The “lateral” or “horizontal” direction is a direction substantially parallel to the major plane of the substrate, while the “longitudinal” or “vertical” direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by the surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0022] As used herein, the term “substantially” with respect to a given parameter, property, or condition means and includes the degree of meeting the given parameter, property, or condition with a degree of variation (such as within an acceptable tolerance) that would be understood by those of ordinary skill in the art. For example, depending on the specific parameter, property, or condition being substantially met, the parameter, property, or condition can be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0023] As used herein, “about” or “approximately” with respect to a numerical value of a specific parameter includes the numerical value and the degree of variance of the numerical value that would be understood by those of ordinary skill in the art within the acceptable tolerance of the specific parameter. For example, “about” or “approximately” with respect to a numerical value can include additional numerical values within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0024] As used herein, spatial relative terms, such as "under", "below", "lower", "bottom", "on", "upper", "top", "front", "rear", "left", "right", etc., may be used for convenience to describe the relationship of one element or feature to another element or feature as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as "under" or "below" or "beneath" or at the "bottom" of another element or feature will be oriented "above" or at the "top" of the other element or feature. Thus, the term "under" can include both above and below orientations, depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatial relative descriptors used herein are to be interpreted accordingly.

[0025] As used herein, the term "memory device" means and includes microelectronic devices that exhibit memory functionality, but need not be limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memories in the form of DRAM, NAND, etc., but also, by way of example only, application specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices that combine logic and memory, or graphics processing units (GPUs) incorporating memory.

[0026] According to embodiments described herein, a microelectronic device includes a stacked structure that includes alternating conductive and insulating structures arranged in layers, each of the layers including a conductive structure and an insulating structure. Memory cell strings may extend through the stacked structure and may include, for example, channel material that extends through the stacked structure. Memory cells of the memory cell strings may be located at intersections between the conductive structures and the channel material, with adjacent memory cells of each string being separated from one another by one of the insulating structures. In some embodiments, the strings may include strings that are laterally aligned with one another and other strings that are at least laterally offset from one another. In some embodiments, the strings may be arranged in a braided pattern. Another stacked structure may be vertically disposed over the stacked structure and the memory cell strings and may include contact structures for providing electrical connectivity between conductive lines (e.g., access lines) and respective strings of the memory cells. Other stacked structures may include pillars that include channel material that vertically overlies each of the memory cell strings of the stacked structure. In some embodiments, the channel material of the pillars is substantially aligned with the channel material of the memory cell strings. The contact structures may include a lateral dimension (e.g., area, cross-sectional area) that is greater than the lateral dimension of the pillars and may facilitate improved formation (e.g., alignment) of the contact structures to the memory cell strings. The increased lateral dimension may assist in forming an electrical connection to the contact structures and thus to the associated memory cell strings.

[0027] A microelectronic device may be formed by forming a first pillar that includes channel material that extends through a stacked structure and forming another stacked structure over the stacked structure. The stacked structure may include layers that include alternating insulating structures and other insulating structures. The other stacked structure may include layers that include alternating insulating structures and sacrificial structures. The sacrificial structures may be configured to be replaced with a conductive material to form conductive structures. In some embodiments, the sacrificial structures include polysilicon. A second pillar that includes channel material may be formed to extend through the other stacked structure and over and laterally aligned with the first pillar. The channel material of the second pillar may be in electrical communication with the channel material of the first pillar. In some embodiments, the channel material extending through the first pillar and the second pillar is substantially continuous. The second pillar may be at least partially filled with an insulating material. A sacrificial material may be formed over the insulating material and may fill the remainder of the second pillar. After forming the sacrificial material, at least a portion (e.g., upper portion) of the sacrificial material may be removed and replaced with a conductive material. In some embodiments, the sacrificial material is directly converted to the conductive material. In other embodiments, the sacrificial material is removed, for example, by etching, and the conductive material is formed over the remaining portion of the sacrificial material. The conductive material may form a seed material over which additional conductive material may be grown to increase the size (e.g., lateral dimension, such as cross-sectional area) of the conductive material and form a self-aligned conductive contact having a larger size than the first pillar or the second pillar.

[0028] After forming the conductive contacts, portions of another stacked structure between adjacent pillars may be removed to form select gate structure trenches. Additionally, portions of other stacked structures located between adjacent second pillar groups may be removed to form additional trenches. After forming the select gate structure trenches and the additional trenches, the sacrificial structures may be replaced (e.g., converted or removed and replaced) with a conductive material passing through the select gate structure trenches and the additional trenches to form a conductive structure. For example, the sacrificial structures may be converted to a conductive material. In other embodiments, the sacrificial structures are removed, e.g., by etching, and a conductive material is formed at a location corresponding to the sacrificial structures to form a conductive structure. After forming the conductive structure, the select gate structure trenches and the additional trenches may be filled with a dielectric material. Replacement gate trenches may be formed through another stacked structure and the stacked structure. Other insulating structures of the stacked structure may be removed, e.g., by wet etching. After removing the other insulating structures, a conductive structure may be formed at a location corresponding to the other insulating structures to form a memory cell string, with each memory cell located at an intersection between the conductive structure and the channel material. The conductive contact structure may be electrically connected to a conductive line (e.g., access line, bit line, digit line) to electrically couple the memory cell string to the conductive line.

[0029] The increased area of the conductive contacts may facilitate forming an electrical connection between the conductive lines and the conductive contacts without having to reposition or shift the conductive contacts relative to the memory cell string. Additionally, forming the conductive contacts before replacing other insulating structures with a conductive structure may help improve the alignment between the conductive contacts and the second pillars and the associated memory cell string compared to conventional microelectronic devices where the conductive contacts are formed after replacing other insulating structures with a conductive structure. For example, replacing other insulating structures with a conductive structure may undesirably cause bending (also referred to as "block bending") of the microelectronic device (e.g., the stacked structure), which increases the difficulty of forming conductive contacts to the memory cell string. However, forming the conductive contacts before replacing other insulating structures with a conductive structure and forming the conductive contacts to have an increased size may help improve the alignment between the conductive contacts and the memory cell string.

[0030] Figures 1A to 1N A method of forming a microelectronic device structure according to an embodiment of the present disclosure is shown. Figure 1A is a simplified cross-sectional view of a microelectronic device structure 100 according to an embodiment of the present disclosure. Figure 1B is Figure 1A a top view of the microelectronic device structure 100. Figure 1A The cross-section of is along Figure 1Btaken along the sectional line A-A. The microelectronic device structure 100 may include a stacked structure 101 that includes insulating structures 104 and other insulating structures 106 in a vertically (e.g., in the Z direction) alternating sequence arranged in layers 102. Each of the layers 102 may individually include a layer of insulating structures 104 directly vertically adjacent to a layer of other insulating structures 106. The insulating structures 104 of the stacked structure 101 may also be referred to herein as "insulating materials", and the other insulating structures 106 of the stacked structure 101 may also be referred to herein as "other insulating materials".

[0031] In some embodiments, the number (e.g., quantity) of layers 102 of the stacked structure 101 may be in the range of 32 to 256 layers 102. In some embodiments, the stacked structure 101 includes 128 layers 102. However, the present disclosure is not limited thereto, and the stacked structure 101 may include a different number of layers 102. Additionally, in some embodiments, the stacked structure 101 includes a first deck structure of layers 102 that vertically overlies a source structure 107 and includes insulating structures 104 and other insulating structures 106, and a second deck structure on the first deck structure, the second deck structure including layers 102 of insulating structures 104 and other insulating structures 106. For example, the stacked structure 101 may include a double-deck 3D NAND device (e.g., a 3D NAND flash memory device).

[0032] The layers of the insulating structures 104 may be formed of and include at least one dielectric material, such as one or more oxide materials (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), and aluminum oxide (A12O3)). In some embodiments, the insulating structures 104 are formed of and include silicon dioxide.

[0033] The layers of the other insulating structures 106 may be formed of and include an insulating material different from the insulating structures 104 and exhibiting an etch selectivity relative to the insulating structures. In some embodiments, the other insulating structures 106 are formed of and include a nitride material (e.g., silicon nitride (Si3N4)) or a oxynitride material (e.g., silicon oxynitride). In some embodiments, the other insulating structures 106 include silicon nitride.

[0034] The stacked structure 101 may be formed on a source structure 107 (e.g., a source plate). The source structure 107 may be formed of a semiconductor material doped with, for example, a P-type conductive material (e.g., polysilicon doped with at least one P-type dopant (e.g., boron ions)) or an N-type conductive material (e.g., polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorus ions, antimony ions)) and include the semiconductor material. Although the Figure 1A stacked structure 101 has been described and illustrated as including directly on (e.g., on top of) the source structure 107, the present disclosure is not limited thereto. In other embodiments, the stacked structure 101 covers a deck structure that includes an additional layer 102 of the insulating structure 104 and other insulating structures 106 separated from the stacked structure 101 by at least one dielectric material.

[0035] The dielectric material 108 may be located above the topmost layer of the layer 102. The dielectric material 108 may be formed of and include an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, the dielectric material 108 includes the same material composition as the insulating structure 104. In some embodiments, the dielectric material 108 includes silicon dioxide.

[0036] The material pillars 110 may extend vertically (e.g., in the Z direction) through the stacked structure 101. As will be described herein, the material of the pillars 110 may form memory cells (e.g., NAND memory cell strings). Each of the pillars 110 may individually include an insulating material 112, a dielectric material 114 horizontally adjacent to the insulating material 112, a channel material 116 horizontally adjacent to the insulating material 112, a tunnel dielectric material (also referred to as a "tunneling dielectric material") 118 horizontally adjacent to the channel material 116, a memory material 120 horizontally adjacent to the tunnel dielectric material 118, and a dielectric barrier material (also referred to as a "charge blocking material") 122 horizontally adjacent to the memory material 120. The dielectric barrier material 122 may be horizontally adjacent to one of the levels of the other insulating structures 106 in the layer 102 of the stacked structure 101. The dielectric material 114 may be horizontally inserted between the insulating material 112 and the channel material 116; the channel material 116 may be horizontally inserted between the dielectric material 114 and the tunnel dielectric material 118; the tunnel dielectric material 118 may be horizontally inserted between the channel material 116 and the memory material 120; the memory material 120 may be horizontally inserted between the tunnel dielectric material 118 and the dielectric barrier material 122; and the dielectric barrier material 122 may be horizontally inserted between the memory material 120 and one of the levels of another insulating structure 106.

[0037] The insulating material 112 can be formed of and include an electrically insulating material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride), dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carboxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 112 includes silicon dioxide.

[0038] The dielectric material 114 can be formed of and include one or more of the materials described above with reference to the insulating material 112. In some embodiments, the dielectric material 114 includes the same material composition as the insulating material 112. In some embodiments, the dielectric material 114 includes silicon dioxide.

[0039] The channel material 116 can be formed of and include one or more of a semiconductor material (at least one elemental semiconductor material, such as polysilicon; at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials) and an oxide semiconductor material. In some embodiments, the channel material 116 includes amorphous silicon or polysilicon. In some embodiments, the channel material 116 includes a doped semiconductor material.

[0040] The tunnel dielectric material 118 can be formed of and include a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions, such as charge transfer caused by hot carrier injection or by Fowler-Nordheim tunneling. As a non-limiting example, the tunnel dielectric material 118 can be formed of and include one or more of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 118 includes silicon dioxide. In other embodiments, the tunnel dielectric material 118 includes silicon oxynitride.

[0041] The memory material 120 may include a charge trapping material or a conductive material. The memory material 120 may be formed of one or more of silicon nitride, silicon oxynitride, polysilicon (doped polysilicon), conductive materials (tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and their alloys, or metal silicides (such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconductor materials, polycrystalline or amorphous semiconductor materials (including at least one elemental semiconductor element or at least one compound semiconductor material), conductive nanoparticles (such as ruthenium nanoparticles), and metal dots and include the one or more thereof. In some embodiments, the memory material 120 includes silicon nitride.

[0042] The dielectric barrier material 122 may be formed of and include a dielectric material, such as one or more of oxides (such as silicon dioxide), nitrides (silicon nitride), and oxynitrides (silicon oxynitride), or another material. In some embodiments, the dielectric barrier material 122 includes silicon oxynitride.

[0043] In some embodiments, the tunnel dielectric material 118, the memory material 120, and the dielectric barrier material 122 together may include a structure configured to trap charge, such as an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunnel dielectric material 118 includes silicon dioxide, the memory material 120 includes silicon nitride, and the dielectric barrier material 122 includes silicon dioxide.

[0044] Reference Figure 1B , the pillars 110 may include some pillars 110 that are aligned with each other (e.g., in the Y direction) and pillars 110 that are offset from each other (e.g., in the Y direction). Thus, the pillars 110 may be arranged in a so-called woven pattern (e.g., a hexagonal close-packed arrangement), which may facilitate an increased density of the pillars 110 (and the resulting memory cell strings) in the stacked structure 101.

[0045] Reference Figure 1C , after forming the pillars 110, a portion of the pillars 110 may be removed to recess the pillars 110 relative to the uppermost surface of the dielectric material 108. In some embodiments, the channel material 124 may be formed in the recess and be in electrical communication with the channel material 116. The channel material 124 may include one or more of the materials described above with reference to the channel material 116. In some embodiments, the channel material 124 includes the same material composition as the channel material 116. Since the channel material 124 may include the same material composition as the channel material 116, as used herein, the channel material 116 may refer to both the channel material 116 and the channel material 124 described with reference to Figure 1A as described.

[0046] Continuing to refer to Figure 1C, after forming the channel material 124, another dielectric material 126 can be formed on the insulating material 112, on the channel material 124, and within the remaining portion of the groove adjacent to the channel material. The other dielectric material 126 can include one or more of the materials described above with reference to the dielectric material 114. In some embodiments, the other dielectric material 126 includes silicon dioxide. Since the other dielectric material 126 can include the same material composition as the dielectric material 114, as used herein, the dielectric material 114 can be used to refer to both the dielectric material 114 and the other dielectric material 126.

[0047] Reference Figure 1D , after forming the additional channel material 124 ( Figure 1C ) and the other dielectric material 126 ( Figure 1C ), another stacked structure 105 can be formed on the stacked structure 101. The other stacked structure 105 can include alternating layers of an insulating structure 104 and a sacrificial structure 128 formed on an etch stop material 125. Figure 1E is Figure 1D a simplified top view of the microelectronic device structure 100.

[0048] The etch stop material 125 can be formed of and include a material (e.g.,) that exhibits an etch selectivity with respect to the insulating structure 104 and the sacrificial structure 128. In some embodiments, the etch stop material 125 includes a carbon-containing material (e.g., silicon carbonitride (SiCN)).

[0049] The sacrificial structure 128 can be formed of and include a sacrificial material that has an etch selectivity different from that of the insulating structure 104. The sacrificial material of the sacrificial structure 128 can be selectively etched, for example, relative to the electrical insulating material of the insulating structure during mutual exposure to an etchant. As a non-limiting example, the sacrificial structure 128 can be formed of and include silicon, doped silicon, polysilicon, doped polysilicon, or silicon nitride. In embodiments where the sacrificial structure 128 is doped, the dopant can include at least one N-type dopant (e.g., one or more of phosphorus (P), arsenic (Ar), antimony (Sb), and bismuth (Bi)), at least one P-type dopant (e.g., one or more of boron (B), aluminum (A1), and gallium (Ga)), carbon (C), fluorine (F), chlorine (C1), bromine (Br), hydrogen (H), deuterium ( 2 H), helium (He), neon (Ne), and argon (Ar). In some embodiments, the sacrificial structure 128 includes polysilicon.

[0050] After forming another stacked structure 105, an opening may be formed through the another stacked structure 105 to expose a portion of the pillar 110 of the stacked structure 101. After forming the opening, a liner material 130 may be formed on the surface (e.g., sidewalls) of the opening. In some embodiments, after forming the liner material 130, a laterally extending portion of the liner material 130 may be removed, for example, by dry etching (e.g., reactive ion etching (RIE)).

[0051] The liner material 130 may be formed of and include, for example, an insulating material, such as one or more of the materials described above with reference to the dielectric material 114. In some embodiments, the liner material 130 includes silicon dioxide.

[0052] After forming the liner material 130, a channel material 132 may be formed on the side surfaces of the liner material 130 and in contact with the channel material 116. The channel material 132 may include one or more of the same materials described above with reference to the channel material 116. In some embodiments, the channel material 132 includes the same material composition as the channel material 116. In some embodiments, the channel material 132 may be continuous with the channel material 116. In some such embodiments, the channel material 132 in the stacked structure 105 may be substantially laterally aligned (e.g., in the X direction, in the Y direction, or both) with the channel material 116 within the pillar 110 of the stacked structure 101. Since the channel material 132 may include the same material composition as the channel material 116, as used herein, the channel material 116 refers to both the channel material 116 and the channel material 132.

[0053] After forming the channel material 132, a portion of the opening may be filled with an insulating material 134. The insulating material 134 may be formed of and include one or more of the materials described above with reference to the dielectric material 114. In some embodiments, the insulating material 134 includes the same material composition as the dielectric material 114. In some embodiments, the insulating material 134 includes silicon dioxide.

[0054] Continuing reference Figure 1D , a sacrificial material 136 may be formed on the insulating material 134. The sacrificial material 136 may include one or more of the materials described above with reference to the sacrificial structure 128. In some embodiments, the sacrificial material 136 includes the same material composition as the sacrificial structure 128. In some embodiments, the sacrificial material 136 includes polysilicon.

[0055] The liner material 130, the channel material 132, the insulating material 134, and the sacrificial material 136 within the another stacked structure 105 may include a pillar 135. The pillar 135 may be substantially laterally aligned (e.g., in the X direction and in the Y direction) with the pillar 110 of the stacked structure 101.

[0056] The microelectronic device structure 100 may be exposed to a chemical mechanical planarization (CMP) process to remove portions of the liner material 130, the channel material 132, the insulating material 134, and the sacrificial material 136 from the uppermost surface of the insulating structure 104.

[0057] Reference Figure 1F , a portion of the sacrificial material 136 may be replaced with a conductive material 138 to form a contact structure (also referred to herein as a "conductive contact structure" or "conductive contact structure") 140 that includes the conductive material 138. In some embodiments, a portion of the sacrificial material 136 may be removed (e.g., by exposing a portion of the sacrificial material 136 to one or more etchants, such as a dry etchant) to selectively remove the sacrificial material 136 and recess the sacrificial material 136 relative to the uppermost insulating structure 104.

[0058] In other embodiments, a portion of the sacrificial material 136 is converted into the conductive material 138. As a non-limiting example, the sacrificial material 136 (e.g., a silicon material, a polysilicon material) may be treated with one or more chemicals that promote the conversion of the sacrificial material 136 to tungsten (e.g., beta-phase tungsten, alpha-phase tungsten). As a non-limiting example, if the sacrificial material 136 includes a doped silicon material, such as doped polysilicon, the sacrificial material 136 may be treated with tungsten hexafluoride (WF6) to form the conductive material 138. In some such embodiments, the silicon (Si) of the sacrificial material 136 may react with WF6 to produce tungsten (W) and silicon tetrafluoride (SiF4). The resulting SiF4 is removed as a gas. The resulting W is retained with any dopants of the sacrificial material 136 to form the conductive material 138. The sacrificial material 136 may be treated with WF6 using conventional CVD equipment at a temperature in the range of about 200°C to about 500°C.

[0059] In some embodiments, the conductive material 138 includes tungsten. In some embodiments, the conductive material 138 includes β-phase tungsten. β-phase tungsten has a metastable A15 cubic structure. The grains of β-phase tungsten can exhibit a generally columnar shape. The tungsten contained within the conductive material 138 can exist only in the β-phase, or can exist in the β-phase and the α-phase. If present, α-phase tungsten has a metastable body-centered cubic structure. The grains of α-phase tungsten can exhibit a generally equidistant shape. If the conductive material 138 contains β-phase tungsten and α-phase tungsten, the amount of β-phase tungsten contained within the conductive material 138 can be different from the amount of α-phase tungsten contained within the conductive material 138, or can be substantially the same as the amount of α-phase tungsten contained within the conductive material 138. In some embodiments, the amount of β-phase tungsten contained within the conductive material 138 is greater than the amount of α-phase tungsten contained within the conductive material 138. For example, at least most (e.g., greater than 50%, such as greater than or equal to about 60%, greater than or equal to about 70%, greater than or equal to about 80%, greater than or equal to about 90%, greater than or equal to about 95% or greater than or equal to about 99%) of the tungsten contained within the conductive material 138 can exist in the β-phase. In embodiments where the sacrificial material 136 includes one or more dopants, the conductive material 138 can contain tungsten and one or more dopants.

[0060] See Figure 1G and Figure 1H , the conductive material 138 within the strut 135 can be used as a seed material to form additional conductive material 139 and increase the size of the contact structure 140. In some embodiments, the additional conductive material 139 grows asymmetrically. In some such embodiments, the lateral dimensions (e.g., in the X direction, in the Y direction, or both) of the additional conductive material 139 can grow faster than the vertical dimension (e.g., in the Z direction). Growing the additional conductive material 139 can form a conductive material having a larger lateral dimension (in the X direction, Y direction, or both) than the strut 135. Accordingly, the contact area of the contact structure 140 can be increased relative to the size of the strut 135. In some embodiments, the additional conductive material 139 extends vertically above the strut 135. In other words, the additional conductive material 139 (and the associated contact structure 140) extends vertically above the topmost layer of the insulating structure 104.

[0061] The size D (e.g., diameter) of the contact structure can be in the range of about 100 nm to about 150 nm, such as about 100 nm to about 110 nm, about 110 nm to about 120 nm, about 120 nm to about 130 nm, or about 130 nm to about 150 nm. In some embodiments, the size is about 100 nm. In other embodiments, the size is greater than about 100 nm, such as greater than about 120 nm. However, the present disclosure is not limited thereto, and the size D can be different from the sizes described.

[0062] The additional conductive material 139 may include the same material composition as the conductive material 138. In some embodiments, the additional conductive material 139 includes tungsten.

[0063] In some embodiments, the conductive material 138 is exposed to one or more of CVD, ALD, PVD, PECVD, and LPCVD to grow the additional conductive material 139. The additional conductive material 139 may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0064] The additional conductive material 139 may be grown by exposing the conductive material 138 to one or more of tungsten hexafluoride (WF6), disilane (Si2H6), tungsten hexacarbonyl (W(CO6)), bis(tert-butylimino)bis(tert-butylamino)tungsten ((C4H9NH2)W(C4H9N)2), bis(tert-butylimino)bis(dimethylamino)tungsten(VI) (((CH3)3CN)2W(N(CH3)2)2), bis(cyclopentadienyl)tungsten(IV) dihydride (C 10 H 12 W), or another tungsten precursor. In some embodiments, the additional conductive material 139 is formed by sequentially exposing the conductive material 138 to WF6 and Si2H6.

[0065] Referring to Figure 1I , after growing the additional conductive material 139, a select gate structure slot (e.g., slit) 142 and an additional slot (e.g., slit) 144 may be formed through another stack structure 105. Figure 1J is Figure 1I a top view of the microelectronic device structure 100. Figure 1I The cross-section of Figure 1J is taken along the section line I-I of

[0066] Referring to Figure 1I and Figure 1J , a select gate structure slot 142 and an additional slot 144 may be formed through another stack structure 105, and a portion of the etch stop material 125 is exposed. The select gate structure slot 142 and the additional slot 144 may be formed by selectively removing the insulating structure 104 and the sacrificial structure 128, for example, by exposing the microelectronic device structure 100 to one or more etchants, while substantially not removing the conductive material 138 of the contact structure 140.

[0067] The select gate structure slot 142 can be formed between adjacent (e.g., in the X-direction and the Y-direction) contact structures 140. The select gate structure slot 142 can extend in the X-direction along the length of the microelectronic device structure 100. Refer to Figure 1J , in some embodiments, approximately half of each of the contact structures 140 can cover the select gate structure slot 142, and approximately half of each of the contact structures 140 can cover other portions of the microelectronic device structure 100 (e.g., the insulating structure 104). In other words, approximately half of each of the contact structures 140 can be laterally aligned (e.g., in the X-direction, in the Y-direction, or in both) with the select gate structure slot 142, and approximately the other half of each of the contact structures 140 can be misaligned with the select gate structure slot 142. In some such embodiments, forming the select gate structure slot 142 can include forming the select gate structure slot 142 in the X-direction and in the Y-direction between the contact structure 140 and the associated pillar 135 ( Figure 1I ) and the pillar 110 ( Figure 1I ).

[0068] The width W1 of the select gate structure slot 142 can be in the range of from about 30 nm to about 150 nm, such as from about 30 nm to about 50 nm, from about 50 nm to about 75 nm, from about 75 nm to about 100 nm, or from about 100 nm to about 150 nm. In some embodiments, the width W1 is about 100 nm. In other embodiments, the width W1 is greater than about 100 nm. However, the present disclosure is not limited thereto, and the width W1 can be different from the described widths.

[0069] Continuing to refer to Figure 1I and Figure 1J , additional slots 144 can be formed between adjacent select gate structure slots 142 (e.g., in the Y-direction) and between adjacent groups of pillars 135 ( Figure 1I ). For example, the additional slots 144 can divide the microelectronic device structure 100 into blocks 143, each block 143 including a first group of pillars 135 and contact structures 140.

[0070] The width W2 of the additional slots 144 can be in the range of from about 100 nm to about 400 nm, such as from about 100 nm to about 200 nm, from about 200 nm to about 300 nm, or from about 300 nm to about 400 nm. In some embodiments, the width W2 of the additional slots 144 can be greater than the width W1 of the select gate structure slot 142. In some embodiments, the width W2 is from about 200 nm to about 300 nm. However, the present disclosure is not limited thereto, and the width W2 of the additional slots 144 can be different from the described widths.

[0071] Refer to Figure 1K, by selecting the gate structure slot 142 and the additional slot 144, the sacrificial structure 128 ( Figure 1I ) can be at least partially replaced by the conductive structure 146. As described above with reference to the removal of the sacrificial material 136, the sacrificial structure 128 can be at least partially removed. For example, the sacrificial structure 128 can be removed by exposing the sacrificial structure 128 to one or more etchants (e.g., dry etchants) to selectively remove the sacrificial material relative to the insulating structure 104 and recess the sacrificial structure 128.

[0072] In other embodiments, the sacrificial structure 128 is at least partially converted to a conductive material to form the conductive structure 146. As a non-limiting example, the sacrificial structure 128 can be treated with one or more chemicals that promote the conversion of the sacrificial structure 128 (e.g., silicon material, polysilicon material) into tungsten (e.g., beta-phase tungsten, alpha-phase tungsten), as described above with reference to the conversion of the sacrificial material 136 to the conductive material 138. As a non-limiting example, if the sacrificial structure 128 includes doped silicon material, such as doped polysilicon, then the sacrificial structure 128 can be treated with tungsten hexafluoride (WF6) to form the conductive structure 146. In some such embodiments, the silicon (Si) of the sacrificial structure 128 can react with WF6 to produce tungsten (W) and silicon tetrafluoride (SiF4). The resulting SiF4 is removed as a gas. The resulting W retains any dopants of the sacrificial structure 128 to form the conductive structure 146. The sacrificial structure 128 can be treated with WF6 at a temperature in the range of about 200°C to about 500°C using conventional CVD equipment, for example.

[0073] In some embodiments, the conductive structure 146 is formed in substantially the same manner as the conductive material 138 of the contact structure 140.

[0074] In some embodiments, the conductive structure 146 includes tungsten. In some embodiments, the conductive structure 146 includes the same material composition as the contact structure 140. In some embodiments, for example, in the case where the sacrificial structure 128 includes polysilicon, forming the conductive structure 146 can include converting the polysilicon of the sacrificial structure 128 into a conductive structure 146 including tungsten.

[0075] The conductive structure 146 can include a so-called select gate structure (e.g., a select drain structure (SDS)). As will be described herein, the conductive structure 146 can be used to select memory cells of a particular memory cell string. Although Figure 1KFour conductive structures 146 are shown, but the present disclosure is not limited thereto. The microelectronic device structure 100 may include any number of conductive structures 146, such as fewer than four conductive structures 146 (e.g., one conductive structure 146, two conductive structures 146, three conductive structures 146) or more than four conductive structures 146 (e.g., five conductive structures 146, six conductive structures 146, seven conductive structures 146, eight or more conductive structures 146).

[0076] Reference Figure 1L , after forming the conductive structures 146 by way of the select gate structure slots 142 and the additional slots 144, the select gate structure slots 142 and the additional slots 144 may be filled with a dielectric material 148. In some embodiments, the dielectric material 148 is formed on the topmost insulating structure 104. The dielectric material 148 may cover and substantially surround the contact structure 140. In some embodiments, the dielectric material 148 extends into and through another stack structure 105. For example, the dielectric material 148 may be located between adjacent conductive contact structures 140 (at positions corresponding to the positions of the select gate structure slots 142 ( Figure 1I , Figure 1J ).

[0077] The dielectric material 148 may be formed of and include an electrically insulating material, such as one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, the dielectric material 148 includes silicon dioxide.

[0078] Reference Figure 1M , after forming the dielectric material 148, replacement gate slots 150 may be formed at positions corresponding to the additional slots 144. The replacement gate slots 150 may extend through another stack structure 105 and the stack structure 101. In some embodiments, the replacement gate slots 150 expose a portion of the source structure 107.

[0079] After forming the replacement gate slots 150, other insulating structures 106 of the stack structure 101 may be removed through the replacement gate slots 150 as part of a so-called "replacement gate" or "post-gate" process. As a non-limiting example, the other insulating structures 106 may be removed by exposing the other insulating structures 106 to a wet etchant including one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another material. In some embodiments, the other insulating structures 106 are removed by exposing the other insulating structures 106 to a so-called "wet nitride strip" including a wet etchant containing phosphoric acid.

[0080] Reference Figure 1N , after removing the other insulating structures 106 ( Figure 1L)Subsequently, a conductive structure 152 can be formed between adjacent insulating structures 104 at positions corresponding to the positions of other insulating structures 106 to form a microelectronic device 100 including a stacked structure 101, the stacked structure including layers 156 of alternating levels of insulating structures 104 and conductive structures 152.

[0081] The conductive structure 152 can be formed of and include a conductive material, such as at least one conductive material, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metal-containing materials (such as metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ) ruthenium oxide (RuO x ), a material including at least one of the above, its alloy, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, other materials exhibiting conductivity, or a combination thereof. In some embodiments, the conductive structure 152 includes tungsten. In some embodiments, the conductive structure 152 includes a material composition different from that of the contact structure 140 and the conductive structure 146.

[0082] In some embodiments, the conductive structure 152 may include a conductive liner material surrounding the conductive structure 152, such as between the conductive structure 152 and the insulating structure 104. The conductive liner material may include, for example, a seed material that can form the conductive structure 152. The conductive liner material can be formed of and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material includes titanium nitride.

[0083] After forming the conductive structure 152, the replacement gate trench 150 can be filled with a dielectric material 158. The dielectric material 158 can extend through another stacked structure 105 and the stacked structure 101. Additionally, the dielectric material 158 can be located between adjacent blocks 143 ( Figure 1J ).

[0084] The dielectric material 158 can be formed of and include one or more of the materials described above with reference to the dielectric material 148. For example, the dielectric material 158 can be formed of and include one or more of phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and silicon dioxide. In some embodiments, the dielectric material 158 includes the same material composition as the dielectric material 148. In some embodiments, the dielectric material 158 includes silicon dioxide.

[0085] The formation of conductive structure 152 can form a string 160 of memory cells 162 located at the intersection of channel material 116 and conductive structure 152. Vertically adjacent memory cells 162 of string 160 can be separated from each other by one of the levels of insulating structure 104.

[0086] Figure 10 is Figure 1N A simplified enlarged view of the box O of FIG. Figure 1A One of the memory cells 162. Reference Figure 1O and Figure 1A , each memory cell 162 may include an insulating material 112, a dielectric material 114 horizontally adjacent to the insulating material 112, a channel material 116 horizontally adjacent to the insulating material 112, a tunnel dielectric material 118 horizontally adjacent to the channel material 116, a memory material 120 horizontally adjacent to the tunnel dielectric material 118, and a dielectric barrier material 122 horizontally adjacent to the memory material 120. The dielectric barrier material 122 may be horizontally adjacent to one of the levels of the conductive structure 152. The channel material 116 may be horizontally inserted between the insulating material 112 and the tunnel dielectric material 118; the tunnel dielectric material 118 may be horizontally inserted between the channel material 116 and the memory material 120; the memory material 120 may be horizontally inserted between the tunnel dielectric material 118 and the dielectric barrier material 122; and the dielectric barrier material 122 may be horizontally inserted between the memory material 120 and the level of the conductive structure 152. Conductive liner material 153 (not shown for clarity) Figure 1N ) may be located between the conductive structure 152 and the insulating structure 104. As described above, the conductive structure 152 may include one or more of a metal (eg, titanium, tantalum), a metal nitride (eg, tungsten nitride, titanium nitride, tantalum nitride).

[0087] After forming the dielectric material 158, the microelectronic device structure 100 can be completed by, for example, forming a conductive line (e.g., an access line, such as a bit line or a digit line) in electrical communication with the contact structure 140. In some embodiments, the conductive line is formed directly on the contact structure 140. Because the contact structure 140 includes the additional conductive material 139 and has an area greater than the area of ​​the pillar 135, the contact structure 140 can facilitate the formation of a conductive line aligned with the contact structure 140 and the string 160 of the memory cell 162 located directly above the pillar 135. Forming the contact structure 140 by growing the additional conductive material 139 from the conductive material 138 can form a self-aligned contact aligned with the memory string 160. The contact structure 140 can be formed without masking materials and photolithography techniques to align the contact structure 140 with the pillar 135 or with the string 160.

[0088] In addition, when forming the replacement gate trench 150 ( Figure 1M ) and before using the conductive structure 152 (Figure 1N ) Replacing the insulating structure 104( Figure 1L ) Forming the contact structure 140 previously can facilitate improved alignment between the contact structure 140 and the string 160 of memory cells 162. By comparison, during the conventional fabrication of a microelectronic device structure, a conductive structure (e.g., conductive structure 152) may be formed before forming a contact structure (e.g., contact structure 140). However, the formation of the conductive structure may induce stress in the stack structure 101 and another stack structure 105, resulting in so-called "block bending". Block bending may cause the upper part of the stack structure to be laterally offset from the lower part of the stack structure, thereby increasing the difficulty of contact alignment for forming contacts with the memory cell string and the access line.

[0089] Although Figure 1N and Figure 1O the memory cells 162 have been described and shown as including various materials, the present disclosure is not limited thereto. Figure 1P is a simplified enlarged view of a memory cell 170 according to an embodiment of the present disclosure. The memory cell 170 may replace Figure 1N one or more of the memory cells 162. Referring to Figure 1P , the memory cell 170 may include the insulating material 112 and the channel material 116 as described above with reference to the memory cell 162. The memory cell 170 may further include a first dielectric material (e.g., tunneling dielectric material) 172 horizontally adjacent to the channel material 116, a second dielectric material (e.g., charge trapping material) 174 horizontally adjacent to the first dielectric material 172, and a third dielectric material (e.g., charge blocking material) 176 horizontally adjacent to the second dielectric material 174 and the conductive structure 152. In some embodiments, the first dielectric material 172 includes an oxide material (e.g., silicon dioxide), the second dielectric material 174 includes a nitride material (e.g., silicon nitride), and the third dielectric material 176 includes an oxide material (e.g., silicon dioxide).

[0090] Although Figure 1O and Figure 1P the memory cells 162, 170 have been illustrated and described as having a specific configuration, the present disclosure is not limited thereto. In other embodiments, the memory cells 162, 170 may include suitable memory cells that may form part of, for example, a NAND string.

[0091] Figure 2 shows a partial cross-sectional perspective view of a portion of a microelectronic device 201 (e.g., a storage device, such as a double-deck 3D NAND flash memory device) including a microelectronic device structure 200. The microelectronic device structure 200 may be substantially similar to the microelectronic device structure 100 described previously with reference to Figures 1A to 1N As Figure 2As shown, the microelectronic device structure 200 may include a stepped structure 220 that defines a contact region for connecting an access line 206 to a conductive layer 205 (e.g., a conductive layer, a conductive plate, such as the conductive structure 152( Figure 1N ))). The microelectronic device structure 200 may include memory cells 203 (e.g., memory cells 162( Figure 1N , Figure 1O ), memory cells 170( Figure 1P )) that are coupled in series with each other to form a vertical string 207 (e.g., string 160( Figure 1N ))). The vertical string 207 may extend vertically (e.g., in the Z direction) and orthogonally to conductive lines and layers 205, such as data lines 202, a source layer 204 (e.g., source structure 107( Figure 1N ), conductive layer 205, access line 206, a first select gate 208 (e.g., an upper select gate, a drain select gate (SGD), such as the conductive structure 146( Figure 1N ), select line 209, and a second select gate 210 (e.g., a lower select gate, a source select gate (SGS)). The select gate 208 may be horizontally divided (e.g., in the Y direction) into a plurality of blocks 232 (e.g., block 143( Figure 1M )) that are horizontally separated (e.g., in the Y direction) from each other by a trench 230 (e.g., a dielectric material 158 formed within a replacement gate trench 150( Figure 1J )).

[0092] As shown, vertical conductive contacts 211 may electrically couple the components to each other. For example, the select line 209 may be electrically coupled to the first select gate 208, and the access line 206 may be electrically coupled to the conductive layer 205. The microelectronic device 201 may further include a control unit 212 located below the memory array, and the control unit may include at least one of string driver circuitry, transfer gates, circuitry for select gates, circuitry for selecting conductive lines (e.g., data lines 202, access lines 206), circuitry for amplifying signals, and circuitry for sensing signals. For example, the control unit 212 may be electrically coupled to the data lines 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, the control unit 212 includes CMOS (complementary metal oxide semiconductor) circuitry. In these embodiments, the control unit 212 is characterized by having an “under-array CMOS” (“CuA”) configuration.

[0093] The first select gate 208 may extend horizontally in a first direction (e.g., the X - direction) and may be coupled to a respective first set of vertical strings 207 of the memory cells 203 at a first end (e.g., the upper end) of the vertical string 207. The second select gate 210 may be formed in a substantially planar configuration and may be coupled to the vertical string 207 at a second opposite end (e.g., the lower end) of the vertical string 207 of the memory cells 203.

[0094] The data line 202 (e.g., bit line) may extend horizontally in a second direction (e.g., the Y - direction) that is at an angle (e.g., perpendicular) to the first direction in which the first select gate 208 extends. The data line 202 may be coupled to a respective second set of vertical strings 207 at a first end (e.g., the upper end) of the vertical string 207. The first set of vertical strings 207 coupled to the respective first select gate 208 may share a particular vertical string 207 with the second set of vertical strings 207 coupled to the respective data line 202. Thus, a particular vertical string 207 may be selected at the intersection of a particular first select gate 208 and a particular data line 202. Accordingly, the first select gate 208 may be used to select the memory cells 203 of the strings 207 of the memory cells 203.

[0095] The conductive layer 205 (e.g., word line plate) may extend in a respective horizontal plane. The conductive layers 205 may be vertically stacked such that each conductive layer 205 is coupled to all of the vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stack of conductive layers 205. The conductive layer 205 may be coupled to or may form the control gate of the memory cells 203 that are coupled to the conductive layer 205. Each conductive layer 205 may be coupled to one memory cell 203 of a particular vertical string 207 of the memory cells 203.

[0096] The first select gate 208 and the second select gate 210 may be operable to select a particular vertical string 207 of the memory cells 203 between a particular data line 202 and the source layer 204. Accordingly, a particular memory cell 203 may be selected and electrically coupled to the data line 202 by the operation (e.g., by selection) of the appropriate first select gate 208, second select gate 210, and conductive layer 205 that are coupled to the particular memory cell 203.

[0097] The stepped structure 220 may be configured to provide an electrical connection between the access line 206 and the layer 205 through the vertical conductive contact 211. In other words, a particular level of the layer 205 may be selected via the access line 206 that is in electrical communication with the respective conductive contact 211, which is in electrical communication with the particular layer 205.

[0098] The data line 202 may pass through the conductive contact structure 234 (e.g., contact structure 140( Figure 1N)) is electrically coupled to the vertical string 207. As described above with reference to Figure 1N As described above, the conductive contact structure 234 may present a relatively large area for forming an alignment contact between the data line 202 and the vertical string 207 of the memory cell 203.

[0099] Thus, in some embodiments, a microelectronic device includes a stacked structure including alternating conductive and insulating structures arranged in layers, each of the layers individually including a conductive structure and an insulating structure; a memory cell string vertically extending through the stacked structure, the memory cell string including a channel material vertically extending through the stacked structure; another stacked structure vertically covering the stacked structure and including alternating levels of other conductive and other insulating structures, the other stacked structure including pillars vertically covering the memory cell string, each pillar including another channel material electrically connected to the channel material of the memory cell string; and a conductive contact structure vertically covering the other stacked structure, each conductive contact structure including a conductive contact at least partially extending into the pillar and a portion extending outside the pillar having a cross-sectional area larger than that of the pillar.

[0100] Thus, in some embodiments, a microelectronic device includes: a stacked structure including layers of alternating conductive and insulating structures; a memory cell string extending through the stacked structure, the memory cell string including at least a dielectric material and a channel material vertically extending through the stacked structure; and a conductive contact structure electrically connected to the channel material of a string in the memory cell string, the conductive contact structure having a cross-sectional area larger than that of the at least one dielectric material and the channel material of the string.

[0101] Thus, in some embodiments, a method of forming a microelectronic device includes: forming a first stacked structure including alternating levels of insulating and other insulating structures; forming a first pillar including a channel material extending through the first stacked structure; forming a second stacked structure on the first stacked structure, the second stacked structure including alternating levels of additional insulating and sacrificial structures; forming a second pillar through the second stacked structure, the second pillar including additional channel material vertically extending through the second pillar and electrically connected to the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0102] Microelectronic devices (e.g., microelectronic device 201) and microelectronic device structures (e.g., microelectronic device structures 100, 200) can be used in embodiments of the electronic systems of the present disclosure, and the microelectronic device structures include self-aligned contact structures 140 with increased dimensions. For example, Figure 3 is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 can include, for example, a computer or computer hardware components, a server or other networked hardware components, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet (e.g., or tablet), an e-book, a navigation device, etc. The electronic system 303 includes at least one memory device 305. For example, the memory device 305 can include the microelectronic device structures previously described herein (e.g., microelectronic device structures 100, 200) or embodiments of the microelectronic devices previously referenced Figures 1A to 1N and Figure 2 described, including self-aligned contact structures 140 with increased dimensions.

[0103] The electronic system 303 can further include at least one electronic signal processor device 307 (commonly referred to as a “microprocessor”). The electronic signal processor device 307 can optionally include embodiments of the microelectronic devices or microelectronic device structures previously described herein (e.g., one or more of the microelectronic device 201 or microelectronic device structures 100, 200 previously referenced Figures 1A to 1N and Figure 2 described). The electronic system 303 can further include one or more input devices 309 for a user to input information into the electronic system 303, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 303 can further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 309 and the output device 311 can include a single touchscreen device, and the single touchscreen device can be used to input information into the electronic system 303 and output visual information to the user. The input device 309 and the output device 311 can be electrically connected to one or more of the memory device 305 and the electronic signal processor device 307.

[0104] Refer to Figure 4, shows a processor-based system 400. The processor-based system 400 may include various microelectronic devices and microelectronic device structures manufactured in accordance with embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures, including one or more of microelectronic device 201 or microelectronic device structures 100, 200). The processor-based system 400 may be any of a variety of types, such as a computer, pager, cellular phone, personal manager, control circuit, or other electronic device. The processor-based system 400 may include one or more processors 402 (e.g., microprocessors) to control system functions and processing of requests in the processor-based system 400. The processor 402 and other sub-components of the processor-based system 400 may include microelectronic devices and microelectronic device structures manufactured in accordance with embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 200).

[0105] The processor-based system 400 may include a power supply 404 operably coupled to the processor 402. For example, if the processor-based system 400 is a portable system, the power supply 404 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power supply 404 may also include an AC adapter; thus, for example, the processor-based system 400 may be plugged into a wall outlet. The power supply 404 may also include a DC adapter such that the processor-based system 400 may be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0106] Depending on the functions performed by the processor-based system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styli, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or combinations thereof. In addition, an RF subsystem / baseband processor 410 may also be coupled to the processor 402. The RF subsystem / baseband processor 410 may include an antenna coupled to an RF receiver and an RF transmitter (not shown). A communication port 412 or more than one communication port 412 may also be coupled to the processor 402. The communication port 412 may be adapted to couple to one or more peripheral devices 414, such as a modem, printer, computer, scanner, or camera, or to a network, such as a local area network, a remote area network, an intranet, or the Internet.

[0107] The processor 402 can control the processor-based system 400 by implementing software programs stored in the memory. The software programs can include, for example, an operating system, database software, graphics software, word processing software, media editing software, or media playback software. The memory is operatively coupled to the processor 402 to store and facilitate the execution of various programs. For example, the processor 402 can be coupled to a system memory 416, which can include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 416 can include volatile memory, non-volatile memory, or a combination thereof. The system memory 416 is typically larger such that it can store dynamically loaded application programs and data. In some embodiments, the system memory 416 can include semiconductor devices, such as the above-described microelectronic devices and microelectronic device structures (e.g., microelectronic device 201 and microelectronic device structures 100, 200) or a combination thereof.

[0108] The processor 402 can also be coupled to a non-volatile memory 418, which does not mean that the system memory 416 must be volatile. The non-volatile memory 418 can include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory for use in combination with the system memory 416. The size of the non-volatile memory 418 is typically chosen to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory 418 can include high-capacity memory, such as disk drive memory, e.g., a hybrid drive including resistive memory or other types of non-volatile solid-state memory. The non-volatile memory 418 can include microelectronic devices, such as the above-described microelectronic devices and microelectronic device structures (e.g., microelectronic device 201 and microelectronic device structures 100, 200) or a combination thereof.

[0109] Thus, in at least some embodiments, the electronic device includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a memory cell string extending through alternating layers of insulating and conductive structures; a pillar within a stacked structure including alternating layers of insulating and conductive structures, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a larger lateral dimension than the memory cell string.

[0110] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0111] Example 1: A microelectronic device, comprising: a stacked structure including alternating conductive and insulating structures arranged in layers, each of the layers individually including a conductive structure and an insulating structure; a memory cell string extending vertically through the stacked structure, the memory cell string including a channel material extending vertically through the stacked structure; another stacked structure vertically covering the stacked structure and including alternating levels of other conductive and other insulating structures, the another stacked structure including pillars vertically covering the memory cell string, each pillar including another channel material electrically connected to the channel material of the memory cell string; and a conductive contact structure vertically covering the another stacked structure, each conductive contact structure including a conductive contact at least partially extending into the pillar and a portion extending outside the pillar having a larger cross-sectional area than the pillar.

[0112] Example 2: The microelectronic device according to Example 1, wherein the other conductive structures of the another stacked structure include a different material composition from the conductive structures of the stacked structure.

[0113] Example 3: The microelectronic device according to Example 1 or Example 2, wherein the conductive structures of the stacked structure include a different material composition from the conductive contact structure.

[0114] Example 4: The microelectronic device according to any one of Examples 1 to 3, wherein the conductive contact structure includes tungsten.

[0115] Example 5: The microelectronic device according to any one of Examples 1 to 4, further comprising insulating material between at least two of the pillars adjacent to each other horizontally in the pillar and extending vertically into the another stacked structure.

[0116] Example 6: The microelectronic device according to Example 5, wherein approximately half of each conductive contact structure covers the insulating material extending vertically into the another stacked structure.

[0117] Example 7: The microelectronic device according to any one of Examples 1 to 6, wherein the other conductive structures of the another stacked structure include select gate structures.

[0118] Example 8: The microelectronic device according to any one of Examples 1 to 7, wherein at least one memory cell string in the memory cell string is laterally offset from at least one other memory cell string in the memory cell string and is laterally aligned with at least one additional memory cell string in the memory cell string.

[0119] Example 9: The microelectronic device according to any one of Examples 1 to 8, further comprising a conductive wire electrically connected to the conductive contact structure.

[0120] Example 10: The microelectronic device according to any one of Examples 1 to 9, wherein: the conductive structure of the stacked structure is in contact with a conductive pad material; and the other conductive structures of the other stacked structure directly contact the other insulating structures of the other stacked structure.

[0121] Example 11: The microelectronic device according to any one of Examples 1 to 10, wherein approximately half of each conductive contact structure is aligned with an insulating material extending into the other stacked structure.

[0122] Example 12: A method of forming a microelectronic device, the method comprising: forming a first stacked structure including alternating layers of insulating structures and other insulating structures; forming a first pillar including a channel material extending through the first stacked structure; forming a second stacked structure on the first stacked structure, the second stacked structure including alternating layers of additional insulating structures and sacrificial structures; forming a second pillar through the second stacked structure, the second pillar including additional channel material extending vertically through the second pillar and electrically connected to the channel material of the first pillar; forming a conductive material in the second pillar; growing additional conductive material on the second pillar to form a conductive contact; and at least partially replacing the sacrificial structure with a conductive material.

[0123] Example 13: The method according to Example 12, wherein forming a conductive material in the second pillar includes: forming a sacrificial material in the second pillar; and replacing at least some of the sacrificial material in the second pillar with the conductive material.

[0124] Example 14: The method according to Example 13, wherein replacing at least some of the sacrificial material in the second pillar with a conductive material includes converting polysilicon to tungsten.

[0125] Example 15: The method according to Example 13 or Example 14, wherein forming a sacrificial material in the second pillar includes forming polysilicon in the second pillar.

[0126] Example 16: The method according to any one of Examples 12 to 14, further comprising removing the other insulating structures and forming conductive structures at positions corresponding to the other insulating structures.

[0127] Example 17: The method according to Example 16, wherein removing the other insulating structure and forming a conductive structure at a position corresponding to the other insulating structure includes removing the other insulating structure and forming a conductive structure at a position corresponding to the other insulating structure after replacing the sacrificial structure with a conductive material.

[0128] Example 18: The method according to Example 16 or Example 17, wherein removing the other insulating structure includes: forming a trench through the first stack and the second stack; and exposing the insulating structure to a wet etchant through the trench.

[0129] Example 19: The method according to any one of Examples 12 to 18, wherein replacing the sacrificial structure with a conductive material includes converting a sacrificial structure including polysilicon into a conductive material including tungsten.

[0130] Example 20: A microelectronic device, comprising: a stack structure including layers of alternating conductive structures and insulating structures; a memory cell string extending through the stack structure, the memory cell string including at least a dielectric material and a channel material extending vertically through the stack structure; and a conductive contact structure in electrical communication with the channel material of a string in the memory cell string, the conductive contact structure having a cross-sectional area larger than at least one of the dielectric material and the channel material of the string.

[0131] Example 21: The microelectronic device according to Example 20, wherein the conductive contact structure includes β-phase tungsten.

[0132] Example 22: The microelectronic device according to Example 20 or Example 21, further comprising a dielectric material extending through the stack structure and separating a first group of memory cell strings from a second group of memory cell strings.

[0133] Example 23: An electronic system, comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: a memory cell string extending through alternating levels of insulating and conductive structures; a pillar within a stack structure including alternating levels of insulating and conductive structures, the pillar being laterally aligned with the memory cell string; and a conductive contact structure electrically connected to a channel material extending vertically through the memory cell string and the pillar, the conductive contact structure having a lateral dimension larger than the memory cell string.

[0134] Although certain illustrative embodiments have been described in connection with the accompanying drawings, those skilled in the art will recognize and understand that the embodiments covered by the present disclosure are not limited to those expressly shown and described herein. On the contrary, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by the present disclosure, such as those claimed below, including statutory equivalents. Additionally, features from one disclosed embodiment can be combined with features from another disclosed embodiment while still being within the scope of the present disclosure.

Claims

1. A microelectronic device, comprising: A memory cell string that vertically extends through a stacked structure including vertically alternating conductive and insulating structures; An additional stacked structure that vertically overlies the stacked structure and includes additional conductive and insulating structures; Channel material that vertically extends through the additional stacked structure and contacts additional channel material of the memory cell string; A conductive contact structure that contacts the channel material; And A select gate trench that vertically extends through the additional stacked structure and terminates before the stacked structure, the conductive contact structure laterally extending into the lateral boundaries of the select gate trench.

2. The microelectronic device according to claim 1, wherein the channel material extends vertically under the select gate trench.

3. The microelectronic device according to claim 1, wherein approximately half of each conductive contact structure extends laterally into the lateral boundary of the select gate trench.

4. The microelectronic device according to claim 1, further comprising a trench structure that extends vertically through the stack structure and is horizontally adjacent to the select gate trench.

5. The microelectronic device according to claim 4, wherein the horizontal width of the trench structure is greater than the horizontal width of the select gate trench.

6. The microelectronic device according to claim 1, wherein the horizontal dimension of the channel material is greater than the horizontal dimension of the additional channel material.

7. The microelectronic device according to claim 1, wherein the additional conductive structures of the additional stack structure individually comprise a different phase from the conductive structures of the stack structure.

8. The microelectronic device according to claim 1, wherein the conductive structure comprises a different material composition from each of the additional conductive structure and the conductive contact structure.

9. A memory device, comprising: A stacked structure including layers of conductive structures vertically alternating with insulating structures; A memory cell string that vertically extends through the stacked structure; An additional stacked structure that vertically overlies the stacked structure and the memory cell string, the additional stacked structure including alternating levels of additional conductive and insulating structures; A pillar that vertically extends through the additional stacked structure; And Conductive contact structures, each conductive contact structure individually configured to be electrically connected to one of the memory cell strings, the conductive contact structures and the additional conductive structures individually including material compositions different from the conductive structures.

10. The memory device according to claim 9, wherein the conductive contact structure and the additional conductive structure comprise tungsten.

11. The memory device according to claim 9, wherein the conductive contact structure comprises doped tungsten.

12. The memory device according to claim 9, wherein the conductive contact structure comprises a greater amount of β-phase tungsten than α-phase tungsten.

13. The memory device according to claim 9, wherein each of the conductive contact structures individually exhibits a larger horizontal dimension than the memory cell string electrically connected to the conductive contact structure.

14. The memory device according to claim 9, wherein the diameter of the conductive contact structure is in the range of about 100 nm to about 150 nm.

15. A microelectronic device, comprising: A memory cell string that vertically extends through a stacked structure including levels of conductive structures alternating with levels of insulating structures; Pillars that vertically extend through an additional stacked structure vertically overlying the stacked structure, the pillars individually including: Channel material contacting additional channel material of one of the memory cell strings; and Polysilicon that contacts the channel material; and Conductive contacts that contact the channel material of the pillars, each conductive contact individually partially extending into one of the pillars and contacting the polysilicon and the channel material of one of the pillars.

16. The microelectronic device according to claim 15, further comprising a pad material horizontally located between the channel material and the additional insulating structure and the additional conductive structure of the additional stack structure.

17. The microelectronic device according to claim 15, wherein the diameter of the additional channel material at the interface of the stack structure and the additional stack structure is larger than the diameter in the memory cell string.

18. The microelectronic device according to claim 15, wherein the horizontal dimension of the polysilicon is smaller than the horizontal dimension of the conductive contact.

19. The microelectronic device according to claim 15, further comprising a select gate trench that vertically extends through the additional stack structure and vertically into the stack structure.

20. The microelectronic device according to claim 19, wherein the sidewalls of the select gate trench are tapered.

Images