High-voltage gallium nitride Schottky diode with groove anode full-self-alignment structure and preparation method of high-voltage gallium nitride Schottky diode

Abstract

According to the high-voltage gallium nitride Schottky diode with the groove anode full-self-alignment structure and the preparation method of the high-voltage gallium nitride Schottky diode, the anode metal layer adopts the groove anode full-self-alignment structure, so that parallel parasitic capacitance caused by a field plate structure can be avoided; the P-GaN terminal structure formed by the three cap layers can reduce the 2DEG concentration in a channel below the P-GaN terminal structure, expand a depletion region and effectively modulate an electric field. The depletion region is further expanded to the tail end of the p-GaN cap layer, a new peak electric field except the Schottky junction appears, and the reverse breakdown voltage of the device is increased. According to the AlGaN / GaN SBD, the groove anode self-alignment process is realized in a mode of removing the sacrificial layer through mechanical polishing, and the high-performance AlGaN / GaN SBD with low parasitic capacitance, high breakdown voltage, low electric leakage and good temperature stability is realized by optimizing epitaxial materials such as the delta-doped AlGaN barrier layer and the p-GaN terminal structure and optimizing the process structure.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure and a preparation method thereof. Background Art

[0002] In various power electronics applications, such as renewable energy generation, industrial motor drives, power grids, and transportation, high-voltage power rectifiers are required. Although the most common diodes used in today's integrated circuits are Si diodes, the characteristics of Si-based devices have approached the theoretical limit values of Si materials. For power semiconductor devices applied in the high-voltage and high-power fields, due to the limitations of Si material characteristics on breakdown voltage, on-resistance, and switching frequency, it is difficult for Si-based power devices to achieve improved conversion efficiency. For example, the commercial voltage of bipolar silicon diodes is as high as 6.5 kV, but there is a problem of slow switching speed. Therefore, people have started to turn their attention to III-V semiconductor devices, such as SiC-based devices and GaN-based devices, which have excellent characteristics such as high reliability, small size, light weight, and high energy efficiency. GaN and SiC have similar superior material characteristics, and SiC-based and GaN-based power devices are two major research hotspots in the high-voltage and high-power fields. Although the development of SiC-based power devices started earlier, due to their high cost, it has severely restricted their promotion in the commercial product market. The well-known success of GaN materials comes from making the invention of blue light-emitting diodes (LEDs) possible. The research on GaN-based power devices started relatively late, but with the in-depth research and the rapid development of gallium nitride epitaxial technology on sapphire, their cost will be greatly reduced. Therefore, GaN-based power devices have great application potential in the high-voltage and high-power fields. GaN / GaN heterojunction epitaxial materials with high critical breakdown electric field, high mobility, and high-density two-dimensional electron gas (2DEG) show great potential in high-power high-frequency electronics. In the past few years, AlGaN / GaN high electron mobility transistors (HEMTs) and Schottky barrier diodes (SBDs) with low voltage (LV, <200V) or medium voltage (MV, <1200V) have been successfully commercialized in fields such as fast charging and server power supplies.

[0003] Although AlGaN / GaN shows superior performance compared to SiC, due to the lack of effective electric field management in AlGaN / GaN electronics, such as the selected-area p-n junction commonly used in high-voltage (HV, >1200V) silicon carbide barrier Schottky (JBS) diodes, lateral AlGaN / GaN SBDs are still mainly concentrated in the LV and MV fields. Currently, many methods have been proposed to improve the performance of gallium nitride Schottky diodes, such as an anode groove structure to reduce the turn-on voltage, a field plate structure to increase the breakdown voltage, and slow low-damage etching technology to reduce the roughness of the etched surface to effectively suppress leakage current.

[0004] During the preparation of the traditional grooved anode structure, in order to avoid the influence of lithography alignment deviation, some field plate structures are usually left at the anode edge to ensure direct contact between the anode metal and the 2DEG. These structures will form a parallel plate capacitor structure with the 2DEG in the channel, resulting in a rapid increase in the anode parasitic capacitance of the device. To meet the requirements of low-cost outer space exploration, oil exploration, and nuclear magnetic resonance, it is necessary to fabricate an AlGaN / GaN SBD with high breakdown voltage, low leakage current, low turn-on voltage, and low turn-on resistance on an Si or Al2O3 substrate.

[0005] Due to its high critical electric field and high-mobility two-dimensional electron gas (2DEG) characteristics, AlGaN / GaN SBD is regarded as a candidate for the next-generation high-voltage devices. For example, patent documents (CN112736207A) and (US20210343561A) both adopt AlGaN / GaN SBD. However, the following problems exist: (1) Current collapse phenomenon: Surface trap states cause carriers in the 2DEG channel to be trapped under high voltage, resulting in a significant increase in the dynamic on-resistance. For example, patent CN112736207A reveals that the dynamic Ron degradation reaches more than 50%. (2) Electric field concentration: The electric field spike at the anode edge limits the increase of the breakdown voltage. The field plate structure adopted in patent US20210343561A will increase the parasitic capacitance and has a high process complexity. (3) It is difficult to balance the breakdown voltage and the on-resistance. The traditional structure is difficult to achieve both a high breakdown voltage, >10 kV, and a low on-resistance, <50 mΩ·cm 2 . (4) The leakage current drift problem of the Schottky junction leakage current increasing at high temperatures, with poor thermal stability. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a grooved anode fully self-aligned structure high-voltage gallium nitride Schottky diode and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] A grooved anode fully self-aligned structure high-voltage gallium nitride Schottky diode includes: a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a UID-GaN cap layer, a p + -GaN cap layer, and a p ++ -GaN cap layer from bottom to top in sequence; wherein, a groove is formed from the central region of the p ++ -GaN cap layer downwards until the inside of the UID-GaN cap layer. Different-side cathode metal layers and anode metal layers are arranged from both sides of the grooved anode fully self-aligned structure high-voltage gallium nitride Schottky to the inside of the GaN channel layer, and the metal layers on both sides are higher than the p ++ -GaN cap layer.

[0008] A preparation method of a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure, comprising:

[0009] S100, select a substrate, and sequentially grow a GaN buffer layer, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a UID-GaN cap layer, a p + -GaN cap layer and a p ++ -GaN cap layer on the substrate to obtain a wafer;

[0010] S200, etch the p ++ -GaN cap layer from top to bottom until inside the GaN channel layer to perform mesa isolation on the area outside the active region of the wafer;

[0011] S300, for each active region on the wafer, etch from the right side of the p ++ -GaN cap layer from top to bottom until inside the GaN channel layer to form a cathode groove, and then deposit cathode metal in the cathode groove to make it higher than the p ++ -GaN cap layer to obtain a cathode metal layer;

[0012] S400, grow a sacrificial layer on the p ++ -GaN cap layer and cover the cathode metal layer;

[0013] S500, for each active region, etch from the left side of the p ++ -GaN cap layer from top to bottom until inside the GaN channel layer to form an anode groove, and then deposit anode metal in the anode groove and on the sacrificial layer to make it higher than the p ++ -GaN cap layer and lower than the sacrificial layer to obtain an anode metal layer;

[0014] S600, remove the anode metal on the sacrificial layer and the sacrificial layer;

[0015] S700, from the central region of the p ++ -GaN cap layer from top to bottom until inside the UID-GaN cap layer to form a groove to obtain a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure.

[0016] Beneficial effects:

[0017] The present invention provides a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure and a preparation method thereof. The anode metal layer adopts a grooved anode fully self-aligned structure, which can avoid the parallel parasitic capacitance brought by the field plate structure. The P-GaN terminal structure formed by three cap layers can reduce the 2DEG concentration in the channel below it, expand the depletion region, and effectively modulate the electric field. The depletion region is further extended to the end of the p-GaN cap layer, and a new peak electric field appears outside the Schottky junction, increasing the reverse breakdown voltage of the device. The present invention realizes the grooved anode self-alignment process by mechanically polishing to remove the sacrificial layer, and through the optimization of epitaxial materials such as the delta-doped AlGaN barrier layer and the p-GaN terminal structure and the optimization of the process structure, a high-performance AlGaN / GaN SBD with low parasitic capacitance, high breakdown voltage, low leakage current, and good temperature stability is achieved.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Brief Description of the Drawings

[0019] Figure 1 is a schematic structural diagram of a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure provided by the present invention;

[0020] Figure 2 is a schematic flow diagram of a preparation method of a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure provided by the present invention;

[0021] Figures 3 - 8 is a schematic diagram of the preparation process of a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure provided by the present invention. Detailed Embodiments

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0023] As Figure 1 shown, the high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure provided by the present invention includes: a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a UID-GaN cap layer, a p + -GaN cap layer, and a p ++ -GaN cap layer from bottom to top in sequence; wherein, a groove is formed from the central region of the p ++ -GaN cap layer downwards until inside the UID-GaN cap layer, and a cathode metal layer and an anode metal layer on different sides are arranged from both sides of the high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure until inside the GaN channel layer, and the metal layers on both sides are higher than the p ++ -GaN cap layer.

[0024] Among them, the GaN buffer layer, GaN channel layer, AlN insertion layer, AlGaN barrier layer, UID-GaN cap layer, p + -GaN cap layer and p ++ -GaN cap layer have thicknesses corresponding to 4 μm, 300 nm, 1 nm, 22 nm, 30 nm, 100 nm, and 15 nm respectively. The AlGaN barrier layer is a 22-nm Sidelta-doped Al 0.25 Ga 0.75 N barrier layer. Considering economic cost factors, sapphire is used as the substrate for device fabrication in the present invention.

[0025] It can be understood that the AlN insertion layer causes a conduction band offset at the AlGaN / GaN interface, confines the 2DEG in a higher barrier, enhances the confinement of the quantum well, which makes the 2DEG further away from the AlGaN barrier layer and closer to the GaN channel layer. And the AlN insertion layer, as a binary compound, does not randomly fluctuate in the compound, thus reducing alloy disorder scattering at the interface. These two effects effectively improve the channel mobility at high carrier concentrations.

[0026] The anode metal layer of the high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure in the present invention adopts a grooved anode fully self-aligned structure, which can avoid the parallel parasitic capacitance brought by the field plate structure. And the GaN terminal structure can reduce the 2DEG concentration in the channel below it, expand the depletion region, and effectively modulate the electric field. A peak electric field appears except at the Schottky junction, the depletion region further extends to the p-GaN end, and at the same time, there will also be a new peak electric field, increasing the reverse breakdown voltage of the device.

[0027] As Figure 2 shown, the present invention provides a method for fabricating a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure, including:

[0028] S100, select a substrate, and sequentially grow a GaN buffer layer, GaN buffer layer, GaN channel layer, AlN insertion layer, AlGaN barrier layer, UID-GaN cap layer, p + -GaN cap layer and p ++ -GaN cap layer on the substrate to obtain a wafer;

[0029] Among them, the growth process of the AlGaN barrier layer includes: using TMG, TMA, and NH3 as precursors, introducing H2 as a carrier gas into the MOCVD system, and growing AlGaN to 10 nm at 1150 °C; stopping the precursor supply for 10 s, maintaining the reaction chamber temperature of the MOCVD system, and then introducing SiH4 for 120 s to form a single-atom doping layer; stopping the SiH4 supply and continuing to grow AlGaN to 22 nm.

[0030] It should be noted that: Delta doping refers to a very thin doped layer (only a few atomic layers thick) in a semiconductor material, which can precisely control the doping concentration and distribution. The delta doping of the AlGaN barrier layer is usually achieved by interrupting the growth of AlGaN during the growth process, introducing a doping gas to form a single atomic layer doping, and then resuming the growth of AlGaN to cover the doped layer.

[0031] In the present invention, a 22-nm-thick Si delta-doped AlGaN barrier layer was grown at 1050 °C. The crystal growth mode was interrupted by closing the Ga and Al sources, and Si impurities (SiH4) were introduced into the growth chamber to achieve a delta doping profile of Si. In an AlGaN / GaN heterostructure, to increase the 2DEG concentration, Si is generally uniformly doped in the GaN channel layer. Compared with the uniform doping of the GaN channel layer, the Si delta doping of the AlGaN barrier layer confines the doping within a thin layer, enabling precise control of the position and density of donor atoms. A higher doping concentration can be achieved without significantly increasing crystal defects, resulting in more efficient ionization and a higher 2DEG density. Delta doping moves the dopants away from the AlGaN / GaN interface, avoiding the introduction of more dislocations and defects, and thus increasing the 2DEG density. At the same time, as the dopants move away from the AlGaN / GaN interface, the leakage current will decrease, and carrier impurity scattering can also be minimized, thereby improving the carrier mobility. Compared with the uniform Si doping of the AlGaN barrier layer, the polarization field in the AlGaN barrier enhances the electron accumulation in the interface channel, resulting in a higher 2DEG density. However, the uniformly distributed doping ions will shield the polarization field. If delta doping is used instead of uniform doping, the adverse shielding effect caused by the uniformly distributed doping ions will be minimized. Therefore, delta doping in the AlGaN barrier can more effectively increase the 2DEG density than the uniform doping scheme. At the same time, as the dopants move away from the AlGaN / GaN interface, the leakage current will decrease, and carrier impurity scattering can also be minimized, thereby improving the carrier mobility.

[0032] The growth of the UID-GaN cap layer above the AlGaN barrier layer is to ensure the etching depth during the subsequent selective etching of p-GaN. It can ensure that the p-GaN cap layer is completely etched, avoiding the residual p-GaN cap layer due to insufficient etching depth, which affects the 2DEG concentration in the channel and reduces the current density. It can also avoid the weakening of polarization and the introduction of more defects near the AlGaN / GaN interface due to over-etching of the AlGaN layer, which reduces the 2DEG concentration. The upper p ++ -GaN / p + -GaN cap layer is activated by N2 annealing treatment in the MOCVD chamber. The heavily doped p ++The -GaN layer is designed to regulate the surface potential and form a barrier-free ohmic contact.

[0033] S200, in the p ++ The -GaN cap layer is etched from top to bottom until inside the GaN channel layer to perform mesa isolation on the area outside the active region of the wafer;

[0034] In this step, BCl3 / Cl2 is introduced into the inductively coupled plasma etching ICP equipment, and the inductively coupled plasma etching ICP equipment is used to etch the p ++ The -GaN cap layer is etched from top to bottom until inside the GaN channel layer to perform mesa isolation on the area outside the active region of the wafer; wherein, the etching rate is 95 nm / min and the etching depth is 250 nm.

[0035] S300, for each active region on the wafer, from the right side of the p ++ -GaN cap layer, it is etched from top to bottom until inside the GaN channel layer to form a cathode groove, and then cathode metal is deposited in the cathode groove to make it higher than the p ++ -GaN cap layer to obtain a cathode metal layer;

[0036] In a specific embodiment of the present invention, S300 includes:

[0037] S310, for each active region on the wafer, SF6 photoresist is spin-coated on the cathode region of the p ++ -GaN cap layer, then AZ5214 photoresist is spin-coated on the SF6, and then area exposure and development are performed;

[0038] S320, from the cathode region, it is etched from top to bottom until inside the GaN channel layer to form a cathode groove;

[0039] S330, cathode metal is evaporated in the cathode groove to make it higher than the p ++ -GaN cap layer to obtain a cathode metal layer, as Figure 3 shown.

[0040] Among them, the evaporation sequence of the cathode metal is: Ti, Al, Ni, Au, and the corresponding thicknesses are 20, 130, 50, 45 nm.

[0041] S340, the remaining photoresist is stripped, and then annealing treatment is performed.

[0042] It should be noted that the present invention uses a novel ohmic contact process to prepare the ohmic contact of the device, i.e., the cathode metal layer. The novel ohmic contact process uses a double-layer photoresist of SF6 + AZ5214. First, a surface pretreatment is carried out at 100 °C in an HMDS pretreatment system to increase the adhesion of the photoresist. The specific process of the double-layer resist is as follows: Set the rotation speed of the spin coater to 2000 rad / min and spin coat for 30 s to complete the spin coating of SF6. Then, pre-bake on a hot plate at 180 °C for 5 min. Next, set the rotation speed of the spin coater to 3000 rad / min and spin coat for 30 s to complete the spin coating of AZ5214. Then, pre-bake on a hot plate at 100 °C for 2 min 30 s. Next, use a MA6 contact ultraviolet lithography machine for area exposure with an exposure time of 3.3 s. Then, place it in a developer for 60 s and post-bake and harden the film on a hot plate at 120 °C for 120 s. Use an inductively coupled plasma etching ICP device to etch the groove in the ohmic region with an etching rate of 95 nm / min and an expected etching depth of 225 nm. Then, based on the property that the AZ5214 photoresist can be reversed from a positive resist to a negative resist under certain conditions, pre-bake on a hot plate at 110 °C for 70 s. After that, after 45 s of flood exposure and 60 s of development, the AZ5214 will become a hard negative resist, and the underlying SF6 resist will sink inward. Then, use electron beam evaporation to deposit metals Ti / Al / Ni / Au: 20 / 130 / 50 / 45 nm, and the metals deposited on the photoresist surface and the semiconductor surface are interrupted. Finally, perform metal lift-off. After soaking in the lift-off solution for 10 min, perform lift-off, and then use acetone and deionized water to wash off the surface photoresist to complete the lift-off. This process can complete the etching of the cathode groove and the evaporation of the cathode metal in a single step. Since the metals on the photoresist surface and the semiconductor surface are interrupted, it is beneficial for metal lift-off and the improvement of ohmic contact. Finally, a rapid annealing treatment is carried out on the alloy metal electrode at a temperature of 850 °C and an annealing time of 32 s in a nitrogen atmosphere to complete the preparation of the ohmic contact electrode of the device.

[0043] S400, grow a sacrificial layer on the p ++ -GaN cap layer to cover the cathode metal layer;

[0044] S500, for each active region, from the p ++ -GaN cap layer, etch from top to bottom on the left side until inside the GaN channel layer to form an anode groove, and then deposit anode metal in the anode groove and on the sacrificial layer so that it is higher than the p ++ -GaN cap layer and lower than the sacrificial layer to obtain an anode metal layer;

[0045] As a specific embodiment of the present invention, S500 includes:

[0046] S510, for each active region, to the p ++Spin-coat and develop photoresist on the anode region on the -GaN cap layer;

[0047] S520, etch away the sacrificial layer in the anode region from top to bottom using CF4 and O2, and then use BCl3 / Cl2 for etching until an anode groove is formed inside the GaN channel layer;

[0048] S530, perform O2 plasma treatment on the etched surface and perform annealing treatment in an N2 atmosphere;

[0049] S540, deposit anode metal in the anode groove and on the sacrificial layer so that it is higher than the p ++ -GaN cap layer and lower than the sacrificial layer to obtain an anode metal layer. Among them, the evaporation sequence of the anode metal is Ni, Au, and the corresponding thicknesses are 30, 200 nm.

[0050] Reference Figures 4 - 6 , first use a PECVD device to grow a 500 nm Si3N4 sacrificial layer. After photolithography and development, use ICP to etch the anode region twice. First, use CF4 and O2 to etch the silicon nitride to completely etch the silicon nitride in the anode region; then use BCl3 / Cl2 for etching, with an etching rate of 95 nm / min and an etching depth of 225 nm. After etching is completed, perform 5 min of O2 plasma treatment on the etched surface and perform 5 min of annealing treatment in an N2 atmosphere at 450 °C to eliminate etching damage. As Figure 6 , form a Schottky contact of the anode by electron beam evaporation of Ni / Au (30 / 200 nm). Because the thickness is much less than the thickness of the passivation layer silicon nitride, it can not only be self-aligned, reducing the photolithography process steps, but also remove the field plate structure at the anode edge.

[0051] S600, remove the anode metal and the sacrificial layer on the sacrificial layer;

[0052] As Figure 7 and Figure 8 shown, in this step, remove the surface metal and a small amount of Si3N4 sacrificial layer by mechanical polishing, and then completely etch away the Si3N4 sacrificial layer.

[0053] The present invention first grows a sacrificial layer, etches an anode groove and grows an anode metal layer, and then removes the excess metal layer and the sacrificial layer by mechanical polishing, simplifying the photolithography and stripping process steps; avoiding the parasitic capacitance brought by the anode field plate structure. The present invention adopts an anode p-GaN terminal structure, and only p-GaN near the anode metal layer is used to modulate the electric field to increase the breakdown voltage. The p-GaN layer near the cathode metal layer is completely etched because the presence of p-GaN in the cathode metal layer will hinder the modulation effect and reduce the reverse breakdown voltage.

[0054] S700, from the said p ++ - From the center region of the GaN cap layer downwards until inside the UID-GaN cap layer, a groove is formed to obtain a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure.

[0055] In this step, an etching region is selected between the anode metal layer and the cathode metal layer, and etching is carried out from top to bottom until inside the UID-GaN cap layer to obtain a high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure; wherein, the etching depth is about 135 nm.

[0056] As Figure 1 shown, in this step, selective etching is carried out between the anode and cathode metal layers, and the etching depth is about 135 nm. According to different etched regions, a p-GaN cap layer of the anode is formed, and the preparation of a high-voltage gallium nitride Schottky diode (SBD) device with a grooved anode fully self-aligned structure is completed. The width of the finally obtained high-voltage gallium nitride Schottky diode with a grooved anode fully self-aligned structure in the present invention is 340 μm, the width of the anode and cathode metal layers is 340 μm, the length is 334 μm, and the distance between the anode metal layer and the cathode metal layer is 100 μm.

[0057] Although the present application has been described in conjunction with various embodiments herein, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of cases.

[0058] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode, characterized in that: include: From bottom to top, they are substrate, GaN buffer layer, GaN channel layer, AlN insertion layer, AlGaN barrier layer, UID-GaN cap layer, p + -GaN cap layer and p ++ -GaN cap layer; wherein, from p ++ A groove is formed from top to bottom in the center area of ​​the UID-GaN cap layer, and cathode metal layers and anode metal layers are set on different sides of the groove anode fully self-aligned structure high-voltage gallium nitride Schottky until the inside of the GaN channel layer, and the metal layers on both sides are higher than the p ++ -GaN cap layer.

2. A method for preparing a groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode, characterized in that: include: S100, selecting a substrate, and sequentially growing a GaN buffer layer, a GaN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a UID-GaN cap layer, and a GaN layer on the substrate. + -GaN cap layer and p ++ -GaN cap layer to obtain wafer; S200, in the p ++ -The GaN cap layer is etched from top to bottom until it reaches the inside of the GaN channel layer to isolate the area outside the active area of ​​the wafer; S300, for each active area on the wafer, from the p ++ -The right side of the GaN cap layer is etched from top to bottom until a cathode groove is formed inside the GaN channel layer, and then cathode metal is deposited in the cathode groove to make it higher than the p ++ -GaN cap layer to obtain cathode metal layer; S400, in the p ++ -Grow a sacrificial layer on the GaN cap layer and cover the cathode metal layer; S500, for each active region, from the p ++ The left side of the GaN cap layer is etched from top to bottom until an anode groove is formed inside the GaN channel layer, and then an anode metal is deposited in the anode groove and on the sacrificial layer to make it higher than the p ++ -GaN cap layer and below the sacrificial layer to obtain an anode metal layer; S600, removing the anode metal and the sacrificial layer on the sacrificial layer; S700, from the p ++ A groove is formed in the central area of ​​the UID-GaN cap layer from top to bottom to obtain a groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode.

3. The method for preparing the groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode according to claim 2, characterized in that: The AlGaN barrier layer is generated in S100 including: Using TMG, TMA, and NH3 as precursors, H2 was introduced into the MOCVD system as a carrier gas, and AlGaN was grown to 10nm at 1150℃; the precursor supply was stopped for 10s, the reaction chamber temperature of the MOCVD system was maintained, and SiH4 was introduced for 120s to form a single-atom doping layer; the SiH4 supply was stopped, and AlGaN was continued to grow to 22nm.

4. The method for preparing the groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode according to claim 2, characterized in that: S200 includes: BCl3 / Cl2 is introduced into the inductively coupled plasma etching ICP equipment, and the inductively coupled plasma etching ICP equipment is used to etch the p ++ The GaN cap layer is etched from top to bottom until the inside of the GaN channel layer to isolate the area outside the active area of ​​the wafer. The etching speed is 95nm / min and the etching depth is 250nm.

5. The method for preparing the groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode according to claim 2, characterized in that: S300 includes: S310, for each active area on the wafer, ++ - Spin-coat SF6 photoresist on the cathode region of the GaN cap layer, then spin-coat AZ5214 photoresist on the SF6, and then perform regional exposure and development; S320, etching from top to bottom from the cathode region until a cathode groove is formed inside the GaN channel layer; S330, evaporating cathode metal in the cathode groove to make it higher than p ++ -GaN cap layer to obtain cathode metal layer; S340, stripping off the remaining photoresist, and then performing annealing treatment.

6. The method for preparing the groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode according to claim 5, characterized in that: The evaporation order of the cathode metal is: Ti, Al, Ni, Au, and the corresponding thicknesses are 20, 130, 50, and 45 nm.

7. The method for preparing the groove anode fully self-aligned structure high voltage gallium nitride Schottky diode according to claim 2, characterized in that: S500 includes: S510, for each active region, ++ - Spin-coat photoresist on the anode region of the GaN cap layer and develop it; S520, etching the sacrificial layer in the anode region from top to bottom using CF4 and O2, and then etching using BCl3 / Cl2 until an anode groove is formed inside the GaN channel layer; S530, performing O2 plasma treatment on the etched surface and performing annealing treatment in a N2 atmosphere; S540, depositing anode metal in the anode groove and on the sacrificial layer to make it higher than p ++ -GaN cap layer and below the sacrificial layer to obtain an anode metal layer.

8. The method for preparing the groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode according to claim 7, characterized in that: The evaporation order of the anode metal is Ni, Au, and the corresponding thicknesses are 30 and 200 nm.

9. The method for preparing a groove anode fully self-aligned structure high voltage gallium nitride Schottky diode according to claim 2, characterized in that: S700 includes: An etching area is selected between the anode metal layer and the cathode metal layer, and etching is performed from top to bottom until the inside of the UID-GaN cap layer to obtain a groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode; wherein the etching depth is about 135nm.

10. The method for preparing a groove anode fully self-aligned structure high voltage gallium nitride Schottky diode according to claim 2, characterized in that: The groove anode fully self-aligned structure high-voltage gallium nitride Schottky diode has a width of 340 μm, a width of the cathode and cathode metal layers of 340 μm, a length of 334 μm, and a distance from the anode metal layer to the cathode metal layer of 100 μm.

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