Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a semiconductor substrate; a first semiconductor region formed in the semiconductor substrate; a second semiconductor region surrounding the first semiconductor region in a plan view; a first conductive layer formed on the first semiconductor region; a first electrode formed on the first conductive layer; a cathode region connected to the first electrode via the first conductive layer; a second conductive layer in contact with the first semiconductor region; a second electrode formed on the second conductive layer; and a first region that is provided between a region in contact with the first conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and that is in contact with the lower surface of the second conductive layer. A depth of the first region is greater than a depth of the cathode region.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-214798, filed on December 20, 2023, including the specification, drawings, and abstract thereof, is hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a Schottky barrier diode.

[0004] A Schottky barrier diode (SBD) is a rectifying element that utilizes a Schottky barrier formed by a junction of a metal and a semiconductor. Compared with a diode using a PN junction, the Schottky barrier diode has lower forward voltage characteristics and faster switching speed. However, there is a problem that the leakage current of the Schottky barrier diode is larger than that of the diode using a PN junction.

[0005] The disclosed technology is listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2006-310555

[0007] Patent Document 1 discloses an SBD including a semiconductor region of a first conductivity type, an anode electrode, a protection ring of a second conductivity type formed along the periphery of the anode electrode, an isolation insulating film that isolates the anode electrode around the protection ring, and a mask for the anode electrode. With this configuration, it is possible to reduce the reverse leakage current of the SBD. SUMMARY OF THE INVENTION

[0008] In the reverse bias state of the Schottky barrier diode, the electric field can not only concentrate at the corner of the Schottky electrode but also reach directly below the Schottky electrode. Due to tunneling, this generation of the electric field can cause leakage current.

[0009] Other problems and novel features will become apparent from the description of this specification and the drawings.

[0010] In the present disclosure, a semiconductor device includes: a semiconductor substrate having an upper surface; a first semiconductor region formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view; a first conductive layer formed on the first semiconductor region; a first electrode formed on the first conductive layer; a cathode region formed in the first semiconductor region and connected to the first electrode via the first conductive layer; a second conductive layer formed on the first semiconductor region and in contact with the first semiconductor region; a second electrode formed on the second conductive layer; and a first region formed in the first semiconductor region and disposed between a region in contact with the second conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and the region is in contact with a lower surface of the second conductive layer. When the upper surface of the semiconductor substrate is used as a reference surface, a depth of the first region is greater than a depth of the cathode region. The semiconductor substrate, the second semiconductor region, and the first region each have a first conductivity type. The first semiconductor region and the cathode region each have a second conductivity type opposite to the first conductivity type.

[0011] The present disclosure can provide a semiconductor device capable of further suppressing leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of the semiconductor device of the first embodiment.

[0013] Figure 2 is a cross-sectional view of the semiconductor device of the first embodiment.

[0014] Figure 3A is a cross-sectional view of the semiconductor device of the first embodiment.

[0015] Figure 3B is a cross-sectional view of the semiconductor device of the first embodiment.

[0016] Figure 4A is a diagram showing the potential distribution of the semiconductor device of the first embodiment.

[0017] Figure 4B is a diagram showing the potential distribution of the semiconductor device of the first embodiment.

[0018] Figure 4C is a diagram showing the potential distribution of the semiconductor device of the first embodiment.

[0019] Figure 5 is a diagram showing the drive voltage and leakage current of the semiconductor device of the first embodiment.

[0020] Figure 6A is a perspective view of the semiconductor device of the first embodiment.

[0021] Figure 6B is a plan view of the semiconductor device of the first embodiment.

[0022] Figure 7A is a diagram showing the leakage current and driving voltage of the semiconductor device of the first embodiment.

[0023] Figure 7B is a diagram showing the leakage current and driving voltage of the semiconductor device of the first embodiment.

[0024] Figure 8 is a plan view of the semiconductor device of the first embodiment.

[0025] Figure 9 is a cross-sectional view of the semiconductor device of the second embodiment.

[0026] Figure 10A is a plan view of the semiconductor device of the second embodiment.

[0027] Figure 10B is a plan view of the semiconductor device of the comparative example.

[0028] Figure 11 shows the electrical characteristics of the semiconductor device of the second embodiment.

[0029] Figure 12A is a cross-sectional view of the semiconductor device of the second embodiment.

[0030] Figure 12B is a cross-sectional view of the semiconductor device of the second embodiment.

[0031] Figure 13 is a diagram showing the electrical characteristics of the semiconductor device of the second embodiment.

[0032] Figure 14A is a diagram showing the electrical characteristics of the semiconductor device of the second embodiment.

[0033] Figure 14B is a diagram showing the electrical characteristics of the semiconductor device of the second embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions are omitted. In the drawings, some configurations may be omitted or simplified for ease of explanation. In addition, at least some of the embodiments may be combined with each other arbitrarily.

[0035] In the semiconductor device of the present disclosure, the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor region, diffusion region, transistor, etc. can be inverted. Therefore, if one conductivity type of n-type and p-type is designated as the first conductivity type and the other conductivity type is designated as the second conductivity type, then the first conductivity type can be p-type and the second conductivity type can be n-type, or the first conductivity type can be n-type and the second conductivity type can be p-type.

[0036] The impurity concentration of the components included in the semiconductor device of the present disclosure refers to the peak value in the measurement region of the component. In addition, when comparing the impurity concentrations of two components, the term "substantially the same" does not mean that they are exactly the same. Even if the impurity concentrations of the two components are different due to manufacturing variations, if the set values of the impurity concentrations of the two components are the same, then the impurity concentrations of the two components are considered to be the same.

[0037] First Embodiment

[0038] As Figure 1 shown, the semiconductor device 1 includes a semiconductor substrate 10 having a first conductivity type and a plurality of regions formed in and on the semiconductor substrate 10. Figure 2 FIGS. 13 to 4 are cross-sectional views showing modified examples of the semiconductor device 1, respectively.

[0039] Examples of the semiconductor device 1 include a semiconductor chip, a semiconductor wafer, and a package. The semiconductor chip includes a Schottky barrier diode. The semiconductor wafer includes a Schottky barrier diode. The semiconductor chip or the semiconductor wafer is internally mounted in the package.

[0040] The semiconductor substrate 10 has an upper surface 11 and a lower surface 12. Hereinafter, unless otherwise specified, Figure 1 the components included in the semiconductor device 1 shown are formed on / at the upper surface 11 of the semiconductor substrate 10.

[0041] A buried region 110 having a second conductivity type opposite to the first conductivity type is formed in the semiconductor substrate 10. For example, the buried region 110 is formed by introducing impurities indicating the second conductivity type into the semiconductor substrate 10.

[0042] The first semiconductor region 100 is formed on the semiconductor substrate 10 and the buried region 110. The first semiconductor region 100 includes a first semiconductor layer 101 having a second conductivity type and a second semiconductor layer 102 disposed below the first semiconductor layer 101 and having a first conductivity type. The impurity concentration of the first semiconductor region 100 is, for example, lower than the impurity concentration of the semiconductor substrate 10 and equal to or less than the impurity concentration of the buried region 110. In addition, the impurity concentrations of the first semiconductor layer 101 and the second semiconductor layer 102 are, for example, substantially the same as each other.

[0043] The cathode region 103 having a second conductivity type is formed in the first semiconductor layer 101 of the first semiconductor region 100. The cathode region 103 is formed at the upper surface of the first semiconductor layer 101. The cathode region 103 is electrically connected to the first electrode 51, which is a contact plug formed on the cathode region 103. The impurity concentration of the cathode region 103 is, for example, higher than the impurity concentration of the first semiconductor layer 101.

[0044] The first electrode 51 is disposed on the cathode region 103. A first conductive layer 50 is formed between the cathode region 103 and the first electrode 51, and the cathode region 103 is connected to the first electrode 51 via the first conductive layer 50.

[0045] The first region 104 is formed in the first semiconductor layer 101 of the first semiconductor region 100. The first region 104 is disposed between the region in contact with the second conductive layer 60 of the first semiconductor region 100 and the cathode region 103 in a direction along the upper surface 11 of the semiconductor substrate 10. The first region 104 is formed by introducing impurities of the first conductivity type into the first semiconductor layer 101. The impurity concentration of the first region 104 is, for example, higher than the impurity concentration of the first semiconductor region 100 and lower than the impurity concentration of the cathode region 103. In addition, when the upper surface 11 of the semiconductor substrate 10 is used as a reference surface, the depth of the first region 104 is greater than the depth of the cathode region 103. It should be noted that even when the upper surface of the first semiconductor region 100 is used as a reference surface, the depth of the first region 104 is greater than the depth of the cathode region 103.

[0046] The second semiconductor region 120 is disposed on the semiconductor substrate 10 and the buried region 110 and is formed to surround the first semiconductor region 100 in a plan view. The second semiconductor region 120 has a first conductivity type, and the impurity concentration of the second semiconductor region 120 is, for example, substantially the same as the impurity concentration of the first semiconductor region 100.

[0047] In the second semiconductor region 120, an anode region 123 having a first conductivity type is formed. The anode region 123 is formed at the upper surface of the second semiconductor region 120. The anode region 123 is electrically connected to a second electrode 61, which is a contact plug formed on the anode region 123. The impurity concentration of the anode region 123 is, for example, higher than that of the second semiconductor region 120.

[0048] The second electrode 61 is disposed on the anode region 123. In addition, in a plan view, the second electrode 61 is disposed to overlap with the anode region 123. A second conductive layer 60 is formed between the anode region 123 and the second electrode 61, and the anode region 123 is connected to the second electrode 61.

[0049] The second conductive layer 60 is formed on the semiconductor substrate to contact the first semiconductor region 100 and the first region 104. In addition, an insulating layer 40 is formed between the second conductive layer 60 and the first conductive layer 50. The second conductive layer 60 and the first conductive layer 50 are electrically isolated from each other by the insulating layer 40.

[0050] A third semiconductor region 130 is disposed in the semiconductor substrate 10 and on the buried region 110, and is formed to surround the first semiconductor region 100 and the second semiconductor region 120 in a plan view. The third semiconductor region 130 has a second conductivity type, and the impurity concentration of the third semiconductor region 130 is, for example, substantially the same as those of the first semiconductor region 100 and the second semiconductor region 120.

[0051] In the third semiconductor region 130, a contact region 133 is formed, and the contact region 133 is a second region having a second conductivity type. In addition, a third conductive layer 70 (electrode pad) is formed on the contact region 133 to contact the contact region 133. The impurity concentration of the contact region 133 is, for example, higher than that of the third semiconductor region 130. On the third conductive layer 70, a third electrode (not shown) is formed, and the contact region 133 is connected to the third electrode via the third conductive layer 70.

[0052] A fourth semiconductor region 140 is formed in the semiconductor substrate 10, and is formed to surround the first semiconductor region 100, the second semiconductor region 120, and the third semiconductor region 130 in a plan view. The fourth semiconductor region 140 has a first conductivity type, and the impurity concentration of the fourth semiconductor region 140 is, for example, substantially the same as those of the first semiconductor region 100, the second semiconductor region 120, and the third semiconductor region 130.

[0053] In the fourth semiconductor region 140, a ground region 143 having a first conductivity type is formed. In addition, a fourth conductive layer 80 (electrode pad) is formed on the ground region 143 to contact the ground region 143. The impurity concentration of the ground region 143 is, for example, higher than that of the fourth semiconductor region 140.

[0054] The buried insulating layer 30 is formed in the semiconductor substrate 10. In a plan view, the buried insulating layer 30 is disposed between the second conductive layer 60 and the third conductive layer 70, and between the third conductive layer 70 and the fourth conductive layer 80. The buried insulating layer 30 is formed by forming trenches for the first conductive layer 50, the second conductive layer 60, the third conductive layer 70, and the fourth conductive layer 80 in the semiconductor substrate 10, and then filling the trenches with an insulating film.

[0055] In the semiconductor device 1 of the first embodiment, a Schottky barrier is formed between the first semiconductor region 100 and the second conductive layer 60, and the first semiconductor region 100 and the second conductive layer 60 are configured to have Figure 1 the Schottky barrier diode of the current path 20 shown. Since the first region 104 is formed in the first semiconductor layer 101 of the first semiconductor region 100, the current path 20 is arranged to be farther from the upper surface 11 than when the first region 104 is not formed. Therefore, the current path 20 is narrowed by the first region 104.

[0056] Therefore, it is possible to relax the electric field concentrated at the corner of the second conductive layer 60 (Schottky electrode) during reverse bias, and to relax the electric field extending directly below the second conductive layer 60, thereby suppressing the tunneling leakage current.

[0057] Next, a modified example of the semiconductor device 1 of the first embodiment will be described. It should be noted that the description may omit the repetition for components similar to those in the first embodiment.

[0058] Figure 2 A modified example of the first region 104 formed in the first semiconductor layer 101 of the first semiconductor region 100 is shown. Figure 2 The first region 104 surrounded by a dashed line in has a first part 105 and a second part 106. Further, in a plan view, the first part 105 is formed to surround the second part 106.

[0059] Similar to Figure 1 the first region 104 in, the first part 105 is formed by introducing impurities indicating the first conductivity type. The impurity concentration of the first part 105 is, for example, higher than the impurity concentration of the first semiconductor region 100.

[0060] Similar to the first portion 105, the second portion 106 is formed by introducing impurities of a first conductivity type. For example, the impurity concentration of the second portion 106 is higher than that of the first portion 105. Further, when the upper surface 11 of the semiconductor substrate 10 is used as a reference surface, the depth of the second portion 106 is greater than the depth of the cathode region 103. It should also be noted that even when the upper surface of the first semiconductor region 100 is used as a reference surface, the depth of the second portion 106 is greater than the depth of the cathode region 103. With this configuration, the second portion 106 acts as an electric potential barrier, allowing the current path 20 to be set farther away from the upper surface of the semiconductor substrate 10 compared to when the first region 104 is not formed. Accordingly, the current path 20 is narrowed by the second portion 106.

[0061] In addition, the first portion 105 has an offset region 107 that separates the second portion 106 from the cathode region 103 in a direction along the upper surface 11 of the semiconductor substrate 10. If only the second portion 106 were formed in the first semiconductor layer 101, the electric field could concentrate at the interface between the second portion 106 and the first semiconductor layer 101. Accordingly, by forming the first portion 105 with the offset region 107, it is possible to ensure the breakdown voltage.

[0062] Figure 3A shows Figure 1 an application example of the semiconductor device 1 shown, and Figure 3B shows Figure 2 an application example of the semiconductor device 1 shown. Compared with Figure 1 and Figure 2 compared, Figure 3A and Figure 3B show a layout in which the Schottky electrode (second conductive layer 60) is disposed inside with respect to the cathode electrode (first electrode 51). Even in this configuration, it is possible to relax the electric field between the second conductive layer 60 and the first electrode 51 during reverse bias. Accordingly, the semiconductor device 1 of the first embodiment is not limited by the layout of the Schottky electrode and the cathode electrode. Further, the first conductive layer 50 can be formed between the cathode region 103 and the first electrode 51.

[0063] Figure 4A , Figure 4B and Figure 4C are diagrams showing simulation results of the electric field strength distribution in the semiconductor device during application of a reverse bias. Figure 4A is a diagram showing the electric potential distribution of the semiconductor device 1 that does not have the first region 104 as a comparative example. Figure 4B shows Figure 1 the electric potential distribution of the semiconductor device 1 shown and Figure 4C shows Figure 2 the electric potential distribution of the semiconductor device 1 shown.

[0064] In the comparative example, as Figure 4A shown by the dashed line in, it can be seen that an electric field concentrated at the corner of the Schottky electrode (second conductive layer 60) and an electric field extending directly below the second conductive layer 60 are observed. On the other hand, in the semiconductor device 1 of the first embodiment, as Figure 4B and Figure 4C shown by the dashed line in, it can be seen that the electric field is relaxed.

[0065] Figure 5 is a diagram showing the correlation between the leakage current and the drive voltage. Figure 5 shows the simulation results (TCAD) of the semiconductor device of the comparative example, Figure 1 the simulation results of the semiconductor device of Figure 2 (Structure-1), and Figure 5 The horizontal axis of Figure 5 indicates the drive voltage Vf, while

[0066] It can be seen that, compared with the semiconductor device of the comparative example, in Figure 1 and Figure 2 the leakage current Ir is suppressed in the semiconductor devices of. On the other hand, in Figure 1 the semiconductor device of, it is found that the decreasing trend of the leakage current Ir saturates near the drive voltage Vf of 0.4V. In addition, in Figure 2 the semiconductor device of, when the leakage current Ir is suppressed, an increase in the drive voltage Vf is observed.

[0067] In order to increase the drive voltage Vf of the semiconductor device 1 in the configuration of Figure 2 FIG. 6 shows an example of modifying the arrangement of the second part 106 in the first region 104. Figure 6A shows a perspective view of a modified example of the semiconductor device 1 of the first embodiment, and Figure 6B shows a plan view of a modified example of the semiconductor device 1 of the first embodiment. In the first part 105 indicated by the dashed line in Figure 6B , when the offset region 107 is fixed, the arrangement and size of the second part 106 are changed, and simulation is performed.

[0068] Figure 7A and Figure 7B show Figure 6A and Figure 6B the simulation results of the correlation between the leakage current and the drive voltage of the semiconductor device 1 shown in. It should be noted that, in order to compare with the simulation results of the semiconductor device 1 shown in Figure 1 , Figure 7A and Figure 7BThe curve in [[]] is normalized at the specified current value of the simulation result for the second part 106 in the houndstooth pattern.

[0069] Figure 7A Shows the positional dependence when Figure 6B the lower part of the second part 106 in [[]] is fixed to the right position, while the upper part of the second part 106 is placed in the left position, the center position, and the right position. It is confirmed from Figure 7A that when the width W of the first part 105 is 0 μm, an increase in Vf is observed while suppressing Ir. On the other hand, when the width W of the first part 105 is 0.795 μm, it is found that due to the wider current path, the positional dependence of the second part 106 is relaxed.

[0070] Figure 7B Shows the dependence of the width of region 105 (which includes Figure 6B the second part 106 in the houndstooth pattern when the upper part of the second part 106 in [[]] is placed in the left position) on the width a3 of the first region 104. At point A in Figure 7B in [[]], Figure 1 a3 of the semiconductor device in the configuration (structure - 1) of [[]] is 3.3 μm, while a3 of the semiconductor device in the configuration of FIG. 6 is 1.8 μm. Therefore, compared with the configuration of Figure 2 in [[]], the configuration of FIG. 6 can reduce the leakage current Ir using a Schottky barrier diode of a smaller size. A significant advantage of the configuration of FIG. 6 is that it allows controlling the drive voltage Vf and the leakage current Ir via the width W of the first part 105 without increasing the size of the Schottky barrier diode.

[0071] Figure 8 is a plan view of the semiconductor device 1 of FIG. 6. In the plan view, the shape of the second part 106 is strip - shaped or dot - shaped. When the shape of the second part 106 is dot - shaped, the shape of the second part 106 can be square, circular, elliptical, triangular, rectangular, trapezoidal, or any polygon with five or more sides. In addition, when the shape of the second part 106 is dot - shaped, a plurality of second parts 106 can form a houndstooth pattern or a linear pattern. Moreover, in the plan view, the shape of the first part 105 can have a strip - shaped or spaced pattern, or as shown in Figure 8 it can have a shape with a gap 108 between two adjacent first parts 105.

[0072] Second Embodiment

[0073] In the second embodiment, a modified example of the semiconductor device 1 of the first embodiment is described. It should be noted that the description of components similar to those in the configuration example of the first embodiment can be omitted.

[0074] Figure 9 The semiconductor device 1 shown has an anode region 123 formed in the second semiconductor region 120, a contact region 133 formed in the third semiconductor region 130, and a wiring 90 formed on the semiconductor substrate 10. In addition, the semiconductor device 1 has a wiring 90 formed on the semiconductor substrate 10, and this wiring 90 connects the anode region 123 and the contact region 133. Thus, the second conductive layer 60 and the third conductive layer 70 are electrically connected to each other. Similar to the first embodiment, a third electrode (not shown) is formed on the third conductive layer 70, and the contact region 133 is connected to the third electrode via the third conductive layer 70. Thus, the second electrode 61 is connected to the third electrode via the wiring 90. This allows suppressing the operation of the parasitic bipolar transistor, thereby preventing leakage current from flowing in the semiconductor substrate.

[0075] In the semiconductor device of the first embodiment, it is possible to suppress leakage current without being restricted by the layout of the Schottky electrode and the cathode electrode. On the other hand, in the semiconductor device 1 of the second embodiment, from the perspective of reducing the region of the Schottky barrier diode, it is preferable that the first electrode 51 is provided in the second electrode 61 (anode electrode). Figure 10A A plan view of the semiconductor device 1 of the second embodiment is shown, and Figure 10B A plan view of a semiconductor device as a comparative example is shown, in which the second electrode 61 is provided inside the first electrode 51. By positioning the cathode electrode (first electrode 51) inside the anode electrode (second electrode 61), it is possible to reduce the region of the Schottky barrier diode. In addition, it is possible to increase the degree of freedom of the layout by reducing the number of wirings.

[0076] Figure 11 A forward waveform of the electrical characteristics of the Schottky barrier diode of the semiconductor device 1 of this embodiment is shown. The drive voltage Vf at a conduction current Ia of 1 μA is 0.39 V, which indicates good electrical characteristics.

[0077] Figure 12A and Figure 12B A modified example of the semiconductor device 1 according to the second embodiment is shown. Figure 12A A configuration is shown in which a metal silicide layer 91 is formed on the first region 104. In addition to the Schottky barrier diode, the semiconductor substrate 10 may also have a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed thereon. Since the metal silicide layer 91 can be formed using the mask for introducing the drift layer of the LDMOSFET around the Schottky barrier diode, the metal silicide layer 91 can be formed without increasing the number of masks.

[0078] Figure 13It is a view showing the simulation result of the electric field intensity distribution in a semiconductor device when a reverse bias is applied. By positioning the end of the metal silicide layer 91 between the first region 104 and the cathode region 103 in a plan view, it is possible to relax the electric field, thereby increasing the breakdown voltage of the Schottky barrier diode.

[0079] Figure 12B It shows the configuration of forming a buried insulating layer 92, which is an insulating region that penetrates the first region 104 and surrounds the first region 104. When the upper surface 11 of the semiconductor substrate 10 is used as a reference surface, it is preferable that the depth of the buried insulating layer 92 is greater than the depth of the first region 104. By forming the buried insulating layer 92, it is possible to narrow the current path 20. In addition, the buried insulating layer 92 can be formed in the same process as the buried insulating layer 30.

[0080] Figure 14A It shows the forward waveform of the electrical characteristics of the Schottky barrier diode of the semiconductor device 1 of the second embodiment. It has been found that when the conduction current Ia is 1 μA, the device has good electrical characteristics at a drive voltage Vf of 0.31 V.

[0081] Figure 14B It shows the reverse waveform of the electrical characteristics of the Schottky barrier diode of the semiconductor device 1 of the second embodiment. When 25 V is applied to the Schottky barrier diode, the leakage current Ir is lower than the specified value shown by the dotted line, and the breakdown voltage BV is 37 V. Therefore, it has been found that the Schottky barrier diode of the semiconductor device 1 of the second embodiment has sufficient resistance.

[0082] Therefore, by combining the configuration of the second embodiment, it is possible to provide a semiconductor device capable of further suppressing leakage current.

[0083] As described above, the invention made by the inventors has been specifically explained based on the embodiments. However, it goes without saying that the present disclosure is not limited to the embodiments that have been mentioned, and various changes can be made without departing from the gist of the present disclosure.

Claims

1. A semiconductor device, comprising: a semiconductor substrate having an upper surface; A first semiconductor region formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view; A first conductive layer is formed on the first semiconductor region; A first electrode is formed on the first conductive layer; a cathode region formed in the first semiconductor region and connected to the first electrode via the first conductive layer; a second conductive layer formed on and in contact with the first semiconductor region; a second electrode formed on the second conductive layer; as well as a first region formed in the first semiconductor region and in contact with a lower surface of the second conductive layer, the first region being disposed between a region in contact with the second conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, wherein when the upper surface of the semiconductor substrate is used as a reference surface, the depth of the first region is greater than the depth of the cathode region, wherein the semiconductor substrate, the second semiconductor region and the first region each have a first conductivity type, and The first semiconductor region and the cathode region each have a second conductivity type opposite to the first conductivity type.

2. The semiconductor device according to claim 1, wherein the first region comprises a first portion and a second portion, wherein when the upper surface of the semiconductor substrate is used as a reference surface, the depth of the second portion is greater than the depth of the cathode region and the depth of the first portion, wherein the first portion includes an offset region, the offset region separating the second portion from the cathode region in the direction along the upper surface of the semiconductor substrate, wherein the offset region is disposed between the cathode region and the second portion, and The impurity concentration of the second portion is higher than the impurity concentration of the first portion.

3. The semiconductor device according to claim 1, The first semiconductor region and the second conductive layer configure a Schottky barrier diode.

4. The semiconductor device according to claim 3, The first semiconductor region comprises: a first semiconductor layer having the second conductivity type; as well as a second semiconductor layer disposed below the first semiconductor layer and having the first conductivity type, and A current path of the Schottky barrier diode is formed in the first semiconductor layer and is narrowed by the first region.

5. The semiconductor device according to claim 2, wherein the shape of the second portion in a plan view is a strip or a dot, and Wherein when the shape of the second portion in a plan view is a dot shape, the shape of the first portion is one of a circle, an ellipse, a triangle, a square, a rectangle, a trapezoid, or a polygon with five or more sides.

6. The semiconductor device according to claim 5, Wherein when the shape of the second portion in a plan view is a dot shape, the second portion includes a plurality of second portions, and the plurality of second portions form a houndstooth pattern or a linear pattern.

7. The semiconductor device according to claim 5, The first portion is shaped like a strip or has a spaced pattern in a plan view.

8. The semiconductor device according to claim 1, further comprising: a buried region formed in the semiconductor substrate, the buried region being disposed below the first semiconductor region and the second semiconductor region, and the buried region having the second conductivity type; as well as a third semiconductor region formed in the semiconductor substrate, the third semiconductor region surrounding the first semiconductor region and the second semiconductor region in a plan view, and the third semiconductor region having the second conductivity type, wherein the third semiconductor region is connected to the buried region.

9. The semiconductor device according to claim 8, further comprising: A third conductive layer is formed on the third semiconductor region; a third electrode formed on the third conductive layer; as well as a second region formed in the third semiconductor region and connected to the third electrode via the third conductive layer, wherein the impurity concentration of the second region is higher than the impurity concentration of the third semiconductor region, and The second electrode and the third electrode are connected to each other via a wiring.

10. The semiconductor device according to claim 9, further comprising: The metal silicide layer is located between the first electrode and the first conductive layer.

11. The semiconductor device according to claim 9, further comprising: an insulating region, arranged to surround the first region in a plan view, Wherein when the upper surface of the semiconductor substrate is used as a reference surface, the depth of the insulating region is greater than the depth of the first region.

12. The semiconductor device according to claim 1, further comprising: an anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer; as well as an insulating layer formed between the first conductive layer and the second conductive layer, wherein the second conductive layer is formed on the first semiconductor region and the second semiconductor region, wherein the first region is formed to surround the cathode region and is disposed below the insulating layer and below the second conductive layer, and In a plan view, the second electrode is arranged to overlap with the anode region.

13. The semiconductor device according to claim 1, further comprising: an anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer; as well as an insulating layer formed between the first electrode and the second conductive layer, wherein the cathode region is formed to surround the first region, wherein the first region is disposed below the insulating layer and below the second conductive layer, and In a plan view, the second electrode is arranged to overlap with the anode region.

14. A semiconductor device comprising: a semiconductor substrate having an upper surface; A first semiconductor region formed in the semiconductor substrate; a second semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region in a plan view; A first conductive layer is formed on the first semiconductor region; A first electrode is formed on the first conductive layer; a cathode region formed in the first semiconductor region and connected to the first electrode via the first conductive layer; A second conductive layer is formed on the first semiconductor region and the second semiconductor region, the second conductive layer is in contact with the first semiconductor region; a second electrode formed on the second conductive layer; an anode region formed in the second semiconductor region and connected to the second electrode via the second conductive layer; a first region formed in the first semiconductor region and disposed between the cathode region and the second semiconductor region in a direction along the upper surface of the semiconductor substrate, the first region being in contact with a lower surface of the second conductive layer; a buried region formed in the semiconductor substrate and disposed below the first semiconductor region and below the second semiconductor region; a third semiconductor region formed in the semiconductor substrate and surrounding the first semiconductor region and the second semiconductor region in a plan view; A third conductive layer is formed on the third semiconductor region; a third electrode formed on the third conductive layer; as well as a second region formed in the third semiconductor region and connected to the third electrode via the third conductive layer, wherein when the upper surface of the semiconductor substrate is used as a reference surface, the depth of the first region is greater than the depth of the cathode region, wherein the semiconductor substrate, the second semiconductor region, the anode region and the first region each have a first conductivity type, wherein the first semiconductor region, the cathode region, the buried region and the third semiconductor region each have a second conductivity type opposite to the first conductivity type, wherein the third semiconductor region is connected to the buried region, wherein the impurity concentration of the second region is higher than the impurity concentration of the third semiconductor region, and The second electrode and the third electrode are connected to each other via a wiring.

15. The semiconductor device according to claim 14, The first semiconductor region and the second conductive layer configure a Schottky barrier diode.

16. The semiconductor device according to claim 15, The first semiconductor region comprises: a first semiconductor layer having the second conductivity type; as well as a second semiconductor layer disposed below the first semiconductor layer and having the first conductivity type, and A current path of the Schottky barrier diode is formed in the first semiconductor layer and is narrowed by the first region.

17. The semiconductor device according to claim 14, further comprising: The metal silicide layer is located between the first electrode and the first conductive layer.

18. The semiconductor device according to claim 14, further comprising: an insulating region, arranged to surround the first region in a plan view, Wherein when the upper surface of the semiconductor substrate is used as a reference surface, the depth of the insulating region is greater than the depth of the first region.

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