Metal-oxide-semiconductor field effect transistor (MOSFET) device and manufacturing method

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) device and a manufacturing method, the MOSFET device comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a dielectric layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a load P + layer, a P well layer and an N well layer, the P-well layer comprises a first P-well layer and a second P-well layer, and the section contours of the first P-well layer and the second P-well layer are L-shaped; a conducting medium is arranged between the first P well layer and the second P well layer, the grid electrode further comprises a U-shaped grid, an opening of the U-shaped grid faces downwards, and the opening of the U-shaped grid is filled with a high-K medium. According to the invention, the U-shaped gate structure is filled with the high-k medium, so that the control area of the gate to the channel is increased, the leakage current is remarkably reduced, high gate capacitance is maintained, and the switching speed and the energy efficiency ratio of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a MOSFET device and a manufacturing method thereof. Background Art

[0002] With the continuous reduction of the size of semiconductor devices, traditional SiO2 gate dielectrics face serious leakage current and power consumption problems in MOSFETs, resulting in a decline in device performance. High-k dielectric materials, due to their higher dielectric constants, can provide a thicker physical layer thickness at the same equivalent oxide thickness (EOT), thereby significantly suppressing gate leakage current. However, in the prior art, the integration of high-k materials is often accompanied by problems such as an increase in interface state density and a decrease in carrier mobility. Therefore, there is an urgent need for an innovative device structure and manufacturing method to solve the above technical bottlenecks by optimizing the co-design of high-k dielectrics with the well region and the drift region.

[0003] A prior patent discloses a high-performance SGT MOSFET device (CN216597598U), and the key points of its technical solution are: including a MOSFET device body, the MOSFET device body is virtually divided into a Cell region and a Ring region, the bottom of the MOSFET device body is provided with an N+ substrate layer, an epi1 layer is provided on the upper part of the N+ substrate layer, and an epi2 layer is provided on the upper part of the epi1 layer. In the technology disclosed in this patent, it is difficult to balance the requirements of low on-resistance and high breakdown voltage in the well region and the drift region of the MOSFET, which restricts the performance of the device in high-power and high-frequency applications. Summary of the Invention

[0004] The present invention provides a MOSFET device and a manufacturing method to solve the existing technical problems and solve the problems in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a MOSFET device includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a source, a gate, a dielectric layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a load P+ layer, a P well layer, and an N well layer. The P well layer includes a P well layer 1 and a P well layer 2, and the cross-sectional profiles of the P well layer 1 and the P well layer 2 are both in an "L" shape; a conductive medium is provided between the P well layer 1 and the P well layer 2.

[0006] Furthermore, the gate further includes a U-shaped gate, and the opening of the U-shaped gate faces downward.

[0007] Furthermore, the opening of the U-shaped gate is filled with a high-K dielectric.

[0008] Further, the load P+ layer further includes a bottle-shaped P+ layer. The cross-sectional profile of the bottle-shaped P+ layer is shaped like a thin top and a round middle, and the bottom end of the bottle-shaped P+ layer is in contact with the N substrate layer.

[0009] Further, a wide-mouth N heavily doped layer is formed by ion implantation in the middle of the N drift layer. The bottom end of the wide-mouth N heavily doped layer is in contact with the N substrate layer, and the top end of the wide-mouth N heavily doped layer extends to the bottom end of the gate.

[0010] Further, a narrow-mouth N heavily doped layer is formed by ion implantation in the middle of the N drift layer. The cross-sectional width of the narrow-mouth N heavily doped layer does not exceed that of the P-well layer 1, and the bottom end of the narrow-mouth N heavily doped layer is in contact with the N substrate layer.

[0011] A manufacturing method of a MOSFET device includes: S1. Providing an N-type semiconductor substrate layer as the basic structure of the device; S2. Epitaxially growing an N drift layer on the N substrate layer to form a low-doped drift region; S3. Through ion implantation and annealing processes, forming a P-well layer 1 and a P-well layer 2 with an "L"-shaped cross-section in the N drift layer, and filling a conductive medium between the P-well layers; S4. Forming a load P+ layer and a bottle-shaped P+ layer by ion implantation, where the bottle-shaped P+ layer has a cross-sectional shape with a thin top and a round middle and is in contact with the N substrate layer; S5. Injecting high-concentration N-type impurities into the middle region of the N drift layer to form a wide-mouth N heavily doped layer and a narrow-mouth N heavily doped layer, which are respectively in contact with the N substrate layer and extend to the bottom of the gate; S6. Etching to form a U-shaped gate structure with an opening downward, and filling a high-K medium in the opening of the U-shaped gate; S7. Through photolithography, deposition, and etching processes, respectively forming metal contacts for the drain, source, and gate.

[0012] Further, in the step S6, the filled high-K medium includes hafnium dioxide or aluminum oxide.

[0013] Further, in the step S7, the MOSFET device forming the drain, source, and gate is subjected to high-temperature annealing to activate the doped ions, and a passivation layer is deposited to protect the device surface.

[0014] A MOSFET device and a manufacturing method provided by the present invention, compared with the prior art, the effects obtained by this method are: 1. By filling a high-k medium through the U-shaped gate structure in the present invention, the control area of the gate over the channel is increased, the leakage current is significantly reduced, and at the same time, a high gate capacitance is maintained, improving the switching speed and energy efficiency ratio of the device.

[0015] 2. The present invention adopts a P-well layer with an "L"-shaped cross-section and an intermediate conductive medium, which improves the electric field distribution, reduces the on-resistance, enhances the carrier migration efficiency, and thus improves the current driving ability.

[0016] 3. The present invention optimizes the contact resistance with the substrate through the cross-section design of the bottle-shaped P+ layer with a thin top and a round middle, reduces the on-loss, and improves the current-carrying capacity.

[0017] 4. The present invention precisely controls the conductivity and electric field distribution of the drift region through the step-by-step implantation technology of the wide-mouth and narrow-mouth N-multiple doped layers, taking into account both the low on-voltage drop and the high breakdown voltage.

[0018] 5. Through the collaborative optimization of the ion implantation and annealing processes, the present invention reduces the parasitic capacitance and process errors, enhances the device stability and reliability, and is applicable to high-performance and low-power semiconductor application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the first embodiment of the present invention; Figure 2 It is a schematic diagram of the second embodiment of the present invention; Figure 3 It is a schematic diagram of the third embodiment of the present invention; Figure 4 It is a schematic diagram of the fourth embodiment of the present invention; Figure 5 It is a schematic diagram of the fifth embodiment of the present invention; Figure 6 It is a schematic diagram of the sixth embodiment of the present invention; Figure 7 It is a comparison diagram of the drain current between the first embodiment of the present invention and the traditional structure; Figure 8 It is a comparison diagram of the breakdown voltage between the first embodiment of the present invention and the traditional structure.

[0020] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Dielectric layer; 5. N-substrate layer; 6. N-drift layer; 7. Load P+ layer; 8. P-well layer 1; 9. P-well layer 2; 10. N-well layer; 11. Conductive medium; 12. High-K dielectric; 13. Wide-mouth N-multiple doped layer; 14. Narrow-mouth N-multiple doped layer; 31. U-shaped gate; 71. Bottle-shaped P+ layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0022] As Figure 1-6 shown, a manufacturing method of a MOSFET device includes: Step 1: Provide an N-type semiconductor substrate layer 5 as the basic structure of the device; Step 2: Epitaxially grow an N-drift layer 6 on the N-substrate layer 5 to form a low-doped drift region; Step 3: Through ion implantation and annealing processes, form a P-well layer 8 and a P-well layer 9 with an "L"-shaped cross-section in the N-drift layer 6, and fill a conductive medium 11 between the P-well layers; By designing the L-shaped P-well layer and filling the conductive medium, the process complexity is simplified, and at the same time, the structural stability of the well region is improved.

[0023] Step 4: Form a load P+ layer 7 and a bottle-shaped P+ layer 71 through ion implantation, where the bottle-shaped P+ layer 71 has a cross-sectional shape that is thin at the top and round in the middle and contacts the N-substrate layer 5; The special cross-sectional shape of the bottle-shaped P+ layer 71 is achieved through ion implantation, precisely controlling the doping distribution and reducing process errors.

[0024] Step 5: Inject high-concentration N-type impurities into the middle region of the N-drift layer 6 to form a wide-mouth N-heavily doped layer 13 and a narrow-mouth N-heavily doped layer 14, which respectively contact the N-substrate layer 5 and extend to the bottom of the gate; The step-by-step injection of the wide-mouth and narrow-mouth N-heavily doped layers respectively optimizes the conductivity and electric field distribution of the drift region, improving the breakdown performance.

[0025] Step 6: Etch to form a U-shaped gate 31 structure with an opening downward, and fill a high-K dielectric 12 inside the U-shaped gate opening; The U-shaped gate 31 structure combined with the filling of the high-k dielectric 12 significantly improves the gate 3 control efficiency, reduces the leakage current, and is suitable for high-performance low-power scenarios. And the high-K dielectric 12 filled in this step includes hafnium dioxide or aluminum oxide.

[0026] Step 7: Through photolithography, deposition, and etching processes, form metal contacts for the drain 1, source 2, and gate 3 respectively. And in this step, the MOSFET device forming the drain 1, source 2, and gate 3 is subjected to high-temperature annealing to activate the doping ions, and a passivation layer is deposited to protect the device surface.

[0027] Example 1 As Figure 1 、 7, as shown in Figure 8, according to one aspect of the present invention, a MOSFET device is provided, which is composed of a plurality of juxtaposed MOS cells. A single MOS cell includes a drain 1, a source 2, a gate 3, a dielectric layer 4, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 5, an N drift layer 6, a load P+ layer 7, a P well layer, and an N well layer 10. The P well layer includes a P well layer 8 and a P well layer 9, and the cross-sectional profiles of both the P well layer 8 and the P well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the P well layer 8 and the P well layer 9. Through the P well layer 8 and the P well layer 9 with an L-shaped cross-section and the intermediate conductive medium 11, a unique well region structure is formed, thereby optimizing the electric field distribution in the well region, reducing the on-resistance, enhancing the carrier migration efficiency, and improving the current driving ability of the device.

[0028] Embodiment 2 As Figure 2 shown, the P well layer includes a P well layer 8 and a P well layer 9, and the cross-sectional profiles of both the P well layer 8 and the P well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the P well layer 8 and the P well layer 9. The gate 3 further includes a U-shaped gate 31, where the opening of the U-shaped gate 31 faces downward. By introducing the U-shaped gate 31 structure with a downward opening, the control area of the gate over the channel is increased, the gate control ability is improved, the threshold voltage is reduced, and the switching speed is increased.

[0029] Embodiment 3 As Figure 3 shown, the P well layer includes a P well layer 8 and a P well layer 9, and the cross-sectional profiles of both the P well layer 8 and the P well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the P well layer 8 and the P well layer 9. The gate 3 further includes a U-shaped gate 31, where the opening of the U-shaped gate 31 faces downward, and a high-K dielectric 12 is filled in the opening of the U-shaped gate 31. By filling the high-k dielectric 12 (such as hafnium dioxide or aluminum oxide) in the opening of the U-shaped gate, taking advantage of the dielectric constant of the high-k material, the gate leakage current is significantly reduced, a relatively high gate capacitance is maintained, and the energy efficiency ratio of the device is enhanced.

[0030] In the fabrication of MOSFET devices, the high-K dielectric refers to an insulating material with a dielectric constant (the dielectric constant is the K value) greater than that of traditional silicon dioxide, which is used to increase the breakdown resistance when traditional silicon dioxide is used as the dielectric layer 4.

[0031] Embodiment 4 As Figure 4As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, and the cross-sectional profiles of both the first P-well layer 8 and the second P-well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the first P-well layer 8 and the second P-well layer 9. The load P+ layer 7 further includes a bottle-shaped P+ layer 71, the cross-sectional profile of the bottle-shaped P+ layer 71 is in the shape of a narrow top and a round middle, and the bottom end of the bottle-shaped P+ layer 71 is in contact with the N-substrate layer 5. By designing the bottle-shaped P+ layer 71, which has a narrow top, a round middle, and is in contact with the N-substrate layer 5, the contact resistance between the P+ layer and the substrate is optimized, the overall conduction loss is reduced, the carrier injection efficiency is improved, and the current-carrying capacity of the device is enhanced.

[0032] Embodiment 5 As Figure 5 shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, and the cross-sectional profiles of both the first P-well layer 8 and the second P-well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the first P-well layer 8 and the second P-well layer 9. A wide-mouth N-heavily doped layer 13 is formed by ion implantation at the middle of the N-drift layer 6, the bottom end of the wide-mouth N-heavily doped layer 13 is in contact with the N-substrate layer 5, and the top end of the wide-mouth N-heavily doped layer 13 extends to the bottom end of the gate 3. By forming the wide-mouth N-heavily doped layer 13 in the middle of the N-drift layer 6 and extending it to the bottom of the gate, the conductivity of the drift region is enhanced, the conduction voltage drop is reduced, and the breakdown voltage is increased by extending the electric field distribution through the heavily doped layer.

[0033] Embodiment 6 As Figure 6 shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, and the cross-sectional profiles of both the first P-well layer 8 and the second P-well layer 9 are in the shape of an "L"; a conductive medium 11 is provided between the first P-well layer 8 and the second P-well layer 9. The load P+ layer 7 further includes a bottle-shaped P+ layer 71, the cross-sectional profile of the bottle-shaped P+ layer 71 is in the shape of a narrow top and a round middle, and the bottom end of the bottle-shaped P+ layer 71 is in contact with the N-substrate layer 5. A narrow-mouth N-heavily doped layer 14 is formed by ion implantation at the middle of the N-drift layer 6, the cross-sectional width of the narrow-mouth N-heavily doped layer 14 does not exceed that of the first P-well layer 8, and the bottom end of the narrow-mouth N-heavily doped layer 14 is in contact with the N-substrate layer 5. By combining the bottle-shaped P+ layer 71 with the narrow-mouth N-heavily doped layer 14, the latter's width not exceeding that of the first P-well layer 8, the narrow-mouth design precisely controls the doping region, reduces the parasitic capacitance, synergistically optimizes the P+ layer and the N-heavily doped layer, and further reduces the dynamic loss and enhances the reliability.

[0034] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A MOSFET device, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a source (2), a gate (3), a dielectric layer (4) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), a load P+ layer (7), a P well layer and an N well layer (10), characterized in that: The P-well layer comprises a first P-well layer (8) and a second P-well layer (9), and the cross-sectional profiles of the first P-well layer (8) and the second P-well layer (9) are both in an "L" shape; a conductive medium (11) is provided between the first P-well layer (8) and the second P-well layer (9).

2. The MOSFET device according to claim 1, characterized in that: The grid (3) further comprises a U-shaped grid (31), wherein the opening of the U-shaped grid (31) faces downward.

3. The MOSFET device according to claim 2, characterized in that: The opening of the U-shaped gate (31) is filled with a high-K medium (12).

4. The MOSFET device according to claim 1, characterized in that: The load P+ layer (7) further comprises a bottle-shaped P+ layer (71), the cross-sectional profile of the bottle-shaped P+ layer (71) being in the shape of a thin top and a round middle, and the bottom end of the bottle-shaped P+ layer (71) is in contact with the N substrate layer (5).

5. The MOSFET device according to claim 1, characterized in that: A wide-mouth N heavily doped layer (13) is formed in the middle of the N drift layer (6) by ion implantation, the bottom of the wide-mouth N heavily doped layer (13) is in contact with the N substrate layer (5), and the top of the wide-mouth N heavily doped layer (13) extends to the bottom of the gate (3).

6. The MOSFET device according to claim 4, characterized in that: A beam-mouth N heavily doped layer (14) is formed in the middle of the N drift layer (6) by ion implantation, the cross-sectional width of the beam-mouth N heavily doped layer (14) does not exceed one layer of the P well (8), and the bottom end of the beam-mouth N heavily doped layer (14) is in contact with the N substrate layer (5).

7. A method for manufacturing a MOSFET device, characterized in that: The device according to any one of claims 1 to 6, wherein the manufacturing method comprises: S1, providing an N-type semiconductor substrate layer (5) as a basic structure of the device; S2, epitaxially growing an N drift layer (6) on the N substrate layer (5) to form a low-doped drift region; S3, forming a P-well layer (8) and a P-well layer (9) having an "L"-shaped cross section in the N-drift layer (6) through ion implantation and annealing processes, and filling a conductive medium (11) between the P-well layers; S4, forming a load P+ layer (7) and a bottle-shaped P+ layer (71) by ion implantation, wherein the bottle-shaped P+ layer (71) has a cross-sectional shape with a thin top and a round middle, and is in contact with the N substrate layer (5); S5, injecting high-concentration N-type impurities into the middle region of the N drift layer (6) to form a wide-mouth N heavily doped layer (13) and a narrow-mouth N heavily doped layer (14), which are in contact with the N substrate layer (5) and extend to the bottom of the gate; S6, etching to form a U-shaped gate (31) structure with an opening downward, and filling the U-shaped gate opening with a high-K dielectric (12); S7. Form metal contacts of the drain (1), the source (2) and the gate (3) respectively through photolithography, deposition and etching processes.

8. The method for manufacturing a MOSFET device according to claim 7, wherein: In the step S6, the filled high-K dielectric (12) includes hafnium dioxide or aluminum oxide.

9. The method for manufacturing a MOSFET device according to claim 7, wherein: In step S7, the MOSFET device having the drain (1), the source (2) and the gate (3) is subjected to high temperature annealing to activate the doped ions, and a passivation layer is deposited to protect the device surface.

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