Vertical charge transfer imaging device and manufacturing method thereof

Abstract

The invention relates to a vertical charge transfer imaging device and a manufacturing method thereof. In the vertical charge transfer imaging device, a gate dielectric layer is at least located between a floating gate and a charge reading area of a pixel area below, at least part of a photosensitive area of the pixel area is not covered by the gate dielectric layer and is exposed, and the floating gate makes contact with the surface of the exposed photosensitive area so as to be electrically connected with a substrate of the photosensitive area. Compared with the condition that the floating gate and the substrate of the photosensitive region are isolated by a gate dielectric layer to form a capacitor, the floating gate and the substrate of the photosensitive region are electrically connected so as to be equipotential, and the capacitor between the floating gate and the substrate of the photosensitive region is no longer arranged between the control gate and the substrate of the photosensitive region; the capacitance value of the total capacitance, namely the gate lining capacitance, between the control gate and the substrate of the photosensitive area is increased, so that the full well charge of the pixel is increased, and the signal-to-noise ratio of the image and the quality of the image are improved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technologies, and particularly to a vertically charge transferring imaging device and a manufacturing method thereof. Background Art

[0002] A vertically charge transferring pixel sensor (VPS) is an image sensor that uses a substrate and a floating gate transistor structure to achieve imaging. The pixels of the vertically charge transferring imaging device generally include a photosensitive region and a charge reading region arranged in the substrate, and a gate structure located on the substrate. The gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked in sequence on the substrate. The gate structure forms a gate-substrate capacitance with the substrate of the photosensitive region, and forms a reading transistor with the source region and the drain region formed in the charge reading region. When the device operates, exposure is first performed. Specifically, a suitable bias voltage is applied across the gate-substrate capacitance to form a depletion region in the substrate. The photoelectrons generated when light is incident into the substrate are collected on the surface of the photosensitive region under the action of the electric field of the depletion region. Then, by detecting the change in the drain current and / or threshold voltage of the reading transistor, the photoelectrons are read, thereby realizing photoelectric sensing.

[0003] Compared with traditional photodiode-based sensor devices (such as CMOS image sensors), the number of transistors in the pixels of the vertically charge transferring imaging device is less, and it has obvious advantages in pixel miniaturization. However, currently, the full well charge (the maximum number of photoelectrons that can be collected during the exposure stage) of the vertically charge transferring imaging device is still low, resulting in a low image signal-to-noise ratio and affecting the improvement of image quality. Summary of the Invention

[0004] In order to increase the full well charge of the vertically charge transferring imaging device, improve the image signal-to-noise ratio and image quality, the present invention provides a vertically charge transferring imaging device and a manufacturing method thereof.

[0005] On the one hand, the present invention provides a vertically charge transferring imaging device, which includes:

[0006] A substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each pixel region;

[0007] A gate dielectric layer covering at least the surface of the charge reading region and exposing a part of the photosensitive region;

[0008] A floating gate is formed corresponding to the pixel region and spans from above the photosensitive region to above the charge reading region. The gate dielectric layer is at least located between the charge reading region and the floating gate. The floating gate contacts the exposed photosensitive region to be electrically connected to the substrate of the photosensitive region;

[0009] An inter-gate dielectric layer is stacked on the surface of the floating gate; and

[0010] A control gate is stacked on the surface of the inter-gate dielectric layer.

[0011] Optionally, the floating gate includes a first floating gate portion located on the gate dielectric layer and the second isolation structure and a second floating gate portion located on the exposed photosensitive region. The arrangement direction of the first floating gate portion and the second floating gate portion is parallel to the surface of the pixel region.

[0012] Optionally, the first floating gate portion and the second floating gate portion are an integrally formed structure.

[0013] Optionally, the first floating gate portion and the second floating gate portion are two non-integrally formed parts.

[0014] Optionally, both the first floating gate portion and the second floating gate portion are made of polysilicon; or, the first floating gate portion is made of polysilicon and the second floating gate portion includes single crystal silicon.

[0015] Optionally, the gate dielectric layer also covers a partial surface of the photosensitive region and surrounds the exposed region of the photosensitive region.

[0016] Optionally, the substrate has a first conductivity type doping and the floating gate has a second conductivity type doping.

[0017] On the one hand, the present invention provides a manufacturing method of a vertical charge transfer imaging device. The manufacturing method includes:

[0018] Providing a substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each of the pixel regions;

[0019] Forming a gate dielectric layer on the surfaces of the photosensitive region and the charge reading region;

[0020] Forming a first floating gate material layer on the substrate. The first floating gate material layer spans from above the photosensitive region of the pixel region to above the charge reading region. The gate dielectric layer is between the first floating gate material layer and the photosensitive region and between the first floating gate material layer and the charge reading region;

[0021] Remove a portion of the first floating gate material layer and a portion of the gate dielectric layer to form an opening exposing at least a portion of the photosensitive region;

[0022] Fill the opening with a second floating gate material layer, the second floating gate material layer contacting the substrate of the photosensitive region and the first floating gate material layer respectively;

[0023] Form a floating gate material layer corresponding to the pixel region, the floating gate material layer including the first floating gate material layer and the second floating gate material layer;

[0024] Stack an inter-gate dielectric material layer and a control gate material layer on the substrate in sequence; and

[0025] Pattern the floating gate material layer, the inter-gate dielectric material layer, and the control gate material layer, form a control gate from the control gate material layer, form an inter-gate dielectric layer from the inter-gate dielectric material layer, and form a floating gate from the floating gate material layer, wherein the floating gate contacts the photosensitive region through the opening to be electrically connected to the substrate of the photosensitive region.

[0026] Optionally, the top surface of the first isolation structure is higher than the top surfaces of the second isolation structure and the photosensitive region; after filling the opening with the second floating gate material layer, the top surface of the first floating gate material layer and / or the second floating gate material layer is higher than the top surface of the first isolation structure; forming the floating gate material layer corresponding to the pixel region includes: performing a planarization process to expose the surface of the first isolation structure, and the remaining first floating gate material layer and second floating gate material layer form the floating gate material layer.

[0027] Optionally, fill the opening with a second floating gate material layer by using an epitaxial process or a chemical vapor deposition process.

[0028] On the one hand, the present invention provides a manufacturing method of a vertical charge transfer imaging device, the manufacturing method including:

[0029] Provide a substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each pixel region;

[0030] Form a gate dielectric layer on the surfaces of the photosensitive region and the charge reading region;

[0031] Remove a portion of the gate dielectric layer to expose at least a portion of the photosensitive region;

[0032] Form a floating gate material layer corresponding to the pixel region, the floating gate material layer spanning from above the photosensitive region to above the charge reading region, the floating gate material layer contacting the exposed photosensitive region;

[0033] Stack the inter-gate dielectric material layer and the control gate material layer on the substrate in sequence; and

[0034] Pattern the floating gate material layer, the inter-gate dielectric material layer and the control gate material layer, form a control gate from the control gate material layer, form an inter-gate dielectric layer from the inter-gate dielectric material layer, and form a floating gate from the floating gate material layer. Wherein, the floating gate contacts the photosensitive area to be electrically connected to the substrate of the photosensitive area.

[0035] Optionally, the top surface of the first isolation structure is higher than the top surfaces of the second isolation structure and the photosensitive area; forming the floating gate material layer includes:[[]]

[0036] Deposit polysilicon material, the polysilicon material covers the substrate and contacts the exposed photosensitive area; and

[0037] Perform a planarization process to expose the surface of the first isolation structure, and the remaining polysilicon material forms the floating gate material layer.

[0038] According to the vertical charge transfer imaging device and the manufacturing method of the vertical charge transfer imaging device provided by the present invention, the gate dielectric layer is at least located between the floating gate and the charge reading area of the underlying pixel area, at least part of the photosensitive area is not covered by the gate dielectric layer and is exposed, the floating gate contacts the exposed photosensitive area to be electrically connected to the substrate of the photosensitive area. Compared with the case where a capacitor is formed by isolating the floating gate from the substrate of the photosensitive area by the gate dielectric layer, the present invention electrically connects the floating gate and the substrate of the photosensitive area to make them at the same potential, and there is no longer the capacitor between the control gate and the substrate of the photosensitive area that exists between the floating gate and the substrate of the photosensitive area, which helps to increase the total capacitance between the control gate and the substrate of the photosensitive area, that is, the capacitance value of the gate-substrate capacitance, and further helps to increase the full well charge of the pixel, improve the image signal-to-noise ratio and the image quality. Description of the Drawings

[0039] Figure 1 is a schematic cross-sectional view of a vertical charge transfer imaging device.

[0040] Figure 2 is Figure 1 a schematic diagram of the capacitance distribution in the vertical charge transfer imaging device shown.

[0041] Figure 3 is a schematic flow chart of the manufacturing method of the vertical charge transfer imaging device according to Embodiment 1 of the present invention.

[0042] Figures 4A to 4J is a schematic cross-sectional view of the manufacturing method of the vertical charge transfer imaging device according to Embodiment 1 of the present invention.

[0043] Figure 5 It is a schematic flow chart of a manufacturing method of a vertical charge transfer imaging device according to the second embodiment of the present invention.

[0044] Figures 6A to 6D It is a schematic cross-sectional view of a manufacturing method of a vertical charge transfer imaging device according to the second embodiment of the present invention. Detailed implementation manners

[0045] The vertical charge transfer imaging device and its manufacturing method of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the embodiments of the present invention. The embodiments of the present invention should not be considered limited to the specific shapes shown in the figures, but may include the actually obtained shapes, such as deviations caused by manufacturing.

[0046] Referring to Figure 1 and Figure 2 , a pixel of a vertical charge transfer imaging device includes a photosensitive region 10 and a charge reading region 20 arranged in a substrate 100, and a gate structure located on the substrate 100. The gate structure includes a gate dielectric layer 101, a floating gate FG, an inter-gate dielectric layer 103, and a control gate CG stacked in sequence on the substrate 100. The gate structure forms a gate-substrate capacitance with the substrate 100 of the photosensitive region 10 and forms a reading transistor with the source region and the drain region (not shown in the figure) formed in the charge reading region 20. And, the control gate CG, the floating gate FG, and the inter-gate dielectric layer 103 therebetween constitute a first capacitor C ONO , the floating gate FG, the substrate 100 of the photosensitive region 10, and the gate dielectric layer 101 therebetween constitute a second capacitor C OX , there is a third capacitor C in the depletion region of the substrate 100 of the photosensitive region 10 Dep , the floating gate FG, the substrate 100 of the charge reading region 20, and the gate dielectric layer 101 therebetween constitute a fourth capacitor C TOX . Thus, the gate-substrate capacitance formed by the gate structure and the substrate 100 of the photosensitive region 10 is the series capacitance of the first capacitor C ONO and the second capacitor C OX .

[0047] Such as Figure 1In the vertical charge transfer imaging device shown, to increase the maximum number of photoelectrons that can be collected during the exposure stage, i.e., to increase the full well charge, one method is to increase the voltage applied to the gate-substrate capacitance (i.e., the gate-substrate bias voltage). To increase this voltage, it is necessary to increase the voltage applied to the control gate CG and / or reduce the voltage applied to the substrate 100. However, the voltage applied to the control gate CG cannot exceed the threshold voltage of the read transistor during the exposure stage, and reducing the voltage applied to the substrate 100 too much easily causes an avalanche in the PN junction between the source / drain region of the read transistor and the substrate 100, affecting the readout of the current signal. Therefore, this method is difficult; Another method to increase the full well charge is to increase the capacitance value of the gate-substrate capacitance. However, for the pixel structure shown in Figure 1 to increase the capacitance value of the gate-substrate capacitance, it is necessary to increase the capacitance value of the first capacitor C ONO and / or the second capacitor C OX . However, the pixel structure has little room for size adjustment. Therefore, it is difficult to increase the capacitance value of the first capacitor C ONO and / or the second capacitor C OX .

[0048] The vertical charge transfer imaging device and the manufacturing method of the vertical charge transfer imaging device according to the embodiments of the present invention, compared with the vertical charge transfer imaging device shown in Figure 1 , at least part of the gate dielectric layer 101 on the photosensitive region 10 is removed, so that the floating gate FG is electrically connected to the substrate 100 of the photosensitive region 10 to be at the same potential. Thus, the above-mentioned second capacitor C OX is no longer formed between the floating gate FG and the substrate 100 of the photosensitive region 10, and the gate-substrate capacitance is no longer the series capacitance of the first capacitor C ONO and the second capacitor C OX , but is basically equal to the first capacitor C ONO . Since the capacitance value of the first capacitor C ONO is larger than the capacitance value of the series capacitance of the first capacitor C ONO and the second capacitor C OX , it is possible to increase the gate-substrate capacitance, thereby helping to increase the full well charge, improve the image signal-to-noise ratio, and improve the image quality.

[0049] Embodiment 1 and Embodiment 2 below describe the manufacturing method of the vertical charge transfer imaging device of the present invention, and Embodiment 3 describes the vertical charge transfer imaging device of the present invention. It should be understood that each embodiment is only an exemplary specific implementation manner for manufacturing and applying the embodiments, and does not constitute a scope limitation in manufacturing and applying the present invention. Moreover, the separate description of multiple embodiments is only to more clearly explain the connotation of the present invention, but the technical features in each embodiment do not belong to the unique features of that embodiment. In some embodiments, the technical features in the following multiple embodiments can also be related and inspired to form new embodiments.

[0050] Embodiment 1

[0051] Referring to Figure 3 and Figure 4A , according to the manufacturing method of the vertical charge transfer imaging device of this embodiment, step S11 is executed to provide a substrate 100. The substrate 100 has a first isolation structure 110 and a plurality of pixel regions defined by the first isolation structure 110, and a second isolation structure 120 and a photosensitive region 10 and a charge reading region 20 defined by the second isolation structure 120 are provided in each of the pixel regions.

[0052] The substrate 100 can adopt various suitable semiconductor substrates in the art, and its materials can include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, etc. The substrate 100 has a first doping type, such as p-type or n-type. In this embodiment, taking the first doping type as p-type as an example, the substrate 100 is, for example, a silicon substrate doped with boron or boron difluoride.

[0053] The first isolation structure 110 is used to define a plurality of pixel regions in the substrate 100. Each of the pixel regions is used to form a pixel, and a gate-substrate capacitor and a reading transistor are formed in the pixel, and the gate-substrate capacitor and the reading transistor in the pixel have a common floating gate. The first isolation structure 110 is formed on one side (i.e., the front side) of the substrate 100 where the reading transistor is formed. As an example, the first isolation structure 110 is, for example, a shallow trench isolation (STI), and the embedding depth of the first isolation structure 110 in the substrate 100 is about To improve the isolation effect between adjacent pixel regions and avoid crosstalk, optionally, a deep trench isolation (DTI) is further formed on the other side (i.e., the back side) of the substrate 100 corresponding to the first isolation structure 110, that is, the shallow trench isolation formed on the front side of the substrate 100 (as the first isolation structure 110) and the deep trench isolation formed on the back side of the substrate 100 are used to isolate adjacent pixel regions. However, the present invention is not limited thereto. The first isolation structure 110 can also be a deep trench isolation (DTI) formed on the front side of the substrate 100, and the deep trench isolation (DTI) can penetrate or not penetrate the substrate 100.

[0054] A second isolation structure 120 is formed in each of the pixel regions and separates each of the pixel regions, such that each pixel region has a photosensitive region 10 and a charge reading region 20 defined by the second isolation structure 120. The second isolation structure 120 adopts, for example, shallow trench isolation (STI). The photosensitive region 10 is used to form a gate-substrate capacitance with a gate structure formed on the substrate 100 subsequently, and the charge reading region 20 is used to form a reading transistor. The first isolation structure 110 and the second isolation structure 120 can be formed by methods disclosed in the art. As Figure 4A shown, in this embodiment, the top surfaces of the first isolation structure 110 and the second isolation structure 120 are not lower than the surface of the substrate 100, and the top surface of the first isolation structure 110 is higher than the top surface of the second isolation structure 120.

[0055] Referring to Figure 3 and Figure 4B , step S12 is performed: a gate dielectric layer 101 is formed on the surfaces of the photosensitive region 10 and the charge reading region 20. As an example, the gate dielectric layer 101 can be formed on the surface of the substrate 100 of the photosensitive region 10 and the charge reading region 20 by using a thermal furnace process, a rapid thermal oxidation process, an in-situ steam generation (ISSG) process, or a decoupled plasma nitridation (DPN) process. The gate dielectric layer 101 includes, for example, silicon oxide.

[0056] Referring to Figure 3 and Figure 4C , step S13 is performed: a first floating gate material layer 131 is formed on the substrate 100, and the first floating gate material layer 131 extends from above the photosensitive region 10 of the pixel region across to above the charge reading region 20, and the gate dielectric layer 101 is interposed between the first floating gate material layer 131 and the photosensitive region 10 and between the first floating gate material layer 131 and the charge reading region 20. The first floating gate material layer 131 is used to form a floating gate (FG) corresponding to each pixel region.

[0057] Exemplarily, step S13 includes the following process: depositing a polysilicon material that covers the substrate 100, and the top surface of the polysilicon material is integrally higher than the first isolation structure 110 and the second isolation structure 120; then, optionally, a planarization process (such as CMP) is performed to make the top surface of the polysilicon material flat, forming the first floating gate material layer 131. Since opening holes, filling holes, and planarization processes will be performed subsequently, in order to facilitate controlling the thickness of the floating gate (FG) to be fabricated, the top surface of the first floating gate material layer 131 is, for example, higher than the top surface of the first isolation structure 110.

[0058] Referring to Figure 3, step S14 is performed: removing part of the first floating gate material layer 131 and part of the gate dielectric layer 101 to form an opening exposing at least part of the photosensitive region 10. In this embodiment, the opening is used to make at least part of the surface of the photosensitive region 10 no longer covered by the gate dielectric layer 101, so as to avoid forming a capacitor between the floating gate (FG) and the substrate 100 of the photosensitive region 10 (i.e., eliminating the need for the gate dielectric layer 101). Figure 2 The second capacitor C OX ), the opening partially overlaps with the floating gate (FG) formation region.

[0059] As an example, step S14 may include the following process: Figure 4D As shown, first, a first through hole 31 is formed in the first floating gate material layer 131 by using photolithography and etching processes. The first through hole 31 falls within the range of the photosensitive region 10 in a top view and partially overlaps with the region where the floating gate (FG) is to be formed. The width of the first through hole 31 is, for example, smaller than the width of the photosensitive region 10. Optionally, the distance between the hole wall of the first through hole 31 and the boundary of the photosensitive region 10 below (the boundary is defined by the first isolation structure 110 and the second isolation structure 120) is greater than 0; as shown in FIG. Figure 4E As shown, the gate dielectric layer 101 exposed by the first through hole 31 is then etched to form a second through hole 32 in the gate dielectric layer 101 to expose the underlying photosensitive region 10 (i.e., the substrate 100 of the photosensitive region 10). The second through hole 32 is formed corresponding to the first through hole 31, so the position and size of the second through hole 32 are substantially consistent with those of the first through hole 31. The first through hole 31 and the second through hole 32, which are connected from top to bottom, constitute an opening 30 that exposes at least a portion of the photosensitive region 10.

[0060] The opening 30 partially overlaps with the floating gate formation region, that is, from a top view, the opening 30 partially overlaps with the range of the floating gate (FG) formed subsequently on the photosensitive region 10. Thus, after the floating gate (FG) is formed subsequently, at least all of the opening 30 and the material filled therein later is not removed. In this embodiment, for example, the opening 30 is located inside the floating gate formation region, and the distances between the opening 30 and the first isolation structure 110 and the second isolation structure 120 are both greater than 0. After the opening 30 is formed, the gate dielectric layer 101 and the first floating gate material layer 131 are still stacked on the surface of the photosensitive region 10 near the boundary. The technical effect is that since the subsequently formed floating gate contacts the substrate 100 of the photosensitive region 10 through the opening 30, by retaining a part of the gate dielectric layer 101 on the surface of the photosensitive region 10, the risk of mutual diffusion of the doped ions in the substrate 100 of the photosensitive region 10 and the doped ions in the floating gate (FG) located on the charge reading region 20 can be reduced, thereby avoiding affecting the device performance. In particular, when the doping type of the substrate 100 is opposite to the doping type of the floating gate (FG), retaining a part of the gate dielectric layer 101 on the surface of the photosensitive region 10 can reduce the risk of the floating gate (FG) on the charge reading region 20 being inverted due to ion diffusion.

[0061] Refer to Figure 3 and Figure 4F , perform step S15: Fill the second floating gate material layer 132 in the opening 30, and the second floating gate material layer 132 contacts the substrate 100 of the photosensitive region 10 and the first floating gate material layer 131 respectively.

[0062] The second floating gate material layer 132 can be formed by an epitaxial process or a chemical vapor deposition process. As an example, in this embodiment, as Figure 4F shown, crystalline silicon is grown on the surface of the substrate 100 of the photosensitive region 10 by an epitaxial process as the second floating gate material layer 132, so that the crystalline silicon fills the opening 30. The crystalline silicon not only directly covers (i.e., contacts and covers) the exposed surface of the substrate 100 of the photosensitive region 10, but also directly covers the first floating gate material layer 131 on the side wall of the opening 30. The crystalline silicon can also cover the top surface of the first floating gate material layer 131. In another embodiment, a polysilicon material is deposited by a chemical vapor deposition process to fill the opening 30 and directly cover the exposed substrate 100 of the photosensitive region 10 and the first floating gate material layer 131 to form the second floating gate material layer 132. The second floating gate material layer 132 can include at least one of monocrystalline silicon and polysilicon. It should be noted that the second floating gate material layer 132 is not limited to being made of silicon, and it can also be other semiconductor materials such as germanium, silicon germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide.

[0063] Refer to Figure 3 and Figure 4G, perform step S16: form a floating gate material layer 130 corresponding to the pixel region, and the floating gate material layer 130 includes a first floating gate material layer 131 and a second floating gate material layer 132.

[0064] The floating gate material layer 130 is used to form a floating gate (FG) corresponding to the corresponding pixel region after subsequent patterning, so its thickness is consistent with the thickness of the floating gate (FG) to be fabricated. The thickness of the floating gate (FG) can be controlled by the first isolation structure 110. After forming the second floating gate material layer 132, the top surface of the first floating gate material layer 131 and / or the second floating gate material layer 132 can be higher than the top surface of the first isolation structure 110.

[0065] In this embodiment, as Figure 4F shown, after forming the second floating gate material layer 132, the top surfaces of the first floating gate material layer 131 and the second floating gate material layer 132 are both higher than the top surface of the first isolation structure 110. In step S16, a planarization process (such as CMP) can be performed to remove part of the first floating gate material layer 131 and / or part of the second floating gate material layer 132, so that the surface of the first isolation structure 110 is exposed (i.e., using the first isolation structure 110 as a polishing stop layer), thereby thinning the overall thickness of the floating gate material to meet the thickness requirement of the floating gate (FG) to be fabricated. After the planarization process is completed, the surface of the first isolation structure 110 is exposed, and the remaining first floating gate material layer 131 and second floating gate material layer 132 are distributed in each pixel region, and the top surface of the formed floating gate material layer 130 is flush with the surface of the first isolation structure 110.

[0066] After the above planarization process, optionally, the floating gate material layer 130 can be ion-implanted to improve its conductivity. In this embodiment, the floating gate material layer 130 is ion-implanted with a second doping type to make the floating gate material layer 130 have a second conductivity type doping (opposite to the doping type of the substrate 100), and the second conductivity type doping is, for example, n-type doping.

[0067] Referring to Figure 3 , then perform step S17: sequentially stack an inter-gate dielectric material layer and a control gate material layer on the substrate 100. In this embodiment, step S17 includes the following process: as Figure 4H shown, remove part of the first isolation structure 110 so that the top surface of the first isolation structure 110 is lower than the top surface of the floating gate material layer 130 and higher than the top surface of the photosensitive region 10, and the top surface of the remaining first isolation structure 110 and the side surface of the floating gate material layer 130 surrounding the first isolation structure 110 enclose a groove 40; then, as Figure 4IAs shown, an inter-gate dielectric material layer 103a is formed to cover the surface of the floating gate material layer 130 and the inner surface of the groove 40. The inter-gate dielectric material layer 103a is, for example, an ONO layer. Then, a control gate material layer 104 is formed on the inter-gate dielectric material layer 103a. The control gate material layer 104 is used to form a control gate (CG), and is formed, for example, by a doped polysilicon layer. The control gate material layer 104 covers the inter-gate dielectric material layer 103a and fills the groove 40, and the top surface of the control gate material layer 104 is higher than the floating gate material layer 130.

[0068] Referring to Figure 3 and Figure 4J , then step S18 is performed: the floating gate material layer 130, the inter-gate dielectric material layer 103a, and the control gate material layer 104 are patterned. The control gate CG is formed from the control gate material layer 104, the inter-gate dielectric layer 103 is formed from the inter-gate dielectric material layer 103a, and the floating gate FG is formed from the floating gate material layer 130. Among them, the floating gate FG contacts the photosensitive region 10 through the opening 30 to be electrically connected to the substrate 100 of the photosensitive region 10.

[0069] Specifically, a dry etching process can be used to etch the stack of the control gate material layer 104, the inter-gate dielectric material layer 103a, and the floating gate material layer 130 to form the above-mentioned floating gate FG, control gate CG, and the inter-gate dielectric layer 103 therebetween. In this embodiment, the boundaries of the floating gate FG, the inter-gate dielectric layer 103, and the control gate CG are located in Figure 4J the vertical direction of the cross-section shown, while Figure 4J the structure within the cross-section shown does not change, and thus Figure 4J is Figure 4I consistent with the cross-sectional structure shown.

[0070] After step S18, part of the charge reading region 20 or part of the gate dielectric layer 101 covering the surface of the charge reading region 20 is exposed on both sides of the control gate CG. Subsequently, source regions and drain regions (not shown in the figure) can be formed in the charge reading regions 20 on both sides of the control gate CG by ion implantation. The source regions, the drain regions, the gate dielectric layer 101 on the charge reading region 20, the floating gate FG, the inter-gate dielectric layer 103, and the control gate CG form a reading transistor. The control gates CG on multiple pixel regions can be connected to form a word line, and multiple word lines are, for example, parallel to each other.

[0071] After step S18, a gate stack including a gate dielectric layer 101, a floating gate FG, an inter-gate dielectric layer 103, and a control gate CG is formed on the pixel region. Among them, the floating gate FG, the inter-gate dielectric layer 103, and the control gate CG span from the charge reading region 20 to the photosensitive region 10. Among them, the floating gate FG includes a first floating gate portion formed by a first floating gate material layer 131 and a second floating gate portion formed by a second floating gate material layer 132. The arrangement direction of the first floating gate portion and the second floating gate portion is parallel to the surface of the pixel region. Among them, the first floating gate portion is located above the gate dielectric layer 101 and the second isolation structure 120, and the second floating gate portion is located on the surface of the photosensitive region 10 and directly contacts the substrate 100 of the photosensitive region 10, so that the floating gate FG is electrically connected to the substrate 100 on one side of the photosensitive region 10. While ensuring the working performance of the pixel, the capacitance value of the gate-substrate capacitance formed between the control gate CG and the substrate 100 of the photosensitive region 10 is increased, which helps to increase the full well charge of the pixel and improve the image signal-to-noise ratio and image quality.

[0072] Embodiment 2

[0073] This embodiment relates to a manufacturing method of a vertical charge transfer imaging device. The main difference from the manufacturing method of the vertical charge transfer imaging device described in Embodiment 1 is that in Embodiment 1, the material of the floating gate FG (including the first floating gate material layer 131 and the second floating gate material layer 132) is obtained through two successive deposition processes. An opening 30 exposing the surface of the photosensitive region 10 is formed in the first floating gate material layer 131 between the two deposition processes. In this embodiment, the material of the floating gate FG is obtained only through one deposition process, and at least part of the surface of the photosensitive region 10 is exposed before performing this deposition process. The following focuses on the manufacturing method of the vertical charge transfer imaging device in this embodiment around the above differences, and the same or similar parts can be referred to the description in Embodiment 1.

[0074] Referring to Figure 5 and Figure 6A , in this embodiment, step S21 is performed: providing a substrate 200, the substrate 200 having a first isolation structure 110 and a plurality of pixel regions defined by the first isolation structure 110, and each of the pixel regions having a second isolation structure 120 and a photosensitive region 10 and a charge reading region 20 defined by the second isolation structure 120. The top surface of the first isolation structure 110 in the substrate 200 is, for example, higher than the top surfaces of the second isolation structure 120 and the photosensitive region 10. After that, step S22 is performed: forming a gate dielectric layer 101 on the surfaces of the photosensitive region 10 and the charge reading region 20.

[0075] Referring to Figure 5 and Figure 6B , then, step S23 is performed: removing a part of the gate dielectric layer 101 to expose at least part of the photosensitive region 10.

[0076] The exposed area of the photosensitive region 10 is used for subsequent contact with the floating gate (FG) extending above the photosensitive region 10. Therefore, the exposed area of the photosensitive region 10 partially overlaps with the floating gate formation region. Specifically, a photolithography process can be used to define the area of the gate dielectric layer 101 to be removed. Then, a dry etching or wet etching process is used to remove part of the gate dielectric layer 101, so that the surface of the substrate 200 in the charge reading region 20 is still covered by the gate dielectric layer 101, while part or all of the surface of the substrate 200 in the photosensitive region 10 is exposed. As an example, the exposed area of the photosensitive region 10 is located in the middle region of the photosensitive region 10, while the boundary regions of the photosensitive region 10 close to the first isolation structure 110 or the second isolation structure 120 are still covered by the gate dielectric layer 101.

[0077] Refer to Figure 5 and Figure 6C , and then step S24 is executed: a floating gate material layer 130 is formed corresponding to the pixel region 10. The floating gate material layer 130 extends from above the photosensitive region 10 across to above the charge reading region 20, and the floating gate material layer 130 contacts the exposed photosensitive region 10.

[0078] In this embodiment, specifically, forming the floating gate material layer 130 may include the following process: depositing a polysilicon material, the polysilicon material covering the substrate 100 and contacting the exposed photosensitive region 10. To ensure that the polysilicon material contacts the exposed photosensitive region 10, according to the situation of the surface of the exposed photosensitive region 10, if a native oxide layer is formed on the surface of the photosensitive region 10, then before depositing the polysilicon material, a process of removing the native oxide layer is first performed; after forming the polysilicon material, a planarization process (such as CMP) is then performed to expose the surface of the first isolation structure 20, so that part of the polysilicon material is removed, and the remaining polysilicon material is located within the respective pixel regions 10 to form the floating gate material layer 130.

[0079] After the planarization process, ion implantation can also be performed on the floating gate material layer 130 to improve its conductivity. For example, ion implantation of a second doping type is performed on the floating gate material layer 130, so that the floating gate material layer 130 has a second conductivity type doping (opposite to the doping type of the substrate 100, for example, n-type doping).

[0080] Compared with the method of forming the first floating gate material layer 131, the second floating gate material layer 132, and the floating gate material layer 130 successively in the first embodiment, in this embodiment, since at least part of the photosensitive region 10 is exposed before depositing the polysilicon material, the deposited polysilicon material contacts and connects with the substrate 200 of the photosensitive region 10. After completing the planarization process, the floating gate material layer 130 also contacts and connects with the substrate 200 of the photosensitive region 10, which can save processes.

[0081] Referring to Figure 5 , after that, referring to the descriptions of steps S17 and S18 in the first embodiment, steps S24 and S25 can be sequentially executed. Specifically, in step S24, an inter-gate dielectric material layer and a control gate material layer are sequentially stacked on the substrate 200; in step S25, the floating gate material layer 130, the inter-gate dielectric material layer, and the control gate material layer are patterned, a control gate CG is formed from the control gate material layer, an inter-gate dielectric layer 103 is formed from the inter-gate dielectric material layer, and a floating gate FG is formed from the floating gate material layer 130, wherein the floating gate FG contacts the photosensitive region 10 and is electrically connected to the substrate 200 of the photosensitive region 10, as Figure 6D shown. In addition, source-drain implantation can further be performed to form a source region and a drain region respectively located on both sides of the control gate CG in the charge reading region 20.

[0082] Using the manufacturing method of the vertical charge transfer imaging device described in this embodiment, a gate stack including a gate dielectric layer 101, a floating gate FG, an inter-gate dielectric layer 103, and a control gate CG can be formed on the pixel region, wherein the floating gate FG, the inter-gate dielectric layer 103, and the control gate CG span from above the charge reading region 20 to above the photosensitive region 10, wherein the floating gate FG contacts the photosensitive region 10 on one side of the photosensitive region 10 and is thus electrically connected to the substrate 200 on one side of the photosensitive region 10. While ensuring the pixel working performance, the capacitance value of the gate-substrate capacitance formed between the control gate CG and the substrate 200 of the photosensitive region 10 is increased, which helps to increase the full well charge of the pixel and improve the image signal-to-noise ratio and image quality.

[0083] Embodiment Three

[0084] The embodiment of the present invention further relates to a vertical charge transfer imaging device. Referring to Figure 4J and Figure 6D , the vertical charge transfer imaging device includes a substrate (such as the substrate 100 in Figure 4J or the substrate 200 in Figure 6D ), the substrate has a first isolation structure 110 and a plurality of pixel regions defined by the first isolation structure 110, and in each of the pixel regions, there is a second isolation structure 120 and a photosensitive region 10 and a charge reading region 20 defined by the second isolation structure 120. The substrate has a first conductive type doping (for example, p-type doping).

[0085] The vertical charge transfer imaging device further includes a gate dielectric layer 101, a floating gate FG, an inter-gate dielectric layer 103, and a control gate CG formed on the substrate. Among them, the gate dielectric layer 101 covers at least the surface of the charge reading area 20 and exposes at least a part of the photosensitive area 10. As an example, in addition to covering the surface of the charge reading area 20, the gate dielectric layer 101 also covers a part of the surface of the photosensitive area 10 and surrounds the exposed area of the photosensitive area 10. However, it is not limited thereto. In one embodiment, the gate dielectric layer 101 covers the surface of the charge reading area 20, and no gate dielectric layer 101 is formed on the surface of the photosensitive area 10, and the surface of the photosensitive area 10 is exposed.

[0086] The floating gate FG is formed corresponding to the pixel area and spans from above the photosensitive area 10 to above the charge reading area 20. The gate dielectric layer 101 is at least located between the charge reading area 20 and the floating gate. The floating gate FG contacts the exposed photosensitive area 10 to be electrically connected to the substrate of the photosensitive area 10. The inter-gate dielectric layer 103 is stacked on the surface of the floating gate FG, and the control gate CG is stacked on the surface of the inter-gate dielectric layer 103. The doping type of the floating gate FG is, for example, opposite to that of the substrate, and the floating gate FG has a second conductive type doping (for example, n-type doping).

[0087] As Figure 4J and Figure 6D shown, the top surface of the first isolation structure 110 and the side surfaces of the floating gate FG located on both sides of the first isolation structure 110 enclose a groove (such as Figure 4H the groove 40 shown), the inter-gate dielectric layer 103 conformally covers the inner surface of the groove, and the control gate CG covers the inter-gate dielectric layer 103 and fills the groove.

[0088] In this embodiment, a part of the floating gate FG contacts the substrate, while other areas do not contact the substrate. As Figure 4J and Figure 6D shown, the floating gate FG includes a first floating gate portion located above the gate dielectric layer 101 and the second isolation structure 120 and a second floating gate portion located on the surface of the exposed photosensitive area 10. The arrangement direction of the first floating gate portion and the second floating gate portion is parallel to the surface of the pixel area 10. As Figure 4J shown, in one embodiment, the first floating gate portion and the second floating gate portion are two non-integrally formed parts, where the first floating gate portion is formed by a first floating gate material layer 131, and the second floating gate portion is formed by a second floating gate material layer 132. However, it is not limited thereto. As Figure 6DAs shown, in another embodiment, the first floating gate portion and the second floating gate portion are integrally formed structures, that is, the polysilicon material forming the first floating gate portion and the polysilicon material forming the second floating gate portion are formed through the same deposition process. The materials of the first floating gate portion and the second floating gate portion may be the same. For example, polysilicon may be used for both, or they may be different. For example, the first floating gate portion uses polysilicon, and the second floating gate portion includes single crystal silicon (such as using single crystal silicon or a combination of single crystal silicon and polysilicon).

[0089] In the vertical charge transfer imaging device described in the embodiments of the present invention, the gate dielectric layer 101 is at least located between the floating gate FG and the charge reading area 20 of the underlying pixel area. At least part of the photosensitive area 10 is not covered by the gate dielectric layer 101 and is exposed. The floating gate FG contacts the exposed photosensitive area 10 to be electrically connected to the substrate of the photosensitive area 10. Compared with the case where a capacitor is formed by isolating the floating gate from the substrate of the photosensitive area by the gate dielectric layer, in the present invention, the floating gate FG is electrically connected to the substrate of the photosensitive area 10 to be at the same potential, so that there is no longer a capacitor between the control gate CG and the substrate of the photosensitive area 10 like the capacitor between the floating gate FG and the substrate of the photosensitive area 10. This helps to increase the capacitance value of the total capacitance between the control gate CG and the substrate of the photosensitive area 10, that is, the gate-substrate capacitance, and further helps to increase the full well charge of the pixel, improve the image signal-to-noise ratio and the image quality.

[0090] It should be noted that the embodiments in this specification are described in a progressive manner. Each part focuses on the differences from the previous part. For the same and similar parts among each part, reference can be made to each other.

[0091] The above description is only a description of the preferred embodiments of the present invention and does not define any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention all fall within the protection scope of the technical solutions of the present invention.

Claims

1. A vertical charge transfer imaging device, characterized in that, Comprising: A substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each of the pixel regions; A gate dielectric layer covering at least the surface of the charge reading region and exposing a part of the photosensitive region; A floating gate formed corresponding to the pixel region and spanning from above the photosensitive region to above the charge reading region, the gate dielectric layer being at least between the charge reading region and the floating gate, and the floating gate contacting the exposed photosensitive region to be electrically connected to the substrate of the photosensitive region; An inter-gate dielectric layer stacked on the surface of the floating gate; And A control gate stacked on the surface of the inter-gate dielectric layer.

2. The vertical charge transfer imaging device according to claim 1, characterized in that, The floating gate includes a first floating gate portion located on the gate dielectric layer and the second isolation structure and a second floating gate portion located on the exposed photosensitive region, and the arrangement direction of the first floating gate portion and the second floating gate portion is parallel to the surface of the pixel region.

3. The vertical charge transfer imaging device according to claim 2, characterized in that, The first floating gate portion and the second floating gate portion are an integrally formed structure.

4. The vertical charge transfer imaging device according to claim 2, characterized in that, The first floating gate portion and the second floating gate portion are two non-integrally formed parts.

5. The vertical charge transfer imaging device according to claim 2, characterized in that, Both the first floating gate portion and the second floating gate portion are made of polysilicon; or, the first floating gate portion is made of polysilicon and the second floating gate portion includes single crystal silicon.

6. The vertical charge transfer imaging device according to claim 1, characterized in that, The gate dielectric layer also covers a part of the surface of the photosensitive region and surrounds the exposed region of the photosensitive region.

7. The vertical charge transfer imaging device according to claim 1, characterized in that, The substrate has a first conductivity type doping, and the floating gate has a second conductivity type doping.

8. A manufacturing method of a vertical charge transfer imaging device, characterized in that, Comprising: Providing a substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each of the pixel regions; Forming a gate dielectric layer on the surfaces of the photosensitive region and the charge reading region; Forming a first floating gate material layer on the substrate, the first floating gate material layer spanning from above the photosensitive region of the pixel region to above the charge reading region, the gate dielectric layer being between the first floating gate material layer and the photosensitive region and between the first floating gate material layer and the charge reading region; Removing a part of the first floating gate material layer and a part of the gate dielectric layer to form an opening exposing at least a part of the photosensitive region; Filling a second floating gate material layer in the opening, the second floating gate material layer contacting the substrate of the photosensitive region and the first floating gate material layer respectively; Forming a floating gate material layer corresponding to the pixel region, the floating gate material layer including the first floating gate material layer and the second floating gate material layer; Sequentially stacking an inter-gate dielectric material layer and a control gate material layer on the substrate; And Patterning the floating gate material layer, the inter-gate dielectric material layer and the control gate material layer to form a control gate from the control gate material layer, an inter-gate dielectric layer from the inter-gate dielectric material layer, and a floating gate from the floating gate material layer, wherein the floating gate contacts the photosensitive region through the opening to be electrically connected to the substrate of the photosensitive region.

9. The manufacturing method according to claim 8, characterized in that, The top surface of the first isolation structure is higher than the top surfaces of the second isolation structure and the photosensitive region; after filling the second floating gate material layer in the opening, the top surface of the first floating gate material layer and / or the second floating gate material layer is higher than the top surface of the first isolation structure; Forming the floating gate material layer corresponding to the pixel region includes: performing a planarization process to expose the surface of the first isolation structure, and the remaining first floating gate material layer and the second floating gate material layer form the floating gate material layer.

10. The manufacturing method according to claim 8, characterized in that, Fill the second floating gate material layer in the opening by using an epitaxial process or a chemical vapor deposition process.

11. A manufacturing method of a vertical charge transfer imaging device, characterized in that, Comprising: Providing a substrate having a first isolation structure and a plurality of pixel regions defined by the first isolation structure, and having a second isolation structure and a photosensitive region and a charge reading region defined by the second isolation structure in each pixel region; Forming a gate dielectric layer on the surfaces of the photosensitive region and the charge reading region; Removing a part of the gate dielectric layer to expose at least a part of the photosensitive region; Forming a floating gate material layer corresponding to the pixel region, the floating gate material layer spanning from above the photosensitive region to above the charge reading region, and the floating gate material layer contacting the exposed photosensitive region; Sequentially stacking an inter-gate dielectric material layer and a control gate material layer on the substrate; And Patterning the floating gate material layer, the inter-gate dielectric material layer, and the control gate material layer, forming a control gate from the control gate material layer, forming an inter-gate dielectric layer from the inter-gate dielectric material layer, and forming a floating gate from the floating gate material layer, wherein the floating gate contacts the photosensitive region to be electrically connected to the substrate of the photosensitive region.

12. The manufacturing method according to claim 11, wherein, The top surface of the first isolation structure is higher than the top surfaces of the second isolation structure and the photosensitive region; Forming the floating gate material layer includes: Depositing a polysilicon material, the polysilicon material covering the substrate and contacting the exposed photosensitive region; And Performing a planarization process to expose the surface of the first isolation structure, and the remaining polysilicon material forms the floating gate material layer.

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