Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, and the display panel comprises an array substrate, a first electrode layer, a leveling layer and an isolation structure. The first electrode layer and the leveling layer are located on one side of the array substrate, and the first electrode layer comprises a plurality of first electrodes arranged at intervals; the isolation structure is located on the side, away from the array substrate, of the leveling layer, and the orthographic projection of the isolation structure on the array substrate and the orthographic projection of the first electrode on the array substrate at least partially coincide. The orthographic projection of the isolation structure on the array substrate and the orthographic projection of the leveling layer on the array substrate at least partially coincide. The problem of poor dark spots of the display panel can be improved, and the display quality of the display panel can be further improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing the display panel, and an electronic device. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to their advantages of high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display panels.

[0003] However, in the related art, the display effect of the display panel is not good enough. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, which includes:

[0005] An array substrate;

[0006] A first electrode layer and a planarizing layer located on one side of the array substrate, the first electrode layer includes a plurality of first electrodes arranged at intervals, and the orthographic projection of the planarizing layer on the array substrate is located outside the orthographic projection of the first electrode on the array substrate;

[0007] An isolation structure located on the side of the planarizing layer away from the array substrate, the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the planarizing layer on the array substrate.

[0008] In a possible implementation manner, the display panel further includes a light-emitting layer and a second electrode layer stacked in sequence along the direction away from the array substrate, the second electrode layer includes a second electrode, and the second electrode is electrically connected to the isolation structure.

[0009] In a possible implementation manner, the isolation structure is provided with an isolation opening, and the light-emitting layer includes a light-emitting portion, and the light-emitting portion is located within the isolation opening.

[0010] In a possible implementation manner, the distance range between the edge of the orthographic projection of the planarizing layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0μm - 2μm;

[0011] The distance range between the edge of the orthographic projection of the planarization layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0 μm - 1 μm;

[0012] Preferably, the distance between the edge of the orthographic projection of the planarization layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0 μm.

[0013] In a possible implementation manner, the display panel further includes an insulating layer on the side of the planarization layer away from the array substrate, and the isolation structure is on the side of the insulating layer away from the array substrate;

[0014] Preferably, the isolation structure is electrically connected to the planarization layer.

[0015] In a possible implementation manner, a via hole is provided on the insulating layer, and the isolation structure is electrically connected to the planarization layer through the via hole;

[0016] Preferably, the material of the insulating layer includes silicon oxide or silicon nitride;

[0017] Preferably, along the direction perpendicular to the array substrate, the thickness range of the insulating layer is 0.1 μm - 1 μm.

[0018] In a possible implementation manner, the isolation structure is further provided with a light-transmitting opening, and the orthographic projection of the light-transmitting opening on the array substrate is located within the orthographic projection of the planarization layer on the array substrate;

[0019] Preferably, the light-emitting part is arranged offset from the light-transmitting opening;

[0020] Preferably, the isolation structure surrounding the light-transmitting opening is electrically connected to the planarization layer;

[0021] Preferably, the material of the planarization layer includes a light-transmitting material;

[0022] Preferably, the material of the planarization layer includes indium tin oxide;

[0023] In a possible implementation manner, along the direction perpendicular to the array substrate, the ratio range of the thickness of the planarization layer to the thickness of the first electrode is 0.1 - 1;

[0024] Preferably, along the direction perpendicular to the array substrate, the thickness of the planarization layer is equal to the thickness of the first electrode;

[0025] Preferably, along the direction perpendicular to the array substrate, the thickness range of the planarization layer is 0.05 μm - 0.5 μm.

[0026] In a possible implementation, the display panel further includes a pixel defining layer located on one side of the array substrate, and the isolation structure is located on the side of the pixel defining layer away from the array substrate; the pixel defining layer includes a pixel opening exposing at least part of the first electrode, and the orthographic projection of the isolation structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate;

[0027] Preferably, the planarization layer is located on the side of the pixel defining layer away from the array substrate;

[0028] Preferably, the isolation structure is provided with an isolation opening, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0029] In a possible implementation, the display panel further includes a first inorganic encapsulation layer located on the side of the second electrode layer away from the array substrate, the first inorganic encapsulation layer includes a plurality of encapsulation units, and the encapsulation units extend from the side of the isolation structure to the side of the isolation structure away from the array substrate;

[0030] Preferably, the display panel further includes an organic encapsulation layer located on the side of the first inorganic encapsulation layer away from the array substrate;

[0031] Preferably, the display panel further includes a second inorganic encapsulation layer located on the side of the organic encapsulation layer away from the array substrate;

[0032] Preferably, the display panel further includes a touch layer located on the side of the second inorganic encapsulation layer away from the array substrate, the touch layer includes a plurality of touch electrodes, and the orthographic projection of the touch electrodes on the array substrate at least partially overlaps with the orthographic projection of the planarization layer on the array substrate.

[0033] In a possible implementation, the isolation structure includes a first isolation portion and a second isolation portion stacked in sequence along the direction away from the array substrate, and the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

[0034] In a possible implementation, the second electrode is electrically connected to the first isolation portion; or the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion;

[0035] Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

[0036] In a possible implementation, the present application further provides a method for manufacturing a display panel, the method comprising:

[0037] Providing an array substrate;

[0038] Forming a first electrode layer and a planarizing layer on one side of the array substrate, the first electrode layer including a plurality of first electrodes arranged at intervals, and the planarizing layer is located outside the orthographic projection of the first electrode on the array substrate in the orthographic projection on the array substrate;

[0039] Forming an isolation structure on the side of the planarizing layer away from the array substrate; the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the planarizing layer on the array substrate.

[0040] In a possible implementation, the step of forming the first electrode layer and the planarizing layer on one side of the array substrate includes:

[0041] Forming a first electrode layer on one side of the array substrate;

[0042] Forming a pixel defining layer on the side of the first electrode layer away from the array substrate, the pixel defining layer including pixel openings exposing at least part of the first electrode;

[0043] Forming a planarizing layer on the side of the pixel defining layer away from the array substrate;

[0044] In a possible implementation, the step of forming the isolation structure on the side of the planarizing layer away from the array substrate includes:

[0045] Forming an insulating layer on the side of the planarizing layer away from the array substrate;

[0046] Forming an isolation structure on the side of the insulating layer away from the array substrate and electrically connecting the isolation structure to the planarizing layer;

[0047] Preferably, before the step of forming the isolation structure on the side of the insulating layer away from the array substrate, further comprising:

[0048] Forming a via hole exposing at least part of the planarizing layer on the insulating layer, so that the isolation structure and the planarizing layer are electrically connected through the via hole.

[0049] In a possible implementation, the present application further provides an electronic device, the electronic device including the display panel described in the present application.

[0050] Compared with the prior art, the present application has the following beneficial effects:

[0051] A display panel, a preparation method thereof, and an electronic device provided by the present application can make the flatness of the isolation structure better and the evaporation process more stable by providing a flattening layer on one side of the isolation structure close to the array substrate, thereby greatly improving the problem of dark spots in the display panel and further improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 A cross-sectional view of a display panel in the prior art provided by an embodiment of the present application;

[0054] Figure 2 A cross-sectional view of a display panel provided by an embodiment of the present application;

[0055] Figure 3 A cross-sectional view of the electrical connection between the isolation structure and the flattening layer provided by an embodiment of the present application;

[0056] Figure 4 A top view of the orthographic projection of the flattening layer and the first electrode on the array substrate provided by an embodiment of the present application;

[0057] Figure 5 A cross-sectional view of a display panel including a first inorganic encapsulation layer provided by an embodiment of the present application;

[0058] Figure 6 A cross-sectional view of a display panel including an organic encapsulation layer and a second inorganic encapsulation layer provided by an embodiment of the present application;

[0059] Figure 7 A cross-sectional view of a display panel including a touch layer provided by an embodiment of the present application;

[0060] Figure 8 A cross-sectional view of an isolation structure including a three-layer film structure provided by an embodiment of the present application;

[0061] Figure 9 A flowchart of a preparation method of a display panel provided by an embodiment of the present application;

[0062] Figure 10Schematic cross-sectional view of forming a first electrode layer on one side of an array substrate provided by an embodiment of the present application;

[0063] Figure 11 Schematic cross-sectional view of forming a pixel defining layer on the side of the first electrode layer away from the array substrate provided by an embodiment of the present application;

[0064] Figure 12 Schematic cross-sectional view of forming a planarization layer on the side of the pixel defining layer away from the array substrate provided by an embodiment of the present application;

[0065] Figure 13 Schematic cross-sectional view of forming an insulating layer on the side of the planarization layer away from the array substrate provided by an embodiment of the present application;

[0066] Figure 14 Schematic cross-sectional view of forming a via hole exposing at least a part of the planarization layer on the insulating layer provided by an embodiment of the present application;

[0067] Figure 15 Schematic cross-sectional view of forming an isolation structure on the side of the planarization layer away from the array substrate provided by an embodiment of the present application.

[0068] Reference numerals: 1, array substrate; 2, pixel defining layer; 21, pixel opening; 3, isolation column; 4, first electrode; 5, light emitting part; 6, second electrode; 7, isolation structure; 71, first isolation part; 72, second isolation part; 73, third isolation part; 8, isolation opening; 9, insulating layer; 91, via hole; 10, planarization layer; 11, light emitting sub-pixel; 12, first inorganic encapsulation layer; 121, encapsulation unit; 13, organic encapsulation layer; 14, second inorganic encapsulation layer; 15, touch control layer; 151, touch control electrode. Detailed Description of the Invention

[0069] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0070] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0071] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

[0072] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0073] It should be noted that, without conflict, the different features in the embodiments of the present application can be combined with each other.

[0074] Please refer to Figure 1 , in the related art, the display panel includes an array substrate 1, a first electrode layer on one side of the array substrate 1, a pixel defining layer 2 on the side of the first electrode layer away from the array substrate 1, and spacer columns 3 on the side of the pixel defining layer 2 away from the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 arranged at intervals. The pixel defining layer 2 includes a plurality of pixel openings 21, and at least part of the first electrodes 4 are exposed through the pixel openings 21. A light-emitting part 5 and a second electrode layer are sequentially arranged in the pixel openings 21 in a direction away from the array substrate 1. The second electrode layer is partitioned by the spacer columns 3 into a plurality of second electrodes 6. The second electrodes 6 are overlapped with the spacer columns 3, and the plurality of second electrodes 6 are electrically connected through the spacer columns 3.

[0075] However, the edge of the first electrode 4 makes the pixel defining layer 2 uneven, and finally makes the surface of the spacer column 3 uneven, which will further affect the side etching of the spacer column 3, the height of the eaves structure of the spacer column 3, and the overall morphology of the spacer column 3, resulting in unstable subsequent evaporation process, and finally resulting in large-area dark spot defects in the display panel, making the display quality of the display panel not good enough.

[0076] In view of this, the present embodiment provides a solution with better display quality, and the solution provided by the present embodiment will be elaborated in detail below.

[0077] Please refer to Figure 2 , the present embodiment provides a display panel, which includes an array substrate 1, a first electrode layer, a pixel defining layer 2, and a flattening layer 10.

[0078] The array substrate 1 may include a substrate and a plurality of driving units located on one side of the substrate. Each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of a plurality of film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of a plurality of film layers.

[0079] The first electrode layer is located on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 arranged at intervals, and the first electrodes 4 are anodes.

[0080] The planarization layer 10 is located on one side of the array substrate 1. The orthographic projection of the planarization layer 10 on the array substrate 1 is located outside the orthographic projection of the first electrode 4 on the array substrate 1. The planarization layer 10 does not overlap with the first electrode 4, so that it is not easy to form a capacitor between the first electrode 4 and the planarization layer 10, reducing the smear phenomenon of the display panel and ultimately improving the display quality of the display panel.

[0081] The pixel defining layer 2 is located on one side of the array substrate 1, and the planarization layer 10 is located on the side of the pixel defining layer 2 away from the array substrate 1; the pixel defining layer 2 includes pixel openings 21 exposing at least part of the first electrode 4; the display panel further includes a light emitting layer and a second electrode layer stacked in sequence along the direction away from the array substrate 1. The second electrode layer includes a plurality of second electrodes 6 arranged at intervals, and the second electrodes 6 are electrically connected to the isolation structure 7, and the second electrodes 6 are cathodes.

[0082] The light emitting layer includes a plurality of light emitting portions 5 arranged at intervals. The first electrode 4, the light emitting portion 5, and the second electrode 6 form a light emitting sub-pixel 11. The light emitting portion 5 and the second electrode 6 of at least part of the light emitting sub-pixels 11 are located in the isolation opening 8. The light emitting sub-pixels 11 may be red sub-pixels, green sub-pixels, or blue sub-pixels.

[0083] The isolation structure 7 is located on the side of the planarization layer 10 away from the array substrate 1. The orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the first electrode 4 on the array substrate 1, and the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the planarization layer 10 on the array substrate 1.

[0084] The orthographic projection of the isolation structure 7 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 21 on the array substrate 1. The isolation structure 7 is provided with an isolation opening 8, the light emitting portion 5 is located in the isolation opening 8, and the orthographic projection of the pixel opening 21 on the array substrate 1 is located in the orthographic projection of the isolation opening 8 on the array substrate 1.

[0085] When forming the second electrode layer, the isolation structure 7 will partition the second electrode layer to form a plurality of second electrodes 6 arranged at intervals. At least part of the second electrodes 6 extend from within the pixel opening 21 to the side of the pixel defining layer 2 away from the array substrate 1 and are in electrical contact with the isolation structure 7.

[0086] Since the second electrode 6 and the planarization layer 10 are complementary in design, at least part of the orthographic projection of the isolation structure 7 on the array substrate 1 coincides with at least part of the orthographic projection of the first electrode 4 on the array substrate 1, and at least part of the orthographic projection of the isolation structure 7 on the array substrate 1 coincides with at least part of the orthographic projection of the planarization layer 10 on the array substrate 1. Therefore, the pixel defining layer 2 corresponding to the isolation structure 7 can be made flatter, and finally the flatness of the isolation structure 7 is better, the process is more stable when evaporating the second electrode layer, and the second electrode 6 formed after the isolation structure 7 cuts off the second electrode layer is more likely to overlap with the isolation structure 7, thereby greatly improving the problem of dark spots in the display panel, and further improving the display quality of the display panel.

[0087] Based on the above design, in this embodiment, by providing the planarization layer 10 on the side of the isolation structure 7 close to the array substrate 1, the flatness of the isolation structure 7 can be better, the process is more stable when evaporating the second electrode layer, and the second electrode 6 is more likely to overlap with the isolation structure 7, thereby greatly improving the problem of dark spots in the display panel, and further improving the display quality of the display panel.

[0088] In a possible implementation manner, please refer to again Figure 2 , the display panel further includes an insulating layer 9 on the side of the planarization layer 10 away from the array substrate 1, and the isolation structure 7 is located on the side of the insulating layer 9 away from the array substrate 1.

[0089] The insulating layer 9 is located between the planarization layer 10 and the isolation structure 7. The insulating layer 9 can also increase the distance between the first electrode 4 and the isolation structure 7, thereby reducing the parasitic capacitance formed by the first electrode 4 and the isolation structure 7, and further improving the display quality of the display panel.

[0090] Preferably, please refer to Figure 3 , the isolation structure 7 is electrically connected to the planarization layer 10. The material of the planarization layer 10 is a conductive material. By electrically connecting the planarization layer 10 and the isolation structure 7, the fixed potential is transmitted to the planarization layer 10 through the isolation structure 7, so that the planarization layer 10 plays a role in shielding electrical signals, improving the crosstalk problem between the electrical signals of the touch layer and the electrical signals in the array substrate 1. On the other hand, it can also improve the voltage drop of the electrical signals applied on the isolation structure 7, making it easier for the display panel to uniformly apply the electrical signals of the second electrode 6 to the light-emitting sub-pixels 11 at different positions, and finally improving the display quality of the display panel.

[0091] In a possible implementation manner, please refer to again Figure 3 , a via 91 is provided on the insulating layer 9, and the isolation structure 7 is electrically connected to the planarization layer 10 through the via 91.

[0092] The material of the insulating layer 9 includes silicon oxide, silicon nitride, etc. After forming the insulating layer 9, a via 91 exposing at least part of the planarization layer 10 is provided on the insulating layer 9. When forming the isolation structure 7, the material of the isolation structure 7 enters the via 91 and contacts the planarization layer 10, thereby making it easier to electrically connect the isolation structure 7 and the planarization layer 10.

[0093] Preferably, please refer to again Figure 3 , along the direction perpendicular to the array substrate 1, the thickness D1 of the insulating layer 9 ranges from 0.1 μm to 1 μm. For example, the thickness D1 can be 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, etc. If the thickness D1 of the insulating layer 9 is set too large, the thickness of the display panel will increase. If the thickness D1 of the insulating layer 9 is set too small, the insulation effect between the insulating layer 9 for the planarization layer and the isolation structure 7 will be reduced, and the capacitance formed between the first electrode 4 and the isolation structure 7 will increase. Therefore, reasonably setting the thickness D1 of the insulating layer 9 can, without excessively increasing the thickness of the display panel, not affect the insulation effect between the insulating layer 9 for the planarization layer 10 and the isolation structure 7, and can reduce the capacitance formed between the first electrode 4 and the isolation structure 7.

[0094] In a possible implementation manner, please refer to again Figure 2 , the distance L between the edge of the positive projection of the planarization layer 10 on the array substrate 1 and the edge of the positive projection of the first electrode 4 on the array substrate 1 ranges from 0 μm to 2 μm. For example, the distance L can be 0 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2 μm, etc. Narrowing the distance between the planarization layer 10 and the first electrode 4 can make the pixel defining layer 2 between the first electrode 4 and the planarization layer 10 flatter, and can make the insulating layer 9 on the side of the planarization layer 10 away from the array substrate 1 flatter. Finally, the isolation structure 7 can be made flatter, so that it is easier for the second electrode 6 and the isolation structure 7 to overlap each other.

[0095] Furthermore, please refer to again Figure 2 , the distance L between the edge of the positive projection of the planarization layer 10 on the array substrate 1 and the edge of the positive projection of the first electrode 4 on the array substrate 1 ranges from 0 μm to 1 μm. For example, the distance L can be 0 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, etc. Further narrowing the distance between the planarization layer 10 and the first electrode 4 can make the pixel defining layer 2 between the first electrode 4 and the planarization layer 10 flatter, and can make the insulating layer 9 on the side of the planarization layer 10 away from the array substrate 1 flatter. Finally, the isolation structure 7 can be made flatter, so that it is easier for the second electrode 6 and the isolation structure 7 to overlap each other.

[0096] Further, please refer to Figure 2 and Figure 4 , the distance between the edge of the orthographic projection of the planarization layer 10 on the array substrate 1 and the edge of the orthographic projection of the first electrode 4 on the array substrate 1 is 0 μm.

[0097] The edge of the orthographic projection of the planarization layer 10 on the array substrate 1 is in contact with the edge of the orthographic projection of the first electrode 4 on the array substrate 1, and the planarization layer 10 and the first electrode 4 are complementarily arranged, which can make the pixel defining layer 2 between the first electrode 4 and the planarization layer 10 further flatter, and can make the insulating layer 9 on the side of the planarization layer 10 away from the array substrate 1 further flatter. Finally, the isolation structure 7 can be made further flatter, so that the second electrode 6 and the isolation structure 7 can be further more easily lapped together.

[0098] In a possible implementation manner, please refer to Figure 3 again, the isolation structure 7 further includes a light-transmitting opening N-N, and the orthographic projection of the light-transmitting opening N-N on the array substrate 1 is located within the orthographic projection of the planarization layer 10 on the array substrate 1.

[0099] The material of the planarization layer 10 includes a light-transmitting material. Optionally, the material of the planarization layer 10 may include indium tin oxide. An optical sensor may be disposed under the display panel, and the optical sensor can receive light from the outside passing through the light-transmitting opening N-N, thereby increasing the functions of the display panel. For example, the photographic function of the display panel can be realized, etc.

[0100] Preferably, please refer to Figure 3 again, the light-emitting part 5 and the light-transmitting opening N-N are arranged in a dislocation manner, that is, the light-emitting part 5 is not located within the light-transmitting opening N-N, and the isolation structure 7 surrounding the light-transmitting opening N-N is electrically connected to the planarization layer 10.

[0101] By arranging the light-emitting part 5 and the light-transmitting opening N-N in a dislocation manner, the light from the outside can pass through the light-transmitting opening N-N of the isolation structure 7 and irradiate under the screen. In this way, the transmittance of the display panel can be improved.

[0102] Preferably, please refer to Figure 3 again, along the direction perpendicular to the array substrate 1, the ratio range of the thickness D2 of the planarization layer 10 to the thickness D3 of the first electrode 4 is 0.1-1. For example, it can be 0.1, 0.3, 0.5, 0.7, 0.9 or 1, etc. By reasonably setting the difference between the thickness D2 of the planarization layer 10 and the thickness D3 of the first electrode 4, the flatness of the isolation structure 7 can be better.

[0103] Preferably, along the direction perpendicular to the array substrate 1, the thickness D2 of the planarization layer 10 is equal to the thickness D3 of the first electrode 4. In this way, the pixel defining layer 2 corresponding to the isolation structure 7 can be made flatter, and finally the flatness of the isolation structure 7 can be better.

[0104] Preferably, please refer to Figure 3 , along the direction perpendicular to the array substrate 1, the thickness D2 of the planarization layer 10 ranges from 0.05 μm to 0.5 μm. For example, the thickness D2 can be 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc. If the thickness D2 is set too large, the thickness of the display panel will increase. If the thickness D2 is set too small, the effect of the planarization layer 10 on making the isolation structure 7 flat will be affected. Therefore, reasonably setting the thickness D2 of the planarization layer 10 can make the isolation structure 7 flatter.

[0105] Preferably, please refer to Figure 5 , the display panel further includes a first inorganic encapsulation layer 12 on the side of the second electrode layer away from the array substrate 1. The first inorganic encapsulation layer 12 includes a plurality of encapsulation units 121, and the encapsulation units 121 extend from the side of the isolation structure 7 to the side of the isolation structure 7 away from the array substrate 1.

[0106] The isolation structure 7 includes a side close to the array substrate 1, a side away from the array substrate 1, and a side surface. The first inorganic encapsulation layer 12 is disconnected on the side of the isolation structure 7 away from the array substrate 1 and forms a plurality of spaced-apart encapsulation units 121. The encapsulation units 121 extend from the side surface of the isolation structure 7 to the side of the isolation structure 7 away from the array substrate 1. The encapsulation units 121 encapsulate the plurality of light-emitting sub-pixels 11 independently.

[0107] Preferably, please refer to Figure 6 , the display panel further includes an organic encapsulation layer 13 on the side of the first inorganic encapsulation layer 12 away from the array substrate 1 and a second inorganic encapsulation layer 14 on the side of the organic encapsulation layer 13 away from the array substrate 1. The organic encapsulation layer 13 and the second inorganic encapsulation layer 14 can further encapsulate the light-emitting sub-pixels 11, so as to provide better protection for the light-emitting sub-pixels 11.

[0108] Preferably, please refer to Figure 7 , the display panel further includes a touch layer 15 on the side of the second inorganic encapsulation layer 14 away from the array substrate 1. The touch layer 15 includes a plurality of touch electrodes 151, and the orthographic projection of the touch electrodes 151 on the array substrate 1 at least partially overlaps with the orthographic projection of the planarization layer 10 on the array substrate 1.

[0109] The array substrate 1 includes a plurality of metal layers, each metal layer includes a plurality of metal traces, and the planarization layer 10 is located between the metal traces of the array substrate 1 and the touch electrodes 151 of the touch layer 15. The planarization layer 10 can shield the metal traces and the touch electrodes 151, thereby reducing the signal interference between the touch electrodes 151 and the metal traces, and further improving the display quality of the display panel.

[0110] In a possible implementation manner, please refer to again Figure 3 , the isolation structure 7 includes a first isolation portion 71 and a second isolation portion 72 that are sequentially stacked in a direction away from the array substrate 1. The orthographic projection of the first isolation portion 71 on the array substrate 1 is located within the orthographic projection of the second isolation portion 72 on the array substrate 1.

[0111] Since the second isolation portion 72 is located on the side of the first isolation portion 71 away from the array substrate 1, and the lateral width of the second isolation portion 72 is greater than the lateral width of the first isolation portion 71, the second isolation portion 72 will disconnect the light-emitting layer and the second electrode layer at the isolation structure 7. In this way, the isolation structure 7 formed by the first isolation portion 71 and the second isolation portion 72 can independently package each light-emitting sub-pixel 11.

[0112] In a possible implementation manner, please refer to again Figure 3 , the second electrode 6 is electrically connected to the first isolation portion 71; please refer to Figure 8 , or the isolation structure 7 further includes a third isolation portion 73 located on the side of the first isolation portion 71 facing the array substrate 1, and the second electrode 6 is electrically connected to the third isolation portion 73; the material of the third isolation portion 73 includes molybdenum metal; and / or the material of the first isolation portion 71 includes aluminum metal; and / or the material of the second isolation portion 72 includes titanium metal.

[0113] The second electrode 6 is electrically connected to the first isolation portion 71, and the first isolation portion 71 is electrically connected to the planarization layer 10 through a via 91; or the second electrode 6 is electrically connected to the third isolation portion 73, and the third isolation portion 73 is electrically connected to the planarization layer 10 through a via 91. In this embodiment, when the isolation structure 7 divides the second electrode layer into the second electrode 6, the second electrode 6 is electrically connected to the first isolation portion 71 or the third isolation portion 73.

[0114] In summary, by providing the planarization layer 10 on the side of the isolation structure 7 close to the array substrate 1 in the present application, the flatness of the isolation structure 7 can be better, the process is more stable when depositing film layers such as the second electrode 6, and the second electrode 6 is easier to overlap with the isolation structure 7, thereby greatly improving the problem of dark spots in the display panel, and further improving the display quality of the display panel.

[0115] In a possible implementation manner, please refer to Figure 9, this application also provides a method for manufacturing a display panel, and the method includes:

[0116] S10: Provide an array substrate 1.

[0117] The array substrate 1 may include a substrate and a plurality of driving units located on one side of the substrate. Each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of a plurality of film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of a plurality of film layers.

[0118] S11: Form a first electrode layer and a planarization layer 10 on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 arranged at intervals. The planarization layer 10 is located outside the orthographic projection of the first electrodes 4 on the array substrate 1 in the orthographic projection on the array substrate 1.

[0119] Please refer to Figure 10 , form a first electrode layer on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 arranged at intervals. The first electrodes 4 are anodes.

[0120] Please refer to Figure 11 , form a pixel defining layer 2 on the side of the first electrode layer away from the array substrate 1. The pixel defining layer 2 includes pixel openings 21 exposing at least part of the first electrodes 4.

[0121] Please refer to Figure 12 , form a planarization layer 10 on the side of the pixel defining layer 2 away from the array substrate 1.

[0122] Please refer to Figure 13 , form an insulating layer 9 on the side of the planarization layer 10 away from the array substrate 1. The material of the insulating layer 9 may include silicon oxide or silicon nitride.

[0123] Please refer to Figure 14 , form a via 91 on the insulating layer 9 to expose at least part of the planarization layer 10. Through the via 91, the planarization layer 10 can be electrically connected to the isolation structure 7, thereby improving the signal crosstalk between the touch electrodes 151 of the touch layer and the metal traces of the array substrate 1 in the display panel.

[0124] S12: Form an isolation structure 7 on the side of the planarization layer 10 away from the array substrate 1; the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the first electrodes 4 on the array substrate 1, and the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the planarization layer 10 on the array substrate 1.

[0125] Please refer to Figure 15, an isolation structure 7 is formed on the side of the planarization layer 10 away from the array substrate 1. The orthographic projection of the isolation structure 7 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 21 on the array substrate 1. The isolation structure 7 encloses to form an isolation opening 8, and the orthographic projection of the pixel opening 21 on the array substrate 1 is located within the orthographic projection of the isolation opening 8 on the array substrate 1. When forming the isolation structure 7, the material of the isolation structure 7 enters the via 91 and contacts the planarization layer 10, so that the isolation structure 7 is electrically connected to the planarization layer 10.

[0126] Please refer to again Figure 3 , along the direction away from the array substrate 1 on the inner edge of the pixel opening 21, a light-emitting layer and a second electrode layer are sequentially formed. When forming the light-emitting layer and the second electrode layer, the isolation structure 7 will partition the light-emitting layer to form a plurality of spaced-apart light-emitting portions 5, and the light-emitting portions 5 are located within the pixel opening 21; the isolation structure 7 will partition the second electrode layer to form a plurality of spaced-apart second electrodes 6, and at least a part of the second electrodes 6 extends from within the pixel opening 21 to the side of the pixel defining layer 2 away from the array substrate 1 and is in electrical contact with the isolation structure 7.

[0127] Since the second electrode 6 and the planarization layer 10 are complementary in design, at least a part of the orthographic projection of the isolation structure 7 on the array substrate 1 coincides with the orthographic projection of the first electrode 4 on the array substrate 1, and at least a part of the orthographic projection of the isolation structure 7 on the array substrate 1 coincides with the orthographic projection of the planarization layer 10 on the array substrate 1. Therefore, the pixel defining layer 2 corresponding to the isolation structure 7 can be made flatter, and finally the flatness of the isolation structure 7 is better, and the process is more stable when depositing film layers such as the second electrode layer. After the isolation structure 7 partitions the second electrode layer, the formed second electrode 6 overlaps with the isolation structure 7, so that the problem of dark spots in the display panel can be greatly improved, and thus the display quality of the display panel can be improved.

[0128] In a possible implementation manner, the present application also provides an electronic device, and the electronic device includes the display panel in the present application. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. Since the electronic device includes the display panel in the present application, the display quality of the electronic device is higher.

[0129] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0130] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: An array substrate; A first electrode layer and a planarization layer located on one side of the array substrate. The first electrode layer includes a plurality of first electrodes arranged at intervals, and the orthographic projection of the planarization layer on the array substrate is located outside the orthographic projection of the first electrode on the array substrate; An isolation structure located on the side of the planarization layer away from the array substrate. The orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the planarization layer on the array substrate.

2. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting layer and a second electrode layer stacked in sequence in a direction away from the array substrate. The second electrode layer includes a second electrode, and the second electrode is electrically connected to the isolation structure.

3. The display panel according to claim 1 or 2, characterized in that, The distance range between the edge of the orthographic projection of the planarization layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0μm - 2μm; Preferably, the distance range between the edge of the orthographic projection of the planarization layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0μm - 1μm; Preferably, the distance between the edge of the orthographic projection of the planarization layer on the array substrate and the edge of the orthographic projection of the edge of the first electrode on the array substrate is 0μm.

4. The display panel according to claim 1 or 2, characterized in that, The display panel further includes an insulating layer located on the side of the planarization layer away from the array substrate, and the isolation structure is located on the side of the insulating layer away from the array substrate; Preferably, the isolation structure is electrically connected to the planarization layer.

5. The display panel according to claim 4, characterized in that, A via hole is provided on the insulating layer, and the isolation structure and the planarization layer are electrically connected through the via hole; Preferably, the material of the insulating layer includes silicon oxide or silicon nitride; Preferably, in a direction perpendicular to the array substrate, the thickness range of the insulating layer is 0.1μm - 1μm.

6. For the display panel according to claim 2, the isolation structure is provided with an isolation opening, the light-emitting layer includes a light-emitting portion, and the light-emitting portion is located within the isolation opening.

7. The display panel according to claim 6, characterized in that, The isolation structure is further provided with a light-transmitting opening, and the orthographic projection of the light-transmitting opening on the array substrate is located within the orthographic projection of the planarization layer on the array substrate; Preferably, the light-emitting part is arranged in a dislocation manner with respect to the light-transmitting opening; Preferably, the isolation structure surrounding the light-transmitting opening is electrically connected to the planarization layer; Preferably, the material of the planarization layer includes a light-transmitting material; Preferably, the material of the planarization layer includes indium tin oxide.

8. The display panel according to claim 1 or 2, characterized in that, In a direction perpendicular to the array substrate, the ratio range of the thickness of the planarization layer to the thickness of the first electrode is 0.1 - 1; Preferably, in a direction perpendicular to the array substrate, the thickness of the planarization layer is equal to the thickness of the first electrode; Preferably, in a direction perpendicular to the array substrate, the thickness range of the planarization layer is 0.05μm - 0.5μm.

9. The display panel according to claim 1 or 2, characterized in that, The display panel further includes a pixel defining layer on one side of the array substrate, and the isolation structure is located on the side of the pixel defining layer away from the array substrate; the pixel defining layer includes a pixel opening exposing at least part of the first electrode, and the orthographic projection of the isolation structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate; Preferably, the planarization layer is located on the side of the pixel defining layer away from the array substrate; Preferably, the isolation structure is provided with an isolation opening, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate.

10. For the display panel according to claim 2, the display panel further includes a first inorganic encapsulation layer on a side of the second electrode layer away from the array substrate, the first inorganic encapsulation layer includes a plurality of encapsulation units, and the encapsulation units extend from a side surface of the isolation structure to a side of the isolation structure away from the array substrate; Preferably, the display panel further includes an organic encapsulation layer on a side of the first inorganic encapsulation layer away from the array substrate; Preferably, the display panel further includes a second inorganic encapsulation layer on a side of the organic encapsulation layer away from the array substrate; Preferably, the display panel further includes a touch layer on a side of the second inorganic encapsulation layer away from the array substrate. The touch layer includes a plurality of touch electrodes, and a positive projection of the touch electrodes on the array substrate at least partially overlaps with a positive projection of the planarization layer on the array substrate.

11. The display panel according to claim 2, wherein The isolation structure includes a first isolation portion and a second isolation portion stacked in sequence along a direction away from the array substrate, and the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

12. The display panel according to claim 11, wherein The second electrode is electrically connected to the first isolation portion; or the isolation structure further includes a third isolation portion on the side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

13. A method for manufacturing a display panel, wherein The method includes: Providing an array substrate; Forming a first electrode layer and a planarization layer on one side of the array substrate, the first electrode layer including a plurality of first electrodes arranged at intervals, and the orthographic projection of the planarization layer on the array substrate is located outside the orthographic projection of the first electrode on the array substrate; Forming an isolation structure on the side of the planarization layer away from the array substrate; the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the planarization layer on the array substrate.

14. The method for manufacturing a display panel according to claim 13, wherein The step of forming the first electrode layer and the planarization layer on one side of the array substrate includes: Forming a first electrode layer on one side of the array substrate; Forming a pixel defining layer on the side of the first electrode layer away from the array substrate, the pixel defining layer including a pixel opening exposing at least part of the first electrode; Forming a planarization layer on the side of the pixel defining layer away from the array substrate.

15. The method for manufacturing a display panel according to claim 13, wherein The step of forming the isolation structure on the side of the planarization layer away from the array substrate includes: Forming an insulating layer on the side of the planarization layer away from the array substrate; Forming an isolation structure on the side of the insulating layer away from the array substrate and electrically connecting the isolation structure to the planarization layer; Preferably, before the step of forming the isolation structure on the side of the insulating layer away from the array substrate, it further includes: Forming a via hole on the insulating layer to expose at least part of the planarization layer, so that the isolation structure and the planarization layer are electrically connected through the via hole.

16. An electronic device, wherein The electronic device includes the display panel according to any one of claims 1-12.

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