Display panel, preparation method of display panel and electronic device

Abstract

The embodiment of the present application provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. The display panel comprises an array substrate, a first electrode layer, a pad layer and an isolation structure. The first electrode layer and the pad layer are located on one side of the array substrate, the first electrode layer comprises a plurality of first electrodes which are arranged at intervals; the isolation structure is located on the side of the pad layer away from the array substrate, the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the pad layer on the array substrate. The present application can improve the problem of dark spot defects of the display panel, and thus the display quality of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the display panel, and an electronic device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display panels.

[0003] However, the display effect of the display panel in the related technology is not good enough. Summary of the Invention

[0004] To overcome the technical problems mentioned in the background, this application provides a display panel, which includes:

[0005] Array substrate;

[0006] A first electrode layer and a padding layer are located on one side of the array substrate. The first electrode layer includes a plurality of spaced first electrodes. The orthographic projection of the padding layer on the array substrate is located outside the orthographic projection of the first electrodes on the array substrate.

[0007] An isolation structure located on the side of the flattening layer away from the array substrate, wherein the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the flattening layer on the array substrate.

[0008] In one possible implementation, the display panel further includes a light-emitting layer and a second electrode layer sequentially stacked along a direction away from the array substrate, the second electrode layer including a second electrode, the second electrode being electrically connected to the isolation structure.

[0009] In one possible implementation, the isolation structure has an isolation opening, and the light-emitting layer includes a light-emitting portion located within the isolation opening.

[0010] In one possible implementation, the distance between the edge of the orthogonal projection of the leveling layer on the array substrate and the edge of the orthogonal projection of the first electrode on the array substrate is in the range of 0 μm-2 μm;

[0011] The distance between the edge of the orthographic projection of the leveling layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is in the range of 0 μm-1 μm;

[0012] Preferably, the distance between the edge of the orthographic projection of the leveling layer on the array substrate and the edge of the orthographic projection of the first electrode on the array substrate is 0 μm.

[0013] In one possible implementation, the display panel further includes an insulating layer located on the side of the flattening layer away from the array substrate, and the isolation structure is located on the side of the insulating layer away from the array substrate;

[0014] Preferably, the isolation structure is electrically connected to the leveling layer.

[0015] In one possible implementation, the insulating layer is provided with a via, and the isolation structure is electrically connected to the leveling layer through the via;

[0016] Preferably, the insulating layer is made of silicon oxide or silicon nitride;

[0017] Preferably, the thickness of the insulating layer is in the range of 0.1 μm to 1 μm along the direction perpendicular to the array substrate.

[0018] In one possible implementation, the isolation structure is further provided with a light-transmitting opening, the orthographic projection of which on the array substrate is located within the orthographic projection of the leveling layer on the array substrate;

[0019] Preferably, the light-emitting part is offset from the light-transmitting opening;

[0020] Preferably, the isolation structure surrounding the light-transmitting opening is electrically connected to the leveling layer;

[0021] Preferably, the material of the leveling layer includes a light-transmitting material;

[0022] Preferably, the material of the leveling layer includes indium tin oxide;

[0023] In one possible implementation, the ratio of the thickness of the leveling layer to the thickness of the first electrode in a direction perpendicular to the array substrate ranges from 0.1 to 1.

[0024] Preferably, the thickness of the leveling layer is equal to the thickness of the first electrode in a direction perpendicular to the array substrate;

[0025] Preferably, the thickness of the leveling layer is in the range of 0.05μm-0.5μm along the direction perpendicular to the array substrate.

[0026] In one possible implementation, the display panel further includes a pixel defining layer located on one side of the array substrate, and the isolation structure is located on the side of the pixel defining layer away from the array substrate; the pixel defining layer includes pixel openings that expose at least a portion of the first electrode, and the orthographic projection of the isolation structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate.

[0027] Preferably, the leveling layer is located on the side of the pixel defining layer away from the array substrate;

[0028] Preferably, the isolation structure has an isolation opening, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0029] In one possible implementation, the display panel further includes a first inorganic encapsulation layer located on the side of the second electrode layer away from the array substrate, the first inorganic encapsulation layer including a plurality of encapsulation units extending from the side of the isolation structure to the side of the isolation structure away from the array substrate;

[0030] Preferably, the display panel further includes an organic encapsulation layer located on the side of the first inorganic encapsulation layer away from the array substrate;

[0031] Preferably, the display panel further includes a second inorganic encapsulation layer located on the side of the organic encapsulation layer away from the array substrate;

[0032] Preferably, the display panel further includes a touch layer located on the side of the second inorganic encapsulation layer away from the array substrate, the touch layer including a plurality of touch electrodes, the orthographic projection of the touch electrodes on the array substrate at least partially overlapping the orthographic projection of the flattening layer on the array substrate.

[0033] In one possible implementation, the isolation structure includes a first isolation portion and a second isolation portion stacked sequentially along a direction away from the array substrate, wherein the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

[0034] In one possible implementation, the second electrode is electrically connected to the first isolation portion; or the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion.

[0035] Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

[0036] In one possible implementation, this application also provides a method for manufacturing a display panel, the method comprising:

[0037] Provide an array substrate;

[0038] A first electrode layer and a padding layer are formed on one side of the array substrate. The first electrode layer includes a plurality of spaced first electrodes. The orthographic projection of the padding layer on the array substrate is located outside the orthographic projection of the first electrodes on the array substrate.

[0039] An isolation structure is formed on the side of the leveling layer away from the array substrate; the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the leveling layer on the array substrate.

[0040] In one possible implementation, the step of forming the first electrode layer and the padding layer on one side of the array substrate includes:

[0041] A first electrode layer is formed on one side of the array substrate;

[0042] A pixel defining layer is formed on the side of the first electrode layer away from the array substrate, the pixel defining layer including pixel openings that expose at least a portion of the first electrode;

[0043] A flattening layer is formed on the side of the pixel defining layer away from the array substrate;

[0044] In one possible implementation, the step of forming an isolation structure on the side of the leveling layer away from the array substrate includes:

[0045] An insulating layer is formed on the side of the leveling layer away from the array substrate;

[0046] An isolation structure is formed on the side of the insulating layer away from the array substrate, and the isolation structure is electrically connected to the padding layer;

[0047] Preferably, before the step of forming an isolation structure on the side of the insulating layer away from the array substrate, the method further includes:

[0048] A via is formed in the insulating layer to expose at least a portion of the leveling layer, so that the isolation structure and the leveling layer are electrically connected through the via.

[0049] In one possible implementation, this application also provides an electronic device, which includes the display panel described in this application.

[0050] Compared with the prior art, this application has the following beneficial effects:

[0051] This application provides a display panel, a method for manufacturing the display panel, and an electronic device. By providing a flattening layer on the side of the isolation structure close to the array substrate, the flatness of the isolation structure can be improved, and the vapor deposition process can be made more stable. This can greatly improve the problem of dark spot defects in the display panel, thereby improving the display quality of the display panel. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A cross-sectional schematic diagram of a display panel in the prior art provided for embodiments of this application;

[0054] Figure 2 A cross-sectional schematic diagram of the display panel provided in an embodiment of this application;

[0055] Figure 3 This is a cross-sectional schematic diagram of the electrical connection between the isolation structure and the leveling layer provided in the embodiments of this application;

[0056] Figure 4 A top view of the orthographic projection of the leveling layer and the first electrode on the array substrate provided in the embodiments of this application;

[0057] Figure 5 A cross-sectional schematic diagram of a display panel including a first inorganic encapsulation layer provided in an embodiment of this application;

[0058] Figure 6 A cross-sectional schematic diagram of a display panel provided in the embodiments of this application, including an organic encapsulation layer and a second inorganic encapsulation layer;

[0059] Figure 7 A cross-sectional schematic diagram of a display panel including a touch layer provided in an embodiment of this application;

[0060] Figure 8 A cross-sectional schematic diagram of the isolation structure provided in the embodiments of this application, including a three-layer membrane structure;

[0061] Figure 9 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0062] Figure 10A cross-sectional schematic diagram showing a first electrode layer formed on one side of an array substrate, provided for an embodiment of this application;

[0063] Figure 11 A cross-sectional schematic diagram showing the formation of a pixel defining layer on the side of the first electrode layer away from the array substrate, provided for an embodiment of this application;

[0064] Figure 12 A cross-sectional schematic diagram showing a flattening layer formed on the side of the pixel defining layer away from the array substrate, provided for an embodiment of this application;

[0065] Figure 13 A cross-sectional schematic diagram showing an insulating layer formed on the side of the leveling layer away from the array substrate, provided for an embodiment of this application;

[0066] Figure 14 A cross-sectional schematic diagram of a via exposed at least part of a padding layer in an insulating layer, provided for an embodiment of this application;

[0067] Figure 15 This is a cross-sectional schematic diagram showing an isolation structure formed on the side of the leveling layer away from the array substrate, as provided in an embodiment of this application.

[0068] Reference numerals: 1. Array substrate; 2. Pixel defining layer; 21. Pixel opening; 3. Isolation pillar; 4. First electrode; 5. Light-emitting part; 6. Second electrode; 7. Isolation structure; 71. First isolation part; 72. Second isolation part; 73. Third isolation part; 8. Isolation opening; 9. Insulating layer; 91. Via; 10. Flattening layer; 11. Light-emitting sub-pixel; 12. First inorganic encapsulation layer; 121. Encapsulation unit; 13. Organic encapsulation layer; 14. Second inorganic encapsulation layer; 15. Touch layer; 151. Touch electrode. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0070] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0071] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0072] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0073] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0074] Please see Figure 1 The display panel in the related technology includes an array substrate 1, a first electrode layer located on one side of the array substrate 1, a pixel defining layer 2 located on the side of the first electrode layer away from the array substrate 1, and isolation pillars 3 located on the side of the pixel defining layer 2 away from the array substrate 1. The first electrode layer includes a plurality of spaced-apart first electrodes 4. The pixel defining layer 2 includes a plurality of pixel openings 21, each pixel opening 21 exposing at least a portion of the first electrodes 4. Within the pixel openings 21, along a direction away from the array substrate 1, a light-emitting portion 5 and a second electrode layer are sequentially provided. The second electrode layer is separated by the isolation pillars 3 and includes a plurality of second electrodes 6. The second electrodes 6 overlap with the isolation pillars 3, and the plurality of second electrodes 6 are electrically connected through the isolation pillars 3.

[0075] However, the edge of the first electrode 4 will make the pixel defining layer 2 uneven, which will eventually make the surface of the isolation pillar 3 uneven. This will further affect the side marking of the isolation pillar 3, the height of the roof structure of the isolation pillar 3, and the overall shape of the isolation pillar 3, resulting in the instability of the subsequent vapor deposition process. Ultimately, this will cause a large area of ​​dark spots to appear on the display panel, making the display quality of the display panel not good enough.

[0076] In view of this, this embodiment provides a solution with better display quality, and the solution provided in this embodiment will be described in detail below.

[0077] Please see Figure 2 This embodiment provides a display panel, which includes an array substrate 1, a first electrode layer, a pixel defining layer 2, and a flattening layer 10.

[0078] The array substrate 1 may include a substrate and a plurality of driving units located on one side of the substrate, each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the combination of multiple film layers in the array substrate 1; for example, the semiconductor switching devices may be thin-film transistors formed by the combination of multiple film layers.

[0079] The first electrode layer is located on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 spaced apart, and the first electrodes 4 are anodes.

[0080] The leveling layer 10 is located on one side of the array substrate 1. The orthographic projection of the leveling layer 10 on the array substrate 1 is outside the orthographic projection of the first electrode 4 on the array substrate 1. The leveling layer 10 and the first electrode 4 do not overlap, so that it is not easy for capacitance to be formed between the first electrode 4 and the leveling layer 10, thereby reducing the ghosting phenomenon of the display panel and ultimately improving the display quality of the display panel.

[0081] The pixel defining layer 2 is located on one side of the array substrate 1, and the flattening layer 10 is located on the side of the pixel defining layer 2 away from the array substrate 1; the pixel defining layer 2 includes a pixel opening 21 that exposes at least part of the first electrode 4; the display panel also includes a light-emitting layer and a second electrode layer stacked sequentially along the direction away from the array substrate 1, the second electrode layer includes a plurality of spaced second electrodes 6, the second electrodes 6 are electrically connected to the isolation structure 7, and the second electrodes 6 are cathodes.

[0082] The light-emitting layer includes a plurality of light-emitting parts 5 spaced apart. The first electrode 4, the light-emitting parts 5 and the second electrode 6 form a light-emitting sub-pixel 11. At least some of the light-emitting parts 5 and the second electrode 6 of the light-emitting sub-pixel 11 are located in the isolation opening 8. The light-emitting sub-pixel 11 can be a red sub-pixel, a green sub-pixel or a blue sub-pixel.

[0083] The isolation structure 7 is located on the side of the flattening layer 10 away from the array substrate 1. The orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the first electrode 4 on the array substrate 1. The orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the flattening layer 10 on the array substrate 1.

[0084] The orthographic projection of the isolation structure 7 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 21 on the array substrate 1. The isolation structure 7 is provided with an isolation opening 8, and the light-emitting part 5 is located inside the isolation opening 8. The orthographic projection of the pixel opening 21 on the array substrate 1 is located inside the orthographic projection of the isolation opening 8 on the array substrate 1.

[0085] When the second electrode layer is formed, the isolation structure 7 will isolate the second electrode layer to form a plurality of spaced second electrodes 6. At least a portion of the second electrodes 6 extend from the pixel opening 21 to the side of the pixel defining layer 2 away from the array substrate 1 and make electrical contact with the isolation structure 7.

[0086] Because the second electrode 6 and the flattening layer 10 are complementary in design, the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially overlaps with the orthographic projection of the first electrode 4 on the array substrate 1, and the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially overlaps with the orthographic projection of the flattening layer 10 on the array substrate 1. Therefore, the pixel defining layer 2 corresponding to the isolation structure 7 can be made flatter, resulting in better flatness of the isolation structure 7 and more stable process when evaporating the second electrode layer. The second electrode 6 formed after the isolation structure 7 isolates the second electrode layer is easier to connect with the isolation structure 7, thereby greatly improving the problem of dark spot defects in the display panel and thus improving the display quality of the display panel.

[0087] Based on the above design, this embodiment provides a flattening layer 10 on the side of the isolation structure 7 close to the array substrate 1, which can improve the flatness of the isolation structure 7, make the process of evaporating the second electrode layer more stable, and make it easier for the second electrode 6 to overlap with the isolation structure 7. This can greatly improve the problem of dark spot defects in the display panel and thus improve the display quality of the display panel.

[0088] In one possible implementation, please refer again. Figure 2 The display panel also includes an insulating layer 9 located on the side of the flattening layer 10 away from the array substrate 1, and an isolation structure 7 located on the side of the insulating layer 9 away from the array substrate 1.

[0089] The insulating layer 9 is located between the leveling layer 10 and the isolation structure 7. The insulating layer 9 can also increase the distance between the first electrode 4 and the isolation structure 7, thereby reducing the parasitic capacitance formed by the first electrode 4 and the isolation structure 7, and thus improving the display quality of the display panel.

[0090] Preferably, please refer to Figure 3 The isolation structure 7 is electrically connected to the leveling layer 10. The leveling layer 10 is made of a conductive material. Through the electrical connection between the leveling layer 10 and the isolation structure 7, a fixed potential is transmitted to the leveling layer 10 through the isolation structure 7, so that the leveling layer 10 can shield electrical signals and improve the crosstalk problem between the electrical signals of the touch layer and the electrical signals in the array substrate 1. On the other hand, it can also improve the voltage drop of the electrical signal applied to the isolation structure 7, making it easier for the display panel to uniformly apply the electrical signal of the second electrode 6 to the light-emitting sub-pixels 11 located in different positions, and ultimately improve the display quality of the display panel.

[0091] In one possible implementation, please refer again. Figure 3 The insulating layer 9 has a through hole 91, and the isolation structure 7 and the leveling layer 10 are electrically connected through the through hole 91.

[0092] The insulating layer 9 is made of materials such as silicon oxide or silicon nitride. After the insulating layer 9 is formed, a via 91 is provided on the insulating layer 9 to expose at least part of the flattening layer 10. When the isolation structure 7 is formed, the material of the isolation structure 7 enters the via 91 and contacts the flattening layer 10, thereby making it easier to electrically connect the isolation structure 7 and the flattening layer 10.

[0093] Preferably, please see again. Figure 3 Along the direction perpendicular to the array substrate 1, the thickness D1 of the insulating layer 9 ranges from 0.1 μm to 1 μm. For example, the thickness D1 can be 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, or 1 μm. If the thickness D1 of the insulating layer 9 is set too large, the thickness of the display panel will increase. If the thickness D1 of the insulating layer 9 is set too small, the insulation effect of the insulating layer 9 between the leveling layer 10 and the isolation structure 7 will decrease, and the capacitance formed between the first electrode 4 and the isolation structure 7 will increase. Therefore, by reasonably setting the thickness D1 of the insulating layer 9, the insulation effect of the insulating layer 9 between the leveling layer 10 and the isolation structure 7 can be maintained without significantly increasing the thickness of the display panel, and the capacitance formed between the first electrode 4 and the isolation structure 7 can be reduced.

[0094] In one possible implementation, please refer again. Figure 2 The distance L between the edge of the orthographic projection of the leveling layer 10 on the array substrate 1 and the edge of the orthographic projection of the first electrode 4 on the array substrate 1 ranges from 0μm to 2μm. For example, the distance L can be 0μm, 0.3μm, 0.5μm, 0.7μm, 1μm, 1.5μm, 1.7μm, 1.9μm, or 2μm. Reducing the distance between the leveling layer 10 and the first electrode 4 makes the pixel defining layer 2 between the first electrode 4 and the leveling layer 10 flatter, and makes the insulating layer 9 on the side of the leveling layer 10 away from the array substrate 1 flatter. Ultimately, this makes the isolation structure 7 flatter, thereby making it easier for the second electrode 6 and the isolation structure 7 to overlap.

[0095] Furthermore, please see again Figure 2 The distance L between the edge of the orthographic projection of the leveling layer 10 on the array substrate 1 and the edge of the orthographic projection of the first electrode 4 on the array substrate 1 ranges from 0μm to 1μm. For example, the distance L can be 0μm, 0.1μm, 0.3μm, 0.5μm, 0.7μm, 0.9μm, or 1μm. Further reducing the distance between the leveling layer 10 and the first electrode 4 can make the pixel defining layer 2 between the first electrode 4 and the leveling layer 10 flatter, and can make the insulating layer 9 on the side of the leveling layer 10 away from the array substrate 1 flatter. Ultimately, it can make the isolation structure 7 flatter, thereby making it easier for the second electrode 6 and the isolation structure 7 to overlap.

[0096] Further, please see Figure 2 and Figure 4 The distance between the edge of the orthogonal projection of the leveling layer 10 on the array substrate 1 and the edge of the orthogonal projection of the first electrode 4 on the array substrate 1 is 0 μm.

[0097] The edge of the orthographic projection of the leveling layer 10 on the array substrate 1 is in contact with the edge of the orthographic projection of the first electrode 4 on the array substrate 1. The leveling layer 10 and the first electrode 4 are complementary, which can make the pixel defining layer 2 between the first electrode 4 and the leveling layer 10 even flatter, and can make the insulating layer 9 on the side of the leveling layer 10 away from the array substrate 1 even flatter. Finally, it can make the isolation structure 7 even flatter, so that the second electrode 6 and the isolation structure 7 can be more easily connected together.

[0098] In one possible implementation, please refer again. Figure 3 The isolation structure 7 also includes a light-transmitting opening NN, the orthogonal projection of the light-transmitting opening NN on the array substrate 1 is located within the orthogonal projection of the flattening layer 10 on the array substrate 1.

[0099] The material of the leveling layer 10 includes a light-transmitting material. Optionally, the material of the leveling layer 10 may include indium tin oxide. An optical sensor can be disposed under the screen of the display panel. The optical sensor can receive light from the outside through the light-transmitting opening NN, thereby increasing the functionality of the display panel, such as enabling the display panel to take pictures.

[0100] Preferably, please see again. Figure 3 The light-emitting part 5 is offset from the light-transmitting opening NN, that is, the light-emitting part 5 is not located inside the light-transmitting opening NN, and the isolation structure 7 surrounding the light-transmitting opening NN is electrically connected to the leveling layer 10.

[0101] By misaligning the light-emitting part 5 with the light-transmitting opening NN, external light can pass through the light-transmitting opening NN of the isolation structure 7 and illuminate the screen below, thereby improving the transmittance of the display panel.

[0102] Preferably, please see again. Figure 3 Along the direction perpendicular to the array substrate 1, the ratio of the thickness D2 of the leveling layer 10 to the thickness D3 of the first electrode 4 ranges from 0.1 to 1, for example, it can be 0.1, 0.3, 0.5, 0.7, 0.9, or 1. By reasonably setting the difference between the thickness D2 of the leveling layer 10 and the thickness D3 of the first electrode 4, the flatness of the isolation structure 7 can be improved.

[0103] Preferably, the thickness D2 of the leveling layer 10 is equal to the thickness D3 of the first electrode 4 along the direction perpendicular to the array substrate 1. This makes the pixel defining layer 2 corresponding to the isolation structure 7 flatter, ultimately resulting in better flatness of the isolation structure 7.

[0104] Preferably, please see again. Figure 3 Along the direction perpendicular to the array substrate 1, the thickness D2 of the leveling layer 10 ranges from 0.05μm to 0.5μm. For example, the thickness D2 can be 0.05μm, 0.1μm, 0.2μm, 0.3μm, 0.4μm, or 0.5μm. If the thickness D2 is set too large, it will increase the thickness of the display panel; if the thickness D2 is set too small, it will affect the effect of the leveling layer 10 in making the isolation structure 7 flat. Therefore, by reasonably setting the thickness D2 of the leveling layer 10, the isolation structure 7 can be made flatter.

[0105] Preferably, please refer to Figure 5 The display panel also includes a first inorganic encapsulation layer 12 located on the side of the second electrode layer away from the array substrate 1. The first inorganic encapsulation layer 12 includes a plurality of encapsulation units 121, which extend from the side of the isolation structure 7 to the side of the isolation structure 7 away from the array substrate 1.

[0106] The isolation structure 7 includes a side close to the array substrate 1, a side away from the array substrate 1, and a side surface. The first inorganic encapsulation layer 12 is broken on the side of the isolation structure 7 away from the array substrate 1 to form a plurality of spaced-apart encapsulation units 121. The encapsulation units 121 extend from the side surface of the isolation structure 7 to the side of the isolation structure 7 away from the array substrate 1. The encapsulation units 121 encapsulate the plurality of light-emitting sub-pixels 11 independently.

[0107] Preferably, please refer to Figure 6 The display panel also includes an organic encapsulation layer 13 located on the side of the first inorganic encapsulation layer 12 away from the array substrate 1, and a second inorganic encapsulation layer 14 located on the side of the organic encapsulation layer 13 away from the array substrate 1. The organic encapsulation layer 13 and the second inorganic encapsulation layer 14 can further encapsulate the light-emitting sub-pixels 11, thereby providing better protection for the light-emitting sub-pixels 11.

[0108] Preferably, please refer to Figure 7 The display panel also includes a touch layer 15 located on the side of the second inorganic encapsulation layer 14 away from the array substrate 1. The touch layer 15 includes a plurality of touch electrodes 151. The orthographic projection of the touch electrodes 151 on the array substrate 1 at least partially overlaps with the orthographic projection of the padding layer 10 on the array substrate 1.

[0109] The array substrate 1 includes multiple metal layers, each metal layer including multiple metal traces. The flattening layer 10 is located between the metal traces of the array substrate 1 and the touch electrode 151 of the touch layer 15. The flattening layer 10 can shield the metal traces and the touch electrode 151, thereby reducing signal interference between the touch electrode 151 and the metal traces, and thus improving the display quality of the display panel.

[0110] In one possible implementation, please refer again. Figure 3 The isolation structure 7 includes a first isolation portion 71 and a second isolation portion 72 stacked sequentially along a direction away from the array substrate 1. The orthographic projection of the first isolation portion 71 onto the array substrate 1 is located within the orthographic projection of the second isolation portion 72 onto the array substrate 1.

[0111] Since the second isolation portion 72 is located on the side of the first isolation portion 71 away from the array substrate 1, and the lateral width of the second isolation portion 72 is greater than the lateral width of the first isolation portion 71, the second isolation portion 72 will disconnect the light-emitting layer and the second electrode layer at the isolation structure 7. In this way, the isolation structure 7 formed by the first isolation portion 71 and the second isolation portion 72 can allow each light-emitting sub-pixel 11 to be independently packaged.

[0112] In one possible implementation, please refer again. Figure 3 The second electrode 6 is electrically connected to the first isolation section 71; please refer to [link / reference]. Figure 8 Alternatively, the isolation structure 7 may also include a third isolation portion 73 located on the side of the first isolation portion 71 facing the array substrate 1, and the second electrode 6 is electrically connected to the third isolation portion 73; the material of the third isolation portion 73 includes molybdenum metal; and / or the material of the first isolation portion 71 includes aluminum metal; and / or the material of the second isolation portion 72 includes titanium metal.

[0113] The second electrode 6 is electrically connected to the first isolation portion 71, and the first isolation portion 71 is electrically connected to the leveling layer 10 through the through-hole 91; or the second electrode 6 is electrically connected to the third isolation portion 73, and the third isolation portion 73 is electrically connected to the leveling layer 10 through the through-hole 91. In this embodiment, when the isolation structure 7 isolates the second electrode layer into the second electrode 6, the second electrode 6 is electrically connected to the first isolation portion 71 or the third isolation portion 73.

[0114] In summary, by providing a flattening layer 10 on the side of the isolation structure 7 close to the array substrate 1, this application can improve the flatness of the isolation structure 7, make the process more stable when depositing the second electrode 6 and other film layers, and make it easier for the second electrode 6 to overlap with the isolation structure 7, thereby greatly improving the problem of dark spot defects in the display panel and thus improving the display quality of the display panel.

[0115] In one possible implementation, please refer to Figure 9This application also provides a method for manufacturing a display panel, the method comprising:

[0116] S10: Provide an array substrate 1.

[0117] The array substrate 1 may include a substrate and a plurality of driving units located on one side of the substrate, each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the combination of multiple film layers in the array substrate 1; for example, the semiconductor switching devices may be thin-film transistors formed by the combination of multiple film layers.

[0118] S11: A first electrode layer and a flattening layer 10 are formed on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 spaced apart. The orthographic projection of the flattening layer 10 on the array substrate 1 is outside the orthographic projection of the first electrodes 4 on the array substrate 1.

[0119] Please see Figure 10 A first electrode layer is formed on one side of the array substrate 1. The first electrode layer includes a plurality of first electrodes 4 spaced apart, and the first electrodes 4 are anodes.

[0120] Please see Figure 11 A pixel defining layer 2 is formed on the side of the first electrode layer away from the array substrate 1. The pixel defining layer 2 includes a pixel opening 21 that exposes at least a portion of the first electrode 4.

[0121] Please see Figure 12 A flattening layer 10 is formed on the side of the pixel defining layer 2 away from the array substrate 1.

[0122] Please see Figure 13 An insulating layer 9 is formed on the side of the padding layer 10 away from the array substrate 1. The material of the insulating layer 9 may include silicon oxide or silicon nitride.

[0123] Please see Figure 14 A via 91 is formed on the insulating layer 9 to expose at least part of the flattening layer 10. The flattening layer 10 can be electrically connected to the isolation structure 7 through the via 91, thereby improving the signal crosstalk between the touch electrode 151 of the touch layer in the display panel and the metal traces of the array substrate 1.

[0124] S12: An isolation structure 7 is formed on the side of the flattening layer 10 away from the array substrate 1; the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the first electrode 4 on the array substrate 1, and the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially coincides with the orthographic projection of the flattening layer 10 on the array substrate 1.

[0125] Please see Figure 15An isolation structure 7 is formed on the side of the leveling layer 10 away from the array substrate 1. The orthographic projection of the isolation structure 7 on the array substrate 1 lies between the orthographic projections of two adjacent pixel openings 21 on the array substrate 1. The isolation structure 7 encloses and forms an isolation opening 8, and the orthographic projection of the pixel opening 21 on the array substrate 1 lies within the orthographic projection of the isolation opening 8 on the array substrate 1. When the isolation structure 7 is formed, the material of the isolation structure 7 enters the via 91 and contacts the leveling layer 10, thereby making the isolation structure 7 electrically connected to the leveling layer 10.

[0126] Please see again Figure 3 Within the pixel opening 21, along the direction away from the array substrate 1, a light-emitting layer and a second electrode layer are sequentially formed. When forming the light-emitting layer and the second electrode layer, the isolation structure 7 will separate the light-emitting layer to form a plurality of spaced light-emitting portions 5, which are located within the pixel opening 21. The isolation structure 7 will also separate the second electrode layer to form a plurality of spaced second electrodes 6, at least a portion of which extend from the pixel opening 21 to the side of the pixel defining layer 2 away from the array substrate 1 and make electrical contact with the isolation structure 7.

[0127] Because the second electrode 6 and the flattening layer 10 are complementary in design, the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially overlaps with the orthographic projection of the first electrode 4 on the array substrate 1, and the orthographic projection of the isolation structure 7 on the array substrate 1 at least partially overlaps with the orthographic projection of the flattening layer 10 on the array substrate 1. Therefore, the pixel defining layer 2 corresponding to the isolation structure 7 can be made flatter, resulting in better flatness of the isolation structure 7 and more stable process when evaporating the second electrode layer and other film layers. The second electrode 6 formed after the isolation structure 7 isolates the second electrode layer overlaps with the isolation structure 7, which can greatly improve the problem of dark spot defects in the display panel and thus improve the display quality of the display panel.

[0128] In one possible implementation, this application also provides an electronic device that includes the display panel described in this application. This electronic device may include a device with image processing capabilities, such as a server, personal computer, laptop computer, etc. Because this electronic device includes the display panel described in this application, it has higher display quality.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Array substrate; A first electrode layer located on one side of the array substrate, the first electrode layer comprising a plurality of spaced first electrodes; A pixel defining layer is located on the side of the first electrode layer away from the array substrate. The side of the pixel defining layer away from the array substrate has a groove recessed in the direction of the array substrate. The orthographic projection of the groove on the array substrate is located between the orthographic projections of two adjacent first electrodes on the array substrate. A leveling layer located within the groove, wherein the orthographic projection of the leveling layer on the array substrate is outside the orthographic projection of the first electrode on the array substrate; An insulating layer located on the side of the leveling layer away from the array substrate; An isolation structure located on the side of the insulating layer away from the array substrate, wherein the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, and the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the flattening layer on the array substrate, wherein the isolation structure is electrically connected to the flattening layer, and the flattening layer makes the isolation structure flat.

2. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting layer and a second electrode layer stacked sequentially along a direction away from the array substrate. The second electrode layer includes a second electrode, which is electrically connected to the isolation structure.

3. The display panel according to claim 1 or 2, characterized in that, The distance between the edge of the orthogonal projection of the leveling layer on the array substrate and the edge of the orthogonal projection of the first electrode on the array substrate is in the range of 0μm-2μm.

4. The display panel according to claim 3, characterized in that, The distance between the edge of the orthogonal projection of the leveling layer on the array substrate and the edge of the orthogonal projection of the first electrode on the array substrate is in the range of 0μm-1μm.

5. The display panel according to claim 4, characterized in that, The distance between the edge of the orthogonal projection of the leveling layer on the array substrate and the edge of the first electrode on the orthogonal projection of the first electrode on the array substrate is 0 μm.

6. The display panel according to claim 1, characterized in that, The insulating layer is provided with vias, and the isolation structure and the leveling layer are electrically connected through the vias. The insulating layer is made of silicon oxide or silicon nitride.

7. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the array substrate, the thickness of the insulating layer ranges from 0.1 μm to 1 μm.

8. The display panel according to claim 2, wherein the isolation structure is provided with an isolation opening, and the light-emitting layer includes a light-emitting part, the light-emitting part being located within the isolation opening.

9. The display panel according to claim 8, characterized in that, The isolation structure is also provided with a light-transmitting opening, and the orthographic projection of the light-transmitting opening on the array substrate is located within the orthographic projection of the leveling layer on the array substrate.

10. The display panel according to claim 9, characterized in that, The light-emitting part is offset from the light-transmitting opening.

11. The display panel according to claim 9, characterized in that, The isolation structure surrounding the light-transmitting opening is electrically connected to the leveling layer; The material of the leveling layer includes a light-transmitting material.

12. The display panel according to claim 11, characterized in that, The material of the leveling layer includes indium tin oxide.

13. The display panel according to claim 1 or 2, characterized in that, Along a direction perpendicular to the array substrate, the ratio of the thickness of the leveling layer to the thickness of the first electrode ranges from 0.1 to 1.

14. The display panel according to claim 1 or 2, characterized in that, Along a direction perpendicular to the array substrate, the thickness of the leveling layer is equal to the thickness of the first electrode.

15. The display panel according to claim 1 or 2, characterized in that, Along a direction perpendicular to the array substrate, the thickness of the leveling layer ranges from 0.05 μm to 0.5 μm.

16. The display panel according to claim 1 or 2, characterized in that, The pixel defining layer includes pixel openings that expose at least a portion of the first electrode, and the orthographic projection of the isolation structure on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate; The isolation structure has an isolation opening, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate.

17. The display panel according to claim 2, the display panel further comprising a first inorganic encapsulation layer located on the side of the second electrode layer away from the array substrate, the first inorganic encapsulation layer comprising a plurality of encapsulation units, the encapsulation units extending from the side of the isolation structure to the side of the isolation structure away from the array substrate; The display panel further includes an organic encapsulation layer located on the side of the first inorganic encapsulation layer away from the array substrate; The display panel further includes a second inorganic encapsulation layer located on the side of the organic encapsulation layer away from the array substrate; The display panel further includes a touch layer located on the side of the second inorganic encapsulation layer away from the array substrate. The touch layer includes a plurality of touch electrodes, and the orthographic projection of the touch electrodes on the array substrate at least partially overlaps with the orthographic projection of the flattening layer on the array substrate.

18. The display panel according to claim 2, characterized in that, The isolation structure includes a first isolation portion and a second isolation portion stacked sequentially along a direction away from the array substrate, wherein the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

19. The display panel according to claim 18, characterized in that, The second electrode is electrically connected to the first isolation portion; or the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion; The material of the third isolation part includes molybdenum metal; and / or the material of the first isolation part includes aluminum metal; and / or the material of the second isolation part includes titanium metal.

20. A method for manufacturing a display panel, characterized in that, The method includes: Provide an array substrate; A first electrode layer is formed on one side of the array substrate, the first electrode layer comprising a plurality of spaced first electrodes; A pixel defining layer is formed on the side of the first electrode layer away from the array substrate. The side of the pixel defining layer away from the array substrate has a groove recessed in the direction of the array substrate. The orthographic projection of the groove on the array substrate is located between the orthographic projections of two adjacent first electrodes on the array substrate. A leveling layer is formed within the groove, and the orthographic projection of the leveling layer on the array substrate is located outside the orthographic projection of the first electrode on the array substrate; An insulating layer is formed on the side of the leveling layer away from the array substrate; An isolation structure is formed on the side of the insulating layer away from the array substrate; the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the first electrode on the array substrate, the orthographic projection of the isolation structure on the array substrate at least partially coincides with the orthographic projection of the flattening layer on the array substrate, the isolation structure is electrically connected to the flattening layer, and the flattening layer makes the isolation structure flat.

21. The method for manufacturing a display panel according to claim 20, characterized in that, Prior to the step of forming an isolation structure on the side of the insulating layer away from the array substrate, the method further includes: A via is formed in the insulating layer to expose at least a portion of the leveling layer, so that the isolation structure and the leveling layer are electrically connected through the via.

22. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-19.

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