A fiber access device

Abstract

The application provides an optical fiber access device, and relates to the technical field of communication, which comprises a programmable logic device, an RS485 interface chip and an SFP optical module. The RS485 interface chip is connected with the SFP optical module through the programmable logic device. The RS485 interface chip is used for sending first sampling data to the programmable logic device. The programmable logic device is used for converting a private frame structure into a PECL level and sending the PECL level to the SFP optical module. The SFP optical module is used for converting the PECL level into an optical signal for transmission on an optical fiber. The first sampling data is a TTL level converted by the RS485 interface chip based on an RS485 interface level. The private frame structure is a private communication frame structure constructed by the programmable logic device based on first sampling data, second sampling data and third sampling data. The optical fiber communication technology is used to successfully break through the limitation of the connection distance of a traditional RS485 cable and to realize the transparent transmission of the RS485 communication interface.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an optical fiber access device. Background Technology

[0002] As a mainstream serial standard in industrial communication, the RS485 data interface boasts advantages such as strong anti-interference capabilities and multi-node networking due to its differential signal transmission mechanism, leading to its widespread application in smart grids and remote device management. However, in existing technologies, access devices based on the RS485 data interface typically communicate via cable connections. This method, due to its physical layer characteristics, limits the transmission distance (cable connection distance is generally no more than 1000 meters), making RS485-based communication devices unable to meet long-distance communication requirements.

[0003] With the development of the Industrial Internet of Things, the demand for monitoring at the kilometer level and cross-regional device interconnection has surged, creating an urgent need for an access device that can extend the communication transmission distance while maintaining RS485 protocol compatibility. Summary of the Invention

[0004] This application provides an optical fiber access device that increases the communication transmission distance while maintaining RS485 protocol compatibility.

[0005] This application provides an optical fiber access device, including a programmable logic device (PLD), an RS485 interface chip, and a small pluggable (SFP) optical module. The RS485 interface chip is connected to the SFP optical module through the PLD. The RS485 interface chip is used to send first sampled data to the PLD. The PLD is used to convert a private frame structure into a positive emitter coupled logic (PECL) level and send it to the SFP optical module. The SFP optical module is used to convert the PECL level into an optical signal for transmission on the optical fiber.

[0006] Wherein, the first sampled data is the transistor-to-transistor logic TTL level of the RS485 interface chip based on RS485 interface level conversion, the private frame structure is the private communication frame structure constructed by the programmable logic device based on the first sampled data, the second sampled data and the third sampled data, the first sampled data includes the first RS485 interface data and the second RS485 interface data, the second sampled data includes the data line data and clock line data of the synchronous, half-duplex communication I2C bus acquired by the programmable logic device, and the third sampled data includes the configuration information of the optical fiber access device.

[0007] Optionally, each private frame in the private frame structure includes a first time slot, a second time slot, a third time slot, a fourth time slot, and a fifth time slot. The first time slot is used to transmit frame byte and overhead information. The frame byte is used for frame synchronization, and the overhead information is used for device management. The second time slot is used to transmit the first RS485 interface data, the third time slot is used to transmit the second RS485 interface data, the fourth time slot is used to transmit the clock line data of the I2C bus, and the fifth time slot is used to transmit the data line data of the I2C bus.

[0008] Optionally, the data structure consisting of the frame byte and the overhead information is an 8-row * 16-column matrix.

[0009] Optionally, the matrix data includes:

[0010] The first field is used to indicate the frame byte, and the first field is not scrambled;

[0011] The second field is a multiframe indicator;

[0012] The third field is used to indicate alarm information of the remote device connected to the RS485 interface chip;

[0013] The fourth field is used to indicate alarm information of the optical path connected to the SFP optical module;

[0014] The fifth field is used to indicate transmission error information;

[0015] The sixth field is used to indicate the configuration information;

[0016] The seventh field is used to indicate reserved information;

[0017] The eighth field is used to indicate the checksum of the first field.

[0018] Optionally, the frame period of the first time slot is 819.2 μs.

[0019] Optionally, the transmission rate of each of the first time slot, the second time slot, the third time slot, the fourth time slot, and the fifth time slot is 2.5 Mbps.

[0020] Optionally, the frame rate of the private frame structure is 12.5 Mbps.

[0021] Optionally, the private frame structure is a private communication frame structure using bit interleaving multiplexing.

[0022] Optionally, it also includes a power drop detection module, wherein the power drop detection module is provided with an energy storage capacitor, and the energy storage capacitor is electrically connected to the programmable logic device.

[0023] Optionally, it also includes a crystal oscillator for sending 25MHz operating clock information to the programmable logic device.

[0024] In this embodiment, the RS485 interface chip enables the conversion of two RS485 interface levels. Specifically, it converts the interface levels corresponding to the first and second RS485 interface data streams to TTL levels to obtain first sampled data. This first sampled data is then sent to a programmable logic device (PLD) for further processing. This achieves the interface between the RS485 interface chip and the PLD. Furthermore, the PLD can sample the data and clock lines of the I2C bus to obtain second sampled data, and sample configuration information to obtain third sampled data. Based on the first, second, and third sampled data, the PLD constructs a private frame structure and converts it to PECL levels before sending it to the SFP optical module. The SFP optical module can then convert the PECL levels into optical signals for transmission over the optical fiber. This utilizes optical fiber communication technology to successfully overcome the limitations of traditional RS485 cable connection distances, enabling an increase in the transparent transmission distance of the RS485 communication interface. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of the fiber optic access device provided in the embodiments of this application;

[0027] Figure 2 This is a schematic diagram of the private frame structure provided in the embodiments of this application;

[0028] Figure 3 This is a schematic diagram of matrix data in the first time slot provided in the embodiments of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0031] like Figure 1 As shown in the figure, this application provides an optical fiber access device, including a programmable logic device, an RS485 interface chip, and a small form pluggable (SFP) optical module. The RS485 interface chip is connected to the SFP optical module through the programmable logic device. The RS485 interface chip is used to send first sampled data to the programmable logic device. The programmable logic device is used to convert a private frame structure into a Pseudo-Emitter Coupled Logic (PECL) level and send it to the SFP optical module. The SFP optical module is used to convert the PECL level into an optical signal for transmission on the optical fiber.

[0032] Wherein, the first sampled data is the transistor-transistor logic (TTL) level of the RS485 interface chip based on RS485 interface level conversion; the private frame structure is a private communication frame structure constructed by the programmable logic device based on the first sampled data, the second sampled data, and the third sampled data; the first sampled data includes the first RS485 interface data and the second RS485 interface data; the second sampled data includes the data line data and clock line data of the synchronous, half-duplex communication (Inter-Integrated Circuit, I2C) bus acquired by the programmable logic device; and the third sampled data includes the configuration information of the fiber optic access device.

[0033] In this embodiment, the RS485 interface chip enables the conversion of two RS485 interface levels. Specifically, it converts the interface levels corresponding to the first and second RS485 interface data streams to TTL levels to obtain first sampled data. This first sampled data is then sent to the programmable logic device (PLD) for further processing. This achieves the interface between the RS485 interface chip and the PLD. Furthermore, the PLD can sample I2C bus data lines and clock lines to obtain second sampled data; and sample configuration information (e.g., Bill of Materials (BOM) version; Printed Circuit Board (PCB) version; Charge Injection Device (CID) type, etc.) to obtain third sampled data. Based on the first, second, and third sampled data, the PLD constructs a private frame structure and converts it to PECL levels before sending it to the SFP optical module. This allows the SFP optical module to convert the PECL levels into optical signals for transmission over the optical fiber. By utilizing fiber optic communication technology, the limitations of traditional RS485 cable connection distances can be successfully overcome, enabling transparent transmission of RS485 communication interfaces over long distances (e.g., 0-40km).

[0034] The RS485 interface chip is connected to an RS485 interface. The two RS485 interface levels (A+, A-; B+, B-) are converted to TTL levels by the RS485 interface chip and then sent to the programmable logic device. The programmable logic device communicates with the SFP optical module to transmit data (TXD), receive data (RXD), serial clock (SCK) signals, and serial data (SDA) signals.

[0035] Before converting the first and second sampled data into PECL levels and sending them to the SFP optical module, the programmable logic device can perform multiplexing processing on the sampled data to optimize resource utilization and achieve concurrent transmission of multiple signals; perform framing processing on the sampled data to ensure clear data boundaries and support synchronization, error correction and protocol parsing; and perform scrambling processing on the sampled data to improve signal reliability and security and avoid physical layer transmission problems.

[0036] Optionally, each private frame in the private frame structure includes a first time slot, a second time slot, a third time slot, a fourth time slot, and a fifth time slot. The first time slot is used to transmit frame byte and overhead information. The frame byte is used for frame synchronization, and the overhead information is used for device management. The second time slot is used to transmit the first RS485 interface data, the third time slot is used to transmit the second RS485 interface data, the fourth time slot is used to transmit the clock line data of the I2C bus, and the fifth time slot is used to transmit the data line data of the I2C bus.

[0037] In this embodiment, the private frame structure may include multiple private frames. Each private frame is configured to include 5 bits, with each bit representing a transmission time slot. In other words, each private frame in the private frame structure includes a first time slot, a second time slot, a third time slot, a fourth time slot, and a fifth time slot. The first time slot can be named FSA, the second time slot can be named TS1, the third time slot can be named TS2, the fourth time slot can be named SCL, and the fifth time slot can be named SDA, etc. Figure 2 As shown. The first time slot FSA is used to transmit the frame byte and overhead information. The frame byte is used for frame synchronization, and the overhead information is used for device management. The second time slot TS1 is used to transmit the first RS485 interface data. The third time slot TS2 is used to transmit the second RS485 interface data. The fourth time slot SCL is used to transmit the clock line data of the I2C bus. The fifth time slot SDA is used to transmit the data line data of the I2C bus.

[0038] This approach allocates the two RS485 interface data streams, I2C clock line data, and I2C data line data to independent time slots, avoiding signal interference. Fixed time slot allocation eliminates the need for complex bus arbitration mechanisms, reducing hardware design complexity. Specifically, the second time slot (TS1) and the third time slot (TS2) can achieve asynchronous data synchronization by matching the baud rate to the time slot period; the fourth time slot (SCL) and the fifth time slot (SDA) can retain the original clock synchronization characteristics, ensuring the receiver can completely reproduce the I2C waveform (such as start, stop, and acknowledge bits). Furthermore, the frame bytes transmitted in the first time slot (FSA) can achieve rapid frame synchronization using a fixed mode (such as 0xFF), avoiding parsing errors caused by misalignment. The overhead information transmitted in the first time slot (FSA) enables a lightweight yet efficient device management mechanism, allowing network maintenance personnel to promptly understand the status of fiber optic access devices and remote devices, improving remote management efficiency.

[0039] The frame bytes and overhead information transmitted in the first time slot FSA are described in detail below:

[0040] Optionally, the data structure formed by the frame byte and the overhead information is an 8-row * 16-column matrix, totaling 256 bytes. This provides good information capacity, reliability, and scalability.

[0041] Optionally, the matrix data includes:

[0042] The first field is used to indicate the frame byte, and the first field is not scrambled;

[0043] The second field is a multiframe indicator;

[0044] The third field is used to indicate alarm information of the remote device connected to the RS485 interface chip;

[0045] The fourth field is used to indicate alarm information of the optical path connected to the SFP optical module;

[0046] The fifth field is used to indicate transmission error information;

[0047] The sixth field is used to indicate the configuration information;

[0048] The seventh field is used to indicate reserved information;

[0049] The eighth field is used to indicate the checksum of the first field.

[0050] In this embodiment, as Figure 3 As shown, an 8x16 matrix can include:

[0051] The first field, the FSA_OH field, is used to indicate the frame byte. It can consist of 6 fixed bytes, which are fixed as: 0xF6, 0xF6, 0xF6, 0x28, 0x28, 0x28. The FSA_OH field is not scrambled, which can avoid the scrambling code from destroying the synchronization code characteristics and ensure that the receiver can quickly capture the frame header through sliding window detection.

[0052] The second field, the MFI field, is a multiframe indicator used to indicate which subframe the current frame belongs to. Its value ranges from 0 to 255 and supports time-division multiplexing of multiple frames.

[0053] The third field, the PRD field, is used to indicate alarm information of the remote device connected to the RS485 interface chip. If the remote device loses power, this field is 1; if the power is normal, it is 0. This enables power failure alarms for the remote device, thus allowing for remote management of the remote device.

[0054] The fourth field, the ALM field, is used to indicate alarm information of the optical path connected to the SFP optical module. If an alarm occurs in the optical path, this field is 1, and if there is no alarm, it is 0. This enables the SFP optical module to be remotely managed.

[0055] The fifth field, the ERR field, is used to indicate transmission error information. If the previous frame failed verification, this field is 1; otherwise, it is 0.

[0056] The sixth field, used to indicate configuration information, may include at least one of the following fields:

[0057] The CID field is used to transmit device type information, with a value of 0-255, which is encoded according to the device type. For example, 0 = optical module, 1 = switch, 2 = sensor.

[0058] The PCB field is used to transmit PCB version information and record the circuit board version (e.g., V1.2→0x12), with a value of 0-255.

[0059] The BOM field is used to transmit BOM version information and record the bill of materials version (e.g., Rev.C→0x03), with a value of 0-255.

[0060] The MOD field is used to transmit module type information. For example, 1 indicates that the transmission module type is remote, and 0 indicates that the transmission module type is local, thus realizing network hierarchical management.

[0061] The LP field is used to transmit loopback configuration information. For example, 1 indicates that loopback is configured, and 0 indicates that loopback is canceled.

[0062] The PWR field is used to transmit power type information. For example, 1 indicates that the power type is AC, and 0 indicates that the power type is DC.

[0063] The seventh field, the RSV field, is used to indicate reserved information that can be used for future expansion functions, such as encryption keys, IPv6 address extensions, etc.

[0064] The eighth field, the FCS field, indicates the checksum of the first field. Cyclic redundancy check is performed on the entire FAS frame to ensure data integrity.

[0065] In this way, the private frame structure achieves fast synchronization and avoids scrambling interference through the FSA_OH framing symbol, the MFI multiframe indicator supports 256 levels of time division multiplexing, the PRD / ALM / ERR three-bit linkage enables millisecond-level fault diagnosis, the CID / PCB / BOM fields support full lifecycle traceability of the device, the LP / PWR fields optimize testing and power management, and RSV reserves expansion space. Combined with the 256-byte matrix architecture and CRC32 check, in the scenario of transparent transmission of long-distance RS485 communication interface using fiber optic communication, the real-time performance, reliability and scalability of fiber optic access equipment are significantly improved.

[0066] Optionally, the transmission rate of each of the first, second, third, fourth, and fifth time slots is 2.5 Mbps. This allows each time slot to transmit a large amount of data in a short time. For example, in a transparent transmission scenario using a long-distance RS485 communication interface with fiber optic communication, it can quickly upload large amounts of data collected by sensors (such as temperature, pressure, flow, etc.), reducing data transmission latency and improving the real-time response capability of fiber optic access equipment.

[0067] Optionally, the frame period of the first time slot is 819.2 µs. This provides a stable time reference for the entire fiber optic access equipment. In transparent transmission scenarios using long-distance RS485 communication interfaces with fiber optic communication, the central office equipment and the remote equipment can perform precise synchronization based on this fixed frame period, ensuring accurate data transmission and reception, and improving the reliability and stability of communication.

[0068] Optionally, the frame rate of the private frame structure is 12.5 Mbps. This ensures that the entire frame structure can transmit data at a high speed.

[0069] Optionally, the private frame structure is a private communication frame structure using bit interleaving multiplexing.

[0070] In this example, a proprietary communication frame structure with a rate of 12.5 Mbps is used. Each frame consists of 5 bits of data, and each bit represents a transmission time slot. Each time slot has a rate of 2.5 Mbps and is used to transmit two RS485 data streams and I2C interface management information for the SFP optical module. The five time slots are multiplexed into a 12.5 Mbps proprietary communication frame using bit-interleaving. This proprietary frame structure, employing bit-interleaving multiplexing, improves spectral efficiency within the frame period by dynamically interleaving multi-service bit streams, enhances resistance to sudden interference, and ensures real-time data transmission.

[0071] Optionally, it also includes a power drop detection module, wherein the power drop detection module is provided with an energy storage capacitor, and the energy storage capacitor is electrically connected to the programmable logic device.

[0072] In this example, the power drop detection module monitors the input power supply voltage in real time. When the voltage is detected to be lower than the threshold, the programmable logic device immediately triggers the energy storage capacitor to supply power, ensuring that a power failure alarm is sent to the central office through the PRD field in the private frame structure at the moment of power drop. At the same time, it maintains the power supply of critical modules for 30ms to complete the last data sampling and transmission, achieving millisecond-level fault response, data integrity protection and industrial-grade wide-temperature reliability. It is particularly suitable for transparent transmission scenarios using fiber optic communication to achieve long-distance RS485 communication interfaces.

[0073] Optionally, it also includes a crystal oscillator for sending 25MHz operating clock information to the programmable logic device.

[0074] In this example, the 25MHz reference clock provided by the crystal oscillator provides a precise timing reference for the programmable logic device, ensuring nanosecond-level synchronization between the 12.5Mbps frame rate and the 2.5Mbps timeslot rate, thereby improving the synchronization, reliability, and anti-interference capability of the fiber optic access equipment.

[0075] This application employs fiber optic communication technology and a proprietary communication frame structure, enabling fiber optic transmission of two RS485 data interfaces at a rate of 12.5 Mbps. It supports transparent transmission of RS485 data interface communication signals, with an RS485 data interface rate range of 4800 bps to 200 kbps. Simultaneously, it enables fiber optic transmission of the I2C management bus, supporting transparent transmission of I2C bus clock and data to manage remote SFP modules. This allows for reporting remote device power failure alarms, optical interface alarms, and device information to the central office. Furthermore, a programmable logic device (PLD) is used to implement proprietary communication framing and frame synchronization, multiplexing and demultiplexing, scrambling and descrambling processing. The PLD is externally connected to an RS485 interface chip, a power drop detection circuit, SFP optical module data circuitry, and I2C management interface circuitry. This successfully overcomes the limitations of traditional RS485 cable connection distances, enabling an increase in the transparent transmission distance of the RS485 communication interface.

[0076] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0077] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0078] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A fiber optic access device, characterized in that, The device includes a programmable logic device, an RS485 interface chip, and a small pluggable SFP optical module. The RS485 interface chip is connected to the SFP optical module through the programmable logic device. The RS485 interface chip is used to send first sampled data to the programmable logic device. The programmable logic device is used to convert a private frame structure into a positive emitter coupled logic (PECL) level and send it to the SFP optical module. The SFP optical module is used to convert the PECL level into an optical signal for transmission on an optical fiber. Wherein, the first sampled data is the transistor-to-transistor logic TTL level of the RS485 interface chip based on RS485 interface level conversion; the private frame structure is a private communication frame structure constructed by the programmable logic device based on the first sampled data, the second sampled data, and the third sampled data; the first sampled data includes the first RS485 interface data and the second RS485 interface data; the second sampled data includes the data line data and clock line data of the synchronous, half-duplex communication I2C bus acquired by the programmable logic device; and the third sampled data includes the configuration information of the fiber optic access device. Each private frame in the private frame structure includes a first time slot for transmitting frame byte and overhead information. The frame byte is used for frame synchronization, and the overhead information is used for device management. The data structure formed by the frame byte and the overhead information is an 8-row * 16-column matrix, which includes: The first field is used to indicate the frame byte, and the first field is not scrambled; The second field is a multiframe indicator; The third field is used to indicate alarm information of the remote device connected to the RS485 interface chip; The fourth field is used to indicate alarm information of the optical path connected to the SFP optical module; The fifth field is used to indicate transmission error information; The sixth field is used to indicate the configuration information; The seventh field is used to indicate reserved information; The eighth field is used to indicate the checksum of the first field.

2. The fiber optic access device according to claim 1, characterized in that, Each private frame in the private frame structure further includes a second time slot, a third time slot, a fourth time slot, and a fifth time slot. The second time slot is used to transmit the first RS485 interface data, the third time slot is used to transmit the second RS485 interface data, the fourth time slot is used to transmit the clock line data of the I2C bus, and the fifth time slot is used to transmit the data line data of the I2C bus.

3. The fiber optic access device according to claim 2, characterized in that, The frame period of the first time slot is 819.2 μs.

4. The fiber optic access device according to claim 2, characterized in that, The transmission rate of each of the first, second, third, fourth and fifth time slots is 2.5 Mbps.

5. The fiber optic access device according to claim 1, characterized in that, The frame rate of the private frame structure is 12.5 Mbps.

6. The fiber optic access device according to claim 1, characterized in that, The private frame structure is a private communication frame structure that uses bit interleaving multiplexing.

7. The fiber optic access device according to claim 1, characterized in that, It also includes a power drop detection module, which is equipped with an energy storage capacitor, and the energy storage capacitor is electrically connected to the programmable logic device.

8. The fiber optic access device according to claim 1, characterized in that, It also includes a crystal oscillator, which is used to send 25MHz operating clock information to the programmable logic device.

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