A pixel circuit and a method of generating a combined converted value of the pixel circuit

Abstract

This disclosure relates to an adaptive data selection for DCG / DAG. A pixel circuit includes: a pixel array comprising a plurality of pixels; a plurality of analog-to-digital converters (ADCs), wherein during pixel data readout, the plurality of ADCs are communicatively coupled to a corresponding pixel among the plurality of pixels to receive image data from the corresponding pixel among the plurality of pixels; a plurality of decision blocks, wherein each decision block is communicatively coupled to a corresponding ADC among the plurality of ADCs, and wherein each decision block is configured to select and transmit gain data based on comparing the output of the corresponding ADC with a predetermined threshold of the corresponding ADC; and an image signal processor (ISP) configured to: receive the outputs from the plurality of ADCs; and combine the outputs of the plurality of ADCs to generate a combined converted value for the corresponding pixel.

Description

Technical Field

[0001] This disclosure generally relates to the design of image sensors, and more particularly to image sensors having improved photodiode illumination. Background Technology

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher image sensor resolution and lower power consumption has driven further miniaturization and integration of image sensors into digital devices.

[0003] An image sensor operates in response to image light from an external scene that is incident on the image sensor. The image sensor includes an array of pixels with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate a corresponding charge in response. The charge of an individual pixel can be measured as the output voltage of each photosensitive element. Generally, the output voltage varies as a function of the intensity and duration of the incident light. The output voltage of the individual photosensitive elements is used to generate a digital image (i.e., image data) representing the external scene.

[0004] In some applications, photodiodes are illuminated by a combination of a lens and a color filter, exposing individual photodiodes to light of a given color (wavelength), such as blue, green, or red. Based on the fact that photodiodes are exposed only to a limited wavelength range, their properties can be optimized so that, for example, the peak sensitivity of a given photodiode is within a target range of light wavelengths. However, lenses and color filters inevitably attenuate the incoming light, thus limiting the dynamic range of the photodiode. Therefore, systems and methods are needed to improve the illumination and dynamic range of image sensors. Summary of the Invention

[0005] One aspect of this disclosure relates to a pixel circuit comprising: a pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs), wherein during pixel data readout, the plurality of ADCs are communicatively coupled to respective plurality of pixels to receive image data from a respective pixel among the plurality of pixels; a plurality of decision blocks, wherein each decision block is communicatively coupled to a respective ADC among the plurality of ADCs, and wherein each decision block is configured to select and transmit gain data based on comparing the output of the respective ADC with a predetermined threshold of the respective ADC; and an image signal processor (ISP) configured to: receive the outputs from the plurality of ADCs; and combine the outputs of the plurality of ADCs to generate a combined converted value for the respective pixel.

[0006] Another aspect of this disclosure relates to a method for generating a combined converted value for a pixel circuit, the pixel circuit comprising: a pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs), wherein during pixel data readout, the plurality of ADCs are communicatively coupled to respective plurality of pixels to receive image data from a respective pixel among the plurality of pixels; and a plurality of decision blocks, wherein each decision block is communicatively coupled to a respective ADC among the plurality of ADCs, and wherein each decision block is configured to select and transmit gain data based on comparing the output of the respective ADC with the predetermined threshold of the respective ADC, the method comprising: transmitting the image data from each respective pixel among the plurality of pixels to the plurality of ADCs; comparing the output of the respective ADC with the predetermined threshold of the respective ADC; selecting the gain data from the output of each ADC using each of the plurality of decision blocks; transmitting the gain data of each ADC among the plurality of ADCs to an ISP; receiving the outputs from the plurality of ADCs using the ISP; and combining the outputs of the plurality of ADCs to generate a combined converted value for the respective pixel.

[0007] Another aspect of this disclosure relates to a method for generating a combined converted value for a pixel circuit according to claim 1, the method comprising: transmitting image data from each corresponding pixel of the plurality of pixels to the plurality of ADCs; comparing the output of the corresponding ADC with a predetermined threshold of the corresponding ADC; selecting gain data from the output of each ADC using each of the plurality of decision blocks; transmitting the gain data of each ADC to the ISP; receiving the outputs from the plurality of ADCs using the ISP; and combining the outputs of the plurality of ADCs to generate a combined converted value for the corresponding pixel. Attached Figure Description

[0008] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein, unless otherwise specified, similar reference numerals refer to similar parts throughout the views.

[0009] Figure 1 The illustration depicts an imaging system according to an embodiment of the present disclosure.

[0010] Figure 2 This is an illustrative schematic diagram of a conventional pixel circuit according to the present disclosure.

[0011] Figure 3 This is an illustrative schematic diagram of a conventional pixel circuit for generating combined converted values ​​of pixels according to the present disclosure.

[0012] Figure 4This is an illustrative schematic diagram of a pixel circuit for generating combined converted values ​​of pixels according to the present disclosure.

[0013] Figure 5A This is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0014] Figure 5B This is an illustrative representation of the ADC code according to this disclosure.

[0015] Figure 5C This is a graph for selecting a predetermined threshold for conversion gain according to embodiments of the present disclosure.

[0016] Figure 6A This is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0017] Figure 6B This is an illustrative diagram of the timing pulses for determining the time sequence according to embodiments of the present disclosure.

[0018] Figure 7A This is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0019] Figure 7B This is a graph used to determine a first threshold and a second threshold for a selected conversion gain according to embodiments of the present disclosure.

[0020] Figure 7C This is a graph used to determine a first threshold and a second threshold for a selected conversion gain according to embodiments of the present disclosure.

[0021] Figure 8A This is a graph used to determine a first threshold and a second threshold for a selected conversion gain according to embodiments of the present disclosure.

[0022] Figure 8B This is a graph used to determine a predetermined threshold for a selected conversion gain according to embodiments of the present disclosure.

[0023] Figure 8C This is a graph used to determine a predetermined threshold T for a selected conversion gain according to embodiments of the present disclosure.

[0024] Figure 9 This is a method for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure.

[0025] Figure 10 This is another method for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure.

[0026] Figure 11 This is another method for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure.

[0027] Figure 12 This is another method for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure.

[0028] Throughout the various views of the drawings, corresponding reference characters indicate the corresponding components. Those skilled in the art will understand that the elements in the drawings are illustrative for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, the dimensions of some elements in the figures may be enlarged relative to other elements. Furthermore, common and well-known elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate a more unobstructed view of these various embodiments of the invention. Detailed Implementation

[0029] Image sensors, and more specifically, image sensors for color routers, are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the stated specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring particular aspects.

[0030] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0031] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” may be used herein to describe the relationship of one element or feature relative to another element(s) as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” other elements or features will be oriented as “above” other elements or features. Therefore, the exemplary terms “below” and “below” may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptions used herein will be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0032] Based on the foregoing, it will be understood that while specific embodiments of the present technology have been described herein for illustrative purposes, various modifications may be made without departing from this disclosure. Furthermore, although various advantages and features associated with particular embodiments have been described in the context of those embodiments, other embodiments may also exhibit such advantages and / or features, and not all embodiments must exhibit such advantages and / or features to fall within the scope of the present technology. In the case of described methods, the methods may include more, fewer, or other steps. Additionally, the steps may be performed in any suitable order. Therefore, this disclosure may encompass other embodiments not explicitly shown or described herein. In the context of this disclosure, the terms “about,” “approximately,” etc., mean + / - 5% of the stated value.

[0033] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that component names and symbols are used interchangeably in this document (e.g., Si and silicon); however, they have the same meaning.

[0034] In short, embodiments of this technology relate to an image sensor for use under various illumination levels. In some embodiments, the image sensor transmits both low-gain data and high-gain data via a plurality of analog-to-digital converters (ADCs). In some embodiments, a decision block selects either low-gain data or high-gain data based on a predetermined threshold. In some embodiments, the predetermined threshold is the saturation state of the most significant bit (MSB). In some embodiments, the predetermined threshold is a voltage reading at a decision timing pulse emitted at a predetermined time. In some embodiments, the predetermined threshold is based on a high-gain code. In some embodiments, the predetermined threshold includes a first threshold and a second threshold. In some embodiments, high gain is transmitted when the output of one of the plurality of ADCs is below the first threshold, and low gain is transmitted when the output of the ADC is above the second threshold. A mixture of high-gain data and low-gain data is transmitted when the output of one of the plurality of ADCs is between the first threshold and the second threshold.

[0035] Figure 1The illustration depicts an exemplary imaging system 100 according to an embodiment of the present disclosure. The imaging system 100 includes a pixel array 102, a control circuitry system 104, a readout circuitry system 106 (also referred to as a pixel circuitry system), and functional logic 110. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2…, Pn). As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the photodiodes acquire image data of an external scene, which can then be used to reproduce 2D images of people, places, objects, etc. However, in other embodiments, the photodiodes may be arranged in a configuration different from the number of rows and columns.

[0036] In one embodiment, after each pixel 112 in the pixel array 102 acquires its image charge, image data is read out by the readout circuitry system 106 via bit line 118 and then transmitted to functional logic 110. In various embodiments, the readout circuitry system 106 may include a signal amplifier, an analog-to-digital (ADC) conversion circuitry system, and a data transmission circuitry system. Functional logic 110 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In some embodiments, control circuitry system 104 and functional logic 110 may be combined into a single functional block to control the capture of the image by the pixels 112 and the readout of image data from the readout circuitry system 106. For example, functional logic 110 may be a digital processor. In one embodiment, the readout circuitry system 106 may read one row of image data at a time along the readout column lines (bit lines 118) or may use various other techniques to read the image data, such as serial readout or simultaneous fully parallel readout of all pixels (not illustrated).

[0037] In one embodiment, control circuitry 104 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously activating all pixels within pixel array 102 to simultaneously capture their respective image data during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal, such that pixels in each row, column, or group are sequentially activated during consecutive acquisition windows. In yet another embodiment, image acquisition is synchronized with an illumination effect, such as a flash.

[0038] In one embodiment, the readout circuitry 106 includes an analog-to-digital converter (ADC) that converts analog image data received from the pixel array 102 into a digital representation. The digital representation of the image data can be provided to functional logic 110. In some embodiments, the data transmission circuitry 108 can receive the digital representation of the image data from the ADC in parallel and can provide the image data to functional logic 110 serially.

[0039] In various embodiments, the imaging system 100 may be included in a digital camera, cellular phone, laptop computer, etc. Additionally, the imaging system 100 may be coupled to other hardware components, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash, electrical inputs (keyboard, touch display, tracking pad, mouse, microphone, etc.), and / or a display. These other hardware components may deliver instructions to the imaging system 100, retrieve image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0040] Figure 2 This is an illustrative schematic diagram of a conventional pixel 210 according to the present disclosure. Pixel 210 can be coupled to bit line 218, for example, to provide a readout column of image data to a readout circuit system such as readout circuit system 106. In operation, pixel 210 can receive control signals from a control circuit system such as control circuit system 104 to control the operation of various transistors of pixel 210. The control circuit system can control the operation of transistors in the desired sequence by ensuring the relative timing of the ordered readout of image data.

[0041] The illustrated embodiment of pixel 210 includes a photodiode (PD) 211, a floating diffuser (FD1) 213 with an inherent capacitor (FDC) 219, a transfer transistor 212, an optional dual floating diffuser (DFD) transistor 216, an optional floating diffuser (FD2) 217 ​​connected to an optional lateral overflow integration capacitor (LOFIC) 215, a reset (RST) transistor 214, a row select (RS) transistor 221, and a source follower (SF) transistor 220. A transfer (TX) transistor 212 (which may also be referred to as transfer gate 212) is coupled between the photodiode PD 211 and the floating diffuser FD1 213. The TX transistor 212 operates based on a TX control signal at its gate terminal. Although the floating diffuser FD1 213 is depicted as connected to the inherent capacitor FDC 219 (which is connected to ground), the combination of FD1 213 and FDC 219 can also be collectively referred to as a floating diffuser.

[0042] RST transistor 214 is coupled to a reference voltage AVDD and can receive a reset control signal at its gate terminal. An additional capacitor LOFIC 215 is coupled between the variable reference voltage VCAP and the floating diffusion node FD2 217. DFD transistor 216 is coupled between FD1 213 and FD2 217, and is further coupled to receive a DFD control signal at its gate terminal. Furthermore, the gate terminal of SF transistor 220 is coupled to the floating diffusion node FD1 213. The source / drain terminals of the SF transistor are coupled between the reference voltage AVDD and the RS transistor. RS transistor 221 is coupled between bit line 218 and SF transistor 220.

[0043] In operation, transistor TX 212 receives a gate signal to achieve charge transfer from PD 211 to the floating diffuser FD1 213. Generally, the amount of charge transfer depends on the exposure of PD 211 and the operation of pixel 210. The equivalent capacitor FDC 219 is illustrated as being coupled to ground.

[0044] In some embodiments, LOFIC 215 may increase the storage, such as capacitance, of the floating diffuser FD2 217. For example, in response to high-intensity illumination, photodiode PD 211 may generate more charge than the floating diffuser FD1 213 can store. The additional charge may be stored by LOFIC 215. In some embodiments, the reference voltage VCAP may be modulated between two or more voltage levels (e.g., a high voltage level "H" and a low voltage level "L") to adjust how much charge is stored by LOFIC 215. Generally, FDC 219 has a smaller capacitance than LOFIC 215. Therefore, the floating diffuser FD1 213 is read out using the high conversion gain (HCG) portion of the data readout, while the floating diffuser FD2 217 and the floating diffuser 213 are read out using the low conversion gain (LCG) portion of the readout. Overall, the HCG and LCG readouts constitute dual conversion gain (DCG) data readout.

[0045] In some embodiments, the operation of RST transistor 214 and DFD transistor 216 can reset the floating diffuser FD1 213 to a high voltage representing a dark state because the voltage proportional to the intensity of the charge on PD 211 decreases as photogenerated electrons are transferred to the floating diffuser FD1 213. To reset the floating diffuser FD1 213, both RST transistor 214 and DFD transistor 216 are enabled (turned on) by their respective gate signals. In other embodiments, RST transistor 214 may be in the on state while the DFD transistor remains in the off state, thus resetting the floating diffuser FD2 217 but not the floating diffuser FD1 213.

[0046] During integration, the variable voltage VCAP coupled to LOFIC 215 can be modulated between two or more voltage levels. In some embodiments, VCAP can be modulated between approximately 0.4V and approximately 1.8V, depending on the value of AVDD. In other embodiments, other voltage levels can be implemented depending on the underlying semiconductor material. When DFD 216 is enabled, the coupling of FD2 217 to FD1213 can provide additional capacitance to store the charge generated by PD 211. For example, when TX 212 is enabled to transfer image charge to the floating diffuser FD1 213, DFD 216 can be enabled to couple additional capacitance LOFIC 215 to the floating diffuser FD1 213 to increase the full well capacity (FWC) of the floating diffuser. In some embodiments, the variable voltage VCAP can be at different voltages depending on whether TX transistor 212 is enabled or disabled.

[0047] Figure 3 This is an illustrative schematic diagram of a conventional pixel circuit 300 for generating combined converted values ​​of pixels according to the present disclosure. In some embodiments, the pixel array 303 is coupled to two or more analog-to-digital converters (ADCs) 311A, 311B, an image signal processor (ISP) 312, and a high dynamic range (HDR) 313. The two or more ADCs 311A, 311B are configured to simultaneously pass both high conversion gain (HCG) data 330 and low conversion gain (LCG) data 335 to the ISP 312. Generally, the HCG data 330 is read from FD1 213 (or FDC 219), while the LCG data 335 is read from FD2217 (or LOFIC 215).

[0048] In operation, the conventional pixel circuit 300 includes a pixel array 303 composed of several pixels (e.g., as shown in the image). Figure 1 (As shown in the diagram). During pixel data readout, two or more ADCs 311A, 311B are communicatively coupled to corresponding pixels among a plurality of pixels to receive image data from said corresponding pixel. The two or more ADCs 311A, 311B then output both HCG data 330 and LCG data 335 to ISP 312A. Both HCG data 330 and LCG data 335 are processed by ISP 312A. HCG data 330 and LCG data 335 are then sent to HDR, which combines HCG data 330 and LCG data 335 into high-low combination (HL) converted data, such as... Figure 3As shown in the diagram. The combined HL conversion data is then transmitted back to the same ISP 312A or another ISP 312B. Since ISPs 312A and 312B determine or select which conversion gain data (HCG data 330, LCG data 335, or a mixture thereof) to combine and forward, additional processing power is utilized. In this way, conventional pixel circuitry requires complex data processing, which can result in longer digital processing times and higher power consumption to transmit HCG data 330 and LCG data 335 to ISPA and ISPAB. Illustratively, for each HCG data 330 and LCG data 335 transmitted from each pixel of pixel array 303, transmitting both HCG data 330 and LCG data 335 may each require up to 10 bits. Additional power is required to combine the transmitted HCG data 330 and LCG data 335. Furthermore, each of the multiple ADCs requires a power gain ranging from approximately 12b to 14b or even greater to transmit the combined HL and HC data to the ISP 312 after combination. Therefore, significant power is required to transmit HCG data 330 and LCG data 335 to the ISPs 312A and 312B and to provide the combined converted values ​​of the pixels from the pixel array 303.

[0049] Figure 4 This is an illustrative schematic diagram of a pixel circuit 400 for generating combined converted values ​​of pixels according to the present disclosure. In some embodiments, the pixel circuit 400 includes a pixel array 403 consisting of a plurality of pixels. It should be understood that in some embodiments, the pixel array 403 is... Figure 1 The pixel array 403. Therefore, in some embodiments, the pixel array 403 consists of a plurality of pixels arranged in a plurality of rows and columns. In some embodiments, the pixel circuitry 400 further includes a plurality of analog-to-digital converters (ADCs) 411A, 411B, a plurality of decision blocks 415A, 415B, an image signal processor (ISP) 412, and a high dynamic range (HDR) 413. Each of the plurality of decision blocks 415A, 415B is communicatively coupled to a corresponding ADC 411A, 411B among the plurality of ADCs. In some embodiments, the plurality of ADCs is at least two ADCs 411A, 411B. In some embodiments, the plurality of decision blocks is at least two decision blocks 415A, 415B.

[0050] Multiple ADCs 411A, 411B are communicatively coupled to corresponding pixels in a plurality of pixels in a pixel array 403. In operation, during pixel readout, individual ADCs 411A, 411B receive image data from corresponding pixels in the plurality of pixels in the pixel array 403. In some embodiments, each decision block 415A, 415B is configured to select and transmit gain data based on comparing the output of the corresponding ADC 411A, 411B with a predetermined threshold of the corresponding ADC 411A, 411B. Figure 5B and 5C As shown in the diagram. ISP 412 receives outputs from multiple ADCs 411A, 411B and combines the outputs of the multiple ADCs 411A, 411B to produce a combined converted value for a corresponding pixel. In some embodiments, the output of each corresponding ADC is a high-gain (HG) code, a low-gain (LG) code, or a combination thereof. HG codes may be interchangeably referred to herein as high-gain (HG) data. Similarly, LG codes may be interchangeably referred to herein as low-gain (LG) data.

[0051] In some embodiments, the gain data is selected from HG data 430A, 430B or LG data 435A, 435B. In some embodiments, the gain data (HG data 430A, 430B or LG data 435A, 435B) transmitted to the ISP 412 is automatically selected based on each column of the signal level data (HG code, LG code, or a combination thereof) of the pixel array 403. The plurality of decision blocks 415A, 415B may contain at least one analog level detector or at least one digital level detector and may be located inside or outside the column circuitry of the pixel array 403.

[0052] During operation, the decision blocks 415A and 415B select gain data (HG data 430A, 430B, LG data 435A, 435B, or a combination thereof), causing the ISP 412 to receive only gain data from the selected gain (HG data 430A, 430B or LG data 435A, 435B, but not both HG and LG data). In this way, processing power is comparable to conventional pixel circuits (e.g., Figure 3 The pixel circuit 303 in the image (within the image) can reduce processing time by up to 50%. Furthermore, processing time can also be reduced by up to 50% compared to the conventional pixel circuit 303. This is because only one gain data (i.e., HG data 430 or LG data 435) is transmitted to the ISP 412. In some embodiments, the pixel circuit 400 may only require 10 bits to transmit high-gain data 430 or low-gain data 435, instead of requiring 10 bits of gain to transmit HG data 430 and 10 bits to transmit LG data 435 (e.g., ...). Figure 3As shown, a total of 20 bits are required. Power can be further saved when transmitting HG data 430 or LG data 435 to the HDR. The HDR can then combine the HG data with the LG data (HL combination) and transmit this combined data back to the ISP 412. Determination blocks 415A and 415B can select HG data 430A and 430B or LG data 435A and 435B based on predetermined thresholds, as described below. Figures 5A to 8B The text provides a more detailed description and presentation.

[0053] Figure 5A This is an illustrative schematic diagram of a pixel circuit 500 according to an embodiment of the present disclosure. In some embodiments, the pixel circuit 500 serves as... Figure 4 The decision blocks 415A and 415B are shown in the diagram. Pixel 500 includes a comparator 511, a low-gain (LG) memory 535, a high-gain (HG) memory 530, at least one saturation determination block 515, and at least one multiplexer (MUX) 540. In some embodiments, the comparator 511 is located in an analog-to-digital converter (ADC) (e.g., Figure 4 The ADC 411 is integrated into the ADC in one of the multiple ADCs 411A, 411B or otherwise.

[0054] In some embodiments, comparator 511 is a digital comparator. In some embodiments, HG memory 530 is memory for an ADC (e.g., ADC 411) and LG memory 535 is counter memory for the ADC. In such embodiments, HG memory 530 and LG memory 535 are combined to form an ADC as described and illustrated herein. It should be understood that the ADC may be, but is not limited to, a single-slope ADC. In some embodiments, the ADC is a successive approximation register (SAR) ADC, etc.

[0055] In some embodiments, at least one saturation determination block 515 is, for example, as shown below. Figure 4The saturation determination block is one of the multiple decision blocks shown. In some embodiments, the predetermined threshold of the saturation determination block 515 is the saturation state of the HG code (or data). It should be understood that the HG data 530 has a higher signal-to-noise ratio (SNR) compared to the LG data 535 until the HG data is saturated. In some embodiments, the saturation state is set based on the output (signal) of the comparator 511 being an HG code at a specific level. For example, in some embodiments, the saturation state is when the HG code is higher than a 1023-bit value, which typically depends on the bit resolution of the ADC. In some embodiments, the saturation state is when the output of the comparator 511 is an LG code at a specific level. In some embodiments, both the HG code and the LG code determine the saturation state. In some embodiments, when the saturation state is not met, the HG data 530 is selected by the saturation determination block 515 and transmitted to the ISP (e.g., Figure 4 (ISP 412 in the example). In some embodiments, when the saturation state is met, LG data 535 is transmitted to the ISP.

[0056] In operation, comparator 511 outputs HG data and LG data. HG data is stored in HG memory 530, while LG data is stored in LG memory 535. In some embodiments, saturation determination block 515 compares the HG data (or code) with a predetermined threshold (e.g., the saturation state of the LG data). When the HG code does not reach the predetermined threshold, the HG data is passed to MUX 540 and transmitted to an image signal processor (ISP), for example... Figure 4 The ISP 412 in the image. This situation can be understood as a low exposure corresponding to a specific pixel, where the intensity of the incoming light is low enough not to saturate FD1 213 (or FDC 219). When the HG code reaches or exceeds a predetermined threshold, HG data is not transmitted; instead, LG data is transmitted to MUX 540 and then to the ISP. This situation can be understood as a relative exposure corresponding to a specific pixel, where the intensity of the incoming light is high enough to saturate FD1 213 (or FDC 219), or at least high enough to exceed a specific predetermined threshold for HG data. Therefore, the MUX can transmit either HG data or LG data based on the selection of the saturation determination block 515.

[0057] Figure 5B This is an illustrative representation of exemplary ADC code according to this disclosure. In some embodiments, a comparator (e.g., comparator 511) is integrated with or coupled to an ADC (e.g., ADC 411A). In some embodiments, the ADC includes a sign bit and additional bits. Figure 5B As shown, the presence of a sign bit and an extra bit (or most significant bit (MSB)) allows the ADC to determine whether saturation (or a predetermined threshold) has been met. Figure 5BThis indicates an instance of a 10-bit ADC with 10 valid bits; however, in different embodiments, ADCs with different resolutions are also possible.

[0058] When the maximum code is reached (i.e., the maximum HG code before saturation), all 10 significant bits are 1. This condition represents the threshold (boundary case), where the sign bit is 0 and the extra bits are also 0. For the light intensity in this case, the HG code is transmitted because saturation has not yet been reached.

[0059] When ambient light levels are higher, the 10 valid bits may not be transmitted correctly. Figure 5B The sign bit is represented as "x". The sign bit remains 0, but the extra bit is set to 1. Therefore, when saturation is achieved, the signal-to-noise ratio (SNR) of the HG code drops significantly, meaning that the HG code can no longer produce acceptable image quality. This condition indicates that the LG code will be transmitted by the decision block.

[0060] Similarly, when there is no light or very low light in the environment, the ADC can transmit negative codes. In this case, the sign bit is set to 1, and neither the 10 valid bits nor the extra bits can be transmitted correctly, and will be blocked or ignored by the saturation determination block 515.

[0061] Figure 5C This is a graph illustrating a predetermined threshold T for selecting a conversion gain (which may be high-gain (HG) data or low-gain (LG) data) according to embodiments of this disclosure. The horizontal axis represents illuminance in lux. The vertical axis represents the signal-to-noise ratio (SNR). Figure 5C As shown, the SNR of HG increases with increasing illuminance (or ambient light level) until a predetermined threshold T. At the predetermined threshold T, the SNR of LG data continues to increase even with increasing illuminance levels. Although LG data generally has higher noise, it can store more light data. Therefore, LG data is better suited than HG data for producing sharp images at higher light (illumination) levels. In some embodiments, the predetermined threshold T is the saturation state of HG data, such as... Figure 5A and 5B As shown and described in the figures. In some embodiments, for a 10-bit ADC, saturation occurs when the HG data (or code) reaches a value of 1023 bits.

[0062] During operation, when the predetermined threshold T has not yet been reached, Figure 5A The pixel circuit 500 transmits HG data. When a predetermined threshold is met, the pixel circuit transmits LG data. In some embodiments, the predetermined threshold T may be based on LG data (or code). In some embodiments, LG data is transmitted when the LG data exceeds a specific threshold.

[0063] In some embodiments, the predetermined threshold is the saturation state of HG data. In operation, when the predetermined threshold is met, the corresponding saturation determination block 515 in the plurality of determination blocks selects LG data, and when the predetermined threshold is not met, the corresponding determination block in the plurality of determination blocks selects HG data.

[0064] Figure 6A This is an illustrative schematic diagram of a pixel circuit 600 according to an embodiment of the present disclosure. In some embodiments, the pixel circuit 600 includes a comparator 611, a high-gain (HG) memory 630 and a low-gain (LG) memory 635, at least one saturation determination block 615, and a multiplexer 640. In some embodiments, the comparator 611 is located in an analog-to-digital converter (ADC) (e.g., Figure 4 The ADC is integrated within or otherwise into one of the multiple ADCs 411A, 411B. In some embodiments, the HG memory 630 is the memory of the ADC (e.g., ADC 411) and the LG memory 635 is the counter memory of the ADC. In such embodiments, the HG memory 630 and the LG memory 635 are combined to form an ADC as described and illustrated herein.

[0065] In some embodiments, at least one saturation determination block 615 is as follows: Figure 4 The saturation determination block is one of the multiple decision blocks shown. In some embodiments, the saturation determination block 615 selects HG data or LG data based on the decision timing pulse P, such as... Figure 6B As shown in the diagram. In operation, a timing pulse P is triggered at a predetermined time to evaluate the output of one of the multiple ADCs (e.g., comparator 611 from the ADC). The saturation determination block 615 can then determine whether the output of the ADC (comparator 611) exceeds a predetermined threshold. If the predetermined threshold is not exceeded, then HG data can be transmitted; and if the predetermined threshold is exceeded, then LG data can be transmitted.

[0066] In some embodiments, comparator 611 may be an analog comparator. In operation, when the analog input exceeds a threshold voltage (e.g., 1023 for a 10-bit ADC), comparator 611 generates a binary voltage value that switches or toggles between two binary levels. In some embodiments, comparator 611 toggles when there is a transition between low and high light conditions in the environment. In some embodiments, a decision timing pulse P is emitted at a predetermined time, such as... Figure 6B As shown in the diagram. When a judgment timing pulse is issued, the output of comparator 611 is measured. If comparator 611 has not toggled within a predetermined time, HG data 630 is transmitted. If comparator 611 has toggled within the predetermined time, LG data 635 is transmitted.

[0067] Figure 6BThis is an illustrative graph of the decision timing pulse P according to an embodiment of the present disclosure. The horizontal axis represents time. At the top of the graph are the voltages for resetting low-gain (LG) data, resetting high-gain (HG) data, the HG signal, and the LG signal. After the reset voltages for the HG data and LG data rise, the pixel circuit (e.g., pixel circuit 600) is turned on. After the pixel circuit is turned on, the HG signal declines, and then the LG signal declines. The vertical axis represents the voltage of at least one decision block, the decision timing pulse P, the output of a comparator (e.g., comparator 611) in high light, and the output of a comparator (e.g., comparator 611) in low light. The vertical line near the HG signal represents a predetermined time T1 at which the decision timing pulse is emitted and the output of the comparator (or ADC) is measured.

[0068] In some embodiments, a timing pulse P is determined at a predetermined time T1 to measure the output of the ADC (or comparator). In operation, the timing pulse P determines whether the comparator is toggled at the predetermined time, as in conjunction with... Figure 6A As described. Figure 6B As shown, under bright light conditions, the comparator does not flip before the ramp signal of the HG signal reaches its end, while under low light conditions, the comparator flips earlier during the descent signal of the HG signal. This is because in low light, the HG code has not yet exceeded saturation, while in bright light, the HG code has exceeded saturation. In this way, a predetermined threshold is evaluated by whether the comparator has flipped. When the comparator has not yet flipped, the decision block selects LG data, and when the comparator has flipped, the decision block selects HG data. Therefore, when bright light is present, LG data is selected, and when low light is present, HG data is selected. In this way, the predetermined threshold can be based on either the HG code or the LG code, but whether the threshold has been met or exceeded is determined by the flipping of the analog comparator.

[0069] Figure 7A This is an illustrative schematic diagram of a pixel circuit 700 according to an embodiment of the present disclosure. In some embodiments, an image signal processor (ISP) (e.g., ISP 412) mixes high-gain (HG) data with low-gain (LG) data near a saturation point (or a predetermined threshold) to achieve a smooth image transition. In some embodiments, the pixel circuit 700 includes a comparator 711, an HG memory 730, an LG memory 735, a plurality of saturation determination blocks 715A, 715B, and AND gates 720, NOR gates 725, a first multiplexer (MUX) 740A, and a second multiplexer (MUX) 740B. In some embodiments, the comparator 711 is located in an analog-to-digital converter (ADC) (e.g., Figure 4The ADC is integrated within or otherwise into one of the multiple ADCs 411A, 411B. In some embodiments, comparator 711 is an analog comparator or a digital comparator. In some embodiments, the predetermined threshold includes a first threshold T1 and a second threshold T2. In some embodiments, multiple saturation determination blocks 715A, 715B determine whether the HG code (or data) has reached the first threshold T1 and / or the second threshold T2. In some embodiments, pixel circuitry 700 is configured to output a flag F. In some embodiments, HG memory 730 is memory of the ADC (e.g., ADC 411) and LG memory 735 is counter memory of the ADC. In such embodiments, HG memory 730 and LG memory 735 are combined to form an ADC as described and illustrated herein. It should be understood that the ADC may be, but is not limited to, a single-slope ADC. In some embodiments, the ADC is a successive approximation register (SAR) ADC, etc.

[0070] In some embodiments, unselected data (i.e., HG data or LG data) is passed to the second MUX 740A, 740B. In some embodiments, unselected data may be clock-gated based on flag F.

[0071] In operation, comparator 711 transmits the outputs of both HG data and LG data. In some embodiments, HG data is stored in HG memory 730, while LG data is stored in LG memory 735. In some embodiments, when transmitting gain data (both LG data and HG data), a first saturation determination block 715A compares its output with a first threshold T1. In some embodiments, the first threshold T1 is based on the HG code. In some embodiments, the first threshold is an approximately 768-bit value. In some embodiments, when the HG code does not meet the first threshold, the first saturation determination block 715A deactivates the LG data signal (LG_EN) 710. The HG data is then transmitted to an AND block 720, which passes the HG data to a first MUX 740A, which ultimately transmits the HG data to an ISP (e.g., an ISP). Figure 4 (ISP 412). Additionally, the first decision block 715A enables the LG data signal (LG_EN) 710. This LG data signal 710 is connected to the second MUX 740B, which issues a flag F to indicate that the LG data is unselected. In this way, the LG data 735 is not transmitted to the ISP.

[0072] In some embodiments, the predetermined threshold further includes a second threshold T2. In some embodiments, when the first threshold T1 is met, HG data is also transmitted to the second saturation determination block 715B of the plurality of saturation determination blocks 715A, 715B. In some embodiments, the second threshold is based on the HG code. In some embodiments, the second threshold is an approximately 1023-bit value. When the first threshold T1 is met but the second threshold T2 is not met, HG data is still transmitted to the AND gate 720 and to the first MUX 740A. When the second threshold T2 is not met, LG data is also transmitted to the AND gate 720, combined with HG data, and transmitted to the first MUX 740A.

[0073] When the second threshold T2 is also met (e.g., when the HG code exceeds 1023 bits), the second saturation determination block 715B selects LG data 735 and does not select HG data. Figure 7A As shown, the HG data signal (HG_EN) 707 is enabled and connected to the second MUX 740B. The second MUX 740B outputs a flag F, thereby specifying HG as unselected data. Those skilled in the art will understand that the bit values ​​discussed herein are merely exemplary (e.g., different bit values ​​may be selected for different thresholds), but are within the limitations of ADC bit resolution.

[0074] Figure 7B This is a graph illustrating first threshold T1 and second threshold T2 for determining selected gain data (e.g., high gain (HG) data, low gain (LG) data, or both) according to embodiments of this disclosure. Illuminance is expressed in lux on the horizontal axis. Signal-to-noise ratio (SNR) is expressed on the vertical axis. Figure 7B As shown, the SNR of HG data increases with increasing illuminance (in lux) until the saturation point SP (which determines the saturation of FD1 213). At the saturation point SP, the SNR of LG continues to increase even when FD1 is saturated. Therefore, after the saturation point SP, LG data (corresponding to the charge stored in LOFIC 215) is better suited than HG data for producing sharp images at higher light (illumination) levels. Figure 7B The diagram also illustrates the first threshold T1 and the second threshold T2. The first threshold T1 and the second threshold T2 divide the data into three gain data transmission zones: the LG data transmission zone H, the mixed gain data transmission zone M (which transmits both HG and LG data), and the HG data transmission zone L.

[0075] like Figure 7B As shown in the figure, when in the high-illuminance zone H, only LG data is transmitted to the ISP (e.g., Figure 4(ISP 412 in the text). When in the medium illuminance band M, both HG data and LG data are transmitted. Finally, when in the low illuminance band L, only HG data is transmitted. In some embodiments, a first threshold T1, a second threshold T2, or both are based on the HG code. In some embodiments, the first threshold T1, the second threshold T2, or both may be based solely on the LG code, or on both the LG code and the HG code. In some embodiments, the first threshold T1 is an HG code of approximately 768 bits and the second threshold T2 is an HG code of approximately 1023 bits. In some embodiments, the medium illuminance band M is higher than the first threshold T1 and lower than the second threshold T2. In some embodiments, the medium illuminance band M is when the HG code is between a 768-bit value and a 1023-bit value. Therefore, in some embodiments, when the HG code is between a 768-bit value and a 1023-bit value, both HG data and LG data are transmitted.

[0076] Figure 7C This is a graph illustrating the determination of a first threshold and a second threshold for a selected conversion gain according to embodiments of the present disclosure. Illuminance is expressed in lux on the horizontal axis. Signal-to-noise ratio (SNR) is expressed on the vertical axis. In some embodiments, the pixel circuitry is configured to transmit high-gain (HG) data, low-gain (LG) data, and mixed conversion gain (MCG) data. In some embodiments, the pixel circuitry further includes LG data transmitted from a lateral overflow integrating capacitor (LOFIC) 215, such as... Figure 1 As described in the text.

[0077] In some embodiments, the first threshold is the saturation state of HG data. In some embodiments, the second threshold is the saturation state of MCG data. Therefore, in some embodiments, the saturation determination block (e.g., saturation determination block 715) selects HG, MCG, or LG data based on the ambient light level (illuminance).

[0078] like Figure 7C As shown, HG data has an acceptable SNR until the illuminance increases to the point where the HG data reaches saturation at the first threshold T1. Then, MCG data has the next acceptable SNR.

[0079] Figure 8AThis is a graph illustrating a first threshold T1 and a second threshold T2 for determining a selected conversion gain (i.e., HG data, LG data, or both) according to embodiments of the present disclosure. The LG code is on the horizontal axis, and the HG code is on the vertical axis. Three gain data transmission bands are also on the horizontal axis: the HG data transmission band HT (labeled "HT" on the horizontal axis), the mixed gain data transmission band MT (transmitting both HG and LG data here), and the LG data transmission band LT (labeled "LT" on the horizontal axis). In some embodiments, the mixing of HG and LG data is dynamically adjusted based on the HG and LG codes. The LG data transmission band LT, the mixed gain data transmission band MT, and the HG data transmission band HT are divided by the second threshold T2. In some embodiments, the combination of the first threshold T1 and the second threshold T2 may be referred to as a predetermined threshold (single) or several predetermined thresholds (multiple). Figure 8A The diagram shows multiple conversion gain coefficients. It should be understood that when the conversion gain coefficient is 1.00x, only HG data is transmitted, and when the conversion gain coefficient is 0.00x, only LG data is transmitted. Furthermore, when the conversion gain coefficient is 0.75x, both 100% of the HG and LG data are transmitted, and the ISP (e.g., ISP 312, 412) produces a combined image with 75% HG data and 25% LG data.

[0080] like Figure 8A As shown, when in the HG data transmission band H, only HG data is transmitted. Similarly, when in the LG data transmission band L, only LG data is transmitted. The hybrid conversion gain transmission band M is when the HG code and LG code are between a first threshold T1 and a second threshold T2. When in the hybrid conversion gain transmission band M, the amount of HG data transmitted decreases as the illuminance increases. When the illuminance level causes the HG code to exceed the second threshold, no HG data is transmitted.

[0081] In the mixed-conversion-gain transmission band M, a combination of HG and LG data is transmitted via an ADC (e.g., ADC 411A, 411B). When the LG code increments but the HG code remains low, only HG data is transmitted (1.00x) until the HG code reaches a specific level, at which point some LG data is transmitted (0.75x). When the HG code increments but the LG data remains low, only HG data is transmitted (1.00x) until the LG data reaches a high level, at which point some LG data is transmitted (0.75x). When both the HG and LG codes increment, less HG data is transmitted and more LG data is transmitted until only LG data is transmitted (0.00x).

[0082] Figure 8BThis is a graph used to determine a predetermined threshold T for a selected conversion gain according to embodiments of the present disclosure. In some embodiments, the predetermined threshold is based solely on a high gain (HG) code. In some embodiments, Figure 8A The predetermined threshold T is either the first threshold or the second threshold as described in this document. The HG code is on the vertical axis.

[0083] Figure 8B The diagram displays multiple conversion gain coefficients. It should be understood that when the conversion gain coefficient is 1.00x, only HG data is transmitted, and when the conversion gain coefficient is 0.00x, only LG data is transmitted. Furthermore, when the conversion gain coefficient is 0.75x, the transmitted gain data is 75% HG data and 25% LG data.

[0084] like Figure 8B As shown, when the HG code exceeds a predetermined threshold T, HG data is not transmitted (0.00x), and LG data is transmitted. Conversely, when the HG code does not exceed the predetermined threshold T, HG data is transmitted (1.00x), while LG data is not transmitted.

[0085] Figure 8C This is a graph illustrating predetermined thresholds T1 and T2 for determining a selected conversion gain according to embodiments of this disclosure. The horizontal axis represents 0. The vertical axis represents the high gain (HG) code. In some embodiments, the predetermined thresholds include a first threshold T1 and a second threshold T2. In some embodiments, the first threshold T1, the second threshold T2, or both are determined based solely on the HG code (or data). Figure 8C The diagram displays multiple conversion gain coefficients. It should be understood that when the conversion gain coefficient is 1.00x, only HG data is transmitted, and when the conversion gain coefficient is 0.00x, only LG data is transmitted. Furthermore, when the conversion gain coefficient is 0.75x, the transmitted gain data is 75% HG data and 25% LG data.

[0086] like Figure 8C As shown, when the HG code does not exceed the first threshold T1, only the HG code is transmitted (1.00x). When the HG code exceeds the first threshold T1, a mixture of HG data and low-gain (LG) data is transmitted (0.75x). Between the first threshold T1 and the second threshold T2, both HG data and LG data are transmitted. As the HG code increases, fewer HG codes are transmitted and more LG data is transmitted. Once the HG data exceeds the second threshold T2, only LG data is transmitted (0.00x).

[0087] Figure 9This is a method 900 for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure. In some embodiments, method 900 is performed using pixel circuits 400, 500, 600, 700, or combinations thereof, as described herein.

[0088] In block 905, image data from each corresponding pixel of a pixel array (e.g., pixel array 411) is transmitted to multiple ADCs (e.g., multiple ADCs 415A, 415B). In some embodiments, the pixel array is pixel array 413 as described herein. In some embodiments, the pixel array consists of a plurality of pixels arranged in a plurality of rows and a plurality of columns, such as... Figure 1 As shown in the figure. In some embodiments, the plurality of ADCs is at least two ADCs. In some embodiments, each of the plurality of ADCs includes at least one comparator, such as comparator 511, 611, or 711. In some embodiments, at least one comparator is an analog comparator, but in other embodiments, at least one comparator is a digital comparator. In some embodiments, the pixel circuitry includes a plurality of decision blocks (e.g., decision block 415). In some embodiments, the pixel circuitry further includes a plurality of saturation determination blocks (e.g., saturation determination blocks 515, 615, and / or 715).

[0089] In block 910, the output of the respective ADC (or comparator) among a plurality of ADCs is compared with a predetermined threshold. In some embodiments, the predetermined threshold is any of the predetermined thresholds described herein. For example, in some embodiments, the predetermined threshold is the saturation state of a high-gain (HG) code, such as... Figures 5A to 5B As shown in the diagram. In another embodiment, the predetermined threshold is based on a decision timing pulse at a predetermined time, such as... Figures 6A to 6B As shown in the figure. In some embodiments, the predetermined threshold includes a first threshold and a second threshold, as illustrated in the figure. Figures 7A to 7B As shown in the figure. In some embodiments, the predetermined threshold is based on both HG data and low gain (LG) data.

[0090] In block 915, the corresponding decision block among a plurality of decision blocks selects the gain data for each ADC based on whether the ADC output meets a predetermined threshold. In some embodiments, the conversion gain is selected from high-gain (HG) data or low-gain (LG) data. In some embodiments, the gain data is selected from a mixture or combination of HG data and LG data, such as... Figures 7A to 7C As shown and described in 8A and 8C. In some embodiments, the decision blocks of a plurality of decision blocks are configured to emit decision timing pulses at predetermined times, and then compare the output of the respective ADC of the plurality of ADCs with a predetermined threshold.

[0091] In block 920, selected gain data is transmitted from each of the plurality of ADCs to an image signal processor (ISP) (e.g., ISP 412). In some embodiments, the pixel circuitry saves processing power and / or time by transmitting only HG or LG data to the ISP.

[0092] In block 925, the ISP receives the output of each of the multiple ADCs. In block 930, the multiple outputs of each of the multiple ADCs are combined (e.g., via high dynamic range (HDR)) to produce a combined converted value for each corresponding pixel of the pixel array.

[0093] Figure 10 This is another method 1000 for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure. In some embodiments, method 1000 is performed using pixel circuits 400, 500, 600, or 700. In some embodiments, method 1000 occurs simultaneously with method 900 or after method 900.

[0094] In block 1010, the output of a corresponding ADC among a plurality of ADCs (e.g., a plurality of ADCs 511A, 511B) is compared with a predetermined threshold. In some embodiments, the comparison occurs at a predetermined time, such as when a decision timing pulse is issued, as described herein. In some embodiments, the predetermined threshold is a saturation state of high-gain (HG) code (or data).

[0095] In decision box 1015, it is determined whether a predetermined threshold (e.g., predetermined threshold T) is met. As described herein, in some embodiments, the predetermined threshold is the HG code. In some embodiments, the predetermined threshold is based on low-gain (LG) data, or both HG and LG data. In some embodiments, the predetermined threshold is when the HG code is at or above 1020 kHz. In some embodiments, the predetermined threshold is based on whether the analog comparator has been toggled. If the predetermined threshold is not met, then method 1000 proceeds to box 1020A.

[0096] In box 1020A, the HG data is selected by the decision block. The ADC can then transmit the HG data to the ISP, such as... Figure 4 As shown in the image.

[0097] Return to box 1015. If the predetermined threshold is met, then method 1000 continues to box 1020B.

[0098] In box 1020B, the decision block selects the LG data. The ADC can then transmit the LG data to the ISP, such as... Figure 4 As shown in the image.

[0099] Figure 11This is another method 1100 for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure. In some embodiments, utilizing... Figure 6A The pixel circuitry is used to execute method 1100. In some embodiments, method 1100 occurs simultaneously with method 900 or occurs after method 900.

[0100] In block 1110, at least one of a plurality of decision blocks sends a decision timing pulse at a predetermined time. In some embodiments, this is achieved by one or more saturation determination blocks (e.g., multiple saturation determination blocks 615A, 615B). In some embodiments, the predetermined time is during a high-gain (HG) signal voltage ramp. In operation, the decision timing pulse determines whether a comparator (e.g., comparator 511 or 611) is toggled at the predetermined time. Figure 6B As shown, the comparator in the high-light phase does not flip before the signal voltage ramp of the HG signal reaches its end, while the comparator receiving the low-light phase flips earlier in the HG signal ramp. In this way, a predetermined threshold is set for whether the comparator has flipped. When the comparator has not yet flipped, the decision block selects LG data, and when the comparator has flipped, the decision block selects HG data. Therefore, based on the decision timing pulses at the HG signal voltage ramp, LG data is selected when high-light is present, and HG data is selected when low-light is present.

[0101] In decision box 1115, it is determined whether a predetermined threshold is met. As described herein, in some embodiments, the predetermined threshold is the saturation state of the high-gain (HG) code. In some embodiments, the predetermined threshold is based on the low-gain (LG) code, or a combination of the LG code and the HG code. If the predetermined threshold is not met, then method 1100 proceeds to box 1120A.

[0102] In box 1120A, the HG data is selected by the decision block.

[0103] Return to box 1115. If the predetermined threshold is met, then method 1100 continues to box 1120B.

[0104] In box 1120B, the LG data is selected by the decision block.

[0105] Figure 12 This is another method 1200 for generating combined converted values ​​for pixels in a pixel circuit according to embodiments of the present disclosure. In some embodiments, method 1200 is performed using pixel circuit 700. In some embodiments, method 1200 occurs simultaneously with method 900 or occurs after method 900.

[0106] In block 1210, the output of a corresponding ADC from a plurality of ADCs (e.g., a plurality of ADCs 511A, 511B) is compared with a predetermined threshold. In some embodiments, the predetermined threshold includes a first threshold and a second threshold. In some embodiments, both the first threshold and the second threshold are based on a high-gain (HG) code. In some embodiments, the first threshold, the second threshold, or both are based on a low-gain (LG) code or both HG and LG codes, for example as... Figure 8C As shown in the image.

[0107] In decision box 1215, it is determined whether a first threshold is met. As described herein, in some embodiments, the first threshold is based on a high-gain (HG) code. In some embodiments, the first threshold is approximately 768 kHz. If the first threshold is not met, then method 1200 proceeds to box 1220.

[0108] In block 1220, high-gain (HG) data is selected by a decision block. In some embodiments, HG data is transmitted to an ISP, such as ISP 411, when the HG code is below approximately 768 kHz.

[0109] Return to box 1215. If the predetermined threshold is met, then method 1200 continues to box 1225.

[0110] In decision box 1225, it is determined whether a second threshold is met. As described herein, in some embodiments, the second threshold is also based on an HG code. In some embodiments, the second threshold is approximately 1023 kHz. If the second threshold is not met, then method 1200 proceeds to box 1230A.

[0111] Optionally, in block 1230A, a decision block selects a combination of high-gain (HG) data and low-gain (LG) data. In some embodiments, when the HG code is between approximately 768 kHz and 1023 kHz, a mixture or combination of HG data and LG data is transmitted.

[0112] Return to box 1225. If the second threshold is met, then method 1200 continues to box 1230B.

[0113] In block 1230B, low gain (LG) data is selected by a decision block. In some embodiments, LG data is transmitted when HG data is above approximately 1023 kHz.

[0114] It should be understood that all methods 900, 1000, 1100, and 1200 should be interpreted as representative only. In some embodiments, the process blocks of all methods 900, 1000, 1100, and 1200 may be performed simultaneously, sequentially, in different orders, or even omitted without departing from the scope of this disclosure.

Claims

1. A pixel circuit, comprising: A pixel array, which comprises multiple pixels; Multiple analog-to-digital converters, wherein during pixel data readout, the multiple analog-to-digital converters are communicatively coupled to a corresponding plurality of pixels to receive image data from a corresponding pixel among the plurality of pixels; A plurality of decision blocks, each communicatively coupled to a corresponding analog-to-digital converter (ADC) among the plurality of ADCs, and each decision block configured to select gain data from the output of the corresponding ADC based on comparing the output of the corresponding ADC with the predetermined threshold of the corresponding ADC, and to transmit the gain data of the corresponding ADC among the plurality of ADCs to an image signal processor; and The image signal processor is configured to: Receive outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the respective pixel. The gain data mentioned therein is selected from high-gain data, low-gain data, or a combination thereof.

2. The pixel circuit of claim 1, wherein the predetermined threshold is based on the high-gain data.

3. The pixel circuit according to claim 1, wherein: When the predetermined threshold is met or exceeded, the corresponding judgment block among the plurality of judgment blocks selects the low-gain data; and When the predetermined threshold is not met, the corresponding judgment block among the plurality of judgment blocks selects the high-gain data.

4. The pixel circuit according to claim 1, wherein the plurality of analog-to-digital converters include at least two analog-to-digital converters, and the plurality of decision blocks include at least two decision blocks.

5. The pixel circuit of claim 1, wherein the predetermined threshold is based on at least one judgment timing pulse emitted by the plurality of judgment blocks at a predetermined time, wherein the judgment timing pulse provides a trigger signal for determining whether the comparator of each of the plurality of analog-to-digital converters is toggled at the predetermined time.

6. The pixel circuit according to claim 1, wherein: The predetermined threshold includes a first threshold; and Specifically, when the high-gain data is lower than the first threshold, the high-gain data is selected.

7. The pixel circuit according to claim 6, wherein: The predetermined threshold further includes a second threshold; and Specifically, when the high-gain data is higher than the second threshold, the low-gain data is selected.

8. The pixel circuit of claim 7, wherein when the high-gain data is between the first threshold and the second threshold, a mixture of the high-gain data and the low-gain data is selected.

9. The pixel circuit of claim 8, wherein the mixing of the high-gain data and the low-gain data is represented by a plurality of conversion gain coefficients, the plurality of conversion gain coefficients being determined based on the percentage of the high-gain data in the high-gain data and the low-gain data.

10. The pixel circuit of claim 9, wherein the mixing of the high-gain data and the low-gain data is dynamically adjusted based on the high-gain data and the low-gain data.

11. The pixel circuit of claim 9, wherein the first threshold is a 768-bit value and the second threshold is a 1023-bit value.

12. A method for generating a combined converted value of a pixel circuit according to claim 1, the method comprising: The image data from each corresponding pixel of the plurality of pixels is transmitted to the plurality of analog-to-digital converters; The output of the corresponding analog-to-digital converter is compared with the predetermined threshold of the corresponding analog-to-digital converter; The gain data is selected from the output of each analog-to-digital converter using each of the plurality of decision blocks; The gain data of each of the plurality of analog-to-digital converters is transmitted to the image signal processor; The image signal processor receives the outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the respective pixel. The gain data mentioned therein is selected from high-gain data, low-gain data, or a combination thereof.

13. A method for generating a combined converted value of a pixel circuit, the pixel circuit comprising: A pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs), wherein during pixel data readout, the plurality of ADCs are communicatively coupled to respective plurality of pixels to receive image data from a respective pixel among the plurality of pixels; and a plurality of decision blocks, wherein each decision block is communicatively coupled to a respective ADC among the plurality of ADCs, and wherein each decision block is configured to select and transmit gain data based on comparing the output of the respective ADC with a predetermined threshold of the respective ADC, the method comprising: The image data from each corresponding pixel of the plurality of pixels is transmitted to the plurality of analog-to-digital converters; The output of the corresponding analog-to-digital converter is compared with the predetermined threshold of the corresponding analog-to-digital converter; The gain data is selected from the output of each analog-to-digital converter using each of the plurality of decision blocks; The gain data of each of the plurality of analog-to-digital converters is transmitted to the image signal processor; The image signal processor receives outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the respective pixel. The gain data mentioned therein is selected from high-gain data, low-gain data, or a combination thereof.

14. The method of claim 13, wherein the method further comprises: When the predetermined threshold is met, the low-gain data is selected using the corresponding judgment block among the plurality of judgment blocks; and When the predetermined threshold is not met, the high-gain data is selected using the corresponding judgment block among the plurality of judgment blocks.

15. The method of claim 13, wherein the predetermined threshold includes the saturation state of the high-gain data.

16. The method of claim 13, wherein the method further comprises: At least one of the multiple decision blocks is used to emit a decision timing pulse at a predetermined time; The output of each of the plurality of analog-to-digital converters is measured at the predetermined time. When the comparator of the analog-to-digital converter is not toggled, the high-gain data is selected; and The low-gain data is selected when the comparator of the analog-to-digital converter is flipped.

17. The method of claim 13, wherein the predetermined threshold includes a first threshold and a second threshold, and wherein the method further comprises: When the high-gain data is lower than the first threshold, the high-gain data is selected; and When the high-gain data is higher than the second threshold, the low-gain data is selected.

18. The method of claim 17, wherein the method further comprises, when the high-gain data is between the first threshold and the second threshold, selecting and transmitting a mixture of both the high-gain data and the low-gain data.

Images