Organic semiconductor heterojunction photonic synapse transistor and preparation method thereof

Abstract

The present invention belongs to organic field-effect transistors, and in particular to an organic semiconductor heterojunction photonic synapse transistor and a preparation method thereof. The organic semiconductor heterojunction photonic synapse transistor includes a source-drain electrode, an organic active layer, a gate insulating layer and a gate; the organic active layer is composed of an N,N'-disalicylidene-1,3-diaminopropane layer and a pentacene layer. The transistor provided by the present invention has good transistor field effect and photonic flash memory performance, and has good light-regulated synaptic performance, and can realize various types of photosynaptic functions. In addition, the device is mainly dominated by NSP, and has the largest photoresponse rate and photoresponse dynamic range at 435 nm, and has good recognition of near-ultraviolet light. Thanks to the relative stability of small molecule materials, the device has no performance degradation within a temperature range of 120°C, and can achieve adaptive learning at different temperatures.

Description

Technical Field

[0001] The present invention relates to an organic field effect transistor, and in particular to an organic semiconductor heterojunction photon synapse transistor and a preparation method thereof. Background Art

[0002] Photonic synaptic transistors (PSTs) have attracted significant attention in neuromorphic computing due to their high-speed operation, energy efficiency, and ability to mimic synaptic plasticity through optical stimulation. These devices typically rely on light to initiate charge transfer processes, effectively mimicking the dynamic behavior of biological synapses, which are crucial for learning and memory functions in the human brain. By utilizing light as a stimulus, PSTs offer a powerful tool for brain-inspired computing architectures, where speed, accuracy, and efficiency are crucial. This unique mechanism holds great potential for diverse applications, including artificial intelligence systems, advanced robotics, sensor processing networks, and cognitive computing platforms. Their ability to process and store information makes them a key research area for the development of more complex and energy-efficient computing technologies. However, despite these advantages, the practical implementation of PSTs faces significant challenges, particularly regarding temperature stability. Temperature fluctuations can profoundly affect the performance of these devices, leading to degraded response characteristics and reduced learning efficiency. This issue is particularly critical in environments where temperature control is difficult.

[0003] Therefore, it is of great significance to provide a temperature-stable organic semiconductor heterojunction photonic synapse transistor. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to address the deficiencies of the existing technology and provide a temperature-stable organic semiconductor heterojunction photonic synapse transistor and a preparation method thereof, thereby providing a new idea for the development of temperature-stable photonic synapse devices.

[0005] In order to solve the above technical problems, the present invention discloses an organic semiconductor heterojunction photon synapse transistor, which includes a source-drain electrode, an organic active layer, a gate insulating layer and a gate arranged in sequence from top to bottom;

[0006] Wherein, the organic active layer consists of an N,N'-disalicylidene-1,3-diaminopropane layer and a pentacene layer.

[0007] Wherein, the source and drain electrodes are made of copper with a thickness of 80-110 nm;

[0008] Specifically, in some embodiments of the present invention, the thickness of the source-drain electrode is 100 nm.

[0009] Wherein, the thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 15-30 nm; the thickness of the pentacene layer is 30-50 nm;

[0010] Specifically, in some embodiments of the present invention, the thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 20-30 nm; and the thickness of the pentacene layer is 30-50 nm.

[0011] Wherein, the gate insulating layer is silicon dioxide with a thickness of 50 to 300 nm;

[0012] Specifically, in some embodiments of the present invention, the gate insulating layer has a thickness of 50 nm.

[0013] Wherein, the gate is highly doped silicon.

[0014] The present invention also provides a method for preparing the organic semiconductor heterojunction photonic synapse transistor, comprising the following steps:

[0015] S1. A gate insulating layer is grown on the gate surface, cleaned after cutting, and then the surface liquid is blown dry and dried, and finally subjected to UV ozone treatment;

[0016] S2. Spin-coating an N,N'-disalicylidene-1,3-diaminopropane solution on the gate insulating layer after UV ozone treatment in S1, and forming an N,N'-disalicylidene-1,3-diaminopropane layer on the gate insulating layer after annealing;

[0017] S3. Sequentially vapor-depositing a pentacene layer and a source-drain electrode on the N,N'-disalicylidene-1,3-diaminopropane layer to obtain the organic semiconductor heterojunction photonic synapse transistor.

[0018] Wherein, in S1, the size after cutting is 1.5 cm×1.5 cm.

[0019] Among them, in S1, the specific cleaning steps are ultrasonic cleaning with acetone, ethanol and deionized water in sequence, the cleaning time is 25 to 30 minutes, and the ultraviolet ozone treatment is 5 minutes.

[0020] Wherein, in S2, the concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3-5 mg / mL, and the solvent is chloroform;

[0021] Specifically, in some embodiments of the present invention, the concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3 mg / mL;

[0022] Specifically, the N,N'-disalicylidene-1,3-diaminopropane (NSP) molecule has good solubility due to the presence of two hydroxyl groups and can be spin-coated into a film through solution. In addition, the NSP molecule contains multiple active sites, and its structure can be modified by functional groups to regulate the electron transfer ability, thereby optimizing the performance parameters of the device.

[0023] The spin coating process parameters are as follows: maintaining a rotation speed of 300-500 rpm for 5-10 s and then maintaining a rotation speed of 1000-3000 rpm for 25-35 s;

[0024] Specifically, in some embodiments of the present invention, the spin coating process parameters are as follows: maintaining at 500 rpm for 9 s and then maintaining at 3000 rpm for 30 s.

[0025] Wherein, the annealing temperature is 60-80°C and the time is 20-40 min;

[0026] Specifically, in some embodiments of the present invention, the annealing is performed at a temperature of 60° C. and for 20 minutes.

[0027] The evaporation is vacuum evaporation with a speed of 0.1-1 Å s -1 The vacuum degree during evaporation is less than 5×10 -4 Pa;

[0028] Specifically, in some embodiments of the present invention, the vacuum evaporation speed is 1 Å s -1 .

[0029] Among them, the channel length and width covered by the mask when evaporating the source and drain electrodes are 100 µm and 1500 µm respectively.

[0030] Beneficial effects:

[0031] 1. The photonic synaptic transistor provided by the present invention has the characteristics of simple structure and easy operation. The organic functional layer is formed by solution spin coating, and the device structure is a bottom-gate top-contact structure. Synaptic plasticity is studied by measuring the current between the source and drain copper electrodes.

[0032] 2. The photonic synaptic transistor provided by the present invention has excellent optical synaptic performance and a precisely controllable response to light stimulation, indicating its potential as a neuromorphic device.

[0033] 3. The photonic synaptic transistor provided by the present invention has good device light response performance regulated by light power. As the light power increases, the device's light response rate and dynamic range increase almost linearly.

[0034] 4. The photonic synaptic transistor provided by the present invention is mainly dominated by NSP, with the largest photoresponsivity and photoresponse dynamic range at 435 nm, and the device has good recognition of near-ultraviolet light.

[0035] 5. The photonic synaptic transistor provided by the present invention benefits from the relative stability of small molecule materials. The photosynaptic function and photoresponse rate remain good in the range of 20°C to 120°C, and the performance does not decline. At the same time, adaptive learning rules can be realized at different temperatures.

[0036] 6. This invention provides valuable insights for developing temperature-stable photonic synaptic devices and demonstrates the potential of defect variations at the interface of pentacene and NSP to improve the performance of neuromorphic computing systems. These findings help advance the field of nanoengineered devices, making them more efficient and reliable for future applications in adaptive computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0038] Figure 1 Schematic diagram of the structure of the organic semiconductor heterojunction photonic synapse transistor of the present invention; wherein 1 is the source and drain electrodes, 2 is the pentacene layer, 3 is the N,N'-disalicylidene-1,3-diaminopropane layer, 4 is the gate insulating layer, and 5 is the gate.

[0039] Figure 2 is the output curve of the photonic synapse transistor device of the present invention.

[0040] Figure 3 is the transfer curve of the photonic synapse transistor device of the present invention.

[0041] Figure 4 This is the forward storage of the photonic synapse transistor device of the present invention.

[0042] Figure 5 This is the negative storage of the photonic synapse transistor device of the present invention.

[0043] Figure 6 The transfer curve of the photonic synapse transistor device of the present invention is shifted at different light wavelengths.

[0044] Figure 7 UV-visible absorption spectra of NSP and pentacene.

[0045] Figure 8 This is the response of the photonic synapse transistor device of the present invention to the duration of the light pulse.

[0046] Figure 9The light-stimulated PPF response and PPF index of the photonic synaptic transistor device of the present invention are shown.

[0047] Figure 10 A set of PTP schematic diagrams of the photonic synapse transistor device of the present invention tested under different light intensities.

[0048] Figure 11 Schematic diagram of increasing the number of light pulses leading to larger EPSCs for the photonic synaptic transistor device of the present invention.

[0049] Figure 12 Schematic diagram of the relationship between the light responsivity and dynamic range of the photonic synaptic transistor device of the present invention and light intensity.

[0050] Figure 13 Schematic diagram of the relationship between the light responsivity and dynamic range of the photonic synapse transistor device of the present invention and the wavelength of light.

[0051] Figure 14 Schematic diagram of the relationship between the threshold voltage shift and light wavelength of the photonic synaptic transistor device of the present invention.

[0052] Figure 15 This is a set of PTP data of the photonic synapse transistor device of the present invention measured within a temperature range of 20°C to 120°C.

[0053] Figure 16 Schematic diagram of the PTP index and synaptic weight of the photonic synaptic transistor device of the present invention from 20°C to 120°C.

[0054] Figure 17 Schematic diagram of the photoresponsivity and dynamic range of the photonic synaptic transistor device of the present invention from 20°C to 120°C.

[0055] Figure 18 Schematic diagram of Pavlov's conditioned reflex experiment.

[0056] Figure 19 This is the Pavlovian conditioned reflex simulation process of the photonic synaptic transistor device of the present invention at 20°C.

[0057] Figure 20 This is the Pavlovian conditioned reflex simulation process of the photonic synaptic transistor device of the present invention at 100°C. DETAILED DESCRIPTION

[0058] The experimental methods described in the following examples are conventional methods unless otherwise specified; the reagents and materials are commercially available unless otherwise specified.

[0059] The highly doped silicon used in the following examples (product name: single-polished oxide silicon wafer; oxide thickness: 50±5 nm; resistivity: 0.001-0.005Ω·cm; type: N; crystal orientation: <100> ) was purchased from Suzhou Jingsi Electronic Technology Co., Ltd.; N,N'-disalicylidene-1,3-diaminopropane (NSP) and pentacene were purchased from TCI.

[0060] The present invention provides a temperature-stable organic semiconductor heterojunction photonic synapse transistor, which has a vertical structure as a whole. Figure 1 As shown, from top to bottom, it includes: source and drain electrodes 1, pentacene layer 2, N,N'-disalicylidene-1,3-diaminopropane layer 3, gate insulating layer 4, and gate electrode 5. The pentacene layer 2 and N,N'-disalicylidene-1,3-diaminopropane layer 3 together constitute the organic active layer. The source and drain electrodes are copper electrodes, the gate insulating layer is silicon dioxide, and the gate is highly doped silicon. The NSP structure is shown in Formula I, and the pentacene structure is shown in Formula II.

[0061]

[0062] Formula I

[0063]

[0064] Formula II

[0065] Example 1: Preparation of organic semiconductor heterojunction photonic synapse transistor

[0066] This embodiment provides a method for preparing a temperature-stable organic semiconductor heterojunction photonic synapse transistor, comprising the following steps:

[0067] S1. A 50 nm thick layer of silicon dioxide (manufactured by Suzhou Jingsi Electronic Technology Co., Ltd.) was grown on the highly doped silicon gate surface to form a gate insulating layer. This layer was then used as a substrate and cut into 1.5 cm × 1.5 cm pieces. The cut substrates were ultrasonically treated in acetone, ethanol, and deionized water for approximately 20 minutes each. After removal, the surface was dried with high-purity nitrogen and placed in a glass Petri dish. The Petri dish was then dried in a 120°C oven for approximately 20 minutes. The dried sample was then subjected to UV-ozone treatment for 5 minutes.

[0068] S2. Dissolve NSP powder in chloroform to prepare a 3 mg / mL solution.

[0069] S3. Use a pipette to draw up the solution prepared in S2 and spin-coat it onto the gate insulating layer of the substrate treated in S1 at 500 rpm for 9 seconds and then at 3000 rpm for 30 seconds. Then, transfer the solution to the substrate and anneal it in an oven at 60°C for 20 minutes to obtain a 20-30 nm thick N,N'-disalicylidene-1,3-diaminopropane layer.

[0070] S4. Place the sample processed in S3 into a vacuum evaporation system and sequentially deposit the pentacene layer and the source and drain electrodes at a rate of 1 Å s. -1 During the evaporation process, the vacuum degree of the evaporation chamber is always kept below 5×10 -4 Pa, the thickness of the pentacene layer is 30~50 nm, and the thickness of the source and drain electrodes is 100 nm; among them, the channel length and width covered by the mask when evaporating the source and drain electrodes are 100 µm and 1500 µm respectively. After the evaporation is completed, the photonic synapse transistor is obtained.

[0071] Example 2: Performance Testing of Organic Semiconductor Heterojunction Photonic Synapse Transistors

[0072] In the following examples, the photonic synapse transistors were tested using a Keithley 4200 semiconductor parameter analyzer.

[0073] To investigate the electrical performance of the photonic synaptic transistor, the device's transfer and output characteristics were measured under dark conditions. The source-drain voltage was swept from 0 V to -15 V, and the output curves were obtained for gate voltages of 0 V, -3 V, -6 V, -9 V, -12 V, and -15 V. The transfer curves were also obtained by sweeping the gate voltage from 10 V to -30 V while maintaining a fixed source-drain voltage of -15 V. Figure 2 is the output curve of the photonic synaptic transistor device, Figure 3 is the transfer curve of the photonic synaptic transistor device, Figure 2 and Figure 3 The output and transfer curves show that the device has a good field effect. The output curve clearly shows the channel current regulated by the gate voltage, with obvious linear and saturation regions. The transfer curve is set at a source-drain voltage of -15 V. The carrier mobility μ = 0.12 cm is calculated by linear fitting of the saturation region. 2 / Vs.

[0074] To investigate the positive and negative storage capabilities of the photonic synaptic transistor, a +30 V gate voltage and a natural light pulse for 1 s were first applied as programming operations, while a negative gate voltage of -30 V for 1 s was used as an erase operation. Figure 4The forward storage capability of the device is shown by Figure 4 It can be seen that after the optical programming operation, the transfer curve basically moves in the positive direction, indicating that electrons are trapped in the N,N'-disalicylidene-1,3-diaminopropane layer. After the electrical erase operation, the transfer curve can move back to its initial state, which means the release of trapped electrons. Different from the forward operation, the write condition is changed to a gate voltage of -40V and the erase condition is changed to a gate voltage of +40V. Figure 5 The negative storage capability of the device is shown by Figure 5 It can be seen that the transfer curve shifts to the negative direction after writing. These results confirm the good field effect and bipolar storage capability of the device.

[0075] In order to study the effect of different wavelengths of light on the photonic synaptic transistor, the changes in the transfer curve of the photonic synaptic transistor were studied by setting no light and applying light with wavelengths of 400 nm, 420 nm, 435 nm, 500 nm, 600 nm, and 650 nm. The illumination time was 3 seconds and the illumination intensity was 20 mW cm -2 . Figure 6 Schematic diagram of different degrees of shift in the transfer curve achieved by applying light of different wavelengths. Figure 6 As the wavelength of light decreases, the transfer curve shifts more positively, indicating the generation and capture of more photogenerated carriers. The results demonstrate that the photonic synaptic transistor possesses excellent photonic flash memory performance and light-regulated synaptic plasticity.

[0076] Figure 7 The UV-visible absorption spectra of NSP and pentacene are shown in Figure 2. Figure 7 It can be seen that the absorption bands of the two materials do not overlap at all, and the absorption peak of NSP is located around 435 nm.

[0077] In biological synapses, when the presynaptic membrane is stimulated, the postsynaptic membrane generates a response current, which is called an excitatory postsynaptic current (EPSC). To study the effect of light pulse duration on photonic synaptic transistors, the gate voltage was fixed at -15V and the light intensity was 2.0 mW / cm 2 The EPSC responses under stimulation with light exposure times of 0.2 s, 0.5 s, 1.0 s, 1.5 s and 2.0 s were tested. Figure 8 is the response of the photonic synaptic transistor device to the duration of the light pulse, Figure 8 It can be seen that increasing the duration of a single light stimulus will result in a higher EPSC and a slower decay.

[0078] Simulating the paired-pulse facilitation (PPF) effect on a photonic synaptic transistor reveals that the photonic synapse exhibits a significant PPF effect. The generation of the PPF can be attributed to the short time interval between the two stimuli. When the second stimulus reaches the presynaptic neuron, the neurotransmitter released by the previous stimulus still remains in the synaptic cleft. Therefore, the PPF is directly related to the time interval between the applied stimuli. Figure 9 The light stimulation PPF response and PPF index of the photonic synaptic transistor device of the present invention are given by Figure 9 It can be seen that the photonic synaptic transistor prepared by the present invention has an obvious PPF effect. Figure 9 The corresponding PPF increment after changing the pulse interval is also shown, where the PPF index is defined as the percentage increase of the second current peak compared to the first current peak. As the time interval increases, the PPF increment decreases significantly and eventually approaches 0.

[0079] Post-tetanic potentiation (PTP) is similar to PPF and refers to the phenomenon in which synaptic weight increases over a certain period of time under repeated high-frequency stimulation. PTP testing can quantify the response characteristics of a device to high-frequency stimulation by adjusting light pulse parameters (such as frequency and duration). A group of PTPs were tested by varying the light intensity and number of light stimuli. Figure 10 A set of PTP schematic diagrams of photonic synaptic transistor devices tested under different light intensities, with the number of light stimuli at each light intensity being 10. Figure 11 Schematic diagram of a photonic synaptic transistor device showing how increasing the number of light pulses at the same light intensity leads to larger EPSCs. The light intensity is 2.0 mW / cm 2 .Depend on Figure 10 and Figure 11 Increasing the intensity and number of light pulses resulted in larger EPSCs. These results demonstrate that the device has excellent photosynaptic properties and a precisely controllable response to light stimulation, indicating its potential as a neuromorphic device.

[0080] Figure 12 Schematic diagram of the relationship between the light responsivity and dynamic range of the photonic synaptic transistor device of the present invention and the light intensity, Figure 13 The following is a schematic diagram showing the relationship between the photoresponsivity and dynamic range of the photonic synaptic transistor device of the present invention and the wavelength of light, wherein the photoresponsivity is defined as the ratio of the photocurrent to the incident light power, and the dynamic range is defined as the ratio of the maximum input light power to the minimum receivable light power. Figure 12 It can be seen that as the optical power increases, the dynamic range of the device's photoresponsivity increases almost linearly, indicating good photoresponse performance of the device regulated by optical power. Figure 13It can be seen that the connection line is similar to the absorption spectrum of the material. The absorption peak of NSP at 435 nm has the highest photoresponsivity and dynamic range, and the absorption peak of pentacene is slightly weaker at around 600 nm, indicating that the photoresponse of the device is dominated by NSP.

[0081] Figure 14 This is a schematic diagram of the relationship between the threshold voltage shift and the wavelength of light of the photonic synaptic transistor device of the present invention, showing the relationship between the threshold voltage shift in the device transfer curve, that is, the storage window, and the wavelength of the incident light. Figure 14 It is from Figure 6 The threshold voltage shift of each transfer curve is extracted from the data and statistically plotted. Figure 14 It can be seen that as the wavelength shortens to near-ultraviolet, the greater the energy of the incident light, the more exciton pairs are excited, and thus the transfer curve shifts more toward the positive direction.

[0082] Figure 15 This is a set of PTP data for online testing of devices at 20°C intervals from 20°C to 120°C. Figure 15 As can be seen, the device performance is very stable before 100°C. Continuous light stimulation causes the channel current to continuously increase, and the relaxation current slowly decays after the light is removed. At 120°C, the device's dark current and relaxation current fluctuate slightly, but the PTP continues to increase.

[0083] Figure 16 Schematic diagram of the PTP index and synaptic weight of the photonic synaptic transistor device of the present invention from 20°C to 120°C. Figure 17 The figure shows the photoresponsivity and dynamic range of the photonic synaptic transistor device of the present invention from 20°C to 120°C, where the PTP index is defined as the percentage increase of the tenth peak relative to the first peak, and the synaptic weight is defined as the percentage increase of the current value when it tends to be stable after the tenth peak stimulation. Figure 16 and Figure 17It can be seen that, in general, the device photoresponsivity increases with increasing temperature, but the PTP index and synaptic weight percentage decrease. This is because the intrinsic excitation of the semiconductor material as temperature rises leads to an increase in intrinsic carriers, increasing the generation and separation of charges under illumination. At the same time, rising temperature affects the properties of organic semiconductor films, resulting in a decrease in crystallinity, an increase in physical defects, and a decrease in relaxation current. Specifically, because pentacene has a certain degree of crystallinity, its crystallinity decreases when the temperature rises. At this time, a high density of physical defects is generated at the interface between pentacene and the NSP and the electrode, affecting charge capture and de-trapping, resulting in a decrease in carrier mobility. At the same time, temperature changes affect the energy barrier between pentacene and the electrode and NSP, increasing the contact resistance. The contact area between the three interfaces in the device increases, and the defects at the interface accelerate charge recombination, resulting in a faster relaxation rate of the light-induced current. These changes in the device at high temperatures can achieve varying degrees of learning and forgetting, which is conducive to simulating more advanced neuromorphic functions.

[0084] Figure 18 This is a diagram of Pavlov's classical conditioning experiment. Initially, when a dog is offered food, it naturally salivates, while the ringing of a bell does not. Then, each time the dog is fed, a bell is rung. Over time, the dog associates food with the bell, and salivates whenever the bell rings, even in the absence of food. Here, food is the unconditioned stimulus (US), which elicits the unconditioned response (UR), namely salivation; the ringing of the bell is the conditioned stimulus (CS). Training the dog to salivate is a conditioned reflex (CR). In Pavlov's experiment, the dog naturally salivates when presented with food but initially does not respond to the ringing of the bell. By repeatedly pairing the bell with food, the dog learns to associate the bell with food, eventually developing a salivation response to the bell itself.

[0085] The photonic synaptic transistor device prepared by the present invention was subjected to a Pavlov classical conditioning experiment, in which a series of -2 V electric pulse signals were applied as conditioned stimuli, and a 435 nm wavelength optical signal was applied as unconditioned stimuli. A threshold current was set. I ,Exceed I =1 nA current level corresponds to "drooling" behavior, that is, the salivation behavior of dogs, and Pavlov's classical conditioning experiment was carried out at 20 ℃ and 100 ℃ respectively. Figure 19 This is the Pavlovian conditioned reflex simulation process of the photonic synaptic transistor device of the present invention at 20°C. Figure 20 This is the Pavlovian conditioned reflex simulation process of the photonic synaptic transistor device of the present invention at 100°C. Figure 19 and Figure 20As can be seen, the current increases faster at 100°C compared to 20°C, indicating a faster training process and more efficient learning in the dog. However, due to the faster current relaxation, the dog also forgets more quickly, indicating a shorter retention of learning. Therefore, while the learning process is shorter, more frequent re-learning and consolidation are required. These results demonstrate the ability to implement multimodal learning rules in the device, facilitating the realization of adaptive and more intelligent neuromorphic functions.

[0086] The present invention provides a concept for an organic semiconductor heterojunction photonic synapse transistor and a method for fabricating the same. Numerous methods and approaches exist for implementing this technical solution. The foregoing merely represents a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Components not specified in this embodiment may be implemented using existing technologies.

Claims

1. An organic semiconductor heterojunction photonic synapse transistor, characterized in that: The organic semiconductor heterojunction photon synapse transistor comprises a source-drain electrode, an organic active layer, a gate insulating layer and a gate electrode arranged in sequence from top to bottom; The organic active layer consists of a pentacene layer and an N,N'-disalicylidene-1,3-diaminopropane layer arranged in sequence from top to bottom.

2. The organic semiconductor heterojunction photonic synapse transistor according to claim 1, wherein: The source and drain electrodes are made of copper and have a thickness of 80-110 nm.

3. The organic semiconductor heterojunction photonic synapse transistor according to claim 1, wherein: The thickness of the N,N'-disalicylidene-1,3-diaminopropane layer is 15-30 nm; the thickness of the pentacene layer is 30-50 nm.

4. The organic semiconductor heterojunction photonic synapse transistor according to claim 1, wherein: The gate insulating layer is silicon dioxide with a thickness of 50-300 nm.

5. The organic semiconductor heterojunction photonic synapse transistor according to claim 1, wherein: The gate is made of highly doped silicon.

6. The method for preparing an organic semiconductor heterojunction photonic synapse transistor according to any one of claims 1 to 5, characterized in that: The steps include: S1. A gate insulating layer is grown on the gate surface, cleaned after cutting, and then the surface liquid is blown dry and dried, and finally subjected to UV ozone treatment; S2. Spin-coating an N,N'-disalicylidene-1,3-diaminopropane solution on the gate insulating layer after UV ozone treatment in S1, and forming an N,N'-disalicylidene-1,3-diaminopropane layer on the gate insulating layer after annealing; S3. Sequentially vapor-depositing a pentacene layer and a source-drain electrode on the N,N'-disalicylidene-1,3-diaminopropane layer to obtain the organic semiconductor heterojunction photonic synapse transistor.

7. The preparation method according to claim 6, characterized in that The concentration of the N,N'-disalicylidene-1,3-diaminopropane solution is 3-5 mg / mL, and the solvent is chloroform.

8. The preparation method according to claim 6, characterized in that The spin coating process parameters are as follows: maintaining a rotation speed of 300-500 rpm for 5-10 s and then maintaining a rotation speed of 1000-3000 rpm for 25-35 s.

9. The preparation method according to claim 6, characterized in that The annealing temperature is 60-80°C and the time is 20-40 min.

10. The preparation method according to claim 6, characterized in that The evaporation is vacuum evaporation with a speed of 0.1-1 Å s -1 The vacuum degree during evaporation is less than 5×10 -4 Pa.

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