A satellite navigation signal acquisition system based on surface acoustic wave filter TDC

Abstract

The present application belongs to the field of microelectronic technology and integrated circuit, and particularly relates to a TDC satellite navigation signal acquisition system based on a surface acoustic wave filter. The acquisition system of the present application adopts a TDC mode for the first time to complete complete signal acquisition with time as a bridge from signal receiving and filtering to corresponding baseband signal processing method. Although TDC has long design cycle and high cost, the delay is usually small, is suitable for scenes with high real-time requirement, and has low dependence on signal amplitude, and is more suitable for processing signals with large dynamic range. Further, the baseband signal processing method uses a partial matching filter and a newly set variable point number fast Fourier transform method to perform multi-point number design to be suitable for signal types of various satellite navigation systems such as GPS and BDS. Finally, the present application realizes high precision, low delay and high adaptability of satellite navigation signal acquisition.

Description

Technical Field

[0001] This invention belongs to the fields of microelectronics and integrated circuits, specifically a TDC satellite navigation signal acquisition system based on a surface acoustic wave filter. Background Technology

[0002] Satellite navigation and positioning technology plays a significant role. In the military field, it enables navigation, guidance, and positioning of moving targets, and can also be used in high-precision military applications such as spaceflight. In the civilian field, it can assist people in geodesy, engineering exploration, and other projects, and is more widely used in car navigation, mobile phone navigation, and other applications.

[0003] A satellite system (such as the BeiDou Navigation Satellite System, BDS) consists of a space segment, a ground segment, and a user segment. The space segment continuously transmits satellite navigation signals to both the ground and user segments, maintaining two-way communication with the ground segment and one-way communication with the user segment. The ground segment monitors the system's operation, promptly repairs any satellite malfunctions, and sends data commands to the navigation message, which is then transmitted to the space segment via antennas. The user segment demodulates the satellite navigation signals, modulating the navigation data codes onto the carrier and ranging signals. By extracting satellite parameter information, the user segment provides services such as positioning and timing.

[0004] The acquisition of existing satellite navigation signals typically involves a receiver generating an analog signal through a series of processes such as surface acoustic wave (SAW) filtering and noise amplification. This analog signal is then converted into an intermediate frequency (IF) digital signal by an ADC (Analog-to-Digital Converter), and various acquisition algorithms are used to acquire the satellite signal. Using an ADC for data conversion has advantages such as short design cycle and low cost, but it also has the following drawbacks: due to limitations in sampling rate and resolution, the accuracy is generally low, and there is a delay; moreover, the dynamic range of the ADC is limited, which may prevent it from processing strong and weak signals simultaneously, resulting in the loss of weak signals or distortion of strong signals. Summary of the Invention

[0005] To address the aforementioned problems and shortcomings, and to solve various issues related to signal acquisition in existing satellite systems, this invention provides a TDC satellite navigation signal acquisition system based on a surface acoustic wave filter.

[0006] The specific technical solution is as follows:

[0007] A TDC satellite navigation signal acquisition system based on a surface acoustic wave (SAW) filter includes: a SAW filter, a low-noise amplifier, a mixer, an image rejection filter, a first variable gain amplifier, an intermediate frequency (IF) filter, a second variable gain amplifier, a PWM module, a TDC module, an IQ_bank_mem module, a windowing module, a partially matched filter, a fast Fourier transform module, a squaring module, a maximum value finding module, and a confirmation acquisition module.

[0008] The surface acoustic wave (SAW) filter is a core component of a satellite navigation system, primarily used to filter out various interference signals in satellite signals, ensuring smooth communication between the satellite and the ground control center. In the complex and harsh environment of space, highly reliable and high-performance SAW devices play a decisive role in the accuracy of satellite communication.

[0009] The low-noise amplifier (LNA) amplifies weak satellite signals and reduces its own noise, ensuring a maximum signal-to-noise ratio and a low noise figure, which is crucial for the stability and accuracy of satellite communication systems.

[0010] The mixer receives the satellite signal amplified by a low-noise amplifier and performs down-conversion using the local oscillator signal. This step modulates the intermediate frequency signal into an intermediate frequency analog signal.

[0011] The image suppression filter receives satellite signals after passing through the mixer and is used to conduct and filter the corresponding signals to prevent image interference.

[0012] The intermediate frequency (IF) filter, positioned between two variable gain amplifiers, filters the data, removing stray high frequencies. The first and second variable gain amplifiers, located at opposite ends of the IF filter, perform automatic gain control, automatically adjusting the gain to cope with rapid changes in signal strength and maintain stable output.

[0013] The PWM module receives analog data from the second variable gain amplifier and converts it into a corresponding pulse signal, thus completing the conversion from analog to time.

[0014] The TDC module receives pulse signals from the PWM module and converts them into corresponding digital signals, completing the conversion from time to digital. Current satellite systems all use ADCs to convert data into digital signals, and there is no precedent for using TDC. This invention uses TDC to achieve higher accuracy.

[0015] The IQ_bank_mem module stores the signal input from the TDC module and divides it into two paths, I and Q, for subsequent calculations.

[0016] The windowing module performs smoothing processing on the I and Q data by applying windows (such as Hamming window, Hanning window, or Blackman window).

[0017] The partially matched filter performs coherent operations on the smoothed input data and the pseudocode data.

[0018] The Fast Fourier Transform (FFT) module performs a Fast Fourier Transform on the coherent operation results of the partially matched filter to design an FFT filter with the required number of points.

[0019] The squaring module squares the data obtained from the FFT filter, which is essentially a non-coherent integration operation to reduce the impact of noise on signal capture.

[0020] The maximum value finding module uses partially matched filters to filter the data. The outputs of the N partially matched filters are not directly summed, but are used as inputs to the N-point FFT for FFT filtering. Therefore, the data after the Fast Fourier Transform is also segmented. It is necessary to find the corresponding maximum data in each segment of the N-point FFT and send it to the subsequent module.

[0021] The confirmed capture module searches for the maximum data generated by the maximum value module and compares it with the capture threshold. If the capture threshold is exceeded, the capture is considered successful, and the corresponding satellite number and signal phase are output. If the capture threshold is not exceeded, the next satellite is traversed.

[0022] Furthermore, the satellite signal is a satellite signal from the BeiDou Navigation Satellite System.

[0023] Furthermore, the windowing module incorporates Hamming windows, Hanning windows, or Blackman windows.

[0024] Furthermore, the compliance requirement in the Fast Fourier Transform module refers to the requirement for adaptation to different satellite systems. Different satellite systems have different point count requirements for their satellite signals. To adapt to various point count operations and meet timing requirements, and to enhance versatility, this invention redesigns a multi-point Fast Fourier Transform module.

[0025] In summary, the acquisition system of this invention, from signal reception and filtering to the corresponding baseband signal processing method, is the first to adopt the Time-Digital Transform (TDC) approach, using time as a bridge to complete the entire signal acquisition process. Although TDC has a long design cycle and high cost, it typically has low latency, making it suitable for scenarios with high real-time requirements. Furthermore, it has low dependence on signal amplitude, making it more suitable for processing signals with a large dynamic range. Moreover, the baseband signal processing method uses a partially matched filter and a newly designed variable-point Fast Fourier Transform (VFT) method for multi-point design, making it applicable to signal types from various satellite navigation systems such as GPS and BDS. Ultimately, this invention achieves high precision, low latency, and high adaptability in satellite navigation signal acquisition. Attached Figure Description

[0026] Figure 1 This is a schematic block diagram of the present invention.

[0027] Figure 2 This is a schematic diagram of the surface acoustic wave filter used in the embodiment.

[0028] Figure 3 The circuit diagram of the PWM module in the example is shown below: a is the rising edge controlled inverter, and b is the falling edge controlled inverter.

[0029] Figure 4 This is a schematic block diagram of the calibration module in an embodiment.

[0030] Figure 5 This is a schematic diagram of the structure of a partial matched filter in the embodiment.

[0031] Figure 6 This is a schematic diagram of the variable-point fast Fourier transform module in the embodiment. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0033] A TDC satellite navigation signal acquisition system based on a surface acoustic wave filter, such as Figure 1 As shown, it includes a surface acoustic wave (SAW) filter, a low-noise amplifier, a mixer, a mirror rejection filter, a first variable gain amplifier, an intermediate frequency (IF) filter, a second variable gain amplifier, a PWM module, a TDC module, an IQ_bank_mem module, a windowing module, a partially matched filter, a fast Fourier transform module, a squaring module, a maximum value finding module, and a confirmation capture module.

[0034] This embodiment illustrates the acquisition process of BeiDou satellite BDS1I signals.

[0035] The B1I signal frequency of the BeiDou Navigation Satellite System (BDS) is 1561.098MHz, which is one of the main frequency bands publicly offered by the BeiDou system and is widely used in civilian navigation and positioning services.

[0036] The satellite signal is received, passes through a surface acoustic wave (SAW) filter, enters the receiver system, and is processed by a series of devices to obtain an analog signal. The analog signal is then converted into a pulse signal based on PWM, and converted into a digital signal by a time-to-digital converter (TDC). Subsequently, the data is filtered by partially matched filtering and fast Fourier transform filtering to capture the satellite signal.

[0037] A surface acoustic wave (SAW) filter is an electronic device that utilizes surface acoustic waves for signal processing, primarily used for filtering radio frequency (RF) and intermediate frequency (IF) signals. Its working principle is based on the propagation characteristics of SAW waves on the surface of piezoelectric materials. In satellite navigation signal processing, the SAW filter's role is to filter out out-of-band interference, improve signal quality, and protect subsequent circuits. Specifically, when an input electrical signal is applied to the input transducer, the piezoelectric substrate surface vibrates mechanically due to the piezoelectric effect, generating a SAW wave. The SAW wave propagates along the substrate surface at the same frequency as the input electrical signal. The characteristics of the SAW wave propagating on the piezoelectric substrate surface (such as velocity and attenuation) are determined by the substrate material and structure. By designing the transducer geometry (such as finger width and spacing), the frequency response of the SAW wave can be controlled. When the SAW wave propagates to the output transducer, the mechanical vibration is converted back into an electrical signal due to the piezoelectric effect. Only SAW waves of specific frequencies can propagate effectively and be received by the output transducer; signals of other frequencies are suppressed. The frequency response of a surface acoustic wave filter is determined by the design of its input and output transducers.

[0038] The surface acoustic wave filter used in this embodiment has the following structure: Figure 2 The diagram shows a composite structure based on X-cut LN / SiO2 / poly-Si / Si. The resonator wavelength λ is 2 μm, the resonator aperture (W) is 50 μm, the electrode width (a) is 0.5 μm, the electrode gap (gap) is 300 nm, the number of interdigitated electrodes is 100 pairs, the number of reflective gratings is 15 pairs, and the pseudofinger length is 2.12λ. The Al electrode thickness is 120 nm, and the X-cut LN thickness is 300 nm.

[0039] The structure of the PWM module used in this embodiment is as follows: Figure 3 As shown, the received analog signal is converted into a corresponding pulse signal, specifically by two inverters, one controlled by the rising edge and the other by the falling edge. The rising edge control structure is shown in Figure a, and the falling edge control structure is shown in Figure b. Input V in It is an intermediate frequency analog signal, clock signal V clk By controlling the inverter with the falling edge, a clock signal V2 with its falling edge delayed by t is generated, while V clkb By controlling the inverter with the rising edge, a clock signal V1 with its rising edge delayed by t is generated. Performing an XOR operation on V1 and V2 yields the pulse width modulation signal V. out .

[0040] In this embodiment, the Time-to-Digital Converter (TDC) employs a high-precision delay chain information calibration circuit, implemented in a Field-Programmable Gate Array (FPGA). This aims to address the issues of long design cycles and high costs, while also offering good flexibility. Specifically, a tapped delay chain method is used for counting, and a code density lookup table method is used for calibration to achieve high precision. The TDC includes a calibration module, a delay module, and a storage module: The calibration module generates a random signal for the delay module, requiring that this signal be independent of the clock cycle. Based on the pulses provided by the tap delay, the decoder result is obtained, and the code density information is written to the storage module. The delay module receives the random signal from the calibration module, records the farthest position reaching the tap and the number of times each random signal reaches each tap; it calculates the delay time of each tap, comprehensively considering the statistical counts of all taps and the clock cycle. The storage module stores the delay information and delay length.

[0041] In actual operation, the calibration module requires decoded information to represent address information. This decoded data comes from the decoder corresponding to the signal generated by the tap information of the tap chain. The storage module can query the corresponding delay length and complete the calibration with that length.

[0042] In this embodiment, the calibration module consists of a zeroing module, a counting module, and a summing module, such as... Figure 4 As shown.

[0043] When the clearing module finishes its work, it releases the `clear_done` signal; when the counting module finishes its work, it releases the `count_done` signal; and when the summing module finishes its work, it releases the `add_done` signal. Based on these three signals, state transitions are performed, represented by the `state` parameter: 001 represents the clearing module, 010 represents the counting module, and 100 represents the summing module. Using one-hot encoding for state representation can reduce jump errors.

[0044] Furthermore, the zeroing module, with a state of 001, clears the data in RAM. Before each recalibration, it writes zeros to the data at each address in the memory, facilitating the writing and summation of the code density delay information in the memory. When the memory is full, it releases the data using `clear_done`, and the state switches to 010, indicating that the counting module has started and will calculate the code density. The memory is implemented using pseudo-dual-port RAM.

[0045] The counting module, with a state of 010, generates random signals from a ring oscillator composed of an odd number of cascaded inverters. When the delay module detects that the first tap of the tap delay chain is pulled high on a certain clock rising edge, the delay chain sends a pulse called "valid" to the counting module. When the counting module receives this signal, it transmits the decoder data to the internal controller of the counting module and performs a write operation on the memory, with the address being the decoder data decremented.

[0046] The summation module, with state 100, performs a summation operation on the data in the memory and then completes the write operation. When the count_done signal is received, the state changes to 100, indicating that the summation module has started and uses the sum of the data stored at each address and the previous address as the value of the next address.

[0047] Furthermore, the delay module includes a delay chain structure, a decoder, and a frequency multiplier circuit.

[0048] Furthermore, the delay chain structure functions to generate delay information for the delay circuit, taking into account the statistical count of all taps and the clock cycle.

[0049] The decoder is a thermometer code decoder.

[0050] The frequency multiplier circuit is used to set the clock period and frequency of the circuit.

[0051] The windowing module is used because the data will be segmented subsequently, and each segment needs to undergo partial matched filtering. Therefore, data truncation is necessary. However, arbitrarily truncated data cannot meet the smoothing requirements and suffers from spectral leakage. Thus, a windowing operation is required. In this embodiment, a Hanning window is chosen. The formula for the Hanning window is as follows:

[0052]

[0053] The partially matched filter described is a filter implemented using a coherent integral followed by an adder tree. It performs coherent operations on the input data and the pseudocode data. Specifically, if the pseudocode is 0, the correlation result is the input data; if the pseudocode is 1, the correlation result is the negative of the input data. After all filters have undergone coherent operations, the coherent results are accumulated using an adder tree, adding two at a time, then adding the results two at a time again, and so on, to calculate the coherent integral. The structure is as follows: Figure 5 As shown.

[0054] The Fast Fourier Transform (FFT) module has different point count requirements for different satellite signals. To adapt to various point counts and meet timing requirements, making the invention more versatile, a multi-point FFT module was designed to perform FFT operations on the data. In BeiDou satellite signal acquisition, FFT is mainly used to quickly detect Doppler shift and code phase, thereby improving acquisition speed and accuracy. The variable-point FFT architecture of this embodiment is as follows: Figure 6 As shown, you can select from 64 points, 128 points, 256 points, 512 points, 1024 points, and 2048 points to perform FFT calculations.

[0055] The specific implementation includes the following modules: data_in_controller module, ram0_group module, ram1_controller module, ram1_group module, switch_ram0_ram1 module, butterfly_radix4_top module, matrix_transpose module, butterfly_radix2_top module, switch_transpose_radix2 module, ram2_group module, ram2_controller module, butterfly_parameter module, and data_out_process module. The connections between these modules and the flow of key data are as follows: Figure 6 As shown.

[0056] Specifically, the steps of data flow and the functions of each sub-module are explained:

[0057] Data from the partially matched filter is sent to the data_in_controller module. In this module, the number of operation points is set, and the data is divided into 4 RAMs and sent to the ram0_group module. The ram0_write_over signal is generated to indicate whether ram0 has been written.

[0058] Data from the data_in_controller is sent to the ram0_group module. The ram0_group module is a ram group consisting of 4 rams. The read and write control signals of the four rams are generated by the data_in_controller module and the ram1_controller module. The output data of ram0_group is sent to the switch_ram0_ram1 module.

[0059] The ram1_controller module accepts the fft_point and ram0_write_over signals; the fft_point signal indicates the selection of the number of FFT points; the ram0_write_over signal indicates that the writing of ram0 is complete; the ram1_controller module generates the fft_stage signal, indicating how many radix-4 butterfly operations were performed, to indicate the specific stage of data operation; and the ram1_controller module controls the read and write operations of the ram0_group and ram1_group modules.

[0060] The ram1_group module receives data from the matrix_transpose module that has already undergone radix-4 butterfly operations and sends the data to the switch_ram0_ram1 module.

[0061] The switch_ram0_ram1 module selects data. One source of the selected data is the original data from the ram0_group module, and the other source is the data that has undergone radix-4 butterfly operations from the ram1_group module. The selection is based on the ram0_write_over signal, and the selected data is then sent to the butterfly_radix4_top module.

[0062] Data from switch_ram0_ram1 undergoes radix-4 butterfly operations in the butterfly_radix4_top module. The operation is based on mathematical principles: the data is multiplied by the butterfly factor, and then the product is added or subtracted accordingly. After each operation, a saturation truncation operation is performed to ensure a fixed data bit width. Finally, the result is sent to the matrix_transpose module.

[0063] The matrix_transpose module receives the data after performing a radix-4 butterfly operation in butterfly_radix4_top, and then divides the data into three paths for further processing: one path performs a radix-2 butterfly operation in the butterfly_radix2_top module; another path loops in the ram1_group module, preparing to perform a radix-4 butterfly operation; and the third path outputs the data to the switch_transpose_radix2 module.

[0064] Data from matrix_transpose undergoes radix-2 butterfly operations in the butterfly_radix2_top module. The operation process follows mathematical principles: the data is multiplied by the butterfly factor, and then the product is added or subtracted accordingly. After each operation, a saturation truncation operation is performed to ensure a fixed data bit width. Finally, the result is sent to the switch_transpose_radix2 module.

[0065] In the switch_transpose_radix2 module, the two received data streams are selected based on the required number of FFT points: one stream is from matrix_transpose, and the other is from butterfly_radix2_top. For example, 64 points represent data that has undergone three radix-4 butterfly operations, 128 points represent data that has undergone three radix-4 butterfly operations and one radix-2 butterfly operation, and 256 points represent data that has undergone four radix-4 butterfly operations. The selected data stream is then output to the ram2_group module, and the ram2_data_valid signal indicating that the data is valid is input to the ram2_controller module.

[0066] In the ram2_controller module, read and write signals for ram2_group are generated, and a flag indicating the end of the FFT operation is generated.

[0067] Data from switch_transpose_radix2 is written to and read from in the ram2_group module, and then output to the final data_out_process module.

[0068] The factors for radix-4 and radix-2 butterfly operations are obtained from the butterfly_parameter module, and the butterfly factors are stored in the ROM. The address for the radix-4 butterfly operation is obtained from ram1_controller, and the address for the radix-2 butterfly operation is obtained from ram2_controller.

[0069] The data_out_process module accepts data ram2_out0\1\2\3 from ram2_group and amplitude adjustment signals (factor) from external sources, selects and adjusts the data, and finally outputs fft_out.

[0070] The maximum value finding module finds and outputs the maximum data in each data segment of the FFT filter output. This embodiment uses a 7680-phase, 256-point FFT as an example. Each phase has 256 points, which remain after incoherent integration by the squaring module. The comparison logic of the maximum value finding module is as follows: First, find the maximum value (compare_update) in each phase (256 points) and record its index value doppler_index (0:255). Then, compare it with compare_upper (maximum value) and compare_lower (minimum value) respectively. Continuously compare the 7680-phase data, update compare_upper and compare_lower, record their index values ​​doppler_index (0:255) and phase_index (0:7679), and send them to the next module for confirmation and capture.

[0071] Finally, by confirming the capture module, the maximum data output by the maximum value search module is compared with the capture threshold: if it exceeds the capture threshold, the capture is considered successful, and the corresponding satellite number and signal phase are output; if it does not exceed the capture threshold, the next satellite is traversed.

Claims

1. A TDC satellite navigation signal acquisition system based on a surface acoustic wave filter, characterized in that: It includes a surface acoustic wave filter, a low-noise amplifier, a mixer, a mirror rejection filter, a first variable gain amplifier, an intermediate frequency filter, a second variable gain amplifier, a PWM module, a TDC module, an IQ_bank_mem module, a windowing module, a partially matched filter, a fast Fourier transform module, a squaring module, a maximum value finding module, and a confirmation capture module. The surface acoustic filter removes various interference signals from satellite signals. The low-noise amplifier (LNA) amplifies satellite signals and reduces its own noise. The mixer receives the satellite signal amplified by a low-noise amplifier, performs down-conversion using a local oscillator signal, and modulates the intermediate frequency signal into an intermediate frequency analog signal. The image rejection filter receives satellite signals after passing through the mixer and is used to conduct and filter the corresponding signals; The intermediate frequency filter is positioned between two variable gain amplifiers to filter the data and remove stray high frequencies; the first and second variable gain amplifiers are located at opposite ends of the intermediate frequency filter to perform automatic gain control on the signal and maintain stable output. The PWM module receives analog data from the second variable gain amplifier and converts it into a corresponding pulse signal. The TDC module receives pulse signals from the PWM module and converts them into corresponding digital signals; The IQ_bank_mem module stores the signal input from the TDC module and divides it into two paths, I and Q, for subsequent calculations. The windowing module applies windowing to both I and Q data streams to smooth the data. The partially matched filter performs coherent operations on the smoothed input data and the pseudocode data; The Fast Fourier Transform (FFT) module performs a Fast Fourier Transform on the coherent operation results of the partially matched filter, designing an FFT filter with the required number of points. The "requirements" in the Fast Fourier Transform module refer to compatibility with the BeiDou Navigation Satellite System. The Fast Fourier Transform module, corresponding to the satellite signals of the BeiDou Navigation Satellite System, includes the following sub-modules: The modules are: data_in_controller, ram0_group, ram1_controller, ram1_group, switch_ram0_ram1, butterfly_radix4_top, matrix_transpose, butterfly_radix2_top, switch_transpose_radix2, ram2_group, ram2_controller, butterfly_parameter, and data_out_process. Specifically, the steps of data flow and the functions of each sub-module are explained: Data from the partially matched filter is sent to the data_in_controller module. In this module, the number of operation points is set, and the data is divided into 4 RAMs and sent to the ram0_group module. The ram0_write_over signal is generated to indicate whether ram0 has been written. Data from the data_in_controller is sent to the ram0_group module. The ram0_group module is a ram group consisting of 4 rams. The read and write control signals of the four rams are generated by the data_in_controller module and the ram1_controller module. The output data of ram0_group is sent to the switch_ram0_ram1 module. The ram1_controller module accepts the fft_point and ram0_write_over signals; the fft_point signal indicates the selection of the number of FFT points; the ram0_write_over signal indicates that the writing to ram0 is complete; the ram1_controller module generates the fft_stage signal, indicating how many radix-4 butterfly operations were performed, to indicate the specific stage of data processing; and the ram1_controller module controls the read and write operations of the ram0_group and ram1_group modules. The ram1_group module receives data from the matrix_transpose module that has already undergone radix-4 butterfly operations and sends the data to the switch_ram0_ram1 module; The switch_ram0_ram1 module selects data. One source of the selected data is the original data from the ram0_group module, and the other source is the data that has undergone radix-4 butterfly operations from the ram1_group module. The selection is based on the ram0_write_over signal, and the selected data is then sent to the butterfly_radix4_top module. Data from switch_ram0_ram1 undergoes radix-4 butterfly operations in the butterfly_radix4_top module. After each operation, a saturation truncation operation is performed, and the result is finally sent to the matrix_transpose module. The matrix_transpose module receives the data after the radix-4 butterfly operation in butterfly_radix4_top, and then divides the data into three paths for further processing: one path performs the radix-2 butterfly operation in the butterfly_radix2_top module; another path loops in the ram1_group module, preparing to perform the radix-4 butterfly operation again; and the third path outputs the data to the switch_transpose_radix2 module. Data from matrix_transpose undergoes radix-2 butterfly operations in the butterfly_radix2_top module. After each operation, a saturation truncation operation is performed, and the result is finally sent to the switch_transpose_radix2 module. In the switch_transpose_radix2 module, the two received data streams will be selected based on the required number of FFT points to be performed: one stream is data from matrix_transpose; the other stream is data from butterfly_radix2_top. The selected data stream will then be output to the ram2_group module, and the signal ram2_data_valid indicating that the data is valid will be input to the ram2_controller module. In the ram2_controller module, read and write signals for ram2_group are generated, and a flag indicating the end of the FFT operation is generated. Data from switch_transpose_radix2 is written and read in the ram2_group module, and the data is output to the final data_out_process module; The factors for radix-4 and radix-2 butterfly operations are obtained from the butterfly_parameter module, and the butterfly factors are stored in the ROM; the address for radix-4 butterfly operations is obtained from ram1_controller, and the address for radix-2 butterfly operations is obtained from ram2_controller. The data_out_process module receives data ram2_out0\1\2\3 from ram2_group and amplitude adjustment signals factor from the outside, selects and adjusts the data, and finally outputs fft_out. The squaring module performs incoherent integration on the data obtained from the FFT filter; The maximum value finding module finds and outputs the corresponding maximum data in each data segment of the FFT filter output. The confirmed capture module compares the maximum data output by the maximum value search module with the capture threshold: if it exceeds the capture threshold, the capture is considered successful, and the corresponding satellite number and signal phase are output. If the capture threshold is not exceeded, proceed to the next satellite.

2. The TDC satellite navigation signal acquisition system based on a surface acoustic wave filter as described in claim 1, characterized in that: The windowing module adds a Hamming window, a Hanning window, or a Blackman window.

3. The TDC satellite navigation signal acquisition system based on a surface acoustic wave filter as described in claim 1, characterized in that: The TDC module employs a high-precision delay chain information calibration circuit, which is implemented in a field-programmable gate array (FPGA).

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