Chip verification method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a chip verification method and device, electronic equipment and storage medium. The chip verification method comprises: obtaining a chip model of a chip, the chip model comprising a physical layer interface and a function model; writing an expected offset for simulating a time sequence offset in an access operation process between the physical layer interface and the function model into the chip model, so that the physical layer interface trains a time sequence of an access operation between the physical layer interface and the function model based on the expected offset; in response to the end of the training of the chip model, obtaining an operation offset for compensation obtained by the physical layer interface based on the training; and determining an offset adjustment capability of the physical layer interface according to the operation offset and the expected offset. The chip verification method can detect the offset adjustment capability of the physical layer interface before silicon.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a chip verification method and apparatus, electronic device, and storage medium. Background Technology

[0002] In the field of chip design and manufacturing, chip tape-out (i.e. chip trial production) involves complex manufacturing steps and expensive equipment, so if there are errors in the design, it may cause the entire batch of chips to be scrapped, resulting in huge economic losses.

[0003] To avoid losses caused by finished chips that do not meet requirements or have poor quality after tape-out, thorough verification and testing before tape-out are crucial. Chip verification and testing are important means of discovering potential chip defects in advance, and can avoid various problems that may occur after silicon (i.e., after the chip is actually manufactured). Therefore, it is necessary to conduct a detailed evaluation and verification of the chip's capabilities before silicon (i.e., before the actual chip manufacturing). Summary of the Invention

[0004] At least one embodiment of this disclosure provides a chip verification method, which includes: obtaining a chip model of a chip, wherein the chip model includes a physical layer interface and a functional model; writing an expected offset for simulating timing offsets during access operations between the physical layer interface and the functional model into the chip model, and training the physical layer interface on the timing of access operations between the physical layer interface and the functional model based on the expected offset; in response to the completion of training of the chip model, obtaining the operation offset obtained by the physical layer interface based on the training for compensation; and determining the offset adjustment capability of the physical layer interface based on the operation offset and the expected offset.

[0005] For example, in the chip verification method provided in at least some embodiments of this disclosure, writing the expected offset of the timing offset during the process of simulating the access operation between the physical layer interface and the functional model into the chip model includes: writing the expected offset into a target register in the chip model so that it can be read by the physical layer interface for training.

[0006] For example, in the chip verification method provided in at least some embodiments of this disclosure, training the timing of access operations between the physical layer interface and the functional model based on the expected offset includes: in response to the start of training of the chip model, causing the physical layer interface to obtain the expected offset written into the chip model, and using it as the current offset between the physical layer interface and the functional model for training.

[0007] For example, in the chip verification method provided in at least some embodiments of this disclosure, before starting the training of the chip model, the chip verification method further includes: configuring the training mode of the chip model so that the chip model is trained in the set working mode.

[0008] For example, in the chip verification method provided in at least some embodiments of this disclosure, before training of the chip model is started, the chip verification method includes: configuring the operating frequency of the chip model to determine the expected offset according to the set operating frequency.

[0009] For example, in the chip verification method provided in at least some embodiments of this disclosure, the functional model includes multiple memory particle models; before training of the chip model is started, the chip verification method further includes: obtaining the encoding of each memory particle model in the functional model according to the set particle encoding rules and the encoding requirements of the physical layer interface; and determining the expected offset corresponding to each memory particle model in the functional model according to the encoding of each memory particle model in the functional model and the set operating frequency.

[0010] For example, in the chip verification method provided in at least some embodiments of this disclosure, the expected offset includes the expected offset value and the expected offset direction. Determining the expected offset corresponding to each memory particle model in the functional model includes: determining a predetermined offset range corresponding to a set operating frequency according to the memory standard protocol supported by the functional model; and determining the expected offset value and the expected offset direction of each memory particle model in the functional model according to the predetermined offset range.

[0011] For example, in the chip verification method provided in at least some embodiments of this disclosure, determining the expected offset value and expected offset direction of each memory particle model in the functional model according to a predetermined offset range includes: obtaining an offset reference value; and in response to the start of training of the chip model, determining the expected offset value and expected offset direction of each memory particle model in the functional model according to the offset reference value and the predetermined offset range.

[0012] For example, in the chip verification method provided in at least some embodiments of this disclosure, the physical layer interface obtains the expected offset written into the chip model and uses it as the current offset between the physical layer interface and the functional model for training, including: obtaining the operation offset based on the offset reference value and the absolute value of the offset value of the expected offset obtained by the physical layer interface.

[0013] For example, in the chip verification method provided in at least some embodiments of this disclosure, writing the expected offset into the target register in the chip model includes: according to the expected offset, storing the corresponding expected offset value and expected offset direction of each storage particle model in the functional model into the target register corresponding to each storage particle model.

[0014] For example, in the chip verification method provided in at least some embodiments of this disclosure, the physical layer interface obtains the expected offset written into the chip model and uses it as the current offset between the physical layer interface and the functional model for training. The method further includes: obtaining the expected offset value and expected offset direction stored in the target register corresponding to each storage particle model according to the physical layer interface, and performing offset calculation based on the obtained expected offset value and the obtained expected offset direction to obtain the offset value and offset direction of the operation offset used for compensation for each storage particle model.

[0015] For example, in the chip verification method provided in at least some embodiments of this disclosure, determining the offset adjustment capability of the physical layer interface based on the operational offset and the expected offset includes: comparing the expected offset direction and the operational offset direction to determine whether the offset direction of the physical layer interface is correct; and comparing the expected offset value and the operational offset value to determine the offset error value of the physical layer interface.

[0016] For example, in the chip verification method provided in at least some embodiments of this disclosure, the offset adjustment capability of the physical layer interface is determined based on the operation offset and the expected offset, and further includes: in response to an error in the offset direction of the physical layer interface, determining that the internal logic or algorithm of the physical layer interface is faulty; and in response to a correct offset direction of the physical layer interface, outputting the offset error value of the physical layer interface.

[0017] For example, in the chip verification method provided in at least some embodiments of this disclosure, the training of the chip model includes: in response to the chip model being in a retraining state or a normal working mode, sending an offset update instruction to the physical layer interface to update the operation offset obtained from the training for compensation to the offset register of the physical layer interface.

[0018] For example, in the chip verification method provided in at least some embodiments of this disclosure, the chip is a DDR chip and the functional model is a DRAM model.

[0019] For example, in the chip verification method provided in at least some embodiments of this disclosure, before starting training on the chip model, the chip verification method further includes: configuring the precision mode of the chip model to configure the training step size.

[0020] At least one embodiment of this disclosure also provides a chip verification apparatus, which includes a chip model corresponding to the chip, comprising a physical layer interface and a functional model. The chip verification apparatus includes an expected offset module and a checking module. The expected offset module is configured to write an expected offset, used to simulate timing offsets during access operations between the physical layer interface and the functional model, into the chip model, thereby training the physical layer interface on the timing of access operations between the physical layer interface and the functional model based on the expected offset. The checking module is configured to, in response to the completion of training of the chip model, obtain the operational offset obtained by the physical layer interface based on the training for compensation; and determine the offset adjustment capability of the physical layer interface based on the operational offset and the expected offset.

[0021] For example, the chip verification apparatus provided in at least some embodiments of this disclosure further includes a configuration module, which is configured to perform one or more of the following configurations: configuring a training mode of the chip model so that the chip model is trained in a set operating mode; configuring the operating frequency of the chip model to determine the expected offset according to the set operating frequency; configuring the precision mode of the chip model to configure the training step size; and configuring the granular coding rules of the chip model so that each storage granular model in the functional model is encoded according to the set granular coding rules.

[0022] At least some embodiments of this disclosure also provide an electronic device including at least one memory and at least one processor. The at least one memory is configured to store computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions, which, when executed by the at least one processor, implement the chip verification method provided in any embodiment of this disclosure.

[0023] At least some embodiments of this disclosure also provide a non-transitory storage medium that non-transitoryly stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, the chip verification method provided in any embodiment of this disclosure is implemented. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 A schematic diagram of a write operation timing that conforms to the DDR protocol is shown.

[0026] Figure 2 A schematic diagram of a read operation timing that conforms to the DDR protocol is shown.

[0027] Figure 3 This diagram illustrates the actual timing of a DDR write operation.

[0028] Figure 4 This diagram illustrates the actual timing of a DDR read operation.

[0029] Figure 5 A schematic flowchart of a chip verification method provided in at least one embodiment of this disclosure is shown;

[0030] Figure 6 A flowchart illustrating an example of a chip verification method provided in at least one embodiment of this disclosure is shown;

[0031] Figure 7 A block diagram of a chip verification apparatus provided in at least one embodiment of the present disclosure is shown;

[0032] Figure 8 A schematic diagram illustrating an example of a chip verification apparatus provided in at least one embodiment of the present disclosure is shown;

[0033] Figure 9 A block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;

[0034] Figure 10 A block diagram of an electronic device according to at least one embodiment of the present disclosure is shown; and

[0035] Figure 11 A schematic diagram of a non-transitory storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0038] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components are omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is indicated by the same or similar reference numerals in each drawing.

[0039] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0040] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0041] DDR (Double Data Rate) memory systems are a crucial component of chips, primarily comprising a DDR controller, a DDR physical layer interface (DDR PHY), and DDR memory modules. The PHY (Physical Layer) refers to the physical layer interface circuitry, while the memory module is, for example, a Dynamic Random Access Memory (DRAM) module. The DDR controller and DDR PHY are connected, and the DDR PHY is connected to the DDR memory module, forming a communication link: DDR controller <-> DDR PHY <-> DDR memory. Because the PHY is critical to the entire chip, pre-processing and error correction verification of the PHY before silicon development is an important method for early detection of chip defects.

[0042] In DDR memory systems, parallel signals transmitted via multiple parallel data lines are limited by signal integrity issues such as interference, reflection, crosstalk, and timing control difficulties as data transfer rates increase. Therefore, it's difficult for parallel signals to reach high operating frequencies. The DDR PHY needs to convert these signals into serial signals for routing on the circuit board to improve signal integrity. The DDR controller's role is to translate upstream read / write control requests into commands that the DDR memory can recognize, generating the timing of address read / write control signals.

[0043] DDR technology allows data transmission on both the rising and falling edges of the clock signal, thus doubling the data transfer rate compared to technologies that transmit data only on either the rising or falling edge. Since its introduction, DDR technology has undergone several iterations. DDR5 is the fifth generation of DDR memory technology. The following explanation uses DDR5 as an example.

[0044] The function of the DDR PHY is to handle timing during access operations (read and write operations) and send the signals of the DDR controller in a better timing order. However, due to the limitations of the internal logic and algorithm of the DDR PHY, the DDR PHY will cause a certain delay when transmitting signals. In order for the output signal of the DDR PHY to meet the requirements of the DDR protocol, the DDR PHY needs to be trained. The DDR PHY adjusts the delay line (Driver Side Delay Line) at the transmitting end so that the DDR memory can successfully sample the control signals and data signals at the receiving end.

[0045] The aforementioned "training" refers to a series of tests and calibrations performed by the controller after system startup or reset to determine optimal operating parameters and apply these parameters to subsequent normal operation. This initialization process aims to optimize and ensure the accuracy and reliability of data transmission by adjusting timing parameters to compensate for various physical effects on the signal path, such as delay, reflection, and crosstalk, thereby achieving optimal data read / write performance. For example, dynamic adjustments or retraining (retraining) are performed when large offsets or other problems are detected during the operation of a DDR memory device. For instance, the DDR controller can be set to perform retraining periodically, which helps compensate for long-term accumulated errors caused by temperature drift, power supply noise, etc.

[0046] Figure 1 A schematic diagram of a write operation timing that conforms to the DDR protocol is shown.

[0047] like Figure 1 As shown, during a write operation, the command / address bus is used to transmit command and address information, such as the command or address signal CA[13:0]. The command signal (CMD) is used to indicate the type of command sent by the memory controller to the memory module. For example, in a write operation, the command type is "WRITE" (write command). After the write command, the CMD signal will display a series of "DES" (data enable suffix) to indicate the end of the command transmission. The chip select signal (CS0_n) is kept low during a write operation to indicate that a specific memory chip is selected for a write operation. Clock signals (CK_t and CK_c) are used to synchronize data transmission, where CK_t and CK_c are two phases of the clock signal. For example, the time window used by the data strobe signal to indicate data validity is called the data eye diagram. The data bus transmits data under the control of the data strobe signals (DQS_t and DQS_c). During a write operation, the data strobe signals are synchronized with the clock signal to ensure that data is sampled in the correct clock cycle.

[0048] For example, in Figure 1 During the write operation, after the time interval (tWPRE) required between the write operation and the precharge operation, the rising or falling edge of the data strobe signal (e.g., DQS_t) needs to be aligned with the center position of each data bit in the data signal DQ[15:0] on the data bus to ensure that the storage module (e.g., the memory module) can correctly acquire the data, and then the write settling time (tWPST) will begin.

[0049] In a write operation, write latency is used to determine the number of clock cycles required from the time a write command is issued until the data is written to memory. For example, write latency (WL) is determined based on write command latency CWL or CL (CAS latency). For example, write latency WL = CWL = (CL - 2).

[0050] Figure 2 A schematic diagram of a read operation timing that conforms to the DDR protocol is shown.

[0051] During a read operation, the command / address bus transmits read commands and address information, such as command or address signals CA[13:0]. The command signal (CMD) indicates the type of command sent by the memory controller to the memory module. For example, in a read operation, the command type is "Read". After the read command, the CMD signal will display a series of "DES" (data enable suffix) to indicate the end of the command transmission. The chip select signal (CS_N) remains low during the read operation to indicate that a specific memory chip is selected for a read operation. Clock signals (CK_t and CK_c) are used to synchronize data transmission, where CK_t and CK_c are two phases of the clock signal. The data bus transmits data under the control of data strobe signals (DQS_t and DQS_c).

[0052] In read operations, the rising or falling edge of a data strobe signal (e.g., DQS_t) is used to indicate the validity of the data; therefore, for example, in Figure 2 In the read operation, after the required time interval (tRPRE) between the read operation and the precharge operation, the rising or falling edge of the data strobe signal (e.g., DQS_t) needs to be aligned with the edge of each data bit in the data signal DQ[15:0] on the data bus, after which the read settling time (tRPST) begins to ensure that the memory controller can sample the data at the correct time. The read latency (RL) is equal to the CAS latency (CL) because the CAS latency defines the time from when the read command is issued to when the data can be sampled by the memory controller.

[0053] Figure 1 and Figure 2 This demonstrates that during initialization, the DDR PHY can find ideal latency parameters (such as read latency RL and write latency WL) through initialization training (TRAIN) to meet the read and write timing requirements of the DDR protocol. For example, at the DDR PHY end, the optimal latency parameters can be found by adjusting the internal receiver side delay line, allowing the DDR PHY to successfully sample the output signals of the memory chips in the DDR memory.

[0054] During chip operation, due to changes in external environment such as temperature, humidity, and voltage, as well as the influence of the chip's own structure, the optimal point of PHY delay parameters may change, and the DDR timing on the actual chip will also change.

[0055] Figure 3 A schematic diagram of the actual timing of a DDR write operation is shown.

[0056] like Figure 3 As shown, the timing relationship between the data strobe signal (e.g., DQS) on the PHY side and the data signal (e.g., DQ) on the data bus satisfies the condition that the rising edge of the data strobe signal is aligned with the center position of each data bit in the data signal DQ[15:0] on the data bus; for example, the rising edge of the data strobe signal is aligned with the center position of data bit D0. However, there is a significant offset error on the DRAM side (e.g., ... Figure 3 The rising edge of the DRAM-side data strobe signal shown is actually aligned with the center position of data bit D1, while data bit D0 is not aligned by the data strobe signal. This makes it impossible for the data signal DQ[15:0] to be correctly written into the DRAM memory (for example, the written data will lose data bit D0).

[0057] Figure 4 A schematic diagram of the actual timing of a DDR read operation is shown.

[0058] like Figure 4 As shown, the timing relationship between the data strobe signal (e.g., DQS) on the DRAM side and the data signal (e.g., DQ) on the data bus satisfies the requirement that the rising edge of the data strobe signal must be aligned with the edge of each data bit in the data signal DQ[15:0] on the data bus. For example, the rising edge of the data strobe signal is aligned with the edge of data bit D0. However, when data is transmitted from the DRAM side to the PHY side, there is a significant offset error on the PHY side (e.g., ...). Figure 4 The second rising edge of the PHY-side data strobe signal shown is actually aligned with the edge of data bit D1, while data bit D0 is not aligned with the edge of the data strobe signal. This makes it impossible for the data signal DQ[15:0] to be read correctly from the memory DRAM (for example, the read data will lose data bit D0).

[0059] like Figure 3 and Figure 4 In actual write and read operations, there is a delay offset phenomenon on different sides, that is, there is an offset error in the write and read operations.

[0060] To address this latency offset issue, the PHY can be re-trained through a complete initialization process (TRAIN) to find the ideal latency parameters again. However, this initialization process requires reloading the firmware, which is time-consuming and significantly impacts the chip's bandwidth. Alternatively, during normal operation, the latency parameters that have the greatest impact on the read and write directions can be retrained (RETRAIN). Retraining occurs during chip execution, acquiring appropriate latency parameters for the current environment to ensure proper read and write operations. For write operations, the PHY needs to output a Data strobe signal (DQS) and a data signal (DQ) conforming to the DDR protocol's write timing, enabling the DRAM to correctly sample the data signal. For read operations, the PHY needs to acquire the correct data signal (DQ), fully retrieve the data, and return it to the memory controller. This retraining method allows for real-time adjustments during chip operation with minimal additional time consumption and almost no impact on the chip's bandwidth.

[0061] The inventors of this disclosure noted that currently, after the PHY training (TRAIN initialization or RETRAIN retraining) is completed, the correctness of the training is detected by the correctness of read and write operations. However, even if the read and write operations are successful, complete compliance with protocol requirements cannot be guaranteed. For example, in the write direction of a write operation, the rising edge of the data strobe signal (DQS) may not be perfectly aligned with the center of the data signal (DQ). This offset error, if not exceeding 1 / 2 clock cycle, will not affect the current read and write operation (e.g., at a frequency of 3200 Mbps, 1 / 2 clock cycle is 156 ps; as long as the offset error does not exceed 156 ps, the read and write operation will not fail). However, such delay parameters for read and write operations are not optimal. If such delay parameters are used, the chip may face problems of weak anti-interference capability and poor signal quality after siliconization (i.e., after the actual chip manufacturing).

[0062] Furthermore, the inventors of this disclosure have noted that while initiating retraining during chip operation can provide real-time adjustments, the adjustment space for chips already running after silicon is limited. Determining the ideal latency parameters of the physical layer interface (PHY) through initialization training (TRAIN) or retraining (RETRAIN) is crucial for the overall chip performance and reliability. Therefore, a detailed evaluation and verification of the PHY's adjustment capabilities is necessary before silicon (i.e., before actual chip manufacturing), especially a precise evaluation of the PHY retraining process, to improve the overall chip performance and reliability and avoid increased costs and risks caused by poor or unreliable finished chips after tape-out.

[0063] At least one embodiment of this disclosure provides a chip verification method, comprising: obtaining a chip model of a chip, wherein the chip model includes a physical layer interface and a functional model; writing an expected offset for simulating timing offsets during access operations between the physical layer interface and the functional model into the chip model, thereby training the physical layer interface on the timing of access operations between the physical layer interface and the functional model based on the expected offset; in response to the completion of training of the chip model, obtaining the operation offset obtained by the physical layer interface based on the training for compensation; and determining the offset adjustment capability of the physical layer interface based on the operation offset and the expected offset.

[0064] In the chip verification method of the above embodiments of this disclosure, a chip model including a physical layer interface and a functional model is obtained before silicon. The expected offset is dynamically given by simulating the timing offset between the physical layer interface and the functional model. Then, the simulation is run and trained during the front-end chip verification simulation process. The operation offset of the physical layer interface obtained through training is compared with the expected offset previously written into the chip model. Thus, the physical layer interface offset adjustment capability can be determined through training before silicon, which improves the accuracy of physical layer interface verification and testing before silicon, thereby improving the accuracy of chip design, reducing possible problems after silicon, and reducing the overall tape-out cost and risk.

[0065] The various embodiments of this disclosure will now be described with reference to specific examples.

[0066] Figure 5 A schematic flowchart of a chip verification method provided in at least one embodiment of the present disclosure is shown.

[0067] like Figure 5 As shown, in some embodiments of this disclosure, the chip verification method described above includes steps S30-S33 as follows.

[0068] Step S30: Obtain the chip model of the chip, wherein the chip model includes the physical layer interface and the functional model.

[0069] Step S31: Write the expected offset, which is used to simulate the timing offset during the access operation between the physical layer interface and the functional model, into the chip model, so that the physical layer interface can train the timing of the access operation between the physical layer interface and the functional model based on the expected offset.

[0070] Step S32: In response to the end of training of the chip model, obtain the operation offset of the physical layer interface based on the training obtained for compensation.

[0071] Step S33: Determine the offset adjustment capability of the physical layer interface based on the operation offset and the expected offset.

[0072] In the embodiments of this disclosure, the chip model can be a model that simulates the internal logic of a real chip by simulating a real chip. For example, the chip model is written in a hardware description language (such as Verilog or HDL). For example, after the chip model is run, it can simulate the chip to perform write and read operations according to standard protocols. For example, it can receive write commands and write write data, and receive read commands and return read data. For example, it can be performed according to the DDR standard protocol.

[0073] The Physical Layer Interface (PHY) is the physical layer interface whose accuracy needs to be verified and tested (hereinafter referred to as PHY).

[0074] A functional model can be a model that works with the physical layer interface to perform write and read operations according to standard protocols, used to simulate a storage module (such as a memory module) on a real chip.

[0075] In some embodiments of this disclosure, the chip in the above-described chip verification method is a DDR (Double Data Rate) chip, and its functional model is a DRAM (Dynamic Random Access Memory) model. For example, the physical layer interface (PHY) can be a DDR PHY.

[0076] For example, the functional model can be a DRAM model configured according to the DRAM protocol requirements. Access operations (including read operations and write operations, hereinafter referred to as read and write operations) can be performed between the PHY and the functional model. For example, the link between the PHY and the functional model for read and write operations is also called a read and write link.

[0077] For example, the PHY mentioned above may be either not yet initialized and trained (TRAIN), or it may have been initialized and trained (TRAIN) and obtained an offset reference value after initialization and training. For example, the delay register in the PHY that has been initialized and trained (TRAIN) stores the offset reference value.

[0078] For example, in step S31, the expected offset is used to simulate the delay on the data line caused by temperature and voltage changes in a real chip. For example, the expected offset is used to simulate the timing offset during the access operation between the physical layer interface and the functional model.

[0079] The expected offset can be applied to the read / write link between the PHY and the functional model in the chip model. For example, the expected offset can be written to the chip model for storage and then applied to the functional model.

[0080] For example, to better test the read / write operations of the PHY and functional models in the chip model, a read / write link interface can be set up on the read / write link between the PHY and the functional model. This read / write link interface connects the PHY and the functional model, forming a read / write link of PHY—read / write link interface—functional model. For example, this read / write link interface can, on the one hand, enable the PHY and DRAM to transmit address control commands and perform read / write operations according to the timing requirements of the DRAM protocol when the chip model is in normal operating mode; on the other hand, the read / write link interface can be used to receive expected offsets on the data lines caused by temperature and voltage changes in a real chip, for example, the expected offsets can be applied to the read / write link interface.

[0081] The expected offset can be generated by software or by hardware. For example, in order to simulate the irregular timing offset of a real chip during access operations, the expected offset can be generated randomly.

[0082] In some embodiments of this disclosure, step S31 of the above chip verification method may further include step S310:

[0083] Step S310: Write the expected offset into the target register in the chip model so that it can be read by the physical layer interface for training.

[0084] For example, the target register in the chip model can be a register in the functional model used to store the current data strobe signal (e.g., DQS) and data signal (e.g., DQ) offset during operation. For example, for the DDR5 technology standard, the target register can be register MR46 and register MR47 in the DRAM model, which is used as a functional model.

[0085] For example, after the expected offset is generated, it can be regarded as the current offset generated by the actual chip in normal working mode. For example, taking the functional model as conforming to the DDR5 technical standard, the values ​​of the corresponding registers MR46 and MR47 in the functional model can be written according to the expected offset.

[0086] In some embodiments of this disclosure, step S31 of the above chip verification method may further include step S311:

[0087] In step S311, in response to the start of training on the chip model, the physical layer interface obtains the expected offset to be written into the chip model and uses it as the current offset between the physical layer interface and the functional model for training.

[0088] The training initiated on the chip model can be either the initialization (TRAIN) training or the retraining (RETRAIN) training. Retraining (RETRAIN) is the training that is initiated again during the operation process after the initialization (TRAIN) training, such as according to instructions.

[0089] For example, the memory controller or PHY in the chip model can send a desired offset fetch instruction to the functional model, allowing the PHY to obtain the desired offset written in the destination register of the functional model before or after the training start (instruction) of the chip model. The memory controller could be a DDR controller, which could send a desired offset fetch instruction to the PHY, which then sends the instruction to the functional model. In response to the training start (instruction) of the chip model, the PHY can snoop (obtain) the desired offset written in the destination register while reading the command stream associated with the desired offset fetch instruction, and save the obtained desired offset. For example, the desired offset fetch instruction could be an MRR (Mode Register Read) instruction, which is used to obtain the values ​​of registers MR46 and MR47 from the destination register of the DDR DRAM.

[0090] It should be noted that after the expected offset is written to the target register in the chip model, the expected offset obtained by the PHY from the target register according to the expected offset acquisition instruction can be a different value from the expected offset. For example, the obtained expected offset is the offset obtained by the simulated PHY by snooping (acquiring) the command stream related to the expected offset acquisition instruction, and the obtained expected offset is a value that has a corresponding calculation relationship with the expected offset according to the DDR technology standard.

[0091] Before training the chip model can be started, the training parameters required in the training environment can be configured through the configuration module. For example, the configuration module can be configured through a configuration interface, such as an apb interface, an axi interface, or other protocol interfaces. The embodiments disclosed herein do not limit this.

[0092] For example, before training of the chip model begins, the chip verification method described above may also include step S40:

[0093] Step S40: Configure the training mode of the chip model so that the chip model can be trained in the set working mode.

[0094] For example, the training modes of the chip model may include power switching mode, normal operation mode (read / write mode) or other modes, and the embodiments of this disclosure do not limit this.

[0095] For example, in power switching mode, the function to be executed after training can be determined based on the training mode encoding configured in the configuration module. For instance, taking a DDR chip model as an example, encoding 0x8 represents a RETRAIN operation, while encoding 0x18 represents a RETRAIN+RELOCK operation. During the RETRAIN operation, the DDR controller sends an SRE (Self-Refresh Enter) command to the functional model (e.g., DRAM), causing the functional model to enter a self-refresh state. At this time, control of the functional model switches from the DDR controller to the PHY. Then, the PHY sends an SRX (Self-Refresh Exit) command, causing the functional model to exit the self-refresh state and begin RETRAIN. After RETRAIN is complete, the PHY sends an SRE command to the functional model, and then switches control of the functional model back from the PHY to the DDR controller.

[0096] For example, in normal read / write mode, the PHY performs training operations in the background, and when there is an offset update instruction, the PHY will automatically update the current delay register.

[0097] For example, in step S32, during training, the PHY obtains the expected offset written to the destination register by the functional model in the chip model, thus obtaining the obtained expected offset. Then, the PHY calculates the operation offset based on the obtained expected offset using its internal logic or algorithm. For example, the PHY stores the operation offset in a delay register. After training the chip model is complete, the operation offset used for compensation based on the training can be obtained, for example, by reading the delay register in the PHY.

[0098] Operation offset is the actual timing offset during access operations between the PHY and the functional model, obtained based on the applied expected offset.

[0099] For example, in step S33, the offset adjustment capability of the physical layer interface can be determined by comparing the operational offset and the expected offset, based on the deviation between the operational offset and the expected offset. For example, the error range can be calculated by comparing the operational offset and the expected offset, and the offset error can be output, thereby evaluating the adjustment capability of the PHY in the chip model.

[0100] The above-described at least one embodiment of this disclosure dynamically generates a predicted offset by simulating the timing offset during a real access operation. This predicted offset is applied to the chip model at the start of training, and the timing of access operations between the physical layer interface and the functional model is trained based on the predicted offset. Then, at the end of training, the operation offset of the physical layer interface is obtained. Thus, the offset adjustment capability of the physical layer interface can be determined based on the operation offset and the predicted offset. This allows for the assessment of the physical layer interface's ability to adjust latency during training through front-end verification before chip silicon is achieved. This enables the resolution of problems caused by inappropriate internal logic and algorithms of the physical layer interface before chip silicon is achieved, avoiding potential defects after chip silicon and saving economic and time costs associated with tape-out.

[0101] In some embodiments of this disclosure, before training of the chip model begins, the chip verification method further includes step S41:

[0102] Step S41: Configure the operating frequency of the chip model to determine the expected offset based on the set operating frequency.

[0103] For example, the operating frequency of the chip model can be configured before training begins. The chip model may support switching between multiple different operating frequencies, such as four. The embodiments of this disclosure do not limit the number of supported operating frequencies.

[0104] After configuring the chip model's operating frequency (or switching the chip model's operating frequency), the set operating frequency is used as the current operating frequency. For example, in response to the start (signal) of training the chip model, the expected offset can be determined based on the set operating frequency.

[0105] The operating frequency can be the operation cycle of the access operation, which can be a clock cycle. For example, the processor state can be updated or basic logic operations can be performed within one clock cycle. Alternatively, the operation cycle can be a machine cycle or an instruction cycle. For example, it can be the machine cycle or instruction cycle required to execute a complete instruction. For instance, one machine cycle or instruction cycle can include multiple clock cycles.

[0106] In some embodiments of this disclosure, the functional model includes multiple memory particle models; before training of the chip model is initiated, the chip verification method further includes steps S42 and S43.

[0107] Step S42: Based on the set particle coding rules and the coding requirements of the physical layer interface, obtain the coding of each storage particle model in the functional model.

[0108] Step S43: Determine the expected offset corresponding to each storage particle model in the functional model based on the encoding of each storage particle model in the functional model and the set operating frequency.

[0109] For example, in step S42, when the functional model is a DRAM model, the multiple memory particle models included in the functional model are DRAM particle models.

[0110] For example, a chip model's particle encoding rule can be configured so that each memory particle model in the functional model is encoded according to the set particle encoding rule. For instance, the particle encoding rule could be to encode each of multiple memory particle models in the functional model (e.g., DRAM) using PDA (PerDRAM Addressability) mode according to the PHY's requirements. For example, in PDA mode, the DDR controller or PHY could individually encode each DRAM particle model by sending specific commands.

[0111] For example, in step S43, different offsets can be set for different storage particle models according to the set operating frequency and the encoding of each storage particle model.

[0112] For example, each storage granular model can be encoded (e.g., numbered) according to the encoding requirements of the physical layer interface. For example, the encoding requirements of the physical layer interface can be determined based on the actual storage modules (e.g., memory modules) on the chip.

[0113] For example, the encoding requirements of the physical layer interface can be determined based on the arrangement of the storage modules. For instance, in dual in-line memory (DIMM) modules, there are different maximum quantity limits and encoding methods for storage chips with different bit widths. For example, for storage chips with a bit width of X4, a dual in-line memory module can have a maximum of 10 storage chips, and these 10 storage chip models corresponding to the functional model can be encoded as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, or other custom numbering methods. For example, for chips with a bit width of X8, a dual in-line memory module can have a maximum of 5 storage chips, and these 5 storage chip models corresponding to the functional model can be encoded as 0, 1, 2, 3, 4, or other custom numbering methods can be used. This disclosure does not limit the specific encoding method for multiple storage chip models.

[0114] In some embodiments of this disclosure, the expected offset includes the expected offset value and the expected offset direction. The chip verification method described above determines the expected offset corresponding to each memory particle model in the functional model, including steps S44 and S45.

[0115] Step S44: Determine the predetermined offset range corresponding to the set operating frequency according to the storage standard protocol supported by the functional model.

[0116] Step S45: Determine the expected offset value and expected offset direction of each storage particle model in the functional model according to the predetermined offset range.

[0117] For example, in step S44, if the functional model supports the DRAM protocol, the predetermined offset range can be determined based on the offset range supported by the DRAM protocol at the corresponding set operating frequency. Different functional models support different memory standard protocols, and the offset range supported at the set operating frequency under the corresponding supported memory standard protocol may also differ. For example, the offset range supported at different set operating frequencies can be determined based on the Tdqs2dq parameter (characterizing the time delay between the edge of the data strobe signal (DQS) and the valid edge of the data signal (DQ)) and the Tdqs2ck parameter (characterizing the time delay between the edge of the data strobe signal (DQS) and the edge of the clock signal (CK)) supported by the DRAM protocol.

[0118] For example, in step S45, based on the predetermined offset range determined above, the expected offset value and expected offset direction can be randomly generated for each storage particle model within the predetermined offset range.

[0119] In some embodiments of this disclosure, step S45 in the above chip verification method includes steps S450 and S451.

[0120] Step S450: Obtain the offset reference value.

[0121] Step S451: In response to the start of training on the chip model, determine the expected offset value and expected offset direction of each memory particle model in the functional model based on the offset reference value and the predetermined offset range.

[0122] For example, in the retraining process, an offset baseline value can be obtained after retraining begins. For example, this offset baseline value can be the offset value (golden value) DQS2DQ_base of the baseline between the data strobe signal (DQS) and the data signal (DQ) during the initial training (TRAIN) phase.

[0123] For example, in step S451, for the retraining (RETRAIN) process, after the chip model has undergone initial training (TRAIN), the offset reference value of the PHY is obtained by reading the result of the initial training (TRAIN). For example, the expected offset value and expected offset direction of each memory particle model in the functional model can be determined randomly based on the offset reference value and within a predetermined offset range. Alternatively, the expected offset value and expected offset direction of each memory particle model in the functional model can be determined in other ways based on the offset reference value and within a predetermined offset range.

[0124] In some embodiments of this disclosure, the chip verification method described above further includes step S3101 in step S310:

[0125] Step S3101: Based on the expected offset, store the expected offset value and expected offset direction of each storage particle model in the functional model into the target register corresponding to each storage particle model.

[0126] For example, each storage granular model in the functional model has its own target register, and the expected offset value and expected offset direction of each storage granular model in the functional model can be stored in the target register corresponding to its respective storage granular model.

[0127] For example, within a predetermined offset range, the expected offset direction and expected offset value can be randomly generated for different memory particle models in the functional model. The expected offset direction and expected offset value for each memory particle model are then applied to the chip model to simulate the irregular timing offsets of each memory particle caused by differences in the arrangement and routing of different memory particles in a real chip's memory module, as well as the varying effects of temperature and voltage changes. For instance, the generated expected offset direction and offset value can be applied to the read / write link connection interface of the chip model.

[0128] It should be noted that, for different storage granularity models, the expected offset direction and expected offset size (value) can be generated in other ways besides random generation. This disclosure does not restrict the specific expected offset generation method.

[0129] By generating expected offset directions and expected offset values ​​for multiple memory particle models corresponding to multiple memory particles in the real memory module in the functional model, the simulation of the functional model is made closer to the working condition of the memory module of the real chip. This allows the real chip to be better tested and verified before silicon by using the functional model.

[0130] In some embodiments of this disclosure, the chip verification method described above further includes step S3110 or step S3111 in step S3111.

[0131] Step S3110: Obtain the expected offset value and expected offset direction stored in the target register corresponding to each storage granular model according to the physical layer interface, and then perform offset calculation based on the obtained expected offset value and expected offset direction to obtain the offset value and offset direction of the operation offset used for compensation for each storage granular model; or

[0132] Step S3111: Obtain the operation offset based on the offset reference value and the absolute value of the expected offset obtained from the physical layer interface.

[0133] For example, in step S3110, the PHY can obtain the expected offset value and expected offset direction stored in the target register of each memory granular model in the functional model. The PHY performs offset calculation based on the obtained expected offset value and expected offset direction to obtain the corresponding operation offset value and operation offset direction for each memory granular model.

[0134] It should be noted that the offset calculation is performed by the PHY based on its own internal logic or algorithm. The obtained expected offset value and expected offset direction are obtained by simulating the PHY by snooping (obtaining) the command stream related to the expected offset acquisition instruction, and are different from the expected offset value and expected offset direction.

[0135] For example, in step S3111, the obtained expected offset value can be converted into the absolute value of the expected offset value (also known as the expected offset value). Based on the calculation result of the offset reference value and the absolute value of the expected offset value obtained from the physical layer interface, the operation offset is obtained.

[0136] For example, the operation offset value and operation offset direction of each storage granular model can be stored separately in the delay register of the PHY. For example, the data of the delay register includes a delay size field and a delay direction field. For example, the operation offset value can be stored in the delay register at the delay size field, and the operation offset direction can be stored in the delay register at the delay direction field.

[0137] In some embodiments of this disclosure, step S33 of the above chip verification method further includes step S330:

[0138] Step S330: Compare the expected offset direction and the operational offset direction to determine whether the offset direction of the physical layer interface is correct; compare the expected offset value and the operational offset value to determine the offset error value of the physical layer interface.

[0139] For example, the expected offset value and expected offset direction can be obtained for each storage granule model in the functional model.

[0140] The operation offset of each storage granular model in the functional model can be obtained from the chip model. For example, the operation offset includes the operation offset value and the operation offset direction. For instance, the delay magnitude field of the operation offset value and the delay direction field of the operation offset direction stored in the PHY can be read.

[0141] It should be noted that if the values ​​read from the delay size field and the delay direction field are inconsistent with the units of the expected offset value and the expected offset direction, the units of the values ​​read from the delay size field and the delay direction field can be converted to obtain the operation offset value and operation offset direction with the units consistent with the expected offset value and the expected offset direction.

[0142] For example, for each storage granular model in the functional model, the expected offset direction and the operational offset direction of each storage granular model can be compared separately, thereby determining whether the offset direction of the PHY is correct for each storage granular model. For instance, if the expected offset direction of a certain storage granular model is the direction of increasing offset, while the operational offset direction is the direction of decreasing offset, then the offset direction of the PHY for that storage granular model is incorrect.

[0143] For example, for each storage granular model in the functional model, the expected offset value and the operation offset value of each storage granular model can be compared, thereby determining the offset error value of the physical layer interface for each storage granular model.

[0144] For example, when the offset direction of a certain storage particle model is correct, the expected offset value and the operational offset value of that storage particle model can be compared to determine the offset error. For instance, if the expected offset value is 38ps and the operational offset value is 35ps when the offset direction of a certain storage particle model is correct, then the offset error value is 38ps - 35ps = 3ps.

[0145] For example, in response to the end of training (signal) of the chip model, the offset error value of each memory particle model in the functional model can be output. Alternatively, the offset error values ​​of all memory particle models in the functional model can be output.

[0146] Although timing offsets (e.g., offset error values) during data transmission do not exceed 1 / 2 ck clock cycle, data reading and writing are generally not affected. For example, at a frequency of 3200 Mbps, an error within 156 ps (within 1 / 2 ck clock cycle), or an offset error of 1 / 4 ck, typically does not affect reading and writing. However, the method described in the above embodiments of this disclosure enables higher accuracy in detecting errors at a frequency of 3200 Mbps (within picoseconds, e.g., 5 ps), thereby allowing the chip verification method of this disclosure to accurately calculate the compensation error (offset error value) of the PHY. This achieves high-precision detection of PHY offset errors before siliconization and also allows for early evaluation of the quality of the data eye diagram of the actual chip, avoiding potential problems that may occur after siliconization.

[0147] In some embodiments of this disclosure, the chip verification method described above further includes step S331 in step S33:

[0148] Step S331: In response to an error in the offset direction of the physical layer interface, determine that there is an error in the internal logic or algorithm of the physical layer interface; in response to a correct offset direction of the physical layer interface, output the offset error value of the physical layer interface.

[0149] For example, the training process of the PHY can be monitored in real time, enabling the PHY to provide a judgment on whether the offset direction is correct and output the offset error value in real time.

[0150] In some embodiments of this disclosure, the chip verification method described above includes step S312 during the training of the chip model:

[0151] Step S312: In response to the chip model being in retraining state or normal operation mode, an offset update instruction is sent to the physical layer interface to update the operation offset obtained from training for compensation into the offset register of the physical layer interface.

[0152] In normal operating mode, an offset update instruction can be sent to update the operation offset to the PHY's delay register.

[0153] In some embodiments of this disclosure, the chip verification method further includes step S46 before starting the training of the chip model:

[0154] Step S46: Configure the precision mode of the chip model to configure the training step size.

[0155] The precision mode of the chip model can be configured before training begins. For example, the configured training step size can be 1 / 128ck (clock cycle), 1 / 64ck (clock cycle), or 40 / 128ck (clock cycle), etc. The embodiments of this disclosure do not limit the size of the training step size. For example, training (including initial training and retraining) can be performed according to the training step size, which affects the training speed and the accuracy of the adjustment.

[0156] Figure 6 A flowchart illustrating an example of a chip verification method provided in at least one embodiment of this disclosure is shown below. Figure 6 The illustrated process is used as an example to describe some embodiments of this disclosure.

[0157] like Figure 6 As shown, the process of retraining (RETRAIN) a write operation is used as an example for illustration.

[0158] First, obtain the offset baseline value.

[0159] This offset reference value can be the offset (golden value) DQS2DQ_base of the data strobe signal (DQS) and data signal (DQ) during the initialization training (TRAIN) phase. This value can be used as the offset reference value for each retraining (RETRAIN) after the initialization training (TRAIN). For example, the offset reference value (e.g., DQS2DQ_base) can be recorded in a corresponding register of the PHY.

[0160] Afterwards, the chip model's PHY is put into normal working mode to perform normal access operations (such as read or write operations) with the functional model to carry out normal data read and write transmission. During this process, errors may occur in the access operation due to changes in voltage and temperature, such as incorrect read or write data.

[0161] Then, send the retraining start command.

[0162] When an error occurs during an access operation, and the read / write link of the read / write operation has already experienced a timing offset, a retraining start command can be sent. For example, the retraining start command can also be issued at any time or periodically before the timing offset occurs to calibrate the read / write link of the read / write operation. For example, it can be sent periodically by the DDR controller or PHY. For example, write link calibration can be performed for write operations. For example, the retraining start command sent could be an MPC_DQS_START command.

[0163] Then, a random expected offset value and a random expected offset direction are generated. The randomly generated expected offset value and expected offset direction are applied to the read / write link connection interface, also known as the connection interface (in the chip model).

[0164] For the retraining process, after the chip model has undergone initial training (TRAIN), the offset baseline value of the PHY is obtained based on the results of the initial training (TRAIN). For example, based on the offset baseline value obtained from the initial training (TRAIN), the expected offset value and expected offset direction of each memory particle model in the functional model can be determined within a predetermined offset range. For example, the expected offset value can be obtained by increasing or decreasing the offset baseline value.

[0165] After sending the retraining start command, the expected offset is written to the destination register in the functional model; then the PHY reads the destination register in the functional model to obtain the acquired expected offset.

[0166] Then, PHY performs calculations based on the obtained expected offset.

[0167] For example, after the PHY obtains the expected offset, it can convert the expected offset into the absolute value of the offset of the current data strobe signal (DQS) and data signal (DQ) (DQS2DQ_now). The absolute value of the expected offset (DQS2DQ_now) and the offset base value (DQS2DQ_base) are then used to calculate the value of the offset that needs to be compensated between the data strobe signal (DQS) and data signal (DQ) (DQS2DQ_delay), which is then used as the operation offset.

[0168] Then, the operation offset is updated to the PHY's delay register.

[0169] In normal operating mode, an offset update instruction can be sent to update the operation offset to the PHY's delay register.

[0170] Then, the expected offset and the operational offset are compared to determine whether they are the same, thereby determining the offset adjustment capability of the physical layer interface.

[0171] The method for comparing the expected offset and the operational offset is the same as that described in the chip verification method above in this disclosure, and therefore will not be repeated here.

[0172] Figure 7 A block diagram of a chip verification apparatus provided in at least one embodiment of the present disclosure is shown.

[0173] At least one embodiment of this disclosure also provides a chip verification apparatus for verifying chip models, such as... Figure 7 As shown, the corresponding chip model 810 includes a physical layer interface and a functional model, as described above; the chip verification device 700 includes an expected offset module 710 and an inspection module 720.

[0174] The expected offset module 710 is configured to write the expected offset, which is used to simulate the timing offset during the access operation between the physical layer interface and the functional model, into the chip model 810, so that the physical layer interface can train the timing of the access operation between the physical layer interface and the functional model based on the expected offset.

[0175] The inspection module 720 is configured to, in response to the end of training of the chip model 810, acquire the operation offset of the physical layer interface based on the training obtained for compensation; and determine the offset adjustment capability of the physical layer interface based on the operation offset and the expected offset.

[0176] In some embodiments of this disclosure, the chip verification apparatus 700 further includes a configuration module 730.

[0177] The configuration module 730 is configured to perform one or more of the following configurations: configure the training mode of the chip model 810 so that the chip model 810 is trained in a set operating mode; configure the operating frequency of the chip model 810 to determine the expected offset according to the set operating frequency; configure the precision mode of the chip model 810 to configure the training step size; and / or configure the granular encoding rules of the chip model 810 so that each storage granular model in the functional model is encoded according to the set granular encoding rules.

[0178] For example, the expected offset module 710 is also configured to write the expected offset into a target register in the chip model for reading by the physical layer interface for training.

[0179] For example, the expected offset module 710 is also configured to, in response to the start of training of the chip model, cause the physical layer interface to acquire the expected offset written into the chip model and use it as the current offset between the physical layer interface and the functional model for training.

[0180] For example, the functional model includes multiple memory particle models; the expected offset module 710 is also configured to obtain the encoding of each memory particle model in the functional model according to the set particle encoding rules and the encoding requirements of the physical layer interface before training of the chip model is started; and to determine the expected offset corresponding to each memory particle model in the functional model according to the encoding of each memory particle model in the functional model and the set operating frequency.

[0181] For example, the expected offset includes the expected offset value and the expected offset direction. The expected offset module 710 is also configured to determine the predetermined offset range corresponding to the set operating frequency according to the storage standard protocol supported by the functional model; and to determine the expected offset value and expected offset direction of each storage particle model in the functional model according to the predetermined offset range.

[0182] For example, the expected offset module 710 is also configured to acquire an offset reference value; in response to the start of training of the chip model, to determine the expected offset value and expected offset direction of each memory particle model in the functional model based on the offset reference value and a predetermined offset range.

[0183] For example, the inspection module 720 is also configured to obtain the operation offset based on the offset reference value and the absolute value of the expected offset obtained from the physical layer interface.

[0184] For example, the expected offset module 710 is also configured to store the expected offset value and expected offset direction of each storage particle model in the functional model into the target register corresponding to each storage particle model, based on the expected offset.

[0185] For example, the inspection module 720 is also configured to obtain the expected offset value and expected offset direction stored in the target register corresponding to each storage granular model according to the physical layer interface, so that the physical layer interface performs offset calculation based on the obtained expected offset value and expected offset direction to obtain the offset value and offset direction of the operation offset used for compensation for each storage granular model.

[0186] For example, the inspection module 720 is also configured to compare the expected offset direction with the operational offset direction to determine whether the offset direction of the physical layer interface is correct; and to compare the expected offset value with the operational offset value to determine the offset error value of the physical layer interface.

[0187] For example, the inspection module 720 is also configured to determine that the internal logic or algorithm of the physical layer interface is faulty in response to an offset direction error of the physical layer interface; and to output the offset error value of the physical layer interface in response to a correct offset direction of the physical layer interface.

[0188] For example, the inspection module 720 is also configured to send an offset update instruction to the physical layer interface in response to the chip model being in a retraining state or normal operating mode, updating the offset register of the physical layer interface based on the operation offset obtained from training for compensation.

[0189] For example, in the example above, the chip model used to simulate the chip is a DDR chip, and the functional model is a DRAM model.

[0190] Figure 8A schematic diagram illustrating an example of a chip verification apparatus provided in at least one embodiment of the present disclosure is shown.

[0191] like Figure 8 As shown, the chip verification device 700 may include an expected offset module 710, an inspection module 720, and a configuration module 730. The chip verification device 700 is applied to the corresponding chip model 810 for verification or testing.

[0192] Chip model 810 includes a physical layer interface (PHY), a functional model, and a read / write link connection interface (hereinafter also referred to as the connection interface) between the two. For example, the write link in chip model 810 is physical layer interface (PHY) -> connection interface -> functional model, and the read link in chip model 810 is functional model -> connection interface -> physical layer interface (PHY).

[0193] For example, the expected offset module 710 includes a particle number (the number of each stored particle model in the functional model), an offset direction (expected offset direction), and an offset value (expected offset value).

[0194] For example, the particle numbers of multiple memory particle models are DRAM(0) ~ DRAM(n), where n is a positive integer. Different expected offset directions and expected offset values ​​can be randomly generated for each memory particle model. For example, in the offset direction, +++ can represent the expected offset direction of increasing offset, and --- can represent the expected offset direction of decreasing offset. For example, the expected offset values ​​corresponding to the multiple memory particle models DRAM(0) ~ DRAM(n) are Delay 0 ~ Delay n, where n is a positive integer.

[0195] The inspection module 720 includes functions for acquiring the operation offset, comparing the offset direction, and calculating the offset error.

[0196] For example, the inspection module 720 can obtain the operation offset of each memory chip model in the functional model from the chip model 810. For example, multiple memory chip models DRAM(0) ~ DRAM(n) correspond to operation offsets 0 ~ operation offset n, respectively. The operation offset includes the operation offset value and the operation offset direction. The expected offset direction and the operation offset direction are compared to determine whether the offset direction of the physical layer interface is correct; the expected offset value and the operation offset value are compared to calculate the offset error value of the physical layer interface.

[0197] The configuration module 730 may include one or more of the following four modules: particle encoding, clock frequency, training mode, and precision mode.

[0198] For example, regarding the training mode, after configuring the training mode of the chip model 810, the configuration module 730 can monitor the start and end of training by monitoring flags in the PHY training process through real-time training monitoring. For instance, real-time training monitoring can be implemented by a real-time training monitoring module. For example, training start can be monitored by recognizing a training start flag, and upon detection, the training start flag is sent to the expected offset module 710. Similarly, training end can be monitored by recognizing a training end flag, and upon detection, the training end flag is sent to the inspection module 720.

[0199] For example, for the precision mode, the configuration module 730 can configure the precision mode of the chip model 810 before training of the chip model 810 is started.

[0200] For example, regarding particle encoding, the configuration module 730 can configure the particle encoding rules of the chip model 810 so that each memory particle model in the functional model is encoded according to the set particle encoding rules. For example, the particle encoding rules can be based on the PHY requirements and use PDA (Per DRAM Addressability) mode to encode each of the multiple memory particle models in the functional model (e.g., DRAM). For example, the configuration module 730 can send the particle encoding rules to the expected offset module 710. For example, in PDA mode, the DDR controller or PHY can send specific commands to encode each DRAM particle model individually. This disclosure does not limit the specific encoding method for multiple memory particle models.

[0201] For example, regarding the clock frequency, the operating frequency of the chip model 810 can be configured via the configuration module 730 before training begins. The configuration module 730, for example, supports switching between multiple different operating frequencies, such as four operating frequencies. The embodiments of this disclosure do not limit the number of supported operating frequencies.

[0202] For example, after configuring the operating frequency of the chip model 810 or after switching the operating frequency, the set operating frequency is used as the current operating frequency. For example, in response to the training start (signal) of the chip model 810, the configuration module 730 transmits the set operating frequency to the expected offset module 710.

[0203] The functional model includes multiple memory particle models; the expected offset module 710 is also configured to obtain the encoding of each memory particle model in the functional model according to the set particle encoding rules and the encoding requirements of the physical layer interface before training of the chip model 810 starts; and to determine the expected offset corresponding to each memory particle model in the functional model according to the encoding of each memory particle model in the functional model and the set operating frequency.

[0204] For example, the expected offset module 710 can set different offsets for different memory particle models based on the set operating frequency and the encoding of each memory particle model.

[0205] For example, after receiving the particle encoding rules sent by the configuration module 730, the expected offset module 710 can encode (e.g., number) each storage particle model according to the encoding requirements of the physical layer interface. For example, the encoding requirements of the physical layer interface can be determined based on the arrangement of storage modules (e.g., memory modules) on the actual chip.

[0206] For example, the expected offset includes the expected offset value and the expected offset direction. The expected offset module 710 is also configured to determine the predetermined offset range corresponding to the set operating frequency according to the storage standard protocol supported by the functional model; and to determine the expected offset value and expected offset direction of each storage particle model in the functional model according to the predetermined offset range.

[0207] For example, the expected offset module 710 is also configured to acquire an offset reference value; in response to the start of training on the chip model 810, the expected offset value and expected offset direction of each memory particle model in the functional model are determined based on the offset reference value and a predetermined offset range.

[0208] For example, the expected offset module 710 is also configured to store the expected offset value and expected offset direction of each storage particle model in the functional model into the target register corresponding to each storage particle model, based on the expected offset.

[0209] For example, each storage granular model in the functional model has its own target register, and the expected offset value and expected offset direction of each storage granular model in the functional model can be stored in the target register corresponding to its respective storage granular model.

[0210] For example, the expected offset module 710 can randomly generate corresponding expected offset directions and expected offset values ​​for different memory particle models in the functional model within a predetermined offset range. The expected offset direction and expected offset value corresponding to each memory particle model are then applied to the chip model 810 to simulate the irregular timing offsets of each memory particle caused by differences in the arrangement and routing of different memory particles in a real chip's memory module, as well as the varying effects of temperature and voltage changes.

[0211] For example, the expected offset direction and expected offset value generated by the expected offset module 710 can be applied to the connection interface of the chip model 810.

[0212] It should be noted that, Figure 8The offset direction and offset size shown are merely examples, and this disclosure does not limit the expected offset direction and expected offset size for different storage granularity models. In addition to random generation, other methods can also be used to generate the expected offset direction and expected offset size, and this disclosure does not limit the specific expected offset generation method.

[0213] For example, the inspection module 720 enables the PHY to obtain the expected offset value and expected offset direction stored in the target register of each memory granular model in the functional model. The PHY performs offset calculations based on the obtained expected offset value and expected offset direction to obtain the corresponding operation offset value and operation offset direction for each memory granular model.

[0214] It should be noted that the offset calculation is performed by the PHY based on its own internal logic or algorithm. The obtained expected offset value and expected offset direction are obtained by simulating the PHY by snooping (obtaining) the command stream related to the expected offset acquisition instruction, and are different from the expected offset value and expected offset direction.

[0215] For example, the operation offset value and operation offset direction of each storage granular model can be stored separately in the delay register of the PHY. For example, the data of the delay register includes a delay size field and a delay direction field; for example, the operation offset value can be stored in the storage delay size field of the delay register, and the operation offset direction can be stored in the storage delay direction field of the delay register.

[0216] For example, the inspection module 720 can obtain the expected offset value and expected offset direction corresponding to each storage particle model in the functional model from the expected offset module 710.

[0217] For example, the inspection module 720 can read the delay size field and the delay direction field of the operation offset value of each storage granular model stored in the delay register of the PHY.

[0218] For example, the inspection module 720 can compare the expected offset direction and the operational offset direction of each storage particle model in the functional model, thereby determining whether the offset direction of the PHY is correct for each storage particle model. For example, if the expected offset direction of a certain storage particle model is the direction of increasing offset, while the operational offset direction is the direction of decreasing offset, then the offset direction of the PHY of that storage particle model is incorrect.

[0219] For example, the inspection module 720 can compare the expected offset value and the operation offset value of each storage particle model in the functional model, thereby determining the offset error value of the physical layer interface for each storage particle model.

[0220] For example, the checking module 720 can compare the expected offset value and the operational offset value of a storage particle model when the offset direction of the storage particle model is correct, and determine the offset error.

[0221] For example, the inspection module 720 can output the offset error value of each memory particle model in the functional model in response to the end of training (signal) of the chip model 810. For example, the offset error values ​​of all memory particle models in the functional model can be output.

[0222] For example, the inspection module 720 is also configured to determine that the internal logic or algorithm of the physical layer interface is faulty in response to an offset direction error of the physical layer interface; and to output the offset error value of the physical layer interface in response to a correct offset direction of the physical layer interface.

[0223] For example, the inspection module 720 is also configured to send an offset update instruction to the physical layer interface in response to the chip model 810 being in a retraining state or normal operation mode, updating the offset register of the physical layer interface based on the operation offset obtained from training for compensation.

[0224] For example, in the example above, the chip simulated by the chip model is a DDR chip, and the functional model is a DRAM model.

[0225] For example, the inspection module 720 can monitor the training process of the PHY in real time, enabling the PHY to provide a judgment on whether the offset direction is correct and output the offset error value in real time.

[0226] The chip model 810 corresponding to the chip verification device 700 in this embodiment, as well as the expected offset module 710, the inspection module 720 and the configuration module 730 in the chip verification device 700, are the same as those described in the embodiments of the chip verification method of this disclosure, and therefore will not be repeated.

[0227] The technical effects of the chip verification apparatus of the above embodiments of this disclosure are the same as those of the chip verification method described above, and therefore will not be repeated.

[0228] Figure 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0229] At least one embodiment of this disclosure also provides an electronic device, such as Figure 9 As shown, the electronic device 600 includes at least one memory 610 and at least one processor 620.

[0230] The aforementioned memory 610 is configured to store computer-executable instructions.

[0231] The processor 620 described above is configured to execute computer-executable instructions, which, when executed by at least one processor, implement the chip verification method provided in any embodiment of this disclosure.

[0232] For example, memory 610 can be any memory capable of storing computer-executable instructions. For example, memory can be dynamic random access memory (DRAM), random access memory (RAM), or static random access memory (SRAM), etc. Memory can be cache or memory, etc., and this disclosure does not impose any restrictions.

[0233] For example, processor 620 can be any processor capable of executing computer-executable instructions, such as a central processing unit (CPU), a microcontroller unit (MCU), or a digital signal processor (DSP), etc., without limitation in this disclosure.

[0234] The technical effects of the electronic device in the above embodiments of this disclosure are the same as those of the chip verification method described above, and therefore will not be repeated.

[0235] Figure 10 This is a block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0236] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 10 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0237] For example, refer to Figure 10In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. For example, processing device 1001 may be at least one processor in any embodiment of this disclosure. Various programs and data required for the operation of the computer system are also stored in RAM 1003. For example, RAM 1003 may be at least one memory in any embodiment of this disclosure. Processing device 1001, ROM 1002, and RAM 1003 are connected via interconnection network 1004. Input / output (I / O) interface 1005 is also connected to interconnection network 1004.

[0238] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 10 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0239] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0240] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of operating device and hardware of chip verification device. The embodiments disclosed herein do not limit this.

[0241] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the chip verification method provided in at least one embodiment of this disclosure is implemented.

[0242] Figure 11 This is a schematic diagram of a non-transitory storage medium provided in some embodiments of this disclosure. For example... Figure 11 As shown, the non-temporary storage medium 900 can non-temporarily store computer-executable instructions 910, which, when executed by a computer, implement the chip verification method provided in any embodiment of this disclosure.

[0243] The following points need to be clarified regarding this disclosure:

[0244] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0245] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0246] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip verification method, comprising: Obtain the chip model of the chip, wherein the chip model includes a physical layer interface and a functional model; The expected offset for simulating the timing offset during the access operation between the physical layer interface and the functional model is written into the chip model, so that the physical layer interface is trained on the timing of the access operation between the physical layer interface and the functional model based on the expected offset, wherein the expected offset includes the expected offset value and the expected offset direction. In response to the completion of training of the chip model, the operation offset for compensation obtained by the physical layer interface based on the training is obtained, wherein the operation offset includes an operation offset value and an operation offset direction; The offset adjustment capability of the physical layer interface is determined based on the operational offset and the expected offset. The step of determining the offset adjustment capability of the physical layer interface based on the operational offset and the expected offset includes: Compare the expected offset direction with the operational offset direction to determine whether the offset direction of the physical layer interface is correct; The offset error value of the physical layer interface is determined by comparing the expected offset value with the operational offset value.

2. The chip verification method as described in claim 1, wherein, The step of writing the expected offset, used to simulate the timing offset during the access operation between the physical layer interface and the functional model, into the chip model includes: The expected offset is written into the target register in the chip model so that it can be read by the physical layer interface for training.

3. The chip verification method as described in claim 1 or 2, wherein, The step of training the timing of access operations between the physical layer interface and the functional model based on the expected offset includes: In response to the initiation of training on the chip model, the physical layer interface acquires the expected offset written into the chip model and uses it as the current offset between the physical layer interface and the functional model for the training.

4. The chip verification method as described in claim 3, wherein, Before training of the chip model begins, the chip verification method further includes: Configure the training mode of the chip model so that the chip model can be trained in the set working mode.

5. The chip verification method as described in claim 3, wherein, Before training of the chip model begins, the chip verification method includes: Configure the operating frequency of the chip model to determine the expected offset based on the set operating frequency.

6. The chip verification method as described in claim 5, wherein, The functional model includes multiple memory particle models; before training of the chip model begins, the chip verification method further includes: Based on the set particle coding rules and the coding requirements of the physical layer interface, obtain the coding of each storage particle model in the functional model; Based on the encoding of each storage particle model in the functional model and the set operating frequency, the expected offset corresponding to each storage particle model in the functional model is determined.

7. The chip verification method as described in claim 6, wherein, Determining the expected offset corresponding to each storage granular model in the functional model includes: Based on the storage standard protocol supported by the functional model, determine the predetermined offset range corresponding to the set operating frequency; The expected offset value and the expected offset direction of each storage particle model in the functional model are determined based on the predetermined offset range.

8. The chip verification method as described in claim 7, wherein, Determining the expected offset value and the expected offset direction of each storage particle model in the functional model according to the predetermined offset range includes: Obtain the offset reference value; In response to the initiation of training on the chip model, the expected offset value and the expected offset direction of each memory particle model in the functional model are determined based on the offset reference value and the predetermined offset range.

9. The chip verification method as described in claim 8, wherein, The step of enabling the physical layer interface to obtain the expected offset written into the chip model, and using it as the current offset between the physical layer interface and the functional model for training, includes: The operational offset is obtained based on the absolute value of the offset reference value and the expected offset value obtained from the physical layer interface.

10. The chip verification method of claim 7, wherein writing the expected offset into the target register in the chip model comprises: Based on the expected offset, the expected offset value and the expected offset direction of each storage particle model in the functional model are stored in the target register corresponding to each storage particle model.

11. The chip verification method of claim 10, wherein the step of enabling the physical layer interface to obtain the expected offset written into the chip model and using it as the current offset between the physical layer interface and the functional model for training further comprises: According to the physical layer interface, the expected offset value and the expected offset direction stored in the target register corresponding to each storage particle model are obtained respectively. The physical layer interface performs offset calculation based on the obtained expected offset value and the obtained expected offset direction to obtain the offset value and the offset direction of the operation offset used for compensation for each storage particle model.

12. The chip verification method as described in claim 1, wherein determining the offset adjustment capability of the physical layer interface based on the operational offset and the expected offset further includes: In response to an error in the offset direction of the physical layer interface, it is determined that the internal logic or algorithm of the physical layer interface is faulty; In response to the correct offset direction of the physical layer interface, the offset error value of the physical layer interface is output.

13. The chip verification method as described in claim 1, wherein, The training of the chip model includes: In response to the chip model being in a retraining state or normal operating mode, an offset update instruction is sent to the physical layer interface to update the operation offset obtained from the training to the offset register of the physical layer interface.

14. The chip verification method as described in claim 1, wherein, The chip is a DDR chip, and the functional model is a DRAM model.

15. The chip verification method as described in claim 1, wherein, Before training of the chip model begins, the chip verification method further includes: Configure the precision mode of the chip model to configure the training step size of the training.

16. A chip verification device, wherein, The chip model corresponding to the chip includes a physical layer interface and a functional model, wherein the chip verification device includes: The expected offset module is configured to write the expected offset, which is used to simulate the timing offset during the access operation between the physical layer interface and the functional model, into the chip model, so that the physical layer interface is trained on the timing of the access operation between the physical layer interface and the functional model based on the expected offset, wherein the expected offset includes an expected offset value and an expected offset direction. The inspection module is configured to, in response to the end of training of the chip model, obtain the operation offset of the physical layer interface obtained based on the training for compensation; and determine the offset adjustment capability of the physical layer interface based on the operation offset and the expected offset, wherein the operation offset includes an operation offset value and an operation offset direction. The inspection module is further configured to compare the expected offset direction with the operation offset direction to determine whether the offset direction of the physical layer interface is correct. The offset error value of the physical layer interface is determined by comparing the expected offset value with the operational offset value.

17. The chip verification apparatus of claim 16, further comprising: The configuration module is configured to perform one or more of the following configurations: Configure the training mode of the chip model so that the chip model can be trained in the set working mode; Configure the operating frequency of the chip model to determine the expected offset based on the set operating frequency; Configure the precision mode of the chip model to configure the training step size of the training; Configure the particle encoding rules of the chip model so that each storage particle model in the functional model is encoded according to the set particle encoding rules.

18. An electronic device comprising: At least one memory is configured to store computer-executable instructions; as well as At least one processor is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the at least one processor, they implement the chip verification method according to any one of claims 1-15.

19. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the chip verification method according to any one of claims 1-15 is implemented.

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