Semiconductor device

Abstract

A semiconductor device includes: a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit connected to the first semiconductor die through a plurality of via structures, where the first interface circuit is configured to generate an error detection code for transmission data, and transmit a data signal including the transmission data and an error detection code to the second interface circuit through at least some of the plurality of via structures, and the second interface circuit is configured to generate response data indicating whether the data signal is normally received and an error correction code of the response data, and transmitting a response signal including the response data and the error correction code to the first interface circuit through at least one via structure of the plurality of via structures.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2023 - 0190870, filed with the Korean Intellectual Property Office on December 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] One or more example embodiments of the present disclosure relate to semiconductor devices.

[0004] Semiconductor devices may include various circuits to perform operations. To improve the performance of semiconductor devices and reduce power consumption, three - dimensional (3D) semiconductor devices have been proposed, in which circuits are distributed on multiple semiconductor dies and the multiple semiconductor dies are stacked. In a 3D semiconductor device, at least some of the circuits included in different semiconductor dies may be connected to each other through a via structure to exchange data signals, clock signals, etc. Therefore, to improve the reliability and integration of 3D semiconductor devices, it is necessary to increase the data transfer rate through the via structure and appropriately limit the number of via structures. Summary of the Invention

[0005] One or more example embodiments of the present disclosure provide a semiconductor device having improved communication reliability between semiconductor dies connected and stacked with each other through a via structure.

[0006] According to an aspect of an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit configured to output a data signal and transmit a clock signal, wherein the first interface circuit includes a CRC encoder configured to generate cyclic redundancy check (CRC) data of transmission data included in the data signal and a buffer memory configured to store the transmission data; a second semiconductor die including a second interface circuit configured to receive the data signal and the clock signal, wherein the second interface circuit includes a CRC decoder configured to decode the CRC data included in the data signal, a response controller configured to generate response data indicating completion of transmission of the transmission data or a request for re - transmission of the transmission data based on the CRC data, and an ECC encoder configured to generate error - correction code (ECC) data of the response data; and a plurality of via structures connecting the first interface circuit to the second interface circuit, wherein the first interface circuit further includes an ECC decoder configured to recover the response data by decoding the ECC data of the response data and, based on the response data, re - transmit the transmission data stored in the buffer memory or transmit new transmission data.

[0007] According to one aspect of an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit, the second interface circuit being connected to the first semiconductor die through a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmitted data and send a data signal including the transmitted data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and wherein the second interface circuit is configured to generate response data indicating whether the data signal is received normally and an error correction code for the response data, and send a response signal including the response data and the error correction code to the first interface circuit through at least one of the plurality of via structures.

[0008] According to one aspect of an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor die including a first interface circuit; and a second semiconductor die including a second interface circuit connected to the first interface circuit through a plurality of via structures, the second semiconductor die being stacked with the first semiconductor die, wherein the first interface circuit includes a plurality of data transmission circuits connected to data via structures among the plurality of via structures and a first-in first-out (FIFO) circuit commonly connected to the plurality of data transmission circuits, and wherein each of the plurality of data transmission circuits includes a latch and at least one flip-flop, each of the latch and the at least one flip-flop being configured to receive transmitted data output from the FIFO circuit, and a multiplexer connected between the latch and the at least one flip-flop and a corresponding data via structure in the data via structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain example embodiments of the present disclosure will be more clearly understood from the following detailed description, in which:

[0010] Figure 1 is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure;

[0011] Figure 2 and Figure 3 is a diagram schematically showing a semiconductor die included in a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 4 is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure;

[0013] Figure 5 is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure;

[0014] Figure 6 andFigure 7 FIG. is a diagram schematically showing a semiconductor die included in a semiconductor device according to an example embodiment of the present disclosure;

[0015] Figure 8 FIG. is a diagram showing operations of a semiconductor device according to one or more example embodiments of the present disclosure;

[0016] Figures 9 to 11 FIG. is a diagram showing operations of a semiconductor device according to one or more example embodiments of the present disclosure;

[0017] Figure 12 FIG. is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure;

[0018] Figure 13 FIG. is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure;

[0019] Figure 14 FIG. shows Figure 13 operations of the interface circuit shown;

[0020] Figure 15 FIG. is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure;

[0021] Figure 16 FIG. is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure;

[0022] Figure 17 and Figure 18 FIG. shows Figure 16 operations of the interface circuit shown; and

[0023] Figure 19 and Figure 20 FIG. is a diagram showing operations of a semiconductor device according to one or more example embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0025] Figure 1 FIG. is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure.

[0026] Reference Figure 1, a semiconductor device 10 according to one or more example embodiments of the present disclosure may include a first semiconductor die SD1 and a second semiconductor die SD2 stacked on each other. However, according to one or more example embodiments, the number of semiconductor dies included in the semiconductor device 10 and stacked on each other may be three or more.

[0027] The first semiconductor die SD1 and the second semiconductor die SD2 may respectively include a front end of line (FEOL) region 20 and 22 and a back end of line (BEOL) region 21 and 23, etc. The FEOL regions 20 and 22 may include a semiconductor substrate and elements disposed on the semiconductor substrate. The device may include an active region formed by implanting impurities into the semiconductor substrate, a gate structure disposed on the upper surface of the semiconductor substrate or partially embedded in the semiconductor substrate, and contacts connected to the active region and the gate structure.

[0028] The BEOL regions 21 and 23 may include a plurality of interconnect patterns and a plurality of vias connected to the devices disposed in the FEOL regions 20 and 22. Circuits providing various functions may be implemented by connecting the elements included in the FEOL regions 20 and 22 to each other using the plurality of interconnect patterns and the plurality of vias included in the BEOL regions 21 and 23. The plurality of interconnect patterns and the plurality of vias may be disposed in an interlayer dielectric layer including an insulating material.

[0029] Reference Figure 1 , the first semiconductor die SD1 and the second semiconductor die SD2 may be connected to each other through a plurality of through-silicon via (TSV) structures. For example, each of the plurality of TSV structures may be formed as a through-silicon via that penetrates the semiconductor substrate included in at least one of the FEOL regions 20 and 22. Each of the plurality of TSV structures may provide a data signal transmission path, a clock signal transmission path, etc. between the first semiconductor die SD1 and the second semiconductor die SD2.

[0030] In an embodiment, the first semiconductor die SD1 and the second semiconductor die SD2 can be implemented as chips that perform different functions. For example, the first semiconductor die SD1 can be a processor chip capable of performing various operations, and the second semiconductor die SD2 can be a memory chip capable of storing data transmitted from the first semiconductor die SD1 and / or reading the stored data in response to a command from the first semiconductor die SD1 and providing the read data to the first semiconductor die SD1. In this way, a single system can be implemented with a semiconductor device 10 that stacks multiple semiconductor dies SD1 and SD2 implemented as chips capable of performing different functions and connects the multiple semiconductor dies SD1 and SD2 to multiple through-silicon via (TSV) structures.

[0031] To exchange data signals and clock signals between the first semiconductor die SD1 and the second semiconductor die SD2 through the multiple through-silicon via (TSV) structures, each of the first semiconductor die SD1 and the second semiconductor die SD2 can include an interface circuit. The interface circuit can include a transmission circuit and a reception circuit, and in an embodiment, each of the transmission circuit and the reception circuit can be implemented as a digital circuit rather than an analog circuit. By implementing the transmission circuit and the reception circuit only with digital circuits (such as flip-flops, latches, and first-in-first-out (FIFO) circuits) instead of analog circuits, the power consumption of the semiconductor device 10 can be reduced.

[0032] Figure 2 and Figure 3 is a diagram schematically showing semiconductor dies included in a semiconductor device according to an exemplary embodiment of the present disclosure.

[0033] Referring Figure 2 , the semiconductor die 30 can include a through-silicon via region 31, an interface circuit 32, a core circuit 33, etc. Multiple through-silicon via (TSV) structures can be provided in the through-silicon via region 31, and the interface circuit 32 can be provided adjacent to the through-silicon via region 31. A transmission circuit, a reception circuit, etc. configured to output and / or receive data signals and clock signals through the multiple through-silicon via (TSV) structures can be provided in the interface circuit 32.

[0034] As Figure 2 shown, the interface circuit 32 can be provided between the core circuit 33 and the through-silicon via region 31. In this way, the interface circuit 32 in which the transmission circuit and / or the reception circuit is provided can be adjacent to (e.g., as close as possible to) the multiple through-silicon via (TSV) structures, and signal distortion and power consumption can be reduced.

[0035] Various circuits for performing the functions of the semiconductor die 30 may be provided in the core circuit 33. For example, when the semiconductor die 30 is a memory chip, a bank or memory block in which a plurality of memory cells are provided, and / or a decoder circuit, a page buffer, a sense amplifier, etc. for performing control operations such as programming, reading, and / or erasing on at least some of the plurality of memory cells may be provided in the core circuit 33.

[0036] Reference Figure 3 , the semiconductor die 40 may include a via region 41, an interface circuit 42, a core circuit 43, etc. In Figure 3 the illustrated embodiment, the interface circuit 42 may be provided around the via region 41 in which a plurality of through-silicon via (TSV) structures are provided, and the core circuit 43 may be provided near the interface circuit 42. As referred to above Figure 2 and Figure 3 stated, the arrangements of the via regions 31 and 41, the interface circuits 32 and 42, and the core circuits 33 and 43 in the semiconductor dies 30 and 40 may vary according to embodiments.

[0037] Figure 4 is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure.

[0038] According to Figure 4 the illustrated embodiment, the semiconductor device 50 may include a first semiconductor die 60 and a plurality of second semiconductor dies 71 to 74 (collectively referred to as 70) stacked on top of each other. In an embodiment, the plurality of second semiconductor dies 70 may each be implemented as a memory chip capable of storing data, and the first semiconductor die 60 may be implemented as a processor chip including a memory controller capable of controlling the memory chips. According to an embodiment, some of the plurality of second semiconductor dies 70 may be implemented as different types of memory chips, or at least one of the second semiconductor dies 70 may be implemented as a processor chip.

[0039] The first semiconductor die 60 may be an application processor including a memory controller, a central processing unit, etc., and may be communicatively connected to other devices. The first semiconductor die 60 may generate command signals, address signals, clock signals, and data signals related to the operation of each of the second semiconductor dies 70, and transmit the generated signals to at least one of the plurality of second semiconductor dies 70 through a plurality of through-silicon via structures 75. For example, each of the plurality of through-silicon via structures 75 may be a through-silicon via penetrating a semiconductor substrate.

[0040] In an embodiment, each of the plurality of second semiconductor dies 70 may include a plurality of banks in which a plurality of memory cells are arranged, and the plurality of banks may be divided into a plurality of channels. InFigure 4 In the illustrated embodiment, each of the second semiconductor dies 70 may include two channels. For example, the second semiconductor die 71 may include a first channel CH1 and a third channel CH3, the second semiconductor die 72 may include a second channel CH2 and a fourth channel CH4, the second semiconductor die 73 may include a fifth channel CH5 and a seventh channel CH7, and the second semiconductor die 74 may include a sixth channel CH6 and an eighth channel CH8. However, this is only an example, and the functions and configurations of the second semiconductor dies 70 may vary according to the embodiments.

[0041] A plurality of via structures 75 may be arranged corresponding to the plurality of channels CH1 to CH8. The plurality of via structures 75 may penetrate the plurality of second semiconductor dies 70, and each of the plurality of second semiconductor dies 70 may include an interface circuit connected to the plurality of via structures 75.

[0042] Referring Figure 4 , the first semiconductor die 60 may include a via region 61 in which a plurality of via structures 75 are provided, an interface circuit 62 provided adjacent to the via region 61, etc. The core circuit for implementing the functions of the first semiconductor die 60 may be provided in most regions other than the interface circuit 62.

[0043] Figure 5 is a simplified block diagram of a semiconductor device according to one or more example embodiments of the present disclosure.

[0044] Referring Figure 5 , a semiconductor device 100 according to one or more example embodiments of the present disclosure may include a first semiconductor die 110 and a second semiconductor die 120, and the first semiconductor die 110 and the second semiconductor die 120 may be connected to communicate with each other. For example, a signal transmission path between the first semiconductor die 110 and the second semiconductor die 120 may be provided by a plurality of via structures connecting the first semiconductor die 110 to the second semiconductor die 120.

[0045] The first semiconductor die 110 may include a first interface circuit 111, a first core circuit 115, etc., and the first interface circuit 111 and the first core circuit 115 may be connected to each other through a first system bus 114. The first interface circuit 111 may include a first transmission circuit 112 and a first reception circuit 113. The first transmission circuit 112 may transmit a data signal DATA1 and a clock signal CLK1 to the second semiconductor die 120, and receive a response signal RESP1 from the second semiconductor die 120. The first reception circuit 113 may receive a data signal DATA2 and a clock signal CLK2 from the second semiconductor die 120, and transmit a response signal RESP2 to the second semiconductor die 120.

[0046] The configuration of the second semiconductor die 120 may be similar to the configuration of the first semiconductor die 110. The second semiconductor die 120 may include a second interface circuit 121, a second system bus 124, a second core circuit 125, etc., and the second interface circuit 121 may include a second transmission circuit 122 and a second reception circuit 123. The functions provided by the first semiconductor die 110 and the second semiconductor die 120 may be determined by the first core circuit 115 and the second core circuit 125, respectively.

[0047] The second transmission circuit 122 may transmit a data signal DATA2 and a clock signal CLK2 to the first semiconductor die 110, and receive a response signal RESP2 from the first semiconductor die 110. The second reception circuit 123 may receive a data signal DATA1 and a clock signal CLK1 from the first semiconductor die 110, and transmit a response signal RESP1 to the first semiconductor die 110. In Figure 5 the illustrated embodiment, the semiconductor device 100 may operate in a source synchronous manner, in which the clock signals CLK1 and CLK2 are transmitted from the transmission side together with the data signals DATA1 and DATA2.

[0048] The response signals RESP1 and RESP2 are signals transmitted from the first reception circuit 113 and the second reception circuit 123 that have received the data signals DATA1 and DATA2 to the transmission side. The response signals RSP1 and RESP2 may be signals indicating whether the data signals DATA1 and DATA2 have been normally received (or whether the transmission of the data signals DATA1 and DATA2 has been successful). For example, the first transmission circuit 112 may generate a data signal DATA1 including transmission data to be transmitted to the second semiconductor die 120 and an error detection code of the transmission data. The second reception circuit 123 may use the error detection code included in the data signal DATA1 to determine whether the transmission data has been normally received, generate response data indicating the determination result, and transmit a response signal RESP1 including the response data to the first transmission circuit 112.

[0049] The first transmission circuit 112 may retransmit the data signal DATA1 or transmit the next data signal to be transmitted based on the response signal RESP1. Since the operation of the first transmission circuit 112 is determined according to the response signal RESP1, if an error occurs during the transmission of the response signal RESP1, the reliability of the semiconductor device 100 including the first semiconductor die 110 and the second semiconductor die 120 may deteriorate.

[0050] In one or more example embodiments of the present disclosure, the second receiving circuit 123 may generate a response signal RESP1 including error correction code for the response data and the response data, and send the response signal RESP1 to the first sending circuit 112. If necessary, the first sending circuit 112 may use the error correction code to recover errors in the response data included in the response signal RESP1. Therefore, the reliability of the response data included in the response signal RESP1 can be improved, and the first sending circuit 112 can accurately determine whether to retransmit the data signal DATA1 based on the response signal RESP1. In an embodiment, the error detection code included in the data signal DATA1 may be cyclic redundancy check (CRC) data, and the error correction code included in the response signal RESP1 may be error correction code (ECC) data.

[0051] Figure 6 And Figure 7 is a diagram schematically showing a semiconductor die included in a semiconductor device according to an example embodiment of the present disclosure.

[0052] Figure 6 is a diagram schematically showing a semiconductor die 200 on the transmitting side of a transmitted signal and included in a semiconductor device according to one or more example embodiments of the present disclosure, Figure 7 is a diagram showing a semiconductor die 300 on the receiving side of a received signal and included in a semiconductor device according to one or more example embodiments of the present disclosure. Referring to Figure 6 , the semiconductor die 200 on the transmitting side may include a FIFO circuit 210, an intermediate circuit 220, a transmitting logic 230, and a receiving logic 240. Data to be transmitted is temporarily stored in the FIFO circuit 210. For example, a core circuit may store data to be transmitted in the FIFO circuit 210 through a system bus.

[0053] The FIFO circuit 210 may be a 1:N1 asynchronous FIFO circuit. For example, the FIFO circuit 210 may output the stored data at a specific timing, and the intermediate circuit 220 may process the data received from the FIFO circuit 210. For example, the CRC encoder 221 of the intermediate circuit 220 may perform CRC encoding on the data to be transmitted to generate CRC data of the data to be transmitted, and the buffer memory 222 may temporarily store the data to be transmitted. The transmitting logic 230 may output a data signal DATA and clock signals CLK1 and CLK2 through a plurality of through-silicon via (TSV) structures TSV provided in a via region 250. The data signal DATA includes the data to be transmitted and the CRC data of the data to be transmitted.

[0054] In an embodiment, the transmission logic 230 may output a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may have different frequencies. For example, the frequency of the first clock signal CLK1 may be twice the frequency of the second clock signal CLK2. The transmission logic 230 may include a frequency divider that generates the second clock signal CLK2 using the first clock signal CLK1. However, according to an embodiment, the transmission logic 230 may output only one clock signal.

[0055] The reception logic 240 may receive the response signal RESP through at least one of a plurality of through-silicon via structures TSV. The response signal RESP may be a signal transmitted by the semiconductor die 300 on the reception side of the received data signal DATA and the clock signals CLK1 and CLK2. The response signal RESP may include response data generated by the semiconductor die 300 on the reception side and ECC data generated by the semiconductor die 300 on the reception side by performing ECC encoding on the response data.

[0056] The ECC decoder 223 of the intermediate circuit 220 may recover the response data by decoding the ECC data included in the response signal RESP. The response data may include at least one of retry response data for requesting retransmission of the data signal DATA and ready response data indicating that the data signal DATA has been normally received. Since the response data included in the response signal RESP can be accurately recovered using the ECC data, the semiconductor die 200 on the transmission side may perform subsequent operations by referring to the response signal RESP received from the semiconductor die 300 on the reception side.

[0057] If the response data includes retry response data, the CRC encoder 221 of the intermediate circuit 220 may re-CRC encode the data stored in the buffer memory 222, and the transmission logic 230 may output the data stored in the buffer memory 222 and the CRC data obtained by the re-CRC encoding as the data signal DATA. If the response data includes ready response data, the buffer memory 222 of the intermediate circuit 220 may delete the stored data. Thereafter, new data received from the FIFO circuit 210 may be stored in the buffer memory 222 and CRC encoded by the CRC encoder 221.

[0058] Figure 7 FIG. is a diagram schematically showing a semiconductor die 300 on the reception side that receives a data signal and a clock signal among the semiconductor dies included in a semiconductor device according to one or more example embodiments of the present disclosure. Refer to Figure 7, the semiconductor die 300 on the receiving side may include a FIFO circuit 310, an intermediate circuit 320, a receiving logic 330, and a transmitting logic 340. The FIFO circuit 310 may temporarily store the data received from the semiconductor die 200 on the transmitting side, and may send the received data to the core circuit via the system bus. The FIFO circuit 310 may be an N2:1 FIFO, and for example, N2 may be less than N1, where N1 is a characteristic of the FIFO circuit 210 on the transmitting side.

[0059] The receiving logic 330 may receive the data signal DATA and the clock signals CLK1 and CLK2 through at least some of the plurality of through-hole structures TSV arranged in the via region 350. As described above, the first clock signal CLK1 and the second clock signal CLK2 may have different frequencies. The receiving logic 330 may receive the data signal DATA with reference to at least one of the first clock signal CLK1 and the second clock signal CLK2.

[0060] The intermediate circuit 320 may include a CRC decoder 321, a response controller 322, and an ECC encoder 323. The CRC decoder 321 may decode the CRC data included in the data signal DATA and determine whether the data signal DATA has been received correctly. If it is determined that the data signal DATA has been received correctly, the response controller 322 may generate ready response data. If it is determined that an error has occurred during the transmission of the data signal DATA, the response controller 322 may generate retry response data. The ECC encoder 323 may generate ECC data by performing ECC encoding on the ready response data or the retry response data.

[0061] The transmitting logic 340 may output a response signal RESP including the response data generated by the response controller 322 and the ECC data generated by the ECC encoder 323. The response signal RESP may be sent to the semiconductor die 200 on the transmitting side, and the semiconductor die 200 on the transmitting side may retransmit the data that has been sent as the data signal DATA or send a data signal DATA including new data based on the response data included in the response signal RESP.

[0062] Errors may also occur during the transmission of the response signal RESP from the semiconductor die 300 on the receiving side to the semiconductor die 200 on the sending side. In one or more example embodiments of the present disclosure, ECC data obtained by performing ECC encoding on the response data by the semiconductor die 300 on the receiving side may be included in the response signal RESP and sent to the semiconductor die 200 on the sending side. When needed, the semiconductor die 200 on the sending side may use the ECC data to recover the response data and ensure the reliability of the response data included in the response signal RESP. Therefore, the accuracy and reliability of communication between the semiconductor die 200 on the sending side and the semiconductor die 300 on the receiving side can be improved, and the performance of the semiconductor device can be improved.

[0063] Figure 8 is a diagram showing the operation of a semiconductor device according to one or more example embodiments of the present disclosure.

[0064] Reference Figure 8 , a semiconductor device according to one or more example embodiments of the present disclosure may include a first semiconductor die SD1 and a second semiconductor die SD2. The first semiconductor die SD1 may be the sending side for sending data, and the second semiconductor die SD2 may be the receiving side for receiving data. The first semiconductor die SD1 and the second semiconductor die SD2 may be stacked on each other in the semiconductor device and connected to each other through a plurality of via structures.

[0065] The first semiconductor die SD1 on the sending side may confirm the original data to be sent (S10). When the original data is confirmed, the first semiconductor die SD1 may divide the original data to generate N pieces of transmission data (S11) and store each of the N pieces of transmission data as a unit in the FIFO circuit. As described above, each piece of transmission data stored in the FIFO circuit may be output at the same timing and input to the intermediate circuit of the first semiconductor die SD1, and the intermediate circuit may perform CRC encoding on the transmission data to generate CRC data of the transmission data.

[0066] Reference Figure 8 , the first semiconductor die SD1 may first generate first CRC data of the first transmission data (S12), and then send the first transmission data and the first CRC data to the second semiconductor die SD2. In an embodiment, the first semiconductor die SD1 may generate a first data signal including the first transmission data and the first CRC data and send the first data signal together with a clock signal to the second semiconductor die SD2.

[0067] The second semiconductor die SD2 may decode the first CRC data included in the first data signal (S14), and determine whether the transmission of the first transmitted data is successful based on the decoded first CRC data. (S15). For example, if it is determined that there is an error in the received first transmitted data as a result of decoding the first CRC data, it may be determined that the transmission of the first data has failed.

[0068] If it is determined that the transmission of the first transmitted data is successful, the second semiconductor die SD2 may generate ready response data and perform ECC encoding on the ready response data to generate ECC data of the ready response data (S16). The second semiconductor die SD2 may send a response signal including the ready response data and the ECC data to the first semiconductor die SD1 (S17), and in response thereto, the first semiconductor die SD1 may delete the first transmitted data stored in the buffer memory and prepare for the transmission of the second transmitted data (S18).

[0069] If it is determined that the transmission of the first transmitted data has failed, the second semiconductor die SD2 may generate retry response data and perform ECC encoding on the retry response data to generate ECC data of the retry response data (S19). The second semiconductor die SD2 may send a response signal including the retry response data and the ECC data to the first semiconductor die SD1 (S20), and in response thereto, the first semiconductor die SD1 may perform re-CRC encoding on the first transmitted data stored in the buffer memory to generate another first CRC data, and re-transmit a data signal including the first transmitted data and the another first CRC data (S21).

[0070] When needed, the first semiconductor die SD1 may use the ECC data included in the response signal to recover the ready response data or the retry response data, and perform subsequent operations according to the transmission result of the data signal in operation S13. Therefore, the accuracy and reliability of data communication between the first semiconductor die SD1 and the second semiconductor die SD2 can be improved.

[0071] Figures 9 to 11 is a diagram showing the operation of a semiconductor device according to one or more example embodiments of the present disclosure.

[0072] Figures 9 to 11 may be a diagram showing the operation of a semiconductor device 400 including a first semiconductor die 410 and a second semiconductor die 420. The first semiconductor die 410 and the second semiconductor die 420 may be connected to each other through a plurality of via structures 430, and the plurality of via structures 430 may include data via structures 431, clock via structures 432 for transmitting clock signals, and response via structures 433 for transmitting response signals.

[0073] In referenceFigures 9 to 11 In the described embodiment, the first semiconductor die 410 may be the transmitting side, and the second semiconductor die 420 may be the receiving side. Refer to Figure 9 , in the first semiconductor die 410, the transmission data stored in the FIFO circuit 411 may be input to the CRC encoder 412 and stored in the buffer memory 413. The CRC encoder 412 may generate CRC data of the transmission data, and the transmission data and the CRC data may be sent to the transmission logic 415.

[0074] The transmission logic 415 may send a data signal including the transmission data and the CRC data to the second semiconductor die 420 through the data via structure 431. The transmission logic 415 may send a clock signal to the second semiconductor die 420 through the clock via structure 432, and according to an embodiment, clock signals having different frequencies may be sent to the second semiconductor die 420 through the clock via structure 432.

[0075] The receiving logic 425 of the second semiconductor die 420 may receive the data signal and the clock signal, and may synchronize with the clock signal to extract the transmission data included in the data signal. In the second semiconductor die 420, the CRC decoder 422 may extract the CRC data included in the data signal, and the response controller 423 may determine whether the transmission data has been sent correctly based on the CRC data, and generate response data according to the determined result.

[0076] If it is determined that the transmission data has been sent correctly, the response controller 423 may generate ready response data as the response data, which notifies the first semiconductor device 410 that the second semiconductor die 420 is ready to receive new transmission data. If the second semiconductor device 420 determines that an error has occurred in the received transmission data, the response controller 423 may generate retry response data requesting retransmission of the transmission data as the response data.

[0077] Refer to Figure 10 , the response data generated by the response controller 423 may be input to the ECC encoder 424 of the second semiconductor die 420 before being sent to the first semiconductor die 410 by the transmission logic 426 of the second semiconductor die 420. The ECC encoder 424 may generate ECC data of the response data, and the transmission logic 426 may send a response signal including the response data and the ECC data to the first semiconductor die 410 through the response via structure 433.

[0078] The receiving logic 416 of the first semiconductor die 410 can receive a response signal. The response signal can be input to the ECC decoder 414, and the first semiconductor die 410 can determine subsequent operations based on the response data. For example, if the response data is ready response data, the first semiconductor die 410 can delete the transmission data stored in the buffer memory 413, as Figure 11 shown. Thereafter, new transmission data to be sent next can be transferred from the FIFO circuit 411 to the CRC encoder 412 and the buffer memory 413.

[0079] If the response data is retry response data, the transmission data stored in the buffer memory 413 can be sent again to the second semiconductor die 420, as described above with reference to Figure 9 described. The transmission data stored in the buffer memory 413 can be sent again to the CRC encoder 412, and a data signal including the CRC data regenerated by the CRC encoder 412 and the transmission data can be sent to the semiconductor die 420 by the sending logic 415.

[0080] If an error occurs during the transmission of the response data, the first semiconductor die 410 can use the ECC data received together with the response data to recover the response data. Accordingly, the reliability of the response data can be increased, and the first semiconductor die 410 can re - send the transmission data that failed to be sent or send new transmission data by referring to the response data sent from the second semiconductor die 420.

[0081] Figure 12 is a diagram schematically showing a semiconductor device according to one or more example embodiments of the present disclosure.

[0082] Figure 12 can be a diagram schematically showing a part of a semiconductor die 500 included in a semiconductor device according to one or more example embodiments of the present disclosure. Referring to Figure 12 , the semiconductor die 500 can include a FIFO circuit 510, a plurality of data sending circuits 521 to 525 (collectively 520), a clock transmission circuit 530, and the like.

[0083] The plurality of data sending circuits 521 to 525 (520) and the clock transmission circuit 530 can be included in an interface circuit. The plurality of data sending circuits 520 can be connected to data via structures 541 arranged in a via region 540, and the clock transmission circuit 530 can be connected to a clock via structure 542. The data via structures 541 can be connected to a plurality of data receiving circuits included in a receiving - side semiconductor die. The plurality of data sending circuits 520 can respectively correspond to the data via structures 541. In Figure 12In the illustrated embodiment, clock signals having different frequencies can be output through the clock via structure 542.

[0084] The semiconductor die 500 may include a clock generation circuit (not shown) configured to generate an internal clock signal CLK. For example, the clock generation circuit may include a phase-locked loop circuit, a delay-locked loop circuit, etc. The FIFO circuit 510 may receive and store the original data DIN that will be sent from the core circuit within the semiconductor die 500 to another semiconductor die via a system bus or the like.

[0085] The FIFO circuit 510 may output at least a part of the original data DIN as transmission data at a specific time with reference to the internal clock signal CLK. The transmission data may be input to a plurality of data transmission circuits 520, and each of the plurality of data transmission circuits 520 may include a latch and / or a flip-flop capable of storing the transmission data one bit at a time.

[0086] In addition, each of the plurality of data transmission circuits 520 may include a multiplexer configured to selectively output the outputs from the latch and / or the flip-flop one by one. For example, the first data transmission circuit 521 may include a latch, a flip-flop, and a multiplexer, and the total number of the latch and the flip-flop may be two or more. The multiplexer may selectively choose the outputs from the latch and the flip-flop one by one and send them to one data via structure 541, so that the first data transmission circuit 521 can be connected to one data via structure 541. By connecting one data via structure 541 to two or more of the latch and the flip-flop using the multiplexer, the number of via structures arranged in the via region 540 can be appropriately limited, and the integration degree of the semiconductor die 500 can be improved.

[0087] According to an embodiment, the operation timing of the multiplexer may be determined by clock signals having different frequencies generated by the clock transmission circuit 530. Using the internal clock signal CLK, the clock transmission circuit 530 may generate a separate clock signal having a frequency different from that of the internal clock signal CLK and output the clock signal to the plurality of data transmission circuits 520 and the clock via structure 542.

[0088] Figure 13 FIG. is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure. Figure 14 FIG. shows Figure 13 the operation of the Figure 13 illustrated interface circuit. For example, Figure 12 the illustrated interface circuit may be included in

[0089] Reference Figure 13, the interface circuit 600 may include a FIFO circuit 610, a latch 620, a flip-flop (FF) 630, a multiplexer (MUX) 640, and an inverter 650. The output terminal of the multiplexer 640 may be connected to a data via structure, and the output terminal of the inverter 650 may be connected to a clock via structure different from the data via structure. The latch 620, the flip-flop 630, and the multiplexer 640 may provide one of a plurality of data transmission circuits commonly connected to the output terminal of the FIFO circuit 610.

[0090] The FIFO circuit 610 may sequentially output transmission data DOUT to the latch 620 and the flip-flop 630. The latch 620 and the flip-flop 630 may operate in response to an internal clock signal CLK output by a clock generation circuit included in the semiconductor die, and store the transmission data DOUT output from the FIFO circuit 610. For example, the latch 620 and the flip-flop 630 may store the transmission data DOUT one bit at a time.

[0091] The multiplexer MUX may transmit the output of one of the latch 620 and the flip-flop 630 as a data signal DATA in response to a selection signal SE. A transmission clock signal TX_CLK may be output by the inverter 650, and according to an embodiment, a buffer circuit or the like may be added to the front and / or rear of the inverter 650.

[0092] Referring together Figure 14 , the FIFO circuit 610 may maintain the output of the transmission data DOUT within a predetermined unit time TM. The predetermined unit time TM may be defined as the time when the period of the internal clock signal CLK (or the transmission clock signal TX_CLK) repeats a predetermined number of times. For example, the FIFO circuit 610 may maintain the output of the first transmission data DOUT0 during a first unit time TM, and the first transmission data DOUT0 may be stored in the latch 620 and the flip-flop 630 during a sampling time TS. For example, a first data D0 included in the first transmission data DOUT0 may be stored in the latch 620, and a second data D1 may be stored in the flip-flop 630. Each of the first data D0 and the second data D1 may be 1-bit data.

[0093] The first data D0 and the second data D1 respectively stored in the latch 620 and the flip-flop 630 may be selected by the multiplexer 640 at a first time T0 and a second time T1 respectively, and may be output as a data signal DATA through the data via structure. For example, the first time T0 may be the time when the transmission clock signal TX_CLK has a low logic value corresponding to "0", and the second time T1 may be the time when the transmission clock signal TX_CLK has a high logic value corresponding to "1".

[0094] The selection signal SE input to the multiplexer 640 may be an internal clock signal CLK. When the selection signal SE is "0", the multiplexer 640 may select the output from the latch 620, and when the selection signal SE is "1", the multiplexer 640 may select the output from the flip - flop 630. Thus, as Figure 14 shown, the first data D0 stored in the latch 620 may be output as the data signal DATA within the first time T0, and the second data D1 stored in the flip - flop 630 may be output as the data signal DATA within the second time T1.

[0095] During the second unit time TM, the FIFO circuit 610 may maintain the output of the second transmitted data DOUT1, and during the sampling time TS, the second transmitted data DOUT1 may be stored one bit at a time in each of the latch 620 and the flip - flop 630. For example, during the sampling time TS of the second unit time TM, the third data D2 may be stored in the latch 620, and the fourth data D3 may be stored in the flip - flop 630.

[0096] Similar to the first unit time TM, in the second unit time TM, the multiplexer 640 may output the output from the latch 620 to the data via structure during the first time T0 when the transmission clock signal TX_CLK is "0", and output the output from the flip - flop 630 to the data via structure during the second time T1 when the transmission clock signal TX_CLK is "1". Thus, as Figure 14 shown, the data signal DATA output to the data via structure may include the third data D2 during the first time T0 and the fourth data D3 during the second time T1.

[0097] As referred to above Figure 13 described, multiple data transmission circuits may be commonly connected to one FIFO circuit 610. For example, multiple data transmission circuits may store the transmitted data output by the FIFO circuit 610 during the sampling time TS. The number of bits that can be stored in each of the multiple data transmission circuits may be determined by the number of the latch 620 and the flip - flop 630, and in Figure 13 the embodiment shown, 2 - bit data may be stored in one data transmission circuit. Thus, when the number of data transmission circuits connected to the FIFO circuit 610 is M, 2M - bit transmitted data may be output through M data via structures per unit time TM.

[0098] Figure 15 is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure. For example, Figure 15 the interface circuit shown may be included inFigure 12 in the semiconductor die 500 shown.

[0099] Reference Figure 15 , the interface circuit 700 may include a plurality of flip - flops 710 to 730, a FIFO circuit 740, and an inverter 750. The input terminals of the first flip - flop 710 and the second flip - flop 720 may be connected to a data via structure that provides a transmission path for the data signal DATA, and the input terminal of the inverter 750 may be connected to a clock via structure that provides a transmission path for the transmission clock signal TX_CLK. The data via structure and the clock via structure may be connected to an interface circuit on the sending side that outputs the data signal DATA and the transmission clock signal TX_CLK.

[0100] The first flip - flop 710 may be synchronized with the transmission clock signal TX_CLK and store the data signal DATA output by the interface circuit on the sending side. For example, the first flip - flop 710 may be synchronized with the rising edge of the transmission clock signal TX_CLK and store the data signal DATA one bit at a time. The transmission clock signal TX_CLK inverted 180 degrees by the inverter 750 may be input to the second flip - flop 720. Thus, the second flip - flop 720 may be synchronized with the falling edge of the transmission clock signal TX_CLK and store the data signal DATA one bit at a time, and different data may be stored in the first flip - flop 710 and the second flip - flop 720.

[0101] Similar to the second flip - flop 720, the third flip - flop 730 may operate in synchronization with the transmission clock signal TX_CLK having a phase inverted 180 degrees by the inverter 750. The FIFO circuit 740 may store the data output one bit at a time from each of the second flip - flop 720 and the third flip - flop 730, and may send the data to a core circuit included in the semiconductor die or an interface circuit 700 adjacent to the core circuit. According to an embodiment, the transmission clock signal TX_CLK having a phase inverted 180 degrees by the inverter 750 may also be input to the FIFO circuit 740.

[0102] Figure 16 is a diagram schematically showing an interface circuit included in a semiconductor device according to one or more example embodiments of the present disclosure. Figure 17 and Figure 18 is a diagram showing Figure 16 the operation of the interface circuit shown. For example, Figure 16 the interface circuit shown may be included in Figure 12 the semiconductor die 500 shown.

[0103] Reference Figure 16, the interface circuit 800 may include a FIFO circuit 810, a latch 820, first to third flip-flops 830 to 850, a multiplexer 860, a clock flip-flop 870, etc. The latch 820, the first to third flip-flops 830 to 850, and the multiplexer 860 may provide one of a plurality of data transmission circuits commonly connected to the output terminal of the FIFO circuit 810. The output terminal of the multiplexer 860 may be connected to a data via structure for outputting a data signal DATA.

[0104] In the interface circuit 800 according to Figure 16 the illustrated embodiment, the transmission data DOUT output from the FIFO circuit 810 may be input to the latch 820 and the first to third flip-flops 830 to 850. The latch 820 and the flip-flop 830 may operate in response to an internal clock signal CLK output from a clock generation circuit included in the semiconductor die, and store the transmission data DOUT output from the FIFO circuit 810. For example, the latch 820 and the flip-flop 830 may store the transmission data DOUT one bit at a time.

[0105] The multiplexer MUX may output the output from one of the latch 820 and the first to third flip-flops 830 to 850 as the data signal DATA in response to selection signals SE0 and SE1. Since the signal selected by the multiplexer MUX is output from the latch 820 and the first to third flip-flops 830 to 850, the multiplexer MUX may receive 2-bit selection signals SE0 and SE1.

[0106] For example, the first selection signal SE0 may be determined by the internal clock signal CLK. The internal clock signal CLK may be a clock signal having a first frequency, and may be output as a first transmission clock signal TX_CLK1 to another semiconductor die through a first clock via structure. The second selection signal SE1 may be determined by a second transmission clock signal TX_CLK2, which is a clock signal having a second frequency different from the first frequency.

[0107] The second transmission clock signal TX_CLK2 may be a signal generated by the clock flip-flop 870. For example, the clock flip-flop 870 may divide the internal clock signal CLK by two to output the second transmission clock signal TX_CLK2, and may transmit the value of the second selection signal SE1 input to the multiplexer 860 based on the second transmission clock signal TX_CLK2. Hereinafter, refer to Figure 17 and Figure 18 to describe the operation of the interface circuit 800.

[0108] Refer to together Figure 17 and Figure 18, the FIFO circuit 810 can maintain the output of the transmitted data within a predetermined unit time TM, and the predetermined unit time TM can be defined as the time when the period of the internal clock signal CLK is repeated a predetermined number of times. Refer to Figure 17 , the FIFO circuit 810 can maintain the output of the first transmitted data DOUT0 within the first unit time TM, and the first transmitted data DOUT0 can be stored in the latch 820 and the first flip-flop 830 to the third flip-flop 850 during the sampling time TS. For example, the first data D0 included in the first transmitted data DOUT0 can be stored in the latch 820, the second data D1 included in the first transmitted data DOUT0 can be stored in the first flip-flop 830. The third data D2 included in the first transmitted data DOUT0 can be stored in the second flip-flop 840, and the fourth data D3 included in the first transmitted data DOUT0 can be stored in the third flip-flop 850. Each of the first data D0 to the fourth data D3 can be 1-bit data.

[0109] The first data D0 to the fourth data D3 stored in each of the latch 820 and the first flip-flop 830 to the third flip-flop 850 can be sequentially selected by the multiplexer 640 during the first time T0 to the fourth time T3, and can be output as the data signal DATA through the data via structure. For example, during the first time T0, the first transmission clock signal TX_CLK1 and the second transmission clock signal TX_CLK2 can have a low logic value corresponding to "0". Therefore, the values of the first selection signal SE0 and the second selection signal SE1 to be input to the multiplexer 860 can be determined as "00", and the output from the latch 820 can be sent to the data via structure.

[0110] During the second time T1, the first transmission clock signal TX_CLK1 can have a high logic value corresponding to "1", and the second transmission clock signal TX_CLK2 can have a low logic value corresponding to "0". Therefore, the values of the first selection signal SE0 and the second selection signal SE1 to be input to the multiplexer 860 can be determined as "10", and the output from the first flip-flop 830 can be sent to the data via structure. During the third time T2, the values of the first selection signal SE0 and the second selection signal SE1 to be input to the multiplexer 860 can be determined as "01", and the output of the second flip-flop 840 can be sent to the data via structure, and during the fourth time T3, the values of the first selection signal SE0 and the second selection signal SE1 to be input to the multiplexer 860 can be determined as "11", and the output from the third flip-flop 850 can be sent to the data via structure.

[0111] Figure 18It may be a diagram showing the operation of the interface circuit 800 during the second unit time TM. Refer to Figure 18 , during the second unit time TM, the FIFO circuit 810 may maintain the output of the second transmission data DOUT1, and during the sampling time TS, the second transmission data DOUT1 may be stored one bit at a time in each of the latch 820 and the first flip-flop 830 to the third flip-flop 850. For example, during the sampling time TS of the second unit time TM, the fifth data D4 included in the second transmission data DOUT1 may be stored in the latch 820, and the sixth data D5 included in the second transmission data DOUT1 may be stored in the first flip-flop 830.

[0112] In the second unit time TM, the multiplexer 860 may sequentially send the outputs from each of the latch 820 and the first flip-flop 830 to the third flip-flop 850 to the data via structure in response to the selection signals SE0 and SE1 determined by the first transmission clock signal TX_CLK1 and the second transmission clock signal TX_CLK2. For example, when the selection signals SE0 and SE1 are "00", the multiplexer 860 may connect the latch 820 to the data via structure during the first time T0, and when the selection signals SE0 and SE1 are "10", the multiplexer 860 may connect the first flip-flop 830 to the data via structure during the second time T1.

[0113] Multiple data transmission circuits may be commonly connected to one FIFO circuit 810, and the multiple data transmission circuits may store the transmission data output from the FIFO circuit 810 during the sampling time TS. The number of bits that can be stored in each of the multiple data transmission circuits may be determined depending on the number of the latch 820 and the flip-flops 830-850. For example, in Figure 16 the illustrated embodiment, 4-bit data can be stored in one data transmission circuit at a time.

[0114] For example, assuming the number of data via structures of the output data signal DATA is M, the number of data transmission circuits may also be M. In this case, the FIFO circuit 810 may output 4M bits of transmission data at a time, and each of the latch 820 and the flip-flops 830 to 850 included in each of the data transmission circuits may store the transmission data one bit at a time. By using the multiplexer 860 included in the data transmission circuits, M bits of transmission data may be output to the semiconductor die on the receiving side synchronously with the first transmission clock signal TX_CLK1 and the second transmission clock signal TX_CLK2 through the M data via structures.

[0115] According to an embodiment, the number of bits stored at a time in each of the data transmission circuits may be more than 4 bits. For example, the total number of latches and flip-flops included in a single data transmission circuit may be 8, and 8-bit transmission data may be stored in a single data transmission circuit at a time. In this case, a first clock signal having a frequency that is 1 / 2 times the frequency of the internal clock signal and a second clock signal having a frequency that is 1 / 4 times the frequency of the internal clock signal may be generated, and the data stored in the eight latches and flip-flops may be sequentially output by controlling a multiplexer with three clock signals including the internal clock signal, the first clock signal, and the second clock signal. In this way, by increasing the number of bits stored at a time in each of the data transmission circuits, the number of data via hole structures required to transmit the same size of transmission data may be reduced.

[0116] Figure 19 and Figure 20 are diagrams illustrating operations of semiconductor devices according to one or more example embodiments of the present disclosure.

[0117] Figure 19 and Figure 20 may be a diagram illustrating a data signal DATA and a transmission clock TX_CLK transmitted between semiconductor dies included in a semiconductor device according to one or more example embodiments of the present disclosure. In Figure 19 and Figure 20 illustrated embodiments, the data signal DATA may be a signal output through a single data via hole structure.

[0118] Referring to Figure 19 , the data signal DATA may be output in synchronization with an edge of the transmission clock signal TX_CLK. For example, the data signal DATA may be transmitted by a double data rate (DDR) method, in which respective data D0 to D7 are output at each rising edge and falling edge of the transmission clock signal TX_CLK. Accordingly, a larger amount of data may be transmitted and received within a given time period, and the rising edge or falling edge of the transmission clock signal TX_CLK may be aligned with the center of respective data D0 to D7, thereby sufficiently ensuring a set-up time margin of flip-flops included in an interface circuit on the receiving side.

[0119] In Figure 20 illustrated embodiments, edges between respective data D0 to D7 included in the data signal DATA may be aligned with a rising edge or a falling edge of the transmission clock signal TX_CLK and transmitted. In Figure 20In the illustrated embodiment, the interface circuit on the receiving side may include a delay circuit that receives a transmission clock signal TX_CLK. The delay circuit may adjust the phase of the transmission clock signal TX_CLK to ensure that there is sufficient setup time margin in the flip-flop for receiving the data signal DATA, and then input the phase-adjusted transmission clock signal TX_CLK into the flip-flop. For example, the appropriate delay value required for aligning the transmission clock signal TX_CLK and the data signal DATA may vary depending on the characteristics of the semiconductor die and the semiconductor device including the semiconductor die. Therefore, the delay value for adjusting the phase of the transmission clock signal TX_CLK by the delay circuit can be determined during the testing of the semiconductor device.

[0120] According to one or more example embodiments of the present disclosure, in the communication between semiconductor dies stacked on top of each other to provide a single semiconductor device, the transmitting side may transmit a data signal including transmitted data and an error detection code for the transmitted data, and the receiving side may determine whether the transmitted data has been transmitted normally (or successfully) by decoding the error detection code, and determine whether to request retransmission of the data signal. Therefore, the communication reliability between semiconductor dies can be improved. In addition, by implementing the transmitting circuit and the receiving circuit with digital circuits including flip-flops, latches, multiplexers, etc. instead of analog physical circuits, power consumption can be reduced.

[0121] Although example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first semiconductor die, comprising a first interface circuit configured to output a data signal and a transmission clock signal, wherein the first interface circuit comprises a CRC encoder configured to generate cyclic redundancy check CRC data of transmission data included in the data signal and a buffer memory configured to store the transmission data; a second semiconductor die, comprising a second interface circuit configured to receive the data signal and the transmission clock signal, wherein the second interface circuit comprises a CRC decoder configured to decode the CRC data included in the data signal, a response controller configured to generate response data based on the CRC data, the response data indicating completion of transmission of the transmission data or requesting retransmission of the transmission data, and an ECC encoder configured to generate error correction code ECC data for the response data; and a plurality of through-hole structures, connecting the first interface circuit to the second interface circuit, The first interface circuit further includes an ECC decoder, which is configured to recover the response data by decoding the ECC data of the response data, and resend the transmission data stored in the buffer memory or send new transmission data based on the response data.

2. The semiconductor device according to claim 1, wherein The first semiconductor die provides a processor and the second semiconductor die provides memory.

3. The semiconductor device according to claim 1, wherein The first semiconductor die includes a first semiconductor substrate, and the second semiconductor die includes a second semiconductor substrate, and Each of the plurality of through-hole structures is a through-silicon via penetrating at least one of the first semiconductor substrate or the second semiconductor substrate.

4. The semiconductor device according to claim 1, wherein: The first semiconductor die includes a first core circuit connected to the first interface circuit via a first system bus, and The second semiconductor die includes a second core circuit connected to the second interface circuit via a second system bus.

5. The semiconductor device according to claim 1, wherein The first interface circuit includes a first-in-first-out FIFO circuit configured to store the data signal and a plurality of data transmission circuits commonly connected to an output terminal of the FIFO circuit.

6. The semiconductor device according to claim 5, wherein: Each of the plurality of data transmission circuits includes a latch and at least one flip-flop, each of the latch and the at least one flip-flop being configured to receive the data signal from the FIFO circuit; and a multiplexer configured to connect one of the latch and the at least one flip-flop to a corresponding via structure among the plurality of via structures.

7. The semiconductor device according to claim 6, wherein: The latch and the at least one flip-flop are synchronized with an internal clock signal input to the first interface circuit to store the data signal at a predetermined time, and the multiplexer is configured to sequentially connect the latch and the at least one flip-flop to the corresponding via structure.

8. The semiconductor device according to claim 6, wherein: The first interface circuit includes a clock trigger, wherein the clock trigger is configured to divide the frequency of the internal clock signal. wherein the transmission clock signal includes a first transmission clock signal having the same frequency as the internal clock signal and a second transmission clock signal output from the clock flip-flop, and Wherein, the multiplexer is configured to receive the first transmission clock signal and the second transmission clock signal.

9. The semiconductor device according to claim 5, wherein: The plurality of via structures include a plurality of data via structures providing transmission paths for the data signal, and the number of the plurality of data via structures is equal to the number of the plurality of data transmitting circuits.

10. The semiconductor device according to claim 1, wherein The second interface circuit includes a plurality of data receiving circuits, each of the data receiving circuits being configured to receive the data signal from the first interface circuit and to receive the transmission clock signal from the first interface circuit through at least one clock via structure among the plurality of via structures, and Each of the plurality of data receiving circuits includes a first trigger and a second trigger connected to a corresponding through-hole structure among the plurality of through-hole structures, and a third trigger connected to the first trigger.

11. The semiconductor device according to claim 10, wherein: The first flip-flop is configured to store the data signal in response to a rising edge of the transmission clock signal, and the second and third flip-flops are configured to store the data signal in response to a falling edge of the transmission clock signal.

12. The semiconductor device according to claim 11, wherein The second interface circuit includes an inverter configured to invert the transmission clock signal and transmit the inverted transmission clock signal to the second flip-flop and the third flip-flop.

13. The semiconductor device according to claim 11, wherein The second interface circuit is connected to a clock via structure among the plurality of via structures, the transmission clock signal is transmitted through the clock via structure, and includes a delay circuit configured to adjust a phase of the transmission clock signal.

14. The semiconductor device according to claim 1, wherein The first interface circuit is configured to delete the transmission data stored in the buffer memory based on the response data indicating that the transmission of the transmission data is completed.

15. The semiconductor device according to claim 1, wherein The first interface circuit is configured to request retransmission of the transmission data based on the response data, and to retransmit the data signal including the transmission data stored in the buffer memory to the second interface circuit.

16. A semiconductor device comprising: a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and comprising a second interface circuit, the second interface circuit being connected to the first semiconductor die through a plurality of through-hole structures, wherein the first interface circuit is configured to generate an error detection code for transmission data, and to send a data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of through-hole structures, and The second interface circuit is configured to generate response data indicating whether the data signal is received normally and an error correction code for the response data, and to send a response signal including the response data and the error correction code to the first interface circuit through at least one through-hole structure among the plurality of through-hole structures.

17. The semiconductor device according to claim 16, wherein: Based on detection of an error from the transmission data included in the data signal according to the error detection code, the second interface circuit is configured to generate the response data requesting retransmission of the transmission data.

18. The semiconductor device according to claim 17, wherein: The first interface circuit is configured to correct an error in the response data by using the error correction code, and determine whether to retransmit the transmission data based on the response data whose error has been corrected.

19. The semiconductor device according to claim 16, wherein: At least some of the plurality of via structures through which the data signal and the error detection code are transmitted are different from the at least one via structure through which the response signal is transmitted.

20. A semiconductor device comprising: a first semiconductor die including a first interface circuit; and a second semiconductor die including a second interface circuit connected to the first interface circuit through a plurality of through-hole structures, the second semiconductor die being stacked with the first semiconductor die, wherein the first interface circuit comprises a plurality of data transmission circuits connected to a data through-hole structure among the plurality of through-hole structures and a first-in-first-out FIFO circuit commonly connected to the plurality of data transmission circuits, and Wherein, each of the multiple data sending circuits includes a latch and at least one trigger, each of the latch and the at least one trigger is configured to receive transmission data output from the FIFO circuit; and a multiplexer connected between the latch and the at least one trigger and the corresponding data through-hole structure in the data through-hole structure.

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