Simulation verification test method and platform of MIPI-DSI protocol

Abstract

The invention provides a simulation verification test method and platform for an MIPI-DSI protocol, and the method comprises the steps that a top layer configurator confirms excitation modes and generates information representing the excitation modes, the excitation modes comprise an external excitation mode and an internal excitation mode, the external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of receiving excitation data from a data input interface; the internal excitation mode is a mode of automatically generating excitation data; the data generator generates excitation data, wherein the excitation data at least comprises configuration information of simulation environment variables; the data processing module generates a serial data code stream according to the excitation data when receiving the excitation data sent by the data generator; the MIPI physical digital-analog hybrid interface converts a serial data code stream into a digital signal, and the register transmission level module performs simulation verification on a chip of an MIPI-DSI protocol according to the digital signal. According to the method and the device, the problem that the simulation verification test of the MIPI-DSI protocol chip is relatively poor in flexibility is solved.

Description

Technical Field

[0001] This application relates to the field of simulation verification testing, and more particularly, to a simulation verification testing method for the MIPI-DSI protocol, a simulation verification testing platform for the MIPI-DSI protocol, a computer-readable storage medium, a computer program product, and an electronic device. Background Art

[0002] The MIPI interface protocol is a series of interface protocols developed and maintained by the MIPI Alliance, which are high-performance, low-power, and low-cost, and are widely used in various mobile devices. In various consumer electronic products such as mobile phones, tablets, game consoles, in-vehicle electronics, and wearable devices, it realizes the standardization and unification of interfaces for external devices such as cameras, displays, and radio frequencies, reduces the complexity of product design, interconnection, and compatibility, and provides higher flexibility. Among them, DSI and DPHY are applied to connect the display timing control chip and the image processor to provide high-bandwidth and high-performance serial data transmission.

[0003] In the process of designing a timing control integrated circuit chip, in order to fully simulate, verify, and test the MIPI-DSI protocol and reduce logic circuit design errors, a large number of simulation verification and test cases need to be developed. The DSI protocol and DPHY interface are a high-speed digital-analog hybrid interface protocol that combines digital logic design and analog circuit design. Ordinary verification methods cannot effectively and comprehensively verify the high-speed digital-analog hybrid interface. In the process of chip design and verification, problems such as insufficient design and verification, personnel changes, and chip architecture adjustments often lead to slow product iteration. Therefore, a simulation verification method and test case set platform for the MIPI-DSI protocol with strong versatility, good portability, and flexibility can greatly improve the accuracy and efficiency of product design, provide a simulation verification basic case and platform support for the next-generation iterative product, and reduce the product mass production error rate.

[0004] The existing simulation verification testing for MIPI-DSI protocol chips has the problem of poor flexibility. Summary of the Invention

[0005] The main purpose of this application is to provide a simulation verification testing method for the MIPI-DSI protocol, a simulation verification testing platform for the MIPI-DSI protocol, a computer-readable storage medium, a computer program product, and an electronic device, so as to at least solve the problem of poor flexibility in the simulation verification testing of MIPI-DSI protocol chips in the prior art.

[0006] To achieve the above object, according to one aspect of the present application, there is provided a simulation verification test method for the MIPI-DSI protocol, including: the top-level configurator confirms the excitation mode and generates information representing the excitation mode, the excitation mode includes an external excitation mode and an internal excitation mode, the external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of self-generating excitation data; the data generator generates first excitation data when receiving the information sent by the top-level configurator representing that the excitation mode is the internal excitation mode, and the first excitation data at least includes configuration information of simulation environment variables; the data processing module generates a first serial data stream according to the first excitation data when receiving the first excitation data sent by the data generator, and the first serial data stream is a serial data stream of the MIPI-DSI protocol; the MIPI physical digital-to-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal; the register transfer level module performs simulation verification on the chip of the MIPI-DSI protocol according to the first digital signal when receiving the MIPI physical digital-to-analog hybrid interface.

[0007] Optionally, the method further includes: the data input interface reads an external input file to obtain second excitation data when receiving the information sent by the top-level configurator representing that the excitation mode is the external excitation mode, and the second excitation data at least includes image data and register configuration information of the chip; the pre-processor integrates the second excitation data into a second serial data stream when receiving the second excitation data sent by the data input interface, and the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; the MIPI physical digital-to-analog hybrid interface converts the second serial data stream into a second digital signal when receiving the second serial data stream sent by the pre-processor; the register transfer level module configures the simulation environment according to the signal representing the register configuration information of the chip in the second digital signal, generates register transfer level source code according to the signal representing the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

[0008] Optionally, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module generates a first serial data stream according to the first excitation data, including: the DSI configurator generates configuration content, which includes pixel format, resolution, and frame rate; when the exciter receives the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, according to the MIPI-DSI protocol and the configuration content, the exciter encapsulates the first excitation data into a DSI protocol packet; when the driver receives the DSI protocol packet sent by the exciter, the driver parses the DSI protocol packet and encapsulates and packs the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; when the DPHY model receives the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data stream.

[0009] Optionally, the DSI agent further includes a monitor. After the exciter sends the DSI protocol packet, the method further includes: the monitor obtains the DSI protocol packet in real time, extracts key data in the DSI protocol packet, and encapsulates and packs the key data into a key data packet. The key data at least includes a data identifier and payload data; a comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, and generates a first comparison result. The expected key data packet represents a protocol packet with a correct data format and correct data content. The first comparison result is a result representing the correctness of the data format and data content of the key data packet; a data output interface outputs the first comparison result.

[0010] Optionally, the method further includes: after the register transfer level module performs simulation verification on the chip, generating a first simulation result and a configuration file, where the first simulation result includes a first test waveform and first image test data, the first test waveform is a waveform characterizing the change of signals of the chip over time during the simulation verification process, the first image test data is data characterizing the image quality, and the configuration file includes first excitation data or second excitation data; the FPGA prototype generates a second simulation result according to the configuration file, the second simulation result includes a second test waveform and second image test data, the second test waveform is a waveform characterizing the change of signals of the FPGA prototype over time in the simulation environment corresponding to the configuration file, and the second image test data is data characterizing the image quality of the image processed by the FPGA prototype; the verification module compares the first simulation result with the second simulation result to generate a second comparison result, and the second comparison result is a result characterizing the consistency degree between the simulation verification and the FPGA prototype test; the data output interface outputs the second comparison result and receives a third simulation result, the third simulation result includes a third test waveform and third image test data, the third test waveform is a waveform characterizing the change of signals obtained by testing the physical chip in the simulation environment corresponding to the configuration file, and the third image test data is data characterizing the image quality of the image processed by the physical chip; the verification module compares the first simulation result with the third simulation result to generate a third comparison result, and the third comparison result is a result characterizing the consistency degree between the simulation verification and the physical chip test.

[0011] Optionally, after the simulation verification is completed, the method further includes: the data output interface outputs the first simulation result generated by the register transfer level module.

[0012] According to another aspect of the present application, there is provided a simulation verification test platform for the MIPI-DSI protocol, including: a top-level configurator for confirming an excitation mode and generating information characterizing the excitation mode, where the excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of self-generating excitation data; a data generator, the input end of the data generator is connected to the output end of the top-level configurator. The data generator is configured to generate first excitation data when receiving information indicating that the excitation mode is the internal excitation mode. The first excitation data at least includes configuration information of simulation environment variables; a data processing module, the input end of the data processing module is connected to the output end of the data generator. The data processing module is configured to generate a first serial data stream according to the first excitation data, and the first serial data stream is a serial data stream of the MIPI-DSI protocol; an MIPI physical digital-analog hybrid interface, the input end of the MIPI physical digital-analog hybrid interface is connected to the output end of the data processing module for receiving the first serial data stream and converting the first serial data stream into a first digital signal; a register transfer level module, the input end of the register transfer level module is connected to the output end of the MIPI physical digital-analog hybrid interface for performing simulation verification on a chip of the MIPI-DSI protocol according to the first digital signal.

[0013] According to yet another aspect of the present application, there is provided a computer-readable storage medium, where the computer-readable storage medium includes a stored program. When the program runs, it controls the device where the computer-readable storage medium is located to execute any one of the above methods.

[0014] According to still another aspect of the present application, there is provided a computer program product including computer instructions, and when the computer instructions are executed by a processor, they implement any one of the above methods.

[0015] According to another aspect of the present application, there is provided an electronic device, including: one or more processors, a memory, and one or more programs, where the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include those for executing any one of the above methods.

[0016] Applying the technical solution of the present application, first, the top-level configurator confirms the excitation mode and generates information characterizing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from the data input interface, and the internal excitation mode is a mode of generating excitation data by itself. Then, when the data generator receives the information sent by the top-level configurator characterizing that the excitation mode is the internal excitation mode, it generates first excitation data, and the first excitation data at least includes configuration information of simulation environment variables. Next, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data, and the first serial data stream is a serial data stream of the MIPI-DSI protocol. After that, the MIPI physical digital-to-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal. Finally, when the register transfer level module receives the MIPI physical digital-to-analog hybrid interface, it performs simulation verification on the chip of the MIPI-DSI protocol according to the first digital signal. By combining the two excitation modes, the present application can randomly generate excitation data by using the internal excitation mode according to actual requirements, or can use the external excitation mode to perform tests for specific test scenarios and boundary conditions, making the simulation verification test of the MIPI-DSI protocol chip more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings forming a part of this application are used to provide a further understanding of the application. The schematic embodiments and descriptions thereof of the application are used to explain the application and do not constitute an improper limitation of the application. In the drawings:

[0018] Figure 1 The hardware structure block diagram of a mobile terminal showing a method for performing simulation verification testing of the MIPI-DSI protocol according to an embodiment of the present application is shown;

[0019] Figure 2 The flowchart showing a method for simulation verification testing of the MIPI-DSI protocol according to an embodiment of the present application is shown;

[0020] Figure 3 The flowchart showing a method for simulation verification testing of the MIPI-DSI protocol according to an embodiment of the present application is shown;

[0021] Figure 4 The structure diagram of a MIPI top-level environment showing a method for simulation verification testing of the MIPI-DSI protocol according to an embodiment of the present application is shown;

[0022] Figure 5 The flowchart showing a method for mutual verification according to an embodiment of the present application is shown.

[0023] Among them, the above-mentioned drawings include the following reference numerals:

[0024] 102, processor; 104, memory; 106, transmission device; 108, input / output device; 22, simulation verification test platform for MIPI-DSI protocol; 24, data generator; 26, top-level configurator; 28, data input interface; 30, preprocessor; 32, exciter; 34, DSI configurator; 36, driver; 38, monitor; 40, clock channel; 42, data channel; 44, MIPI physical digital-to-analog hybrid interface; 46, register transfer level module; 48, comparator; 50, data output interface; 52, DSI agent; 54, DPHY model; 56, FPGA prototype test; 60, chip system test; 62, configuration file. Specific embodiments

[0025] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances for the embodiments of the present application described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] As introduced in the background art, the flexibility of the simulation verification test of MIPI-DSI protocol chips in the prior art is poor. To solve the above technical problems, the embodiments of the present application provide a simulation verification test method for MIPI-DSI protocol, a simulation verification test platform for MIPI-DSI protocol, a computer-readable storage medium, a computer program product, and an electronic device.

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0030] The method embodiments provided in the embodiments of this application can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 is a hardware structure block diagram of a mobile terminal for a simulation verification test method of the MIPI-DSI protocol in an embodiment of the present invention. As Figure 1 shown, the mobile terminal may include one or more ( Figure 1 only one is shown in Figure 1 the figure) processors 102 (the processors 102 may include, but are not limited to, processing devices such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Among them, the mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown in Figure 1 the figure is only schematic and does not limit the structure of the mobile terminal. For example, the mobile terminal may further include more or fewer components than

[0031] shown in

[0032] In this embodiment, a simulation verification test method for the MIPI-DSI protocol running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0033] Figure 2 It is a flowchart of the simulation verification test method for the MIPI-DSI protocol according to an embodiment of the present application. As Figure 2 shown, the method includes the following steps:

[0034] Step S201, the top-level configurator confirms the excitation mode and generates information characterizing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of generating excitation data by itself;

[0035] Step S202, when the data generator receives the information sent by the top-level configurator characterizing that the excitation mode is the internal excitation mode, it generates first excitation data. The first excitation data includes at least configuration information of simulation environment variables;

[0036] Specifically, the configuration information includes the number of instantiations of each component.

[0037] Step S203, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data. The first serial data stream is a serial data stream of the MIPI-DSI protocol;

[0038] Step S204, the MIPI physical digital-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal;

[0039] Step S205, when the register transfer level module receives the MIPI physical digital-analog hybrid interface, it performs simulation verification on the MIPI-DSI protocol chip according to the first digital signal.

[0040] In the described embodiment, first, the top-level configurator confirms the excitation mode and generates information representing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of generating excitation data by itself. Then, when the data generator receives the information sent by the top-level configurator representing that the excitation mode is the internal excitation mode, it generates first excitation data. The first excitation data at least includes configuration information of simulation environment variables. Next, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data. The first serial data stream is a serial data stream of the MIPI-DSI protocol. After that, the MIPI physical digital-to-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal. Finally, when the register transfer level module receives the MIPI physical digital-to-analog hybrid interface, it performs simulation verification on the MIPI-DSI protocol chip according to the first digital signal. By combining the two excitation modes, the present application can randomly generate excitation data using the internal excitation mode according to actual requirements, or use the external excitation mode to test specific test scenarios and boundary conditions, making the simulation verification test of the MIPI-DSI protocol chip more flexible.

[0041] Specifically, the first excitation data further includes the pixel content of image data required during the simulation and register configuration information. The generation of excitation data by itself is the generation of excitation data by an internal excitation library.

[0042] In an alternative solution, the method further includes: when the data input interface receives the information sent by the top-level configurator indicating that the excitation mode is the external excitation mode, the data input interface reads an external input file to obtain second excitation data, where the second excitation data at least includes image data and register configuration information of the chip; when the pre-processor receives the second excitation data sent by the data input interface, the pre-processor integrates the second excitation data into a second serial data stream, where the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; when the MIPI physical digital-to-analog hybrid interface receives the second serial data stream sent by the pre-processor, the MIPI physical digital-to-analog hybrid interface converts the second serial data stream into a second digital signal; when the register transfer level module receives the second digital signal sent by the MIPI physical digital-to-analog hybrid interface, the register transfer level module configures the simulation environment according to the signal indicating the register configuration information of the chip in the second digital signal, generates register transfer level source code according to the signal indicating the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

[0043] In the embodiment, the external excitation mode can directly read the external input file, can set the test scenario targeted, can cover more test cases, and further enhances the flexibility of the verification process.

[0044] Specifically, the external input file can be set targeted according to the simulation result.

[0045] In another alternative solution, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module generating a first serial data stream according to the first excitation data includes: the DSI configurator generating configuration content, where the configuration content includes pixel format, resolution, and frame rate; when the exciter receives the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, the exciter encapsulates the first excitation data into a DSI protocol packet according to the MIPI-DSI protocol and the configuration content; when the driver receives the DSI protocol packet sent by the exciter, the driver parses the DSI protocol packet and encapsulates and packages the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; when the DPHY model receives the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data stream.

[0046] In the described embodiment, through the DSI agent and DPHY model in the data processing module, flexible configuration, protocol encapsulation, and data decomposition and serialization of the first excitation data are achieved, thus ensuring the accurate and efficient simulation of the data transmission process and providing a solid foundation for subsequent test verification.

[0047] Specifically, the DPHY model includes a clock channel and a data channel, and the two cooperate to perform the data transmission task.

[0048] In another alternative solution, the DSI agent further includes a monitor. After the exciter sends the DSI protocol packet, the method further includes: the monitor obtains the DSI protocol packet in real time, extracts the key data in the DSI protocol packet, encapsulates and packs the key data into a key data packet, and the key data at least includes a data identifier and payload data; the comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, generates a first comparison result, the expected key data packet represents a protocol packet with a correct data format and correct data content, and the first comparison result is a result representing the correctness of the data format and data content of the key data packet; the data output interface outputs the first comparison result.

[0049] In the described embodiment, the monitor can obtain the DSI protocol packet sent by the exciter in real time, extract and pack the key data in the DSI protocol packet, and send the key data packet to the comparator for comparison, ensuring that each DSI protocol packet in the data transmission process can be recorded and monitored in a timely manner. The comparator compares the received key data packet with the expected key data packet to accurately judge whether the actually transmitted data packet conforms to the expectation, thereby effectively identifying possible deviations or errors in the data during transmission. The result of the comparison is output through the data output interface, enabling the tester to immediately obtain the result of the data comparison, providing direct feedback and a basis for subsequent test verification and fault troubleshooting.

[0050] Specifically, the test results can be stored in a specified file or database through specific simulation parameters and configurations.

[0051] In some other exemplary embodiments of the present application, the method further includes: after the register transfer level module performs simulation verification on the chip, it generates a first simulation result and a configuration file. The first simulation result includes a first test waveform and first image test data. The first test waveform is a waveform representing the variation of the signals of the chip over time during the simulation verification process, and the first image test data is data representing the image quality. The configuration file includes first excitation data or second excitation data; the FPGA prototype generates a second simulation result according to the configuration file. The second simulation result includes a second test waveform and second image test data. The second test waveform is a waveform representing the variation of the signals of the FPGA prototype over time in the simulation environment corresponding to the configuration file, and the second image test data is data representing the image quality of the image processed by the FPGA prototype; the verification module compares the first simulation result with the second simulation result to generate a second comparison result, and the second comparison result is a result representing the degree of consistency between the simulation verification and the FPGA prototype test; the data output interface outputs the second comparison result and receives a third simulation result. The third simulation result includes a third test waveform and third image test data. The third test waveform is a waveform representing the variation of the signals obtained by testing the physical chip in the simulation environment corresponding to the configuration file, and the third image test data is data representing the image quality of the image processed by the physical chip; the verification module compares the first simulation result with the third simulation result to generate a third comparison result, and the third comparison result is a result representing the degree of consistency between the simulation verification and the physical chip test.

[0052] In the embodiment, after the chip simulation verification, the generated configuration file is provided for the FPGA prototype test. The configuration file serves as a bridge between the simulation test verification environment and the FPGA prototype test environment, ensuring the consistency between the simulation verification environment and the FPGA prototype test environment. Through the verification module, the test results of the FPGA prototype and the physical chip are compared with the simulation results to further verify the correctness and reliability of the chip design in the actual environment. Through the tests of the FPGA prototype and the physical chip, potential problems not exposed in the simulation can be discovered.

[0053] Specifically, when the excitation mode is the internal excitation mode, the configuration file includes first excitation data; when the excitation mode is the external excitation mode, the configuration file includes second excitation data.

[0054] In an alternative embodiment, after the simulation verification is completed, the method further includes: the data output interface outputs the first simulation result generated by the register transfer level module.

[0055] In the described embodiment, the simulation results are uniformly output to a specified directory, facilitating subsequent centralized management and analysis of the simulation data, enhancing the traceability of the project, and facilitating quick location and access to the simulation data when needed.

[0056] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0057] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the simulation verification test method of the MIPI-DSI protocol of the present application will be described in detail below in conjunction with specific embodiments.

[0058] This embodiment relates to a specific simulation verification test method for the MIPI-DSI protocol, as Figure 3 shown, and includes the following steps:

[0059] Step S1: Determine whether it is an internal excitation mode. If it is an internal excitation mode, then execute steps S2, S3, S4, and S5. If it is not an internal excitation mode, then execute steps S2', S3', S4, and S5;

[0060] Step S2: The data generator generates excitation data;

[0061] Step S2': Read the external input file to obtain excitation data;

[0062] Step S3: The data processing module processes the data;

[0063] Step S3': The preprocessor processes the data;

[0064] Step S4: The MIPI physical digital-to-analog hybrid interface converts the data;

[0065] Step S5: Simulation verification;

[0066] Step S6: Comparison of simulation results.

[0067] Exemplarily, first build a simulation verification test platform for the MIPI-DSI protocol. The simulation verification test platform for the MIPI-DSI protocol includes: a DSI agent, a DPHY model, a MIPI physical digital-analog hybrid interface, a data generator, a top-level configurator, a comparator, a data input interface, a data output interface, and other components. Among them, the DSI agent includes an exciter, a DSI configurator, a driver, and a monitor, and the DPHY model includes a clock channel and a data channel. When the simulation platform starts running, first confirm the source of the excitation method. First, select the external excitation method. By reading the pixel content of the image data and the register configuration information of the external input file, the preliminary setting of the simulation verification test platform for the MIPI-DSI protocol is realized; the information read from the external input file is integrated into a serial data stream through a preprocessor, and the pixel content and register configuration information are forcibly connected to the MIPI physical digital-analog hybrid interface through the data input interface for simulation verification, and the simulation data, data analysis results and other file contents are automatically output and stored in a specified directory for archiving and storage. Second, select the internal excitation method. The data generator generates data packets such as pixel content of image data, register configuration information, and simulation environment settings. The simulation environment instantiates models, configures the environment, etc. through the above information for pre-simulation initialization work; after the register transfer level module runs the simulation script, the simulation verification of the MIPI test case is carried out, and the simulation data, data analysis results and other file contents are automatically output and stored in a specified directory for archiving and storage, or the simulation verification process is directly ended. In addition, for the internal excitation method, the external excitation method can be directly adopted to directly set the simulation environment, forcibly input data packets such as pixel content of image data, register configuration information, and platform environment settings, and then carry out simulation verification and result comparison.

[0068] This application also provides a Figure 4The simulation verification test platform 22 for the MIPI-DSI protocol shown includes: a top-level configurator 26, which is used to confirm the excitation mode and generate information characterizing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from the data input interface 28, and the internal excitation mode is a mode of generating excitation data by itself; a data generator 24, the input end of the data generator 24 is connected to the output end of the top-level configurator 26. The data generator 24 is used to generate first excitation data when receiving information characterizing the excitation mode as the internal excitation mode. The first excitation data at least includes configuration information of simulation environment variables; a data processing module, the input end of the data processing module is connected to the output end of the data generator 24. The data processing module is used to generate a first serial data stream according to the first excitation data. The first serial data stream is a serial data stream of the MIPI-DSI protocol; an MIPI physical digital-analog hybrid interface 44, the input end of the MIPI physical digital-analog hybrid interface 44 is connected to the output end of the data processing module, and is used to receive the first serial data stream and convert the first serial data stream into a first digital signal; a register transfer level module 46, the input end of the register transfer level module 46 is connected to the output end of the MIPI physical digital-analog hybrid interface 44, and is used to perform simulation verification on the chip of the MIPI-DSI protocol according to the first digital signal.

[0069] In the embodiment, the built simulation verification test platform 22 for the MIPI-DSI protocol can randomly generate excitation data by using the internal excitation mode according to actual needs, or can perform tests for specific test scenarios and boundary conditions by using the external excitation mode, making the simulation verification test of the MIPI-DSI protocol chip more flexible.

[0070] Specifically, the configuration information includes the number of instances of each component.

[0071] Specifically, the first excitation data further includes the pixel content of the image data and the register configuration information required during the simulation process. The generation of the excitation data by itself is the generation of excitation data by the internal excitation library.

[0072] In an optional solution, the data input interface is further used to read an external input file to obtain second excitation data when receiving information characterizing the excitation mode as the external excitation mode sent by the top-level configurator. The second excitation data at least includes image data and the register configuration information of the chip. The simulation platform further includes:

[0073] A preprocessor, the input end of the preprocessor is connected to the output end of the data input interface. The preprocessor is configured to, when receiving the second excitation data sent by the data input interface, integrate the second excitation data into a second serial data stream. The second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal.

[0074] A MIPI physical digital-to-analog hybrid interface, the input end of the MIPI physical digital-to-analog hybrid interface is connected to the output end of the preprocessor. The MIPI physical digital-to-analog hybrid interface is configured to, when receiving the second serial data stream sent by the preprocessor, convert the second serial data stream into a second digital signal.

[0075] The register transfer level module is further configured to, when receiving the second digital signal sent by the MIPI physical digital-to-analog hybrid interface, configure the simulation environment according to the signal in the second digital signal that represents the register configuration information of the chip, generate register transfer level source code according to the signal in the second digital signal that represents the image data, load the register transfer level source code into the simulation environment, run the simulation environment, and perform simulation verification on the chip.

[0076] In the embodiment, the external excitation method can directly read an external input file, can set a test scenario targeted, can cover more test cases, and further enhances the flexibility of the verification process.

[0077] Specifically, the external input file can be set targeted according to the simulation result.

[0078] In another alternative solution, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module is further configured to generate a first serial data stream according to the first excitation data. The DSI configurator is configured to generate configuration content, and the configuration content includes a pixel format, a resolution, and a frame rate. The exciter is configured to, when receiving the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, encapsulate the first excitation data into a DSI protocol packet according to the MIPI-DSI protocol and the configuration content. The driver is configured to, when receiving the DSI protocol packet sent by the exciter, parse the DSI protocol packet and encapsulate and pack the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol. The DPHY model is configured to, when receiving the DPHY protocol packet sent by the driver, decompose the DPHY protocol packet into the first serial data stream.

[0079] In the described embodiment, through the DSI agent and DPHY model in the data processing module, flexible configuration, protocol encapsulation, and data decomposition and serialization of the first excitation data are achieved, thereby ensuring accurate and efficient simulation of the data transmission process and providing a solid foundation for subsequent test verification.

[0080] Specifically, the DPHY model includes a clock channel and a data channel, which cooperate to perform data transmission tasks.

[0081] In another alternative solution, the DSI agent further includes: a monitor for real-time acquisition of the DSI protocol packet, extraction of key data in the DSI protocol packet, and encapsulation and packaging of the key data into a key data packet, where the key data at least includes a data identifier and payload data; a comparator for receiving the key data packet sent by the monitor, comparing the key data packet with an expected key data packet, and generating a first comparison result, where the expected key data packet represents a protocol packet with a correct data format and correct data content, and the first comparison result is a result representing the correctness of the data format and data content of the key data packet; and a data output interface for outputting the first comparison result.

[0082] In the described embodiment, the monitor can real-time acquire the DSI protocol packet sent by the exciter, extract and package the key data in the DSI protocol packet, and send the key data packet to the comparator for comparison, ensuring that each DSI protocol packet in the data transmission process can be recorded and monitored in a timely manner. The comparator compares the received key data packet with the expected key data packet to accurately determine whether the actually transmitted data packet matches the expectation, thereby effectively identifying possible deviations or errors in the data during transmission. The result of the comparison is output through the data output interface, enabling testers to immediately obtain the result of the data comparison and providing direct feedback and basis for subsequent test verification and fault troubleshooting.

[0083] Specifically, the test result can be stored in a specified file or database through specific simulation parameters and configurations.

[0084] In another alternative solution, after the register transfer level module performs simulation verification on the chip, it is further used to generate a first simulation result and a configuration file. The first simulation result includes a first test waveform and first image test data. The first test waveform is a waveform representing the change of the signals of the chip over time during the simulation verification process, and the first image test data is data representing image quality. The configuration file includes the first excitation data or the second excitation data. The simulation verification test platform for the MIPI-DSI protocol further includes:

[0085] An FPGA prototype for generating a second simulation result according to the configuration file, the second simulation result including a second test waveform and second image test data, the second test waveform being a waveform of the signal of the FPGA prototype changing with time in the simulation environment corresponding to the configuration file, and the second image test data being data characterizing the image quality processed by the FPGA prototype;

[0086] A verification module for comparing the first simulation result with the second simulation result to generate a second comparison result, the second comparison result being a result characterizing the degree of consistency between the simulation verification and the FPGA prototype test;

[0087] A data output interface for outputting the second comparison result and receiving a third simulation result, the third simulation result including a third test waveform and third image test data, the third test waveform being a waveform of the signal obtained by testing a physical chip in the simulation environment corresponding to the configuration file, and the third image test data being data characterizing the image quality processed by the physical chip;

[0088] The verification module is further configured to compare the first simulation result with the third simulation result to generate a third comparison result, the third comparison result being a result characterizing the degree of consistency between the simulation verification and the physical chip test.

[0089] In another alternative solution, the simulation verification test platform for the MIPI-DSI protocol further includes: a data output interface for outputting the first simulation result generated by the register transfer level module after the simulation verification is completed.

[0090] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the simulation verification test method for the MIPI-DSI protocol of the present application will be described in detail below with reference to specific embodiments.

[0091] Such as Figure 4As shown in the figure, the top-level environment of the simulation verification test platform 22 for the MIPI-DSI protocol uses the uvm library source code to establish a basic verification platform. Inside the platform, module program components such as a DSI agent 52, a DPHY model 54, a MIPI physical digital-analog hybrid interface 44, a data generator 24, a top-level configurator 26, a comparator 48, a data input interface 28, and a data output interface 50 are instantiated. The top-level configurator 26 is responsible for configuring top-level environment variables, the number of component instantiations, and basic function enable switches, etc., and is also responsible for configuring the image pixel content type to control the data generator 24 component. The data generator 24 is a UVM image database that contains various image data generation mechanisms and is responsible for generating various common and special test image data such as random images, solid-color images, grayscale images, checkerboard images, slashes, and crosshairs. This stimulus library ensures the accurate generation of image stimulus data, reduces the work of personnel coding and debugging, and the project iteration time, while improving the stability and reliability of the verification platform. The generated test image data will be passed to the DSI agent 52. The DSI agent 52 is an important component for implementing the DSI protocol. The stimulator 32 in the DSI agent 52 will generate DSI protocol packets according to the MIPI-DSI protocol and the configuration content of the DSI configurator 34, parse the DSI protocol packets through the driver 36, and encapsulate and pack the DSI protocol packets into DPHY protocol packets according to the DPHY protocol, and send the DPHY protocol data packets to the DPHY model 54; at the same time, the monitor 38 will continuously monitor the behavior of the driver 36 and send the monitored image data packets to the comparator 48 for image data and configuration data analysis and comparison. The DPHY model 54 receives the DPHY protocol data packets, decomposes and packs the image data packets into a serial data stream according to the MIPI-DPHY protocol, and under the cooperation of the clock channel 40 and the data channel 42, sends the data stream to the MIPI physical digital-analog hybrid interface 44. The MIPI physical digital-analog hybrid interface 44 includes a verilog-HDL model and an analog high-speed circuit extraction file. These two modules implement the digital circuit and analog circuit hybrid handover process of the serial data stream and test the basic functions of the digital circuit and the analog circuit from the aspect of simulation verification. Finally, the data stream passing through the MIPI physical digital-analog hybrid interface 44 enters the register transfer level module 46 to complete the simulation verification work of the MIPI-DSI protocol part of the entire timing control chip. In order to achieve diversified data excitation methods, this solution adds a method of forcibly accessing excitation data from the data input interface 28 to accelerate the simulation verification process and quickly realize the direct forced transfer of the image data stream, thereby reducing the simulation time and cost during the verification process and facilitating the project iteration and update work.The specific implementation method is as follows: The data input interface 28 reads the image data pixels and register configuration information of the external input file to initially set the simulation platform environment; the simulation verification test platform 22 of the MIPI-DSI protocol automatically integrates the pixel content and register configuration information into the MIPI-DSI protocol serial image data stream through the preprocessor 30 and forcibly accesses it to the MIPI physical digital-to-analog hybrid interface 44 to implement forced operation on the interface; finally, the data stream passing through the MIPI physical digital-to-analog hybrid interface 44 enters the register transfer level module 46 to complete the simulation verification work of the MIPI-DSI protocol part of the entire timing control chip. After the simulation verification of the two excitation methods is completed, files such as simulation data, data analysis results, and data record information will be automatically output, stored in the specified directory, and archived and saved. As. Figure 5 As shown, after the register transfer level module 46 passes the simulation verification, it generates a configuration file 62 to provide to the FPGA prototype test 56 to achieve accurate and seamless docking of the register configuration data; at the same time, it will also confirm the waveforms and data information of the FPGA prototype test 56 with the register transfer level module 46 to mutually verify the MIPI-DSI simulation test results; similarly, after the timing control chip is fabricated and returned, the chip system test 60 operation process is carried out, and the test waveforms, data information, and the register transfer level module 46 are used to confirm the results and mutually verify the MIPI-DSI simulation test results. Finally, through the analysis of the test results in three aspects and multi-dimensional simulation verification and confirmation, the reliability, accuracy, and flexibility of the MIPI-DSI protocol verification test are improved to meet the requirements of project simulation verification and R & D iteration.

[0092] The embodiment of the present invention provides a computer-readable storage medium, and the computer-readable storage medium includes a stored program, wherein when the program runs, it controls the device where the computer-readable storage medium is located to execute the simulation verification test method of the MIPI-DSI protocol.

[0093] Specifically, the simulation verification test method of the MIPI-DSI protocol includes:

[0094] Step S201, the top-level configurator confirms the excitation method and generates information representing the excitation method. The excitation method includes an external excitation method and an internal excitation method. The external excitation method is a method of receiving excitation data from the data input interface, and the internal excitation method is a method of self-generating excitation data;

[0095] Step S202, when the data generator receives the information sent by the top-level configurator representing that the excitation method is the internal excitation method, it generates first excitation data, and the first excitation data includes at least the configuration information of the simulation environment variables;

[0096] In step S203, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data, and the first serial data stream is a serial data stream of the MIPI-DSI protocol;

[0097] In step S204, the MIPI physical digital-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal;

[0098] In step S205, when the register transfer level module receives the MIPI physical digital-analog hybrid interface, it performs simulation verification on the MIPI-DSI protocol chip according to the first digital signal.

[0099] Specifically, the first excitation data further includes the pixel content of the image data and the register configuration information required during the simulation process, and the self-generated excitation data is the excitation data generated by the internal excitation library.

[0100] Optionally, the method further includes: when the data input interface receives the information sent by the top-level configurator indicating that the excitation mode is the external excitation mode, it reads an external input file to obtain second excitation data, and the second excitation data at least includes image data and the register configuration information of the chip; when the pre-processor receives the second excitation data sent by the data input interface, it integrates the second excitation data into a second serial data stream, and the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; when the MIPI physical digital-analog hybrid interface receives the second serial data stream sent by the pre-processor, it converts the second serial data stream into a second digital signal; when the register transfer level module receives the second digital signal sent by the MIPI physical digital-analog hybrid interface, it configures the simulation environment according to the signal indicating the register configuration information of the chip in the second digital signal, generates register transfer level source code according to the signal indicating the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

[0101] Optionally, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module generates a first serial data stream according to the first excitation data, including: the DSI configurator generates configuration content, which includes pixel format, resolution, and frame rate; when the exciter receives the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, according to the MIPI-DSI protocol and the configuration content, the exciter encapsulates the first excitation data into a DSI protocol packet; when the driver receives the DSI protocol packet sent by the exciter, the driver parses the DSI protocol packet and encapsulates and packages the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; when the DPHY model receives the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data stream.

[0102] Optionally, the DSI agent further includes a monitor. After the exciter sends the DSI protocol packet, the method further includes: the monitor obtains the DSI protocol packet in real time, extracts key data in the DSI protocol packet, and encapsulates and packages the key data into a key data packet. The key data at least includes a data identifier and payload data; a comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, and generates a first comparison result. The expected key data packet represents a protocol packet with a correct data format and correct data content, and the first comparison result is a result representing the correctness of the data format and data content of the key data packet; a data output interface outputs the first comparison result.

[0103] Optionally, the method further includes: after the register transfer level module performs simulation verification on the chip, generating a first simulation result and a configuration file, where the first simulation result includes a first test waveform and first image test data, the first test waveform is a waveform characterizing the change of the signals of the chip over time during the simulation verification process, the first image test data is data characterizing the image quality, and the configuration file includes first excitation data or second excitation data; the FPGA prototype generates a second simulation result according to the configuration file, the second simulation result includes a second test waveform and second image test data, the second test waveform is a waveform characterizing the change of the signals of the FPGA prototype over time in the simulation environment corresponding to the configuration file, and the second image test data is data characterizing the image quality of the image processed by the FPGA prototype; the verification module compares the first simulation result with the second simulation result to generate a second comparison result, and the second comparison result is a result characterizing the degree of consistency between the simulation verification and the FPGA prototype test; the data output interface outputs the second comparison result and receives a third simulation result, the third simulation result includes a third test waveform and third image test data, the third test waveform is a waveform characterizing the change of the signals of the physical chip over time tested in the simulation environment corresponding to the configuration file, and the third image test data is data characterizing the image quality of the image processed by the physical chip; the verification module compares the first simulation result with the third simulation result to generate a third comparison result, and the third comparison result is a result characterizing the degree of consistency between the simulation verification and the physical chip test.

[0104] Optionally, after the simulation verification is completed, the method further includes: the data output interface outputs the first simulation result generated by the register transfer level module.

[0105] The present application also provides a computer program product, including computer instructions, and when the computer instructions are executed by a processor, at least the following method steps are implemented:

[0106] Step S201, the top-level configurator confirms the excitation mode and generates information characterizing the excitation mode, where the excitation mode includes an external excitation mode and an internal excitation mode, the external excitation mode is a mode of receiving excitation data from the data input interface, and the internal excitation mode is a mode of generating excitation data by itself;

[0107] Step S202, when the data generator receives the information sent by the top-level configurator characterizing that the excitation mode is the internal excitation mode, it generates first excitation data, and the first excitation data at least includes configuration information of simulation environment variables;

[0108] Step S203, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data, and the first serial data stream is a serial data stream of the MIPI-DSI protocol;

[0109] Step S204, the MIPI physical digital-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal;

[0110] Step S205, when the register transfer level module receives the MIPI physical digital-analog hybrid interface, it performs simulation verification on the MIPI-DSI protocol chip according to the first digital signal.

[0111] Specifically, the first excitation data further includes the pixel content of the image data and the register configuration information required during the simulation process, and the self-generated excitation data is the excitation data generated by the internal excitation library.

[0112] Optionally, the method further includes: when the data input interface receives the information sent by the top-level configurator indicating that the excitation method is the external excitation method, it reads an external input file to obtain second excitation data, and the second excitation data at least includes image data and the register configuration information of the chip; when the pre-processor receives the second excitation data sent by the data input interface, it integrates the second excitation data into a second serial data stream, and the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; when the MIPI physical digital-analog hybrid interface receives the second serial data stream sent by the pre-processor, it converts the second serial data stream into a second digital signal; when the register transfer level module receives the second digital signal sent by the MIPI physical digital-analog hybrid interface, it configures the simulation environment according to the signal representing the register configuration information of the chip in the second digital signal, generates register transfer level source code according to the signal representing the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

[0113] Optionally, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module generates a first serial data stream according to the first excitation data, including: the DSI configurator generates configuration content, which includes pixel format, resolution, and frame rate; when the exciter receives the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, according to the MIPI-DSI protocol and the configuration content, the exciter encapsulates the first excitation data into a DSI protocol packet; when the driver receives the DSI protocol packet sent by the exciter, the driver parses the DSI protocol packet and encapsulates and packs the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; when the DPHY model receives the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data stream.

[0114] Optionally, the DSI agent further includes a monitor. After the exciter sends the DSI protocol packet, the method further includes: the monitor obtains the DSI protocol packet in real time, extracts key data in the DSI protocol packet, and encapsulates and packs the key data into a key data packet. The key data at least includes a data identifier and payload data; a comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, and generates a first comparison result. The expected key data packet represents a protocol packet with a correct data format and correct data content. The first comparison result is a result representing the correctness of the data format and data content of the key data packet; a data output interface outputs the first comparison result.

[0115] Optionally, the method further includes: after the register transfer level module performs simulation verification on the chip, generating a first simulation result and a configuration file, where the first simulation result includes a first test waveform and first image test data, the first test waveform is a waveform representing the change of signals of the chip over time during the simulation verification process, the first image test data is data representing image quality, and the configuration file includes first excitation data or second excitation data; the FPGA prototype generates a second simulation result according to the configuration file, the second simulation result includes a second test waveform and second image test data, the second test waveform is a waveform representing the change of signals of the FPGA prototype over time in the simulation environment corresponding to the configuration file, and the second image test data is data representing the image quality processed by the FPGA prototype; the verification module compares the first simulation result with the second simulation result to generate a second comparison result, and the second comparison result is a result representing the degree of consistency between the simulation verification and the FPGA prototype test; the data output interface outputs the second comparison result and receives a third simulation result, the third simulation result includes a third test waveform and third image test data, the third test waveform is a waveform representing the change of signals obtained by testing the physical chip in the simulation environment corresponding to the configuration file, and the third image test data is data representing the image quality processed by the physical chip; the verification module compares the first simulation result with the third simulation result to generate a third comparison result, and the third comparison result is a result representing the degree of consistency between the simulation verification and the physical chip test.

[0116] Optionally, after the simulation verification ends, the method further includes: the data output interface outputs the first simulation result generated by the register transfer level module.

[0117] An embodiment of the present invention provides a device, which includes a processor, a memory, and a program stored on the memory and executable on the processor. When the processor executes the program, it implements at least the following steps:

[0118] Step S201, the top-level configurator confirms the excitation mode and generates information representing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from the data input interface, and the internal excitation mode is a mode of generating excitation data by itself;

[0119] Step S202, when the data generator receives the information sent by the top-level configurator representing that the excitation mode is the internal excitation mode, it generates first excitation data, and the first excitation data includes at least configuration information of simulation environment variables;

[0120] Step S203, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data, and the first serial data stream is a serial data stream of the MIPI-DSI protocol;

[0121] Step S204, the MIPI physical digital-to-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal;

[0122] Step S205, when the register transfer level module receives the MIPI physical digital-to-analog hybrid interface, it performs simulation verification on the MIPI-DSI protocol chip according to the first digital signal.

[0123] Specifically, the first excitation data further includes the pixel content of the image data and the register configuration information required during the simulation process, and the self-generated excitation data is the excitation data generated by the internal excitation library.

[0124] The device in this article can be a server, PC, PAD, mobile phone, etc.

[0125] Optionally, the method further includes: when the data input interface receives the information sent by the top-level configurator indicating that the excitation mode is the external excitation mode, it reads an external input file to obtain second excitation data, and the second excitation data at least includes image data and the register configuration information of the chip; when the pre-processor receives the second excitation data sent by the data input interface, it integrates the second excitation data into a second serial data stream, and the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; when the MIPI physical digital-to-analog hybrid interface receives the second serial data stream sent by the pre-processor, it converts the second serial data stream into a second digital signal; when the register transfer level module receives the second digital signal sent by the MIPI physical digital-to-analog hybrid interface, it configures the simulation environment according to the signal representing the register configuration information of the chip in the second digital signal, generates register transfer level source code according to the signal representing the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

[0126] Optionally, the data processing module includes a DSI agent and a DPHY model. The DSI agent includes an exciter, a driver, and a DSI configurator. The data processing module generates a first serial data stream according to the first excitation data, including: the DSI configurator generates configuration content, which includes pixel format, resolution, and frame rate; when the exciter receives the first excitation data sent by the data generator and the configuration content sent by the DSI configurator, according to the MIPI-DSI protocol and the configuration content, the exciter encapsulates the first excitation data into a DSI protocol packet; when the driver receives the DSI protocol packet sent by the exciter, the driver parses the DSI protocol packet and encapsulates and packs the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; when the DPHY model receives the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data stream.

[0127] Optionally, the DSI agent further includes a monitor. After the exciter sends the DSI protocol packet, the method further includes: the monitor real-time obtains the DSI protocol packet and extracts key data in the DSI protocol packet, and encapsulates and packs the key data into a key data packet. The key data at least includes a data identifier and payload data; a comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, and generates a first comparison result. The expected key data packet represents a protocol packet with a correct data format and correct data content. The first comparison result is a result representing the correctness of the data format and data content of the key data packet; a data output interface outputs the first comparison result.

[0128] Optionally, the method further includes: after the register transfer level module performs simulation verification on the chip, generating a first simulation result and a configuration file, where the first simulation result includes a first test waveform and first image test data, the first test waveform is a waveform representing the change of signals of the chip over time during the simulation verification process, the first image test data is data representing image quality, and the configuration file includes first excitation data or second excitation data; the FPGA prototype generates a second simulation result according to the configuration file, the second simulation result includes a second test waveform and second image test data, the second test waveform is a waveform representing the change of signals of the FPGA prototype over time in the simulation environment corresponding to the configuration file, and the second image test data is data representing the image quality processed by the FPGA prototype; the verification module compares the first simulation result with the second simulation result to generate a second comparison result, and the second comparison result is a result representing the consistency degree between the simulation verification and the FPGA prototype test; the data output interface outputs the second comparison result and receives a third simulation result, the third simulation result includes a third test waveform and third image test data, the third test waveform is a waveform representing the change of signals obtained by testing the physical chip in the simulation environment corresponding to the configuration file, and the third image test data is data representing the image quality processed by the physical chip; the verification module compares the first simulation result with the third simulation result to generate a third comparison result, and the third comparison result is a result representing the consistency degree between the simulation verification and the physical chip test.

[0129] Optionally, after the simulation verification is completed, the method further includes: the data output interface outputs the first simulation result generated by the register transfer level module.

[0130] Obviously, those skilled in the art should understand that each module or each step of the present invention can be implemented by a general computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order from here, or they can be separately made into individual integrated circuit modules, or multiple modules or steps among them can be made into a single integrated circuit module to implement. In this way, the present invention is not limited to any specific combination of hardware and software.

[0131] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code.

[0132] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the specified functions in Figure 1 one or more of the processes Figure 1 or multiple processes and / or blocks

[0133] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the specified functions in Figure 1 one or more of the processes Figure 1 or multiple processes and / or blocks

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the specified functions in Figure 1 one or more of the processes Figure 1 or multiple processes and / or blocks

[0135] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0136] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0137] A computer-readable medium includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information accessible by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0138] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0139] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0140] 1), The simulation verification test method of the MIPI-DSI protocol of the present application. First, the top-level configurator confirms the excitation mode and generates information representing the excitation mode. The excitation mode includes an external excitation mode and an internal excitation mode. The external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of generating excitation data by itself. Then, when the data generator receives the information sent by the top-level configurator representing that the excitation mode is the internal excitation mode, it generates first excitation data. The first excitation data includes at least configuration information of simulation environment variables. Next, when the data processing module receives the first excitation data sent by the data generator, it generates a first serial data stream according to the first excitation data. The first serial data stream is a serial data stream of the MIPI-DSI protocol. After that, the MIPI physical digital-analog hybrid interface receives the first serial data stream sent by the data processing module and converts the first serial data stream into a first digital signal. Finally, when the register transfer level module receives the MIPI physical digital-analog hybrid interface, it performs simulation verification on the chip of the MIPI-DSI protocol according to the first digital signal. By combining the two excitation modes, the present application can randomly generate excitation data using the internal excitation mode according to actual needs, or use the external excitation mode to test specific test scenarios and boundary conditions, making the simulation verification test of the MIPI-DSI protocol chip more flexible.

[0141] 2), The simulation verification test platform of the MIPI-DSI protocol of the present application. The built simulation verification test platform of the MIPI-DSI protocol can randomly generate excitation data using the internal excitation mode according to actual needs, or use the external excitation mode to test specific test scenarios and boundary conditions, making the simulation verification test of the MIPI-DSI protocol chip more flexible.

[0142] The foregoing are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A simulation verification test method for MIPI-DSI protocol, characterized in that: include: The top-level configurator confirms the excitation mode and generates information characterizing the excitation mode, wherein the excitation mode includes an external excitation mode and an internal excitation mode, wherein the external excitation mode is a mode of receiving excitation data from a data input interface, and the internal excitation mode is a mode of generating excitation data by itself; The data generator generates first excitation data when receiving the information sent by the top-level configurator indicating that the excitation mode is the internal excitation mode, wherein the first excitation data at least includes configuration information of simulation environment variables; The data processing module generates a first serial data code stream according to the first excitation data when receiving the first excitation data sent by the data generator, wherein the first serial data code stream is a serial data code stream of the MIPI-DSI protocol; The MIPI physical digital-analog hybrid interface receives the first serial data code stream sent by the data processing module, and converts the first serial data code stream into a first digital signal; When receiving the MIPI physical digital-analog hybrid interface, the register transfer level module simulates and verifies the chip of the MIPI-DSI protocol according to the first digital signal.

2. The method according to claim 1, characterized in that: The method further comprises: The data input interface, when receiving the information sent by the top-level configurator indicating that the excitation mode is the external excitation mode, reads the external input file to obtain second excitation data, wherein the second excitation data at least includes image data and register configuration information of the chip; The preprocessor integrates the second excitation data into a second serial data stream when receiving the second excitation data sent by the data input interface, wherein the second serial data stream is a serial data stream of the MIPI-DSI protocol, and the second serial data stream is an analog signal; The MIPI physical digital-analog hybrid interface converts the second serial data code stream into a second digital signal when receiving the second serial data code stream sent by the preprocessor; When the register transfer level module receives the second digital signal sent by the MIPI physical digital-analog hybrid interface, the register transfer level module configures the simulation environment according to the signal representing the register configuration information of the chip in the second digital signal, generates a register transfer level source code according to the signal representing the image data in the second digital signal, loads the register transfer level source code into the simulation environment, runs the simulation environment, and performs simulation verification on the chip.

3. The method according to claim 1, characterized in that: The data processing module includes a DSI agent and a DPHY model, the DSI agent includes an exciter, a driver and a DSI configurator, and the data processing module generates a first serial data code stream according to the first excitation data, including: The DSI configurator generates configuration content, the configuration content including pixel format, resolution and frame rate; Upon receiving the first stimulus data sent by the data generator and the configuration content sent by the DSI configurator, the exciter encapsulates the first stimulus data into a DSI protocol packet according to the MIPI-DSI protocol and the configuration content; When receiving the DSI protocol packet sent by the actuator, the driver parses the DSI protocol packet and encapsulates and packages the DSI protocol packet into a DPHY protocol packet according to the DPHY protocol; When receiving the DPHY protocol packet sent by the driver, the DPHY model decomposes the DPHY protocol packet into the first serial data code stream.

4. The method according to claim 3, characterized in that The DSI agent further includes a monitor. After the activator sends the DSI protocol packet, the method further includes: The monitor acquires the DSI protocol packet in real time, extracts key data in the DSI protocol packet, and encapsulates and packages the key data into a key data packet, wherein the key data at least includes a data identifier and payload data; The comparator receives the key data packet sent by the monitor, compares the key data packet with an expected key data packet, and generates a first comparison result, wherein the expected key data packet represents a protocol packet with a correct data format and correct data content, and the first comparison result represents the correctness of the data format and data content of the key data packet; The data output interface outputs the first comparison result.

5. The method according to claim 1 or 2, characterized in that: The method further comprises: After simulating and verifying the chip, the register transfer level module generates a first simulation result and a configuration file, wherein the first simulation result includes a first test waveform and first image test data, wherein the first test waveform is a waveform representing a change of a signal of the chip over time during the simulation verification process, the first image test data is data representing image quality, and the configuration file includes first stimulus data or second stimulus data; The FPGA prototype generates a second simulation result according to the configuration file, the second simulation result includes a second test waveform and second image test data, the second test waveform is a waveform of a signal of the FPGA prototype changing over time under the simulation environment corresponding to the configuration file, and the second image test data is data representing the quality of an image processed by the FPGA prototype; The verification module compares the first simulation result with the second simulation result to generate a second comparison result, where the second comparison result is a result that characterizes the consistency between the simulation verification and the FPGA prototype test; The data output interface outputs the second comparison result and receives a third simulation result, wherein the third simulation result includes a third test waveform and third image test data, wherein the third test waveform is a waveform of a signal variation over time obtained by testing the physical chip under the simulation environment corresponding to the configuration file, and the third image test data is data representing the quality of an image processed by the physical chip; The verification module compares the first simulation result with the third simulation result to generate a third comparison result, where the third comparison result is a result that characterizes the consistency between the simulation verification and the physical chip test.

6. The method according to any one of claims 1 to 4, characterized in that After the simulation verification is completed, the method further includes: The data output interface outputs the first simulation result generated by the register transfer level module.

7. A simulation verification test platform for the MIPI-DSI protocol, characterized in that: include: The top-level configurator is used to confirm the excitation mode and generate information representing the excitation mode, wherein the excitation mode includes an external excitation mode and an internal excitation mode, wherein the external excitation mode is a mode of receiving excitation data from a data input interface and the internal excitation mode is a mode of generating excitation data by itself; A data generator, wherein an input end of the data generator is connected to an output end of the top-level configurator, and the data generator is used to generate first excitation data when receiving information indicating that the excitation mode is the internal excitation mode, wherein the first excitation data at least includes configuration information of simulation environment variables; A data processing module, wherein an input end of the data processing module is connected to an output end of the data generator, and the data processing module is used to generate a first serial data code stream according to the first excitation data, wherein the first serial data code stream is a serial data code stream of the MIPI-DSI protocol; A MIPI physical digital-analog hybrid interface, the input end of which is connected to the output end of the data processing module, and is used to receive the first serial data code stream and convert the first serial data code stream into a first digital signal; A register transfer level module, the input end of which is connected to the output end of the MIPI physical digital-analog hybrid interface, and is used to simulate and verify the chip of the MIPI-DSI protocol according to the first digital signal.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 6.

9. A computer program product comprising computer instructions, characterized in that When the computer instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include methods for executing any one of claims 1 to 6.

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