Solar cell and method of manufacturing the same

Abstract

The application relates to the technical field of solar cells, and discloses a solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a plated silicon wafer; forming an initial grid line on at least one side surface of the plated silicon wafer, and forming an alloy layer on the surface of the plated silicon wafer in contact with the initial grid line; performing oxidation treatment on part of the surface of the initial grid line to form an oxidation layer on the initial grid line; and removing the oxidation layer to form a grid line on the plated silicon wafer, wherein the projection area of the grid line on the plated silicon wafer is smaller than the projection area of the alloy layer on the plated silicon wafer. The initial grid line with a relatively large density is prepared first, the alloy layer with a relatively large area is formed on the plated silicon wafer to realize confluence, and the electrical performance is ensured; then the initial grid line is locally removed after oxidation treatment, the grid line with a smaller projection area than the alloy layer is obtained, the light-shielding loss is effectively reduced, the optical performance is improved, the electrical performance is not affected, and the photoelectric conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically to a solar cell and its fabrication method. Background Technology

[0002] With the rapid development of the photovoltaic industry, the key to further promoting photovoltaic applications is to improve the photoelectric conversion efficiency of solar cells and reduce production costs. The fabrication process of solar cells includes printing paste onto the surface of the solar cell to form grid lines. These grid lines typically include main grid lines and sub-grid lines. The sub-grid lines are densely distributed on the surface of the cell to collect internal charge carriers, while the main grid lines connect to the sub-grid lines to achieve a current collection function.

[0003] Generally, the factors affecting the photoelectric conversion efficiency of solar cells can be attributed to two aspects: electrical performance and optical performance. The shading loss of the grid lines on the front side of the solar cell is currently a significant obstacle to improving optical performance. Related technologies reduce shading loss and improve optical performance by narrowing the linewidth of the screen used to print the grid lines, while also reducing paste content and costs. However, extremely narrow grid lines can easily lead to a reduction in the contact area between the grid lines and the solar cell, causing printing yield problems such as broken grids, incomplete printing, and missing printing. This affects the carrier collection performance inside the solar cell, thus impacting the electrical performance of the solar cell, and also increases the difficulty of screen development and fabrication. Summary of the Invention

[0004] In view of this, the present invention provides a method for fabricating grid lines of a solar cell to solve the problem that existing solar cells are unable to simultaneously achieve electrical and optical performance.

[0005] In a first aspect, the present invention provides a method for preparing a solar cell, comprising:

[0006] Provide coated silicon wafers;

[0007] An initial gate line is formed on at least one side surface of the coated silicon wafer, so that an alloy layer is formed on the surface of the coated silicon wafer that is in contact with the initial gate line;

[0008] A portion of the surface of the initial gate line is oxidized to form an oxide layer on the initial gate line;

[0009] The oxide layer is removed to form gate lines on the coated silicon wafer. The projected area of ​​the gate lines on the coated silicon wafer is smaller than the projected area of ​​the alloy layer on the coated silicon wafer.

[0010] Beneficial Effects: The solar cell fabrication method of this invention first prepares a high-density initial grid line on a coated silicon wafer. This ensures that the alloy layer area formed when the initial grid line makes ohmic contact with the silicon substrate of the coated silicon wafer is sufficiently large, thereby increasing the size of the carrier confluence channel inside the coated silicon wafer and ensuring electrical performance. Then, by oxidizing a portion of the surface of the initial grid line, the resulting oxide layer has different structural properties from the unoxidized portion. This oxide layer is easier to remove in subsequent processing, ultimately leaving grid lines with a smaller projected area on the coated silicon wafer. These grid lines are even difficult to see with the naked eye when forming a module, exhibiting an "invisible" effect. However, they can still achieve electrical connection with the solder ribbon when the cells are connected in series to form a photovoltaic module. The grid lines obtained after removing the oxide layer effectively reduce the light-shielding loss on the coated silicon wafer compared to the initial grid lines, improving optical performance without affecting electrical performance, ultimately ensuring the photoelectric conversion efficiency of the solar cell.

[0011] In one alternative embodiment, the step of oxidizing at least a portion of the surface of the initial gate line includes oxidizing the sidewalls of the initial gate line.

[0012] Beneficial effects: This invention specifically oxidizes the sidewalls of the initial gate line to form an oxide layer on both sides of the initial gate line. This facilitates the reduction of the initial gate line's width without affecting its height, ensuring that the cross-sectional area of ​​the subsequently obtained gate line is not too small. This avoids the increase in the line resistance and current loss of the gate line due to the small cross-sectional area, ultimately improving the current output efficiency.

[0013] In one alternative embodiment, oxidizing the sidewalls of the initial gate lines includes:

[0014] A protective layer is applied to a portion of the surface of the initial gate lines;

[0015] At least a portion of the surface of the initial gate line is oxidized in an oxygen-containing atmosphere.

[0016] Beneficial effects: By setting a protective layer during the oxidation process to shield areas that do not require oxidation, precise and efficient oxidation of the initial gate line sidewalls is achieved. An oxygen-containing atmosphere is initially formed on the initial gate lines on the coated silicon wafer, providing the basis for the oxidation process.

[0017] In one alternative embodiment, the oxidation process includes laser oxidation.

[0018] Beneficial effects: Compared with thermal oxidation, chemical vapor deposition oxidation and other methods, the laser oxidation process of the present invention has controllable laser precision, high precision for partial oxidation of small grid structures, fast processing speed and low cost.

[0019] In one optional embodiment, the laser oxidation treatment includes ultraviolet laser oxidation treatment, wherein the wavelength range of the ultraviolet laser is 200-400 nm, the power range of the ultraviolet laser oxidation treatment is 2-20 W, and the time range of the ultraviolet laser oxidation treatment is 1-20 s.

[0020] Beneficial effects: The ultraviolet laser used in this invention has a short wavelength and high energy. Oxygen can absorb ultraviolet light, causing oxygen molecules to turn into oxygen atoms. These oxygen atoms then combine to form ozone molecules. The high energy of the ozone molecules enables efficient and precise oxidation of the initial grid surface. Furthermore, limiting the laser oxidation power to between 2 and 20 W avoids excessive power that could directly ablate and vaporize the grid. Similarly, limiting the laser treatment time to between 1 and 20 seconds prevents excessive oxidation of the initial grid due to prolonged processing time, thus avoiding an excessively small cross-sectional area of ​​the final grid, which would increase line resistance and current loss.

[0021] In one alternative embodiment, the oxygen-containing atmosphere comprises oxygen and an inert gas, with the oxygen content ranging from 10 to 50 vol%.

[0022] Beneficial effects: Setting the oxygen content between 10 and 50 vol% ensures sufficient oxygen content during laser processing; in addition, using an inert gas in the oxygen-containing atmosphere ensures its stability, which also improves the stability and safety of the laser oxidation process.

[0023] In one alternative embodiment, removing the oxide layer includes: acid treatment of the initial gate line on which the oxide layer is formed to remove the oxide layer.

[0024] Beneficial effects: Acid treatment removes the oxide layer after oxidation treatment. For example, the entire solar cell, including the laser-treated initial grid lines, can be immersed in an acid solution, or the acid solution can be sprayed onto the oxide layer. Compared to the unoxidized portion, the oxide layer reacts with the acid solution faster in the initial grid lines. This difference in reaction rate allows for rapid and precise removal of the oxide layer located on the sidewalls of the initial grid lines. The initial grid lines become narrower, reducing light shading on the coated silicon wafer and improving the optical performance of the solar cell. Furthermore, due to the stable properties of the alloy layer and its small exposed area, the acid treatment process does not affect the current-collecting function of the alloy layer. In other words, the acid treatment process improves optical performance without affecting electrical performance, ultimately ensuring the photoelectric conversion efficiency of the solar cell.

[0025] In one optional embodiment, in the step of acid treatment of the initial gate line with the oxide layer, the oxide layer is removed by hydrochloric acid solution or nitric acid solution, the concentration of hydrochloric acid solution or nitric acid solution is in the range of 5 to 40 wt%, the temperature of acid treatment is in the range of 10 to 40°C, and the time of acid treatment is in the range of 5 to 60 s.

[0026] Beneficial effects: This invention limits the type and concentration of acid treatment solution, as well as the temperature and time of acid treatment, to avoid unnecessary reduction or damage to the grid lines caused by excessive acid treatment. At the same time, such limitations are adapted to crystalline silicon solar cells to ensure the photoelectric conversion efficiency of crystalline silicon solar cells.

[0027] In one optional embodiment, the coated silicon wafer is the coated silicon wafer in a crystalline silicon solar cell, and the grid lines are sub-grids.

[0028] Beneficial effects: This invention primarily targets crystalline silicon solar cells and is compatible with most commercially available solar cells. The grid lines mainly target the sub-grids because sub-grids are numerous in solar cells, significantly increasing light shading on the coated silicon wafer and impacting optical performance. Furthermore, the sub-grids require ohmic contact with the silicon substrate through sintering, also significantly affecting electrical performance. Therefore, improving the sub-grids can greatly enhance both the optical and electrical performance of the solar cell.

[0029] Secondly, the present invention also provides a solar cell, which is prepared by the above-described method for preparing a solar cell, comprising: a coated silicon wafer, grid lines and an alloy layer, wherein the grid lines are disposed on one side surface of the coated silicon wafer; the alloy layer is formed between the coated silicon wafer and the grid lines, and the projected area of ​​the grid lines on the coated silicon wafer is smaller than the projected area of ​​the alloy layer on the coated silicon wafer.

[0030] Beneficial effects: In the solar cell of the present invention, the area of ​​the alloy layer formed first, which serves as the carrier confluence channel inside the silicon wafer after coating, is larger than the area of ​​the grid lines finally obtained later. The alloy layer area is large enough to help ensure the electrical performance of the solar cell. The projected area of ​​the grid lines retained on the silicon wafer after coating is smaller than the projected area of ​​the alloy layer. That is, the grid lines in this embodiment are thinner than the grid lines in the conventional scheme, resulting in less shading of the silicon wafer after coating. This effectively reduces the shading loss of the silicon wafer after coating and improves the optical performance. The large alloy layer and the small grid lines take into account both the electrical and optical performance of the cell, ultimately improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic flowchart of the method for preparing a solar cell according to an embodiment of the present invention.

[0033] Figure 2 This is a partial structural schematic diagram of a solar cell after the initial grid lines are formed on a silicon wafer after coating, according to an embodiment of the present invention.

[0034] Figure 3 This is a partial structural schematic diagram of a solar cell when the initial grid lines are oxidized according to an embodiment of the present invention.

[0035] Figure 4 This is a partial structural schematic diagram of a solar cell according to an embodiment of the present invention.

[0036] Figure 5 This is a partial structural diagram of a solar cell after a protective layer is provided on the initial grid lines, according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures:

[0038] 100, Initial gate line; 101, Oxide layer; 200, Protective layer;

[0039] 1. Silicon wafer after coating; 2. Alloy layer; 3. Gate line. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the drawings, not all structures. In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the drawings. These figures are not drawn to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if one layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component can be "below" that other layer / component.

[0041] refer to Figures 1 to 5 This embodiment provides a method for preparing a solar cell. Figure 1 The diagram below illustrates the process of this preparation method, which specifically includes the following steps:

[0042] Step S101: Provide the coated silicon wafer 1.

[0043] For example, the aforementioned coated silicon wafer 1 includes a silicon substrate and a surface film layer disposed on the silicon substrate. The specific structural composition of the coated silicon wafer 1 is determined according to the type of solar cell to be fabricated. The surface film layer includes a passivation and antireflection layer and a transparent conductive oxide layer. For instance, in a tunnel oxide passivated contact (TOPCon) cell, the surface film layer on the light-receiving side of the coated silicon wafer 1 is a passivation and antireflection layer formed by stacking an aluminum oxide film and a silicon nitride film. The aluminum oxide film is deposited on the silicon wafer surface to reduce surface recombination, and the silicon nitride film is deposited on the aluminum oxide film, serving to reduce reflection and further passivate. In a heterojunction (HJT) cell, the surface film layer on the light-receiving side of the coated silicon wafer 1 is a transparent conductive oxide (TCO) layer.

[0044] In step S102, an initial gate line 100 is formed on at least one side surface of the coated silicon wafer 1, so that an alloy layer 2 is formed on the surface of the coated silicon wafer 1 that is in contact with the initial gate line 100.

[0045] refer to Figure 2 First, a corresponding paste is printed on the front or back of the coated silicon wafer 1. Then, sintering is used to react and fix the paste onto the coated silicon wafer 1. Specifically, a high-temperature sintering process is first used, with materials such as glass powder, to fuse the metallic silver in the paste with the silicon of the coated silicon wafer 1. After cooling and crystallization, an alloy layer 2 of silver-silicon alloy is formed that penetrates deep into the coated silicon wafer 1. The alloy layer 2 constitutes a large carrier transport channel, thus ensuring electrical performance. It should be noted that the aforementioned "front" refers to the light-receiving surface of the coated silicon wafer 1. The initial grid lines 100 can be set only on the front of the coated silicon wafer 1, only on the back of the coated silicon wafer 1, or simultaneously on both the front and back of the coated silicon wafer 1, depending on the type of solar cell and specific requirements. Furthermore, the initial grid lines 100 can be printed with a relatively higher printing density, resulting in a sufficiently large alloy layer 2. This increases the carrier transport channels within the coated silicon wafer 1. Even if the initial grid lines 100 cause significant light shading on the coated silicon wafer 1, the subsequent initial grid line narrowing process further reduces shading losses. Therefore, the overall performance of the solar cell will not decrease. The main purpose of this step is to ensure electrical performance. Specifically, the relatively increased printing density in this embodiment refers to a higher number of grid lines 3 compared to conventional solutions, while maintaining consistent width and height. In conventional grid lines 3, the width of the main grid is typically between 50 and 200 μm, and the height is between 10 and 50 μm; the width of the sub-grid is typically between 10 and 50 μm, and the height is between 5 and 20 μm. The specific values ​​are selected based on the actual requirements for solar cell fabrication.

[0046] The aforementioned pastes can be divided into main gate paste and sub-gate paste. The main gate paste generally serves as a current collector and does not participate in the sintering ohmic contact of the silicon wafer 1 after coating. Therefore, the main gate paste is generally non-corrosive or has low corrosivity, and the resistivity of the main gate paste in contact with the silicon substrate is greater than or equal to 10 mΩ / cm. 2 The main gate paste typically includes low-aluminum-doped silver powder, resin binder, and solvent. The aluminum content of the low-aluminum-doped silver powder is less than or equal to 0.5 wt%. The resin binder is dispersible latex powder or modified resin, and the solvent is disodium ethylenediaminetetraacetate or stearic acid. The secondary gate paste, because it needs to form an ohmic contact with the silicon substrate in the coated silicon wafer 1, often needs to have higher corrosivity. The resistivity of the secondary gate paste in contact with the silicon substrate is less than 10 mΩ / cm. 2The subgrid paste typically includes highly aluminum-doped silver powder, lead- and / or bismuth-containing glass powder as a binder, and a solvent. The aluminum content of the highly aluminum-doped silver powder is greater than or equal to 1 wt%, the total lead and / or bismuth content of the lead- and / or bismuth-containing glass powder is greater than or equal to 1 wt%, and the solvent is terpineol or methyl formate.

[0047] Furthermore, the number of main gates is typically between 10 and 30, and the number of sub-gates is typically between 100 and 300. The increased printing density described in this embodiment mainly targets the sub-gates. Of course, in other embodiments, it can also target the main gates or both the main gates and the fine gates. More sub-gates are more beneficial for electrical contact with the coated silicon wafer 1, thereby improving the collection of charge carriers inside the coated silicon wafer 1 and thus improving electrical performance. For example, the increased printing density in this embodiment can be achieved by setting the initial fine gates to 230 or 250, when the conventional scheme uses 200 fine gates.

[0048] Step S103: Oxidize a portion of the surface of the initial gate line 100 to form an oxide layer 101 on the initial gate line 100.

[0049] refer to Figure 3 The initial gate line 100 is partially oxidized to form a structural property different from other parts, thereby enabling targeted local removal. For example, the oxidation process can be thermal oxidation (including dry oxidation and wet oxidation), chemical vapor deposition (including low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition), and laser oxidation.

[0050] Step S104: Remove oxide layer 101 to form gate line 3 on silicon wafer 1 after coating. The projected area of ​​gate line 3 on silicon wafer 1 after coating is smaller than the projected area of ​​alloy layer 2 on silicon wafer 1 after coating.

[0051] For example, the oxide layer 101 on the initial grid line 100 can be locally removed by solution immersion or solution spraying, and the remaining portion of the initial grid line 100 serves as the grid line 3 of the solar cell for subsequent current extraction, such as... Figure 4As shown. Specifically, since the oxide layer 101 on the initial grid line 100 after oxidation treatment has different structural properties from the initial grid line 100 without oxidation treatment, the reaction rate of the oxide layer 101 is faster during the removal process, while the reaction rate of the unoxidized initial grid line 100 is slower. This difference in reaction rate can be used to remove the oxide layer 101 on the initial grid line 100, thereby reducing the projected area of ​​the initial grid line 100 on the coated silicon wafer 1 and reducing the light-shielding loss of the coated silicon wafer 1. However, the area of ​​the alloy layer 2, which serves as the carrier collection and merging channel of the coated silicon wafer 1, remains unchanged. Moreover, due to the stable properties of the alloy, the optical performance is greatly improved without affecting the electrical performance, thus ensuring the photoelectric conversion efficiency of the solar cell.

[0052] In summary, the solar cell fabrication method of this embodiment first prepares a high-density initial grid line 100 on the coated silicon wafer 1. This ensures that the area of ​​the alloy layer 2 formed when the initial grid line 100 makes ohmic contact with the silicon substrate of the coated silicon wafer 1 is sufficiently large, thereby increasing the size of the carrier confluence channel inside the coated silicon wafer 1 and ensuring electrical performance. Then, by oxidizing a portion of the surface of the initial grid line 100, the resulting oxide layer 101 has different structural properties from the remaining unoxidized portion. The oxide layer 101 is more easily removed in subsequent processing, ultimately leaving grid lines 3 with a smaller projected area on the coated silicon wafer 1. These grid lines 3 are even difficult to see with the naked eye when forming a module, exhibiting an "invisible" effect. However, they can still achieve electrical connection with the solder ribbon when the cells are connected in series to form a photovoltaic module. The grid lines 3 obtained after removing the oxide layer 101 effectively reduce the light-shielding loss on the coated silicon wafer 1 compared to the initial grid line 100, improving optical performance without affecting electrical performance, ultimately ensuring the photoelectric conversion efficiency of the solar cell.

[0053] Of course, the above steps S103 and S104 can be repeated multiple times according to product requirements until the required width of the gate line 3 is achieved, or the overall density of the gate line 3 is achieved.

[0054] In this embodiment, the coated silicon wafer 1 is the coated silicon wafer 1 of a crystalline silicon solar cell. That is, the solution of this embodiment is mainly for crystalline silicon solar cells and is compatible with most solar cell structures on the market. In addition, the grid line 3 is a sub-grid. This is because there are many sub-grids in the solar cell, which greatly shades the coated silicon wafer 1 and has a significant impact on optical performance. Moreover, the sub-grid needs to be sintered into ohmic contact with the silicon substrate, which also has a significant impact on electrical performance.

[0055] For example, the aforementioned crystalline silicon solar cells include various types such as conventional crystalline silicon cells, PERC cells (passivated emitter and back cell), TOPCon cells (tunneling oxide passivated contact cells), HJT cells (heterojunction cells), IBC cells (back contact cells), HBC cells (heterojunction back contact cells), and TBC cells (tunneling oxide passivated back contact cells).

[0056] In a preferred embodiment, step S103 of oxidizing at least a portion of the surface of the initial gate line 100 includes oxidizing the sidewalls of the initial gate line 100.

[0057] In other words, this embodiment specifically oxidizes the sidewalls of the initial gate line 100 to form oxide layers 101 on both sides of the initial gate line 100. This facilitates the reduction of the width dimension of the initial gate line 100 without affecting its height dimension, ensuring that the cross-sectional area of ​​the subsequently obtained gate line 3 is not too small. This avoids the increase in line resistance and current loss of the gate line 3 due to the small cross-sectional area, ultimately improving the current output efficiency.

[0058] refer to Figure 5 The above-mentioned step of oxidizing the sidewalls of the initial gate line 100 includes:

[0059] First, a protective layer 200 is formed on a portion of the surface of the initial gate line 100 that is relatively far from the silicon wafer 1 after coating.

[0060] Specifically, the protective layer 200 can be made of materials such as solder paste or insulating adhesive, which shields areas that do not need to be oxidized during the oxidation process, thereby achieving precise and efficient oxidation of the sidewalls of the initial grid lines 100. In this embodiment, the protective layer 200 is preferably located in the central region of the surface of the initial grid lines 100 on the side away from the solar cell.

[0061] The initial gate line 100 described above can be of different shapes such as trapezoidal, rectangular, or semi-circular, and is not specifically limited in this embodiment. It should be noted that when the initial gate line 100 is a trapezoidal or rectangular shape with a planar upper surface, the protective layer 200 can be easily disposed on the planar surface; when the initial gate line 100 is a circular shape with a curved upper surface, the protective layer 200 disposed on the curved surface can also partially shield the initial gate line 100 under the action of surface tension and chemical bonds, ensuring that its height is not affected during the oxidation process.

[0062] Subsequently, at least a portion of the surface of the initial gate line 100 is oxidized in an oxygen-containing atmosphere.

[0063] Specifically, an oxygen-containing atmosphere can be formed on the initial gate line 100 on the coated silicon wafer 1 using structures such as oxygen-permeable tubes, providing a basis for oxidation treatment.

[0064] The aforementioned protective layer 200 can be removed by cleaning with an organic solvent such as acetone after acid treatment.

[0065] See Figure 3 As shown, the oxidation process in this embodiment is laser oxidation. Compared to thermal oxidation and chemical vapor deposition oxidation, laser oxidation offers controllable laser precision, high accuracy for partial oxidation of small gate line structures, fast processing speed, and low cost.

[0066] Specifically, the aforementioned laser oxidation treatment includes ultraviolet laser oxidation treatment, wherein the wavelength range of the ultraviolet laser is 200–400 nm, the power range of the ultraviolet laser oxidation treatment is 2–20 W, and the time range of the ultraviolet laser oxidation treatment is 1–20 s.

[0067] Ultraviolet lasers have short wavelengths and high energy. Oxygen can absorb ultraviolet light, causing oxygen molecules to transform into oxygen atoms. These oxygen atoms then combine to form ozone molecules. The high energy of these ozone molecules allows for efficient and precise oxidation of the initial grid line 100 surface. It is important to limit the laser oxidation power to between 2 and 20 W to prevent excessive power from directly ablating and vaporizing the grid line 3. Similarly, limiting the laser treatment time to between 1 and 20 seconds is to avoid over-oxidation of the initial grid line 100 due to prolonged treatment. Over-oxidation can lead to an excessively small cross-sectional area of ​​the formed grid line 3, ultimately increasing line resistance and current loss.

[0068] Furthermore, in one embodiment, the aforementioned oxygen-containing atmosphere includes oxygen and an inert gas, with the oxygen content ranging from 10 to 50 vol%. Here, oxygen content specifically refers to the volume ratio of oxygen in the entire oxygen-containing atmosphere. Setting the oxygen content between 10 and 50 vol% ensures sufficient oxygen content during laser processing; additionally, using inert gases such as nitrogen or argon ensures the stability of the oxygen-containing atmosphere, while also improving the stability and safety of the laser oxidation process.

[0069] Based on the above scheme, the step S104 of removing oxide layer 101 includes: acid treatment of the initial gate line 100 on which oxide layer 101 is formed to remove oxide layer 101.

[0070] The oxidized oxide layer 101 is removed by acid treatment. For example, the entire solar cell, including the laser-treated initial grid lines 100, is immersed in an acid solution, or the acid solution is sprayed onto the oxide layer 101. Compared to the unoxidized portion of the initial grid lines 100, the oxide layer 101 reacts with the acid solution at a faster rate. This difference in reaction rate is used to quickly and accurately remove the oxide layer 101 located on the sidewalls of the initial grid lines 100. The initial grid lines 100 become narrower, forming grid lines 3, which reduces light shading on the coated silicon wafer 1 and improves the optical performance of the solar cell. Moreover, due to the stable properties of the alloy layer 2 and its small exposed area, the acid treatment process does not affect the current-collecting function of the alloy layer 2. That is, the acid treatment process improves optical performance without affecting electrical performance, ultimately ensuring the photoelectric conversion efficiency of the solar cell.

[0071] Specifically, in the above-mentioned step of acid treatment of the initial gate line 100 with oxide layer 101, hydrochloric acid solution or nitric acid solution is used to remove oxide layer 101, the concentration range of hydrochloric acid solution or nitric acid solution is 5 to 40 wt%, the temperature range of acid treatment is 10 to 40°C, and the time range of acid treatment is 5 to 60 s.

[0072] In this embodiment, the acid treatment solution is hydrochloric acid or nitric acid, and the concentration of the hydrochloric acid solution and nitric acid solution is limited to 5-40 wt%. The concentration here specifically refers to the mass ratio of hydrochloric acid or nitric acid solute in the whole solution. The temperature during acid treatment is limited to 10-40°C, and the treatment time is limited to 5-60 seconds. This avoids excessive acid treatment from causing unnecessary reduction or damage to the grid line 3. At the same time, such limitations are used to adapt to crystalline silicon solar cells and ensure the photoelectric conversion efficiency of crystalline silicon solar cells.

[0073] refer to Figure 4 This embodiment also provides a solar cell, which is prepared by the above-described method for preparing a solar cell, comprising: a coated silicon wafer 1, grid lines 3, and an alloy layer 2, wherein the grid lines 3 are disposed on one side surface of the coated silicon wafer 1; the alloy layer 2 is formed between the coated silicon wafer 1 and the grid lines 3, and the projected area of ​​the grid lines 3 on the coated silicon wafer 1 is smaller than the projected area of ​​the alloy layer 2 on the coated silicon wafer 1.

[0074] In this embodiment, the area of ​​the alloy layer 2, which serves as the carrier confluence channel inside the silicon wafer 1 after coating, is larger than the area of ​​the grid lines 3 that are ultimately obtained. The sufficiently large area of ​​the alloy layer 2 helps to ensure the electrical performance of the solar cell. The projected area of ​​the grid lines 3 retained on the silicon wafer 1 after coating is smaller than the projected area of ​​the alloy layer 2. That is, the grid lines 3 in this embodiment are thinner than the grid lines 3 in the conventional scheme, resulting in less shading of the silicon wafer 1 after coating. This effectively reduces the shading loss of the silicon wafer 1 after coating and improves the optical performance. The larger area of ​​the alloy layer 2 and the smaller area of ​​the grid lines 3 take into account both the electrical and optical performance of the cell, ultimately improving the photoelectric conversion efficiency of the solar cell.

[0075] Further functional descriptions of the above structures are the same as those of the corresponding embodiments described above, and will not be repeated here.

[0076] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0077] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: Provide coated silicon wafers; An initial gate line is formed on at least one side surface of the coated silicon wafer, and an alloy layer is formed on the surface of the coated silicon wafer that is in contact with the initial gate line; A portion of the surface of the initial gate line is oxidized to form an oxide layer on the initial gate line; The oxide layer is removed to form gate lines on the coated silicon wafer, the projected area of ​​the gate lines on the coated silicon wafer being smaller than the projected area of ​​the alloy layer on the coated silicon wafer.

2. The method for preparing a solar cell according to claim 1, characterized in that, The step of oxidizing at least a portion of the surface of the initial gate line includes oxidizing the sidewalls of the initial gate line.

3. The method for preparing a solar cell according to claim 2, characterized in that, The oxidation treatment of the sidewalls of the initial gate line includes: A protective layer is provided on a portion of the surface of the initial gate line; At least a portion of the surface of the initial gate line is oxidized in an oxygen-containing atmosphere.

4. The method for preparing a solar cell according to claim 3, characterized in that, The oxidation treatment methods include laser oxidation treatment.

5. The method for preparing a solar cell according to claim 4, characterized in that, The laser oxidation treatment includes ultraviolet laser oxidation treatment, wherein the wavelength range of the ultraviolet laser is 200-400nm, the power range of the ultraviolet laser oxidation treatment is 2-20W, and the time range of the ultraviolet laser oxidation treatment is 1-20s.

6. The method for preparing a solar cell according to claim 5, characterized in that, The oxygen-containing atmosphere comprises oxygen and inert gas, wherein the oxygen content ranges from 10 to 50 vol%.

7. The method for preparing a solar cell according to any one of claims 1-6, characterized in that, The removal of the oxide layer includes: acid treatment of the initial gate line on which the oxide layer is formed to remove the oxide layer.

8. The method for preparing a solar cell according to claim 7, characterized in that, In the step of acid treatment of the initial gate line on which the oxide layer is formed, the oxide layer is removed by hydrochloric acid solution or nitric acid solution, the concentration of the hydrochloric acid solution or nitric acid solution is in the range of 5 to 40 wt%, the temperature range of the acid treatment is 10 to 40°C, and the time range of the acid treatment is 5 to 60 s.

9. The method for preparing a solar cell according to claim 1, characterized in that, The coated silicon wafer is suitable for crystalline silicon solar cells, and the grid lines are sub-grids.

10. A solar cell, prepared by the method for preparing a solar cell according to any one of claims 1-9, characterized in that, include: Silicon wafers after coating; Gate lines, the gate lines being disposed on one side surface of the coated silicon wafer; An alloy layer is formed between the coated silicon wafer and the gate line, wherein the projected area of ​​the gate line on the coated silicon wafer is smaller than the projected area of ​​the alloy layer on the coated silicon wafer.

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