Display device and manufacturing method thereof

Abstract

The present disclosure provides a display device and a method of manufacturing the same, the display device including a hole injection layer on a bank layer and including at least one hole, and the display device having an advantage of being driven at low power by preventing lateral leakage current.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of Korean Patent Application No. 10 - 2023 - 0190801, filed with the Korean Intellectual Property Office on December 26, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to an electronic device having a display, and more particularly, to a display device and a method of manufacturing the display device. Background art

[0004] As display technologies have evolved to provide more functions, display devices can provide functions such as an image capturing function, a sensing function, etc., as well as an image display function.

[0005] To provide these functions, display devices may need to include optoelectronic devices, such as light receiving devices, cameras, sensors for detecting images, etc.

[0006] To receive light passing through the front of the display device, it may be desirable for such optoelectronic devices to be located in areas of the display device that can increasingly receive and detect incident light from the front.

[0007] To achieve the above - mentioned purpose, in display devices, optoelectronic devices have been designed to be located at the front of the display device so that cameras, sensors, etc., which are optoelectronic devices, are increasingly exposed to incident light.

[0008] To install optoelectronic devices in the display device in this way, the bezel area of the display device may be increased, or it may be necessary to form notches or holes in the display area of the related display panel.

[0009] Therefore, even when optoelectronic devices (such as cameras, sensors, etc.) that receive or detect incident light and perform predefined functions are attached to the display device, it may be desirable for the display device to have a higher transmittance to perform the intended functions. Summary of the invention

[0010] The inventors of the present disclosure have invented a display device capable of blocking the flow of lateral leakage current (LLC).

[0011] In addition, the inventors have also invented a display device that can improve the transmittance of a light - transmitting region by removing electrode patterning materials remaining in the light - transmitting region after patterning of an electrode layer.

[0012] One or more aspects of the present disclosure may provide a display device capable of being driven at low power by preventing lateral leakage current and a method of manufacturing the display device.

[0013] One or more aspects of the present disclosure may provide a display device capable of increasing the transmittance of a light-transmitting region and a method of manufacturing the display device.

[0014] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, including: a substrate on which a normal region capable of setting a plurality of first pixels and having a first resolution and an optical region capable of setting a plurality of second pixels and having a second resolution lower than the first resolution are defined; a first electrode layer located above the substrate; a bank layer located above the substrate, covering a part of the first electrode layer and including an opening region; a hole injection layer located on the first electrode layer and the bank layer, and including at least one hole located on the bank layer; a hole transport layer located on the hole injection layer; and a light-emitting layer located on the hole transport layer.

[0015] According to one or more exemplary embodiments of the present disclosure, a method of manufacturing a display device may be provided, including: forming a first electrode layer; forming a hole injection layer on the first electrode layer; forming a hole in the hole injection layer; forming a hole transport layer on the hole injection layer and filling the hole with the hole transport layer; forming an electron transport layer on the light-emitting layer; and forming a second electrode layer on the electron transport layer.

[0016] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, including a substrate on which a normal region for setting a plurality of first pixels and having a first resolution and an optical region for setting a plurality of second pixels and having a second resolution lower than the first resolution are defined, wherein at least one of the normal region and the optical region includes a plurality of sub-pixels, and each of the plurality of sub-pixels includes a light-emitting element located above the substrate, and wherein the light-emitting element includes: a first electrode layer; a hole injection layer located on the first electrode layer and including at least one hole; a hole transport layer located on the hole injection layer; a light-emitting layer located on the hole transport layer; and a second electrode layer located on the light-emitting layer.

[0017] According to one or more aspects of the present disclosure, a display device capable of being driven at low power by preventing lateral leakage current and a method of manufacturing the display device may be provided.

[0018] According to one or more aspects of the present disclosure, a display device capable of increasing the transmittance of a light-transmitting region through process optimization and a method of manufacturing the display device may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present disclosure includes drawings to provide a further understanding of the present disclosure. The drawings are incorporated into and constitute a part of this application. The drawings illustrate aspects of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0020] Figure 1A and Figure 1B and Figure 1C and Figure 1D are plan views showing example display devices according to aspects of the present disclosure;

[0021] Figure 2 shows an example system configuration of a display device according to aspects of the present disclosure;

[0022] Figure 3 shows an example equivalent circuit of sub-pixels in a display device according to aspects of the present disclosure;

[0023] Figure 4 shows the arrangement of sub-pixels in three example regions included in the display area of a display device according to aspects of the present disclosure;

[0024] Figure 5A is Figure 4 an example enlarged plan view of the normal area NA in;

[0025] Figure 5B is Figure 4 an example enlarged plan view of the first optical area OA1 in.

[0026] Figure 5C is Figure 4 an example enlarged plan view of the second optical area OA2 in.

[0027] Figure 6A is an example cross-sectional view taken along line A-A' of Figure 5A ;

[0028] Figure 6B is an example cross-sectional view taken along line B-B' of Figure 5B ;

[0029] Figure 6C and 6D is an example cross-sectional view taken along line C-C' of Figure 5C ;

[0030] Figure 7A and Figure 7B and Figure 7C are Figure 5A example enlarged plan views of the first pixel group PG1, the second pixel group PG2, and the third pixel group PG3 of;

[0031] Figure 8A and Figure 8B and Figure 8C is a flowchart showing an example manufacturing method of a display device according to aspects of the present disclosure;

[0032] Figure 9is an exemplary schematic diagram showing the existence of lateral leakage current in a display device according to an aspect of the present disclosure; and

[0033] Figure 10 is an exemplary graph showing the variation of the extinction coefficient and refractive index with respect to wavelength in a display device according to an aspect of the present disclosure. Detailed Description

[0034] Now, reference will be made in detail to the exemplary embodiments of the present disclosure, examples of which are shown in the accompanying drawings. In the following description, unless otherwise specified, the structures, embodiments, implementations, methods, and operations described herein are not limited to the specific examples or examples set forth herein and may be changed as known in the art. Throughout the specification, unless otherwise specified, the same reference numerals refer to the same elements. The names of the individual elements used in the following description are only selected for convenience in writing the specification and may therefore be different from the names used in actual products. The advantages and features of the present disclosure and the methods for realizing them will be clarified by the exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the present disclosure will be thorough and complete and will help those of ordinary skill in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, if a detailed description of a related known function or configuration may unnecessarily obscure aspects of the present disclosure, the detailed description of such known function or configuration may be omitted. The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. When using terms such as "comprising", "having", "containing", "including", "constituting", "consisting of", "formed by", etc., one or more other elements may be added unless a term such as "only" is used. Elements described in the singular are intended to include a plurality of elements, and vice versa, unless the context clearly dictates otherwise.

[0035] Although terms such as "first", "second", A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms because they are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0036] When referring to the first element and the second element being "connected or combined", "in contact or overlapping", etc., it should be interpreted that not only can the first element be "directly connected or combined" or "directly in contact or overlapping" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or combined", "in contact or overlapping", etc. with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or combined", "in contact or overlapping", etc. with each other.

[0037] When describing the positional relationship, for example, when using "above", "upper", "below", "lower", "beside", "near", etc. to describe the positional relationship between two parts, unless more restrictive terms such as "adjacent to", "directly", or "against" are used, one or more other parts can be located between these two parts. For example, when one element or layer is "above" another element or layer, a third element or layer can be inserted therebetween. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "upper", "lower", etc. refer to any reference system.

[0038] In addition, when referring to any dimensions, relative sizes, etc., even if the relevant description is not explicitly stated, the numerical values or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "can".

[0039] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0040] Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D are plan views showing an exemplary display device 100 according to an aspect of the present disclosure.

[0041] Referring to Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D , in one or more exemplary embodiments, the display device 100 may include a display panel 110 for displaying an image and one or more optoelectronic devices (11 and / or 12). Herein, the optoelectronic device may be referred to as a photodetector, a photoreceiver, or a photosensing device. The optoelectronic device may include one or more of a camera, a camera lens, a sensor, a sensor for detecting an image, etc.

[0042] The display panel 110 may include a display area DA configured to be capable of displaying one or more images and a non-display area NDA that does not display images.

[0043] A plurality of sub-pixels may be provided in the display area DA, and various types of signal lines for driving the plurality of sub-pixels may be provided therein.

[0044] The non-display area NDA may refer to an area outside the display area DA.

[0045] Various types of signal lines may be provided in the non-display area NDA, and they may be connected to various types of driving circuits.

[0046] At least a part of the non-display area NDA may be bent so as not to be visible from the front of the display device 100, or may be covered by a housing or casing (not shown) of the display device 100.

[0047] The non-display area NDA may also be referred to as a bezel or a bezel area.

[0048] Refer to Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D In one or more aspects, one or more optoelectronic devices (11 and / or 12) included in the display device 100 may be located below or in the lower part of the display panel 110 (on the opposite side of its viewing surface).

[0049] Light may enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optoelectronic devices (11 and / or 12) located below or in the lower part of the display panel 110 (on the opposite side of the viewing surface).

[0050] One or more optoelectronic devices (11 and / or 12) may be devices capable of receiving or detecting light passing through the display panel 110 and performing a predefined function based on the received light.

[0051] For example, one or more optoelectronic devices (11 and / or 12) may include one or more of the following: an image capturing device, such as a camera (image sensor), etc.; or a sensor, such as a proximity sensor, an illuminance sensor, etc.

[0052] Refer to Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D, in one or more aspects, the display area DA defined in the display panel 100 may include a normal area NA and one or more optical areas (OA1 and / or OA2). As used herein, the term "normal area" NA may be an area that, although present in the display area DA, does not overlap with one or more optoelectronic devices (11 and / or 12). The normal area NA may also be referred to as a non-optical area.

[0053] Referring to Figure 1A , Figure 1B , Figure 1C and Figure 1D , one or more optical areas (OA1 and / or OA2) may be one or more areas that respectively overlap with one or more optoelectronic devices (11 and / or 12).

[0054] According to Figure 1A the example of, the display area DA may include a first optical area OA1 and a normal area NA.

[0055] In this example, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11.

[0056] Figure 1A It is shown that the first optical area OA1 has a circular structure, but the shape of the first optical area OA1 according to the exemplary embodiments of the present disclosure is not limited thereto.

[0057] For example, the first optical area OA1 may be octagonal, or may be various polygons according to design requirements.

[0058] According to Figure 1C the example of, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA.

[0059] In Figure 1C the example of, at least a portion of the normal area NA may be present between the first optical area OA1 and the second optical area OA2.

[0060] In this example, at least a portion of the first optical area OA1 may overlap with the first optoelectronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0061] According to Figure 1D the example of, the display area DA may include a first optical area OA1, a second optical area OA2, and a normal area NA.

[0062] In Figure 1D the example of, there may be no normal area NA between the first optical area OA1 and the second optical area OA2.

[0063] For example, the first optical region OA1 and the second optical region OA2 may be in contact with each other (e.g., directly in contact with each other).

[0064] In this example, at least a part of the first optical region OA1 may overlap with the first optoelectronic device 11, and at least a part of the second optical region OA2 may overlap with the second optoelectronic device 12.

[0065] In one or more aspects, one or more optical regions (OA1 and / or OA2) included in the display panel 110 or the display device 100 need to be configured with an image display structure and a light-transmitting structure simultaneously.

[0066] For example, since one or more optical regions (OA1 and / or OA2) are corresponding parts of the display region DA, it is desirable that sub-pixels for displaying an image are arranged in one or more optical regions (OA1 and / or OA2).

[0067] In addition, in order for the light entering the display panel 110 or the display device 100 to reach one or more optoelectronic devices (11 and / or 12), it is also desirable that one or more optical regions (OA1 and / or OA2) are each configured with a light-transmitting structure.

[0068] It should be noted that although one or more optoelectronic devices (11 and / or 12) are devices that need to receive light, one or more optoelectronic devices (11 and / or 12) may be located on the back surface of the display panel 110 (e.g., on the opposite side of its viewing surface). Therefore, one or more optoelectronic devices (11 and / or 12) can receive the light passing through the display panel 110.

[0069] For example, one or more optoelectronic devices (11 and / or 12) may not be exposed on the front surface (viewing surface) of the display panel 110 or the display device 100.

[0070] Therefore, when the user views the front surface of the display device 110, one or more optoelectronic devices (11 and / or 12) are positioned such that the user cannot see them.

[0071] The first optoelectronic device 11 may be a camera, for example, and the second optoelectronic device 12 may be a sensor, which may be a proximity sensor, an illuminance sensor, an infrared sensor, etc.

[0072] In one or more aspects, the camera may be a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor, and the sensor may be an infrared sensor capable of detecting infrared light.

[0073] In one or more aspects, the first optoelectronic device 11 may be a sensor, and the second optoelectronic device 12 may be a camera.

[0074] In the following, for convenience of description, a discussion is provided based on an example where the first optoelectronic device 11 is a camera and the second optoelectronic device 12 is a sensor. However, it should be understood that the scope of the present disclosure also includes examples where the first optoelectronic device 11 is a sensor and the second optoelectronic device 12 is a camera.

[0075] The camera can be, for example, a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor.

[0076] In an example where the first optoelectronic device 11 is a camera, the camera can be located on the back surface (e.g., below or in the lower part thereof) of the display panel 110, and the camera can be a front camera capable of photographing an object or an image in the front direction of the display panel 110.

[0077] Accordingly, a user can photograph an image or an object that is not visible on the viewing surface while viewing the viewing surface of the display panel 110 through the camera.

[0078] Although the normal area NA and one or more optical areas (OA1 and / or OA2) included in the display area DA have a common function of being able to display an image, the difference is that the normal area NA can be an area where a light-transmitting structure does not need to be implemented, but one or more optical areas (OA1 and / or OA2) can be areas where a light-transmitting structure needs to be implemented. Therefore, in one or more aspects, the normal area NA can be an area where a light-transmitting structure is not implemented or included, but one or more optical areas (OA1 and / or OA2) can be areas where a light-transmitting structure is implemented or included.

[0079] In one or more aspects, one or more optical areas (OA1 and / or OA2) can have a transmittance greater than or equal to a predetermined level, that is, have a relatively high transmittance, and the normal area NA can have a transmittance less than the predetermined level or no light transmittance.

[0080] For example, one or more optical areas (OA1 and / or OA2) can have a different resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, line arrangement structure, etc. from the normal area NA.

[0081] For example, the number of sub-pixels per unit area in one or more optical areas (OA1 and / or OA2) may be less than the number of sub-pixels per unit area in the normal area NA.

[0082] For example, the resolution of one or more optical areas (OA1 and / or OA2) may be lower than the resolution of the normal area NA.

[0083] Here, the number of sub-pixels per unit area can be a unit for measuring resolution, such as the number of pixels (or sub-pixels) per inch (PPI), which represents the number of pixels (or sub-pixels) within 1 inch.

[0084] For example, the number of sub-pixels per unit area in the first optical region OA1 can be less than the number of sub-pixels per unit area in the normal region NA.

[0085] For example, the number of sub-pixels per unit area in the second optical region OA2 can be greater than or equal to the number of sub-pixels per unit area in the first optical region OA1.

[0086] In Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D each of

[0087] In Figure 1C and Figure 1D each of

[0088] the first optical region OA1 and the second optical region OA2 can have various shapes, such as circular, oval, quadrilateral, hexagonal, octagonal, etc.

[0089] Referring to Figure 1D , in an example where the first optical region OA1 and the second optical region OA2 are in contact with each other (e.g., in direct contact with each other), the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes, such as circular, oval, quadrilateral, hexagonal, octagonal, etc.

[0090] Hereinafter, for the sake of convenience of explanation, discussions are provided based on an example where both the first optical region OA1 and the second optical region OA2 are circular. However, it should be understood that the scope of the present disclosure also includes examples where at least one of the first optical region OA1 and the second optical region OA2 is in a shape other than circular.

[0091] In this document, in an example where the display device 100 has a structure in which a first optoelectronic device 11 such as a camera is located below or at the lower part of the display panel 100 without being exposed to the outside, such a display device 100 can be referred to as a display applying under-display camera (UDC) technology.

[0092] According to these examples, since there is no need to form a notch or a camera hole for exposing the camera in the display panel 110, the display device 100 can have the advantage of avoiding a reduction in the size of the display area DA.

[0093] In fact, since there is no need to form a notch or a camera hole for exposing the camera in the display panel 110, the display device 100 can further provide the following advantages: reducing the size of the bezel area and increasing the design freedom due to the elimination of these design limitations.

[0094] Even if one or more optoelectronic devices (11 and / or 12) are located on the back surface (e.g., below or in the lower part) of the display panel 110 of the display device 100 (e.g., hidden or not exposed), one or more optoelectronic devices (11 and / or 12) are required to perform a predefined function by normally receiving or detecting light.

[0095] In addition, in the display device 100, even if one or more optoelectronic devices (11 and / or 12) are located on the back surface (e.g., below or in the lower part) of the display panel 110 and are hidden and located at a position overlapping with the display area DA, it is necessary to normally perform image display in one or more optical areas (OA1 and / or OA2) overlapping with one or more optoelectronic devices (11 and / or 12) in the display area DA. Therefore, in one or more examples, even if one or more optoelectronic devices (11 and / or 12) are located on the back surface of the display panel, images can be displayed in a normal manner (e.g., without degrading the image quality) in one or more optical areas (OA1 and / or OA2) overlapping with one or more optoelectronic devices (11 and / or 12) in the display area DA.

[0096] Figure 2 An example system configuration of the display device 100 according to an aspect of the present disclosure is shown.

[0097] Referring to Figure 2 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying one or more images.

[0098] The display driving circuit may be a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and other components.

[0099] The display panel 110 may include a display area DA configured to be able to display one or more images and a non-display area NDA that does not display images.

[0100] The non-display area NDA may be an area outside the display area DA and may also be referred to as an edge area or a bezel area.

[0101] All or part of the non-display area NDA may be an area visible from the front of the display device 100, or an area that is curved and not visible from the front of the display device 100.

[0102] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB.

[0103] The display panel 110 may also include various types of signal lines to drive the plurality of sub-pixels SP.

[0104] In one or more aspects, the display device 100 may be a liquid crystal display device or the like, or may also be a self-emitting display device that emits light from the display panel 210 itself.

[0105] In an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0106] For example, the display device 100 according to an aspect of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement the light-emitting element.

[0107] In another example, the display device 100 according to an aspect of the present disclosure may be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to implement the light-emitting element.

[0108] In yet another example, the display device 100 according to an aspect of the present disclosure may be a quantum dot display device that uses quantum dots as light-emitting elements, where the quantum dots are self-emitting semiconductor crystals.

[0109] The structure of each of the plurality of sub-pixels SP may have different configurations or designs according to the type of the display device 100.

[0110] For example, in an example where the display device 100 is a self-emitting display device including self-emitting sub-pixels SP, each sub-pixel SP may include a self-emitting light-emitting element, one or more transistors, and one or more capacitors.

[0111] In one or more aspects, for example, various types of signal lines arranged in the display device 100 may include a plurality of data lines DL for transmitting data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for transmitting gate signals (which may be referred to as scan signals), and the like.

[0112] The plurality of data lines DL and the plurality of gate lines GL may cross each other.

[0113] Each of the plurality of data lines DL may be configured to extend in a first direction.

[0114] Each of the plurality of gate lines GL may be configured to extend in a second direction.

[0115] For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction.

[0116] In another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction.

[0117] The data driving circuit 220 may be a circuit for driving the plurality of data lines DL, and may supply data signals to the plurality of data lines DL.

[0118] The gate driving circuit 230 may be a circuit for driving the plurality of gate lines GL, and may supply gate signals to the plurality of gate lines GL.

[0119] The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230, and may control the driving time of the plurality of data lines DL and the driving time of the plurality of gate lines GL.

[0120] The display controller 240 may supply a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and may supply a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.

[0121] The display controller 240 may receive input image data from the host system 250, and supply image data Data to the data driving circuit 220 based on the input image data.

[0122] The data driving circuit 220 may control the supply of data signals to the plurality of data lines DL according to the driving timing of the display controller 240.

[0123] The data driving circuit 220 may receive digital image data Data from the display controller 240, convert the received image data Data into an analog data signal, and output the obtained analog data signal to the plurality of data lines DL.

[0124] The gate driving circuit 230 may control the supply of gate signals to the plurality of gate lines GL according to the timing of the display controller 240.

[0125] The gate driving circuit 230 may receive a first gate voltage corresponding to the conduction level voltage and a second gate voltage corresponding to the cutoff level voltage, as well as various gate driving control signals GCS, generate a gate signal, and supply the generated gate signal to the plurality of gate lines GL.

[0126] In one or more aspects, the data driving circuit 220 can be connected to the display panel 110 by tape automated bonding (TAB) technology, or to the conductive pads (such as bonding pads) of the display panel 110 by chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 110 by chip on film (COF) technology.

[0127] In one or more aspects, the gate driving circuit 230 can be connected to the display panel 110 by tape automated bonding (TAB) technology, or to the conductive pads (such as bonding pads) of the display panel 110 by chip on glass (COG) technology or chip on panel (COP) technology, or to the display panel 110 by chip on film (COF) technology.

[0128] In one or more aspects, the gate driving circuit 230 can be disposed in the non-display area NDA of the display panel 110 by in-panel gate (GIP) technology.

[0129] The gate driving circuit 230 can be disposed on the substrate or connected to the substrate.

[0130] In an example where the gate driving circuit 230 is implemented by GIP technology, the gate driving circuit 230 can be disposed in the non-display area NDA of the substrate.

[0131] In an example where the gate driving circuit 230 is implemented by chip on glass (COG) technology, chip on film (COF) technology, etc., the gate driving circuit 230 can be connected to the substrate.

[0132] In one or more aspects, at least one of the data driving circuit 220 and the gate driving circuit 230 can be disposed in the display area DA of the display panel 110.

[0133] For example, at least one of the data driving circuit 220 and the gate driving circuit 230 can be configured not to overlap with the sub-pixels SP, or configured to overlap with one or more or all of the sub-pixels SP, or to overlap with at least one or more parts of one or more sub-pixels.

[0134] In one or more aspects, the data driving circuit 220 can be disposed on and / or electrically connected to one side or a part (such as the upper edge or the lower edge) of the display panel 110, but not limited thereto.

[0135] In one or more aspects, depending on the driving scheme, panel design scheme, etc., the data driving circuit 220 may be located at and / or electrically connected to at least two sides or portions (e.g., upper edge and lower edge) of the display panel 110 or four sides or portions (e.g., upper edge, lower edge, left edge, and right edge) of the display panel 110, but is not limited thereto.

[0136] In one or more aspects, the gate driving circuit 230 may be located at and / or electrically connected to one side or portion (e.g., left edge or right edge) of the display panel 110, but is not limited thereto.

[0137] In one or more aspects, depending on the driving scheme, panel design scheme, etc., the gate driving circuit 230 may be located at and / or electrically connected to at least two sides or portions (e.g., left edge and right edge) of the panel 110 or four sides or portions (e.g., upper edge, lower edge, left edge, and right edge) of the panel 110, but is not limited thereto.

[0138] The display controller 240 may be implemented as a component separate from the data driving circuit 220 or incorporated into the data driving circuit 220 and thus implemented as an integrated circuit.

[0139] The display controller 240 may be a timing controller used in typical display technologies, or may be a controller or control device that can perform other control functions in addition to the functions of a typical timing controller. In one or more embodiments, the display controller 240 may be a controller or control device different from the timing controller, or may be a circuit or component included in the controller or control device.

[0140] Various circuits or electronic components (e.g., integrated circuits (ICs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processors, etc.) may be used to implement the display controller 240.

[0141] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the gate driving circuit 220 and the data driving circuit 230 through a printed circuit board, a flexible printed circuit, etc.

[0142] The display controller 240 may send signals to and receive signals from the data driving circuit 220 through one or more predefined interfaces.

[0143] For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc.

[0144] In one or more aspects, in order to further provide a touch sensing function and an image display function, the display device 100 may include a touch sensor and a touch sensing circuit, and the touch sensing circuit can detect whether a touch object such as a finger or a pen applies a touch or detect the position (or touch coordinates) of the touch by sensing the touch sensor.

[0145] The touch sensing circuit may include: a touch driving circuit 260, which can generate and provide touch sensing data by driving and sensing the touch sensor; a touch controller 270, which can detect whether a touch is applied or detect the position (or touch coordinates) of the touch by using the touch sensing data; and one or more other components.

[0146] The touch sensor may include a plurality of touch electrodes.

[0147] The touch sensor may further include a plurality of touch lines to electrically connect the plurality of touch electrodes to the touch driving circuit 260.

[0148] The touch sensor may be implemented in the form of a touch panel outside the display panel 110 or integrated inside the display panel 110.

[0149] In an example where the touch sensor is implemented in the form of a touch panel located outside the display panel 110, such a touch sensor may be referred to as an external type.

[0150] In an example where an external touch sensor is provided in the display device 100, the touch panel and the display panel 110 may be separately manufactured and combined together in the assembly process.

[0151] The external touch panel may include a touch panel substrate and a plurality of touch electrodes provided on the touch panel substrate.

[0152] In an example where the touch sensor is integrated inside the display panel 110, during the manufacturing process of the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving.

[0153] The touch driving circuit 260 may supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0154] The touch sensing circuit may perform touch sensing through self - capacitance sensing technology or mutual - capacitance sensing technology.

[0155] In an example where the touch sensing circuit performs touch sensing through self - capacitance sensing technology, the touch sensing circuit may perform touch sensing based on the capacitance between one or more touch electrodes and an object such as a finger or a pen.

[0156] According to the self - capacitance sensing method, each of the plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode.

[0157] The touch driving circuit 260 can drive all or one or more of the plurality of touch electrodes and can sense all or one or more of the plurality of touch electrodes.

[0158] In an example where the touch sensing circuit performs touch sensing through the mutual - capacitance sensing technique, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0159] According to the mutual - capacitance sensing technique, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes.

[0160] The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0161] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit can be implemented as separate devices or a single device.

[0162] In addition, the touch driving circuit 260 and the data driving circuit 220 can be implemented as separate devices or a single device.

[0163] The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and / or the touch sensing circuit.

[0164] In some aspects, the display device 100 can be a mobile terminal, such as a smart phone, a tablet computer, etc., or a display, a television (TV), etc. Such devices can be configured in various types, sizes, and shapes. The display device 100 according to the aspects of the present disclosure is not limited thereto and can include various types, sizes, and shapes configured to display information or images.

[0165] As described above, the display area DA of the display panel 110 may include a normal area NA and one or more optical areas (OA1 and / or OA2), as shown in FIG. 1.

[0166] The normal area NA and one or more optical areas (OA1 and / or OA2) can be areas configured to be able to display images.

[0167] Here, it should be noted that the normal area NA can be an area where a light - transmissive structure does not need to be implemented, and one or more optical areas (OA1 and / or OA2) can be areas where a light - transmissive structure needs to be implemented.

[0168] As described above for Figure 1A 、 Figure 1B 、 Figure 1Cand Figure 1D As discussed in the example of Figure 1D , although the display area DA of the display panel 110 may include one or more optical areas (OA1 and / or OA2) in addition to the normal area NA, for convenience of description, in the following discussion, unless otherwise clearly stated, it is assumed that the display area DA includes a first optical area and a second optical area (OA1 and OA2) and the normal area NA, as shown in Figure 1C and Figure 1D ; and the normal area NA of the display area DA includes Figure 1A , Figure 1B , Figure 1C and Figure 1D the normal area NA in Figure 1A , Figure 1B , Figure 1C and Figure 1D , and the first optical area OA1 and the second optical area OA2 of the display area DA respectively include Figure 1C and Figure 1D the first optical area OA1 in

[0169] Figure 3 FIG. Figure 3 shows an example equivalent circuit of a sub-pixel SP in the display panel 110 according to an aspect of the present disclosure.

[0170] Each sub-pixel SP provided in the normal area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA of the display panel 110 may include a light-emitting element ED, a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT for transmitting a data voltage Vdata to a first node N1 of the driving transistor DRT, a storage capacitor Cst for maintaining the voltage at an approximately constant level during one frame, and the like.

[0171] The driving transistor DRT may include a first node N1 to which a data voltage is applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which a driving voltage ELVDD transmitted through a driving voltage line DVL is applied.

[0172] In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0173] The light-emitting element ED may include a first electrode layer AE, a light-emitting layer EL, and a second electrode layer CE.

[0174] The first electrode layer AE may be a pixel electrode provided in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP.

[0175] The second electrode layer CE can be a common electrode provided in all or some of the plurality of sub-pixels SP. For example, a base voltage ELVSS can be applied to the second electrode layer CE.

[0176] For example, the first electrode layer AE can be a pixel electrode, and the second electrode layer CE can be a common electrode.

[0177] In another example, the first electrode layer AE can be a common electrode, and the second electrode layer CE can be a pixel electrode.

[0178] Hereinafter, for the sake of convenience of explanation, a discussion is provided based on an example in which the first electrode layer AE is a pixel electrode and the second electrode layer CE is a common electrode.

[0179] In one or more aspects, the light-emitting element ED can be an organic light-emitting diode (OLED), a micro light-emitting diode (micro LED), a mini light-emitting diode (mini LED), a quantum dot light-emitting diode (QLED), an inorganic light-emitting diode, etc.

[0180] In an example where the light-emitting element ED is an organic light-emitting diode (OLED), the light-emitting layer EL of the light-emitting element ED can include an organic light-emitting layer containing an organic material.

[0181] The scanning transistor SCT can be turned on and off by a scanning signal SCAN, which is a gate signal applied through a gate line GL, and the scanning transistor SCT is electrically connected between a first node N1 of a driving transistor DRT and a data line DL.

[0182] A storage capacitor Cst can be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT.

[0183] Each sub-pixel SP can include two transistors (2T: DRT and SCT) and one capacitor (1C: Cst) (which can be referred to as a "2T1C structure"), as Figure 3 shown, and in some cases, each sub-pixel SP can further include one or more transistors, or further include one or more capacitors.

[0184] The storage capacitor Cst can be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor that may be formed between the first node N1 and the second node N2 of the driving transistor DRT, such as a parasitic capacitor (e.g., Cgs or Cgd).

[0185] In one or more aspects, each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or can be a p-type transistor.

[0186] In one or more aspects, each of the driving transistor DRT and the scanning transistor SCT can be a low-temperature polycrystalline silicon transistor.

[0187] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, at least one of the driving transistor DRT and the scanning transistor SCT can be an oxide thin film transistor.

[0188] Since the circuit elements included in each sub-pixel SP (especially the light-emitting element ED implemented using an organic light-emitting diode including an organic material) are vulnerable to external moisture or oxygen, the encapsulation layer ENCAP can be configured to cover the circuit elements (e.g., the light-emitting element ED) to prevent external moisture or oxygen from penetrating into such circuit elements.

[0189] Figure 4 The arrangement of sub-pixels SP in three example regions (NA, OA1, and OA2) included in the display area of the display device 100 according to an aspect of the present disclosure is shown.

[0190] Refer to Figure 4 , in one or more exemplary embodiments, each of the normal region NA, the first optical region OA1, and the second optical region OA2 included in the display area DA can be provided with a plurality of sub-pixels SP.

[0191] For example, the plurality of sub-pixels SP can include a red sub-pixel (Red SP) that emits red light, a green sub-pixel (Green SP) that emits green light, and a blue sub-pixel (Blue SP) that emits blue light.

[0192] Therefore, each of the normal region NA, the first optical region OA1, and the second optical region OA2 can include one or more light-emitting regions EA of one or more red sub-pixels (Red SP), one or more light-emitting regions EA of one or more green sub-pixels (Green SP), and one or more light-emitting regions EA of one or more blue sub-pixels (Blue SP).

[0193] Refer to Figure 4 , the normal region NA may not include a light-transmitting structure but may include a light-emitting region EA.

[0194] In one or more aspects, each of the first optical region OA1 and the second optical region OA2 may need to include a light-transmitting structure and a light-emitting region EA.

[0195] Thus, in one or more aspects, the first optical region OA1 may include one or more light-emitting regions EA and one or more first light-transmitting regions TA1, and the second optical region OA2 may include one or more light-emitting regions EA and one or more second light-transmitting regions TA2.

[0196] The difference between the light-emitting region EA and the light-transmitting regions (TA1 and TA2) from each other may be whether they can transmit light.

[0197] For example, the light-emitting region EA may be a region configured not to transmit light (e.g., light cannot transmit to the back of the display panel), and the light-transmitting regions (TA1 and TA2) may be regions configured to be able to transmit light (e.g., light can transmit to the back of the display panel).

[0198] The difference between the light-emitting region EA and the light-transmitting regions (TA1 and TA2) from each other may also be whether the second electrode layer CE is provided (e.g., Figure 3 the second electrode layer CE).

[0199] For example, although the second electrode layer CE may be provided in the light-emitting region EA, the second electrode layer CE may not be provided in the light-transmitting regions (TA1 and TA2).

[0200] In one or more aspects, a protective layer (not shown) may be provided in the light-transmitting regions (TA1 and TA2).

[0201] The protective layer may include an organic material and may be configured to cover at least a part of the light-transmitting regions (TA1 and TA2) using a fine metal mask (FMM).

[0202] The protective layer may be used to increase the light transmittance of the light-transmitting regions (TA1 and TA2) and may be used to effectively pattern the second electrode layer CE formed in the corresponding light-emitting region EA.

[0203] For example, after forming the protective layer in the light-transmitting regions (TA1 and TA2) using a fine metal mask (FMM), the second electrode layer CE may be deposited in the corresponding light-emitting region EA using an opening metal mask (OMM). Thus, the second electrode layer CE can be effectively formed in the light-emitting region EA except for the protective layer. For example, by appropriately controlling the surface energy of the protective layer, the second electrode layer CE may not be formed on the protective layer but only in the region without the protective layer.

[0204] Thus, the protective layer and the second electrode layer CE may be in the same layer.

[0205] However, the exemplary embodiments of the present disclosure are not limited to the examples of forming and retaining the protective layer in the light-transmitting regions (TA1 and TA2). For example, in order to increase the transmittance of the light-transmitting regions (TA1 and TA2), the protective layer may be removed after forming the second electrode layer CE.

[0206] For example, the protective layer may not be retained in the light-transmitting regions (TA1 and TA2).

[0207] In one or more aspects, a light-shielding layer may be provided in the light-emitting region EA, and the light-shielding layer may not be provided in the light-transmitting regions (TA1 and TA2).

[0208] Since the first optical region OA1 includes the first light-transmitting region TA1 and the second optical region OA2 includes the second light-transmitting region TA2, both the first optical region OA1 and the second optical region OA2 may be regions configured to be capable of transmitting light.

[0209] The transmittance (degree of transmission) of the first optical region OA1 and the transmittance (degree of transmission) of the second optical region OA2 may be substantially the same.

[0210] In this context, considering the minor differences due to errors in the manufacturing process of the display panel 110 or the display device 100, substantially the same may mean to the extent of being regarded as equivalent to each other.

[0211] According to this definition, the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 may have substantially the same shape or size.

[0212] In one or more aspects, even if the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first light-transmitting region TA1 in the first optical region OA1 and the ratio of the second light-transmitting region TA2 in the second optical region OA2 may also be substantially the same.

[0213] However, the exemplary embodiments of the present disclosure are not limited thereto. For example, the transmittance (degree of transmission) of the first optical region OA1 and the transmittance (degree of transmission) of the second optical region OA2 may be different from each other.

[0214] In the present embodiment, the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 may have different shapes or sizes.

[0215] In one or more aspects, even if the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 have substantially the same shape or size, the ratio of the first light-transmitting region TA1 in the first optical region OA1 and the ratio of the second light-transmitting region TA2 in the second optical region OA2 can be different from each other.

[0216] For example, in an example where the first optoelectronic device 11 overlapping the first optical region OA1 is a camera and the second optoelectronic device 12 overlapping the second optical region OA2 is a sensor for detecting an image, the camera may require a larger amount of light than the sensor.

[0217] In this example, the transmittance (degree of transmission) of the first optical region OA1 can be greater than the transmittance (degree of transmission) of the second optical region OA2.

[0218] In this embodiment, the area of all or each of the first light-transmitting regions TA1 of the first optical region OA1 can be greater than the area of all or each of the second light-transmitting regions TA2 of the second optical region OA2.

[0219] In one or more aspects, even if the first light-transmitting region TA1 of the first optical region OA1 and the second light-transmitting region TA2 of the second optical region OA2 have substantially the same size, the ratio of the first light-transmitting region TA1 in the first optical region OA1 can also be greater than the ratio of the second light-transmitting region TA2 in the second optical region OA2.

[0220] In one or more aspects, as Figure 4 shown, the first light-transmitting region TA1 of the first optical region OA1 can have a circular shape in a cross-sectional view, but the exemplary embodiments of the present disclosure are not limited to this shape for the first light-transmitting region TA1.

[0221] For example, the first light-transmitting region TA1 of the first optical region OA1 can have an octagonal shape in a plan view, or can have an elliptical or polygonal shape.

[0222] As described above, by changing the shape of the first light-transmitting region TA1, the transmittance of the first light-transmitting region TA1 can be adjusted, and the area or size of the light-emitting region of the first optical region OA1 can be adjusted.

[0223] Hereinafter, for the sake of convenience of explanation, a discussion is provided based on an example where the transmittance (degree of transmission) of the first optical region OA1 is greater than the transmittance (degree of transmission) of the second optical region OA2.

[0224] In addition, as Figure 4 shown, the light-transmitting regions (TA1 and TA2) can be referred to as transparent regions, and the transmittance can also be referred to as transparency.

[0225] In the following discussion, as Figure 4 shown, it is assumed that the first optical region OA1 and the second optical region OA2 are located in the upper part of the display area DA of the display panel 110 and are arranged side by side left and right.

[0226] Referring to Figure 4 , the horizontal display area provided with the first optical region OA1 and the second optical region OA2 may be referred to as the first horizontal display area HA1, and the horizontal display area not provided with the first optical region OA1 and the second optical region OA2 may be referred to as the second horizontal display area HA2.

[0227] Referring to Figure 4 , the first horizontal display area HA1 may include a normal area NA, a part of the first optical region OA1 and the second optical region OA2.

[0228] The second horizontal display area HA2 may only include the normal area NA.

[0229] Figures 5A to 5C is Figure 4 an example enlarged plan view of the three regions (NA, OA1, and OA2) in

[0230] Referring to Figure 5A , the normal area NA may include a plurality of sub-pixels SP arranged in a matrix form.

[0231] Each sub-pixel SP may be one of a red sub-pixel (Red SP), a green sub-pixel (Green SP), and a blue sub-pixel (Blue SP). A unit pixel may be implemented to include two or more of the red sub-pixel (Red SP), the green sub-pixel (Green SP), and the blue sub-pixel.

[0232] In one or more aspects, each of the plurality of sub-pixels SP may further include a white sub-pixel.

[0233] In one or more aspects, two sub-pixels may be implemented as one pixel using a sub-pixel rendering algorithm.

[0234] For example, each first pixel group PG1 may be configured to include a red sub-pixel Red SP and a green sub-pixel Green SP.

[0235] In another example, each second pixel group PG2 may be configured to include a blue sub-pixel Blue SP and a green sub-pixel Green SP.

[0236] In another example, each third pixel group PG3 may be configured to include a blue sub-pixel Blue SP and a red sub-pixel Red SP.

[0237] In these examples, through a sub-pixel rendering algorithm, based on the average value of the corresponding color data of adjacent pixels, such a color performance deficiency in each of the pixel groups (PG1, PG2, and PG3) can be compensated for.

[0238] Figure 5A It is shown that the sub-pixels are arranged such that a plurality of pixels each including a red sub-pixel Red SP, a green sub-pixel GreenSP, a blue sub-pixel Blue SP, and a green sub-pixel Green SP are arranged in a zigzag form in the x-axis direction, but the exemplary embodiments of the present disclosure are not limited thereto.

[0239] Figure 5B and Figure 5C are enlarged plan views of the optical regions (OA1 and OA2).

[0240] Figure 5B and Figure 5C The configuration of the sub-pixels SP shown may be substantially the same as that of the sub-pixels SP in Figure 5A Considering this similarity, for ease of description, the discussion of the sub-pixels SP and the light-transmitting regions (TA1 and TA2) in

[0241] Additionally, Figure 5B and Figure 5C The configuration of the light-transmitting regions (TA1 and TA2) may be substantially the same as that of the light-transmitting regions (TA1 and TA2) in Figure 4 is omitted. Figure 5B and Figure 5C is a cross-sectional view taken along line A-A' of

[0242] Figure 6A is an exemplary cross-sectional view taken along line A-A' of Figure 5A Referring to

[0243] Referring to Figure 6A various types of patterns (ACT, SD1, GATE, etc.), various types of insulating layers (BUF, GI, ILD1, ILD2, PAS, etc.), and various types of metal patterns (TM, GM, ML1, ML2, etc.) for forming one or more transistors (e.g., a driving transistor DRT, a scanning transistor SCT, etc.) may be provided on or above the substrate SUB.

[0244] Referring to Figure 6A a buffer layer BUF may be provided on the substrate SUB.

[0245] A first metal layer ML1 and a second metal layer ML2 may be provided on the substrate SUB.

[0246] For example, the first metal layer ML1 and the second metal layer ML2 may be a light shielding layer LSL configured to shield light.

[0247] The buffer layer BUF may be disposed on the first metal layer ML1 and the second metal layer ML2.

[0248] The active layer ACT of the driving transistor DRT may be disposed on the buffer layer BUF.

[0249] The gate insulating layer GI may be configured to cover the active layer ACT.

[0250] The gate GATE of the driving transistor DRT may be disposed on the gate insulating layer GI.

[0251] In one or more aspects, together with the gate layer GATE of the driving transistor DRT, the gate material layer GM may be disposed on the gate insulating layer GI at a position different from the region where the driving transistor DRT is formed.

[0252] The first interlayer insulating layer ILD1 may be configured to cover the gate layer GATE and the gate material layer GM.

[0253] The metal pattern TM may be disposed on the first interlayer insulating layer ILD1.

[0254] The metal pattern TM may be located at a position different from the region where the driving transistor DRT is formed.

[0255] The second interlayer insulating layer ILD2 may be configured to cover the metal pattern TM on the first interlayer insulating layer ILD1.

[0256] Two first source / drain pattern layers SD1 may be disposed on the second interlayer insulating layer ILD2.

[0257] One of the two first source / drain pattern layers SD1 may be the source node of the driving transistor DRT, and the other may be the drain node of the driving transistor DRT.

[0258] The two first source / drain pattern layers SD1 may be electrically connected to corresponding portions (e.g., the first side and the second opposite side) of the active layer ACT through contact holes in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI.

[0259] The portion of the active layer ACT overlapping with the gate layer GATE may be used as the channel region.

[0260] For example, one of the two first source-drain pattern layers SD1 can be connected to one side of the channel region of the active layer ACT, and the other of the two first source-drain pattern layers SD1 can be connected to the other side of the channel region of the active layer ACT.

[0261] The passivation layer PAS can be configured to cover the two first source-drain pattern layers SD1.

[0262] At least one planarization layer PLN can be provided on the passivation layer PAS.

[0263] The at least one planarization layer PLN can include a first planarization layer PLN1 and a second planarization layer PLN2.

[0264] The first planarization layer PLN1 can be provided on the passivation layer PAS.

[0265] A second source-drain pattern layer SD2 can be provided on the first planarization layer PLN1.

[0266] The second source-drain pattern layer SD2 can be connected to one of the two first source-drain pattern layers SD1 (which can correspond to Figure 3 the second node N2 of the driving transistor DRT in the sub-pixel SP) through a contact hole in the first planarization layer PLN1.

[0267] The second planarization layer PLN2 can be configured to cover the second source-drain pattern layer SD2.

[0268] A light-emitting element ED can be provided on the second planarization layer PLN2.

[0269] The light-emitting element ED can have a stacked structure configured with a stack as discussed below. A first electrode layer AE can be provided on the second planarization layer PLN2.

[0270] The first electrode layer AE can include a material having a relatively high work function.

[0271] For example, the first electrode layer AE can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), indium oxide (In2O3), tin oxide (SnO2), etc., but the exemplary embodiments of the present disclosure are not limited thereto.

[0272] The first electrode layer AE can be electrically connected to the second source-drain pattern layer SD2 through a contact hole in the second planarization layer PLN2.

[0273] The bank layer BNK can be configured to cover a part of the first electrode layer AE.

[0274] A portion of the bank layer BNK corresponding to the light-emitting region EA of the corresponding sub-pixel SP may be open to form an opening region OPN.

[0275] For example, a portion of the first electrode layer AE may be exposed in the opening region OPN of the bank layer BNK.

[0276] The light-emitting layer EL may be located on the side surface of the bank layer BNK and in the opening region OPN of the bank layer BNK.

[0277] All or at least a portion of the light-emitting layer EL may be located between adjacent portions of the bank layer BNK.

[0278] In the opening region OPN of the bank layer BNK, the light-emitting layer EL may be in contact with the first electrode layer AE.

[0279] A second electrode layer CE may be provided on the light-emitting layer EL.

[0280] The second electrode layer CE may include a material having a relatively low work function, such as a metal, an alloy, a conductive compound, or a mixture of two or more thereof.

[0281] For example, a transmissive electrode as the second electrode layer CE may be obtained by forming lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), etc. in the form of a thin film.

[0282] In this regard, various modifications may be made. For example, in a structure where the light-emitting element is configured to emit light forward toward the display device 100 having a top-emission structure, an ITO or IZO is used to form the transmissive electrode.

[0283] The light-emitting layer EL may include an organic material.

[0284] The light-emitting layer EL may include a red light-emitting layer R_EL provided in the red sub-pixel Red SP, a green light-emitting layer G_EL provided in the green sub-pixel Green SP, and a blue light-emitting layer B_EL provided in the blue sub-pixel Blue SP.

[0285] For example, the wavelengths of the light emitted from the light-emitting layers (R_EL, G_EL, and B_EL) in descending order of length may be the red light-emitting layer R_EL, the green light-emitting layer G_EL, and the blue light-emitting layer B_EL.

[0286] The red light-emitting layer R_EL may include a red host and a red dopant.

[0287] The red host can be Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more of them, but the exemplary embodiments of the present disclosure are not limited thereto.

[0288] The red dopant can be PtOEP, Ir(piq)3, Btp2Ir(acac), Ir(2-phq)2(acac), Ir(2-phq)3, Ir(flq)2(acac), Ir(fliq)2(acac) or a compound containing DCM or DCJTB, but the embodiments of the present disclosure are not limited thereto.

[0289] The green light-emitting layer G_EL can include a green host and a green dopant.

[0290] The green host can be Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more of them, but the exemplary embodiments of the present disclosure are not limited thereto.

[0291] The green dopant can be Ir(ppy)3 tris(2-phenylpyridine) iridium, Ir(ppy)2(acac) (bis(2-phenylpyridine)(acetylacetonato)iridium(III), Ir(mppy)3 (tris(2-(4-tolyl)phenylpyridine) iridium, C545T 10-(2-benzothiazolyl)-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]benzopyrano[6,7,8-ij]-quinazolin-11-one, etc., but the exemplary embodiments of the present disclosure are not limited thereto.

[0292] The blue light-emitting layer B_EL can include a blue host and a blue dopant.

[0293] The blue host can be Alq3, CBP (4,4'-N,N'-dicarbazole-biphenyl), PVK (poly(n-vinylcarbazole)), ADN (9,10-bis(naphthalen-2-yl)anthracene), TCTA, TPBI (1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene), TBADN (3-tert-butyl-9,10-bis(naphthalen-2-yl)anthracene), E3, DSA (distyrylarylene), or a mixture of two or more of them, but the exemplary embodiments of the present disclosure are not limited thereto.

[0294] The blue dopant can be a compound containing F2Irpic, (F2ppy)2Ir(tmd), Ir(dfppz)3, ter-fluorene, DPAVBi (4,4'-bis(4-diphenylaminostyryl)biphenyl), TBPe, etc., but the embodiments of the present disclosure are not limited thereto.

[0295] As described above, as part of the layers included in the stacked structure of the light-emitting element ED, the first electrode layer AE, the light-emitting layer EL, and the second electrode layer CE have been discussed.

[0296] Hereinafter, as other layers included in the stacked structure of the light-emitting element ED, reference is made to Figure 6A discuss the hole injection layer HIL and the hole transport layer HTL.

[0297] The hole injection layer HIL can be provided on the first electrode layer AE and the bank layer BNK in the light-emitting element ED.

[0298] The hole injection layer HIL can include at least one hole H on the bank layer BNK.

[0299] For example, at least one hole H can be formed between the opening region OPN of the red sub-pixel Red SP and the opening region OPN of the blue sub-pixel Blue SP. In this embodiment, since the lateral leakage current LLC generated when the blue sub-pixel Blue SP is driven and flowing along the hole injection layer HIL can be blocked by the hole H, it is possible to prevent the red sub-pixel Red SP adjacent to the blue sub-pixel Blue SP from being accidentally driven to emit an unexpected color.

[0300] Therefore, the hole H of the hole injection layer HIL can be used to minimize such lateral leakage current LLC.

[0301] Figure 6A It is shown that the hole H is located in the inclined portion of the bank layer BNK, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the hole H can be located in the flat portion of the bank layer BNK.

[0302] Figure 6A It is shown that only one hole H is formed in each light-emitting element ED, but the exemplary embodiments of the present disclosure are not limited thereto. For example, each light-emitting element ED can form a plurality of holes H.

[0303] In an example where a plurality of holes H are formed in each light-emitting element ED, the plurality of holes H can be configured to be spaced apart from each other on the bank layer BNK.

[0304] For example, in an example where the holes H are configured to overlap each other, the size of the holes caused by the overlap of the holes H may become larger. For example, one or more holes H can be formed in the flat portion or one or more inclined portions of the bank layer BNK, or two or more holes H can be formed in one or more inclined portions and flat portions of the bank layer BNK.

[0305] The absolute value of the lowest unoccupied molecular orbital (LUMO) energy level of the hole injection layer HIL can be greater than the absolute value of the energy level of the metal contained in the first electrode layer AE.

[0306] The hole injection layer (HIL) can prevent the deterioration of the hole transport layer (HTL) by restricting electrons from entering the HIL along the HTL.

[0307] In addition, due to the dipole characteristics of the HIL, hole injection from the first electrode layer (AE) with a low work function energy level can be promoted.

[0308] For example, an amine derivative or the like can be used as the material for the hole injection layer (HIL).

[0309] The hole injection layer (HIL) can include a p-type dopant to improve the hole injection ability.

[0310] In one or more aspects, using one or more suitable methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, etc., the hole transport layer (HTL) can be formed on the hole injection layer (HIL).

[0311] When a voltage is applied between the first electrode layer (AE) and the second electrode layer (CE) of the light-emitting device (ED), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (not shown) can move to the light-emitting layer (EL) and form excitons, enabling the light-emitting layer (EL) to emit visible light.

[0312] For example, a carbazole derivative (such as N-phenylcarbazole, polyvinylcarbazole, etc.) and an amine derivative having an aromatic condensed ring (such as NPB, etc.) can be used as the material for the hole transport layer (HTL).

[0313] For example, TCTA, which can be used as the material for the hole transport layer (HTL), can not only be used to transport holes but also prevent excitons from diffusing from the light-emitting layer (EL).

[0314] The thickness of the hole transport layer can be about 5 nm to 100 nm, preferably 10 nm to 70 nm.

[0315] When the thickness of the hole transport layer satisfies this range, excellent hole transport characteristics can be obtained without significantly increasing the driving voltage.

[0316] In one or more aspects, the hole transport layer (HTL) can include a common hole transport layer (not shown) disposed on the hole injection layer (HIL).

[0317] The hole transport layer (HTL) can include a light-emitting auxiliary layer (not shown) disposed between the hole transport layer (HTL) and the common hole transport layer.

[0318] The light-emitting auxiliary layer can include a red light-emitting auxiliary layer, a green light-emitting auxiliary layer, and a blue light-emitting auxiliary layer disposed on the hole transport layer (HTL).

[0319] For example, a light-emitting auxiliary layer can be used to transport holes and can include a hole transport material (e.g., a hole transport layer (HTL) material). Each light-emitting auxiliary layer can include the same material or compound, or can include different materials or compounds.

[0320] The light-emitting element ED can include an electron blocking layer (not shown) located between the hole transport layer HTL and the light-emitting layer EL.

[0321] In one or more aspects, although Figure 6A not shown in, the light-emitting element ED can include a hole blocking layer (not shown) on the light-emitting layer EL located between the second electrode layer CE and the light-emitting layer EL, an electron transport layer (not shown) on the hole blocking layer, and an electron injection layer (not shown) on the electron transport layer.

[0322] In one or more aspects, by way of example, Figure 6A the light-emitting element ED is shown to have a single stacked structure, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the light-emitting element ED can have a multi-stacked structure including a plurality of light-emitting layers EL.

[0323] Referring to Figure 6A , an encapsulation layer ENCAP can be provided on the light-emitting element ED.

[0324] The encapsulation layer ENCAP can have a single-layer structure or a multi-layer structure.

[0325] For example, the encapsulation layer ENCAP can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0326] In this example, the first encapsulation layer and the third encapsulation layer can be inorganic layers, and the second encapsulation layer can be an organic layer.

[0327] Among the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer, the second encapsulation layer can be the thickest and can be used as a planarization layer.

[0328] The encapsulation layer ENCAP can be provided on the second electrode layer CE and is provided closest to the light-emitting element ED.

[0329] The first encapsulation layer can include an inorganic insulating material that can be deposited using low-temperature deposition.

[0330] The first encapsulation layer can include a metal oxide layer, a metal nitride layer, a metal nitride layer, etc.

[0331] For example, the first encapsulation layer may include MoOx (x = 2 to 4), Al2O3, Sb2O3, BaO, CdO, CaO, Ce2O3, CoO, Cu2O, DyO, GdO, HfO2, La2O3, Li2O, MgO, NbO, NiO, Nd2O3, PdO, Sm2O3, ScO, SiO2, SrO, Ta2O3, TiO, WO3, VO2, YbO, Y2O3, ZnO, ZrO, AlN, BN, NbN, SiN, TaN, TiN, VN, YbN, ZrN, SiON, AlON, or a mixture thereof, but the exemplary embodiments of the present disclosure are not limited thereto.

[0332] Since the first encapsulation layer can be deposited in a low-temperature atmosphere, in the deposition process, the first encapsulation layer can prevent the light-emitting layer EL containing organic materials susceptible to high-temperature atmospheres from being damaged.

[0333] The second encapsulation layer may be configured to have a smaller area than the first encapsulation layer.

[0334] In this embodiment, the second encapsulation layer may be configured to expose both ends of the first encapsulation layer.

[0335] The second encapsulation layer can be used as a buffer to buffer the stress between the corresponding layers when the display device 100 is bent or folded, and also for enhancing the planarization performance.

[0336] For example, the second encapsulation layer may include an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbide (SiOC), etc.

[0337] For example, inkjet technology can be used to set the second encapsulation layer.

[0338] The third encapsulation layer may be disposed above the substrate SUB on which the second encapsulation layer is disposed, such that the third encapsulation layer covers the corresponding top surfaces and the corresponding one or more side surfaces of at least one of the second encapsulation layer and the first encapsulation layer.

[0339] The third encapsulation layer can minimize or block the penetration of external moisture or oxygen into the first encapsulation layer and the second encapsulation layer.

[0340] For example, the third encapsulation layer may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc.

[0341] Hereinafter, with reference to Figure 6B Describe the stacked structure of the first optical region OA1.

[0342] Figure 6B is along Figure 5BAn exemplary cross-sectional view taken along line B-B'.

[0343] Figure 6B The configurations of the driving transistor DRT and the light-emitting element ED can be substantially the same as those of Figure 6A the driving transistor DRT and the light-emitting element ED.

[0344] Similar to Figure 6A in the example of Figure 6B at least one hole H can be formed between the opening region OPN of the red sub-pixel Red SP and the opening region OPN of the blue sub-pixel Blue SP. In the present embodiment, since the lateral leakage current LLC generated when the blue sub-pixel Blue SP is driven and flowing along the hole injection layer HIL can be blocked by the hole H, it is possible to prevent the red sub-pixel Red SP adjacent to the blue sub-pixel Blue SP from being accidentally driven to emit an unexpected color.

[0345] For example, one or more holes of the hole injection layer HIL can be formed not only in Figure 6A the normal region NA of Figure 6B but also in the first optical region OA1 of

[0346] In this example, by forming such a hole H in the hole injection layer HIL on the bank layer between a sub-pixel of one color and an adjacent sub-pixel of another color, the lateral leakage current LLC can be prevented, so that the sub-pixel of another color can be prevented from being accidentally driven to emit light, thereby enabling the display device 100 to be driven at low power.

[0347] Therefore, in order to increase the lifespan of the light-emitting element ED in the optical regions (OA1, OA2) by low-power driving to reduce the brightness difference between the normal region NA and the optical regions (OA1, OA2), it is desirable to form one or more holes H only in one or more optical regions (OA1 and / or OA2).

[0348] Referring to Figure 6B , it should be noted that the layer stack structures of the non-light-transmitting region (for example, the remaining region except the light-transmitting region TA1) in the first optical region OA1 and the normal region NA discussed above can be substantially the same.

[0349] Therefore, the layer stack structure of the first light-transmitting region TA1 in the first optical region OA1 will be described in detail below.

[0350] A second electrode layer CE can be provided in the normal region NA and the non-light-transmitting region of the first optical region OA1, but the second electrode layer CE may not be provided in the first light-transmitting region TA1 of the first optical region OA1.

[0351] For example, the first light-transmitting region TA1 of the first optical region OA1 may correspond to an opening (or opening region) of the second electrode layer CE.

[0352] In one or more aspects, a light-shielding layer LSL including at least one of the first metal layer ML1 and the second metal layer ML2 may be provided in the normal region NA and the light-blocking region of the first optical region OA1, but the light-shielding layer LSL may not be provided in the first light-transmitting region TA1 of the first optical region OA1.

[0353] For example, the first light-transmitting region TA1 of the first optical region OA1 may correspond to an opening (or opening region) of the light-shielding layer LSL.

[0354] In one or more aspects, the substrate SUB and various types of insulating layers (BUF, GI, ILD1, ILD2, PAS, PLN1, PLN2, BNK, and ENCAP) provided in the normal region NA and the light-blocking region of the first optical region OA1 may be similarly provided in the first light-transmitting region TA1 of the first optical region OA1.

[0355] For example, among the elements or layers provided in the normal region NA and the light-blocking region of the first optical region OA1, a material layer having electrical properties other than the insulating layer (e.g., a metal material layer, a semiconductor layer, etc.) may not be provided in the first light-transmitting region TA1 of the first optical region OA1.

[0356] For example, referring to Figure 6B , the metal material layers (ML1, ML2, GATE, GM, TM, SD1, and SD2) and the semiconductor layer ACT related to the transistor may not be provided in the first light-transmitting region TA1 of the first optical region OA1.

[0357] In one or more aspects, the first electrode layer AE and the second electrode layer CE included in the light-emitting element ED may not be provided in the first light-transmitting region TA1.

[0358] In one or more aspects, it should be noted that, according to design requirements, the light-emitting layer EL included in the light-emitting element ED may be provided in the first light-transmitting region TA1, or may not be provided in the first light-transmitting region TA1.

[0359] Therefore, since a material layer having electrical properties (e.g., a metal material layer, a semiconductor layer, etc.) is not provided in the first light-transmitting region TA1 of the first optical region OA1, the transmittance of the first light-transmitting region TA1 of the first optical region OA1 can be improved.

[0360] Therefore, the first optoelectronic device 11 can receive light passing through the first light-transmitting region TA1 and perform a predetermined function (e.g., image sensing, image capturing, etc.).

[0361] Since all or at least a part of the first light-transmitting region TA1 in the first optical region OA1 overlaps with the first optoelectronic device 11, it is necessary to increase the transmittance of the first light-transmitting region TA1 in the first optical region OA1 so that the first optoelectronic device 11 can operate normally.

[0362] In one or more aspects, to achieve this configuration, as Figure 6B shown, among multiple insulating layers, the first planarization layer PLN1 may include at least one uneven portion (e.g., at least one recessed portion or / and at least one protruding portion).

[0363] For example, the first planarization layer PLN1 may be an organic insulating layer.

[0364] In an example where a part of the first planarization layer PLN1 is recessed and / or protrudes downward, the second planarization layer PLN2 may basically serve as a planarization layer.

[0365] In one or more aspects, the second planarization layer PLN2 may also be recessed and / or protrude downward. In this embodiment, the second encapsulation layer PCL may basically serve as a planarization layer.

[0366] Referring to Figure 6B , the downward protruding portion of the first planarization layer PLN1 and the portion of the passivation layer PAS disposed along the bottom of this portion of the first planarization layer PLN1 may pass through the insulating layers (ILD1, ILD2, and GI) for forming the transistor DRT and the buffer layer SUB located below the insulating layers. Then, this portion of the passivation layer PAS may reach a part of the substrate SUB (e.g., the upper part, the side part, etc.).

[0367] In one or more aspects, the substrate SUB may include at least one recessed portion to increase the transmittance.

[0368] For example, in the first light-transmitting region TA1, the upper part of the substrate SUB may be recessed, or a part of the substrate SUB may be perforated.

[0369] Hereinafter, referring to Figures 6C to 6D describe the stacked structure of the second optical region OA2.

[0370] Figure 6C and Figure 6D are example cross-sectional views taken along the line C-C' of Figure 5C .

[0371] Figure 6C andFigure 6D The configurations of the respective driving transistors DRTs and the respective light-emitting elements EDs therein may be substantially the same as those of the driving transistors DRTs and the light-emitting elements EDs in Figure 6A .

[0372] In Figure 6C and Figure 6D In each example, at least one hole H may be formed between the opening region OPN of the red sub-pixel Red SP and the opening region OPN of the green sub-pixel Green SP. In this embodiment, since the lateral leakage current LLC generated when the green sub-pixel Green SP is driven and flowing along the hole injection layer HIL can be blocked by the hole H, it is possible to prevent the red sub-pixel Red SP adjacent to the green sub-pixel Green SP from being accidentally driven and emitting an unexpected color.

[0373] For example, one or more holes of the hole injection layer HIL may be formed not only in the Figure 6A normal region NA of Figure 6C and Figure 6D but also in the second optical region OA2 of

[0374] In this example, by forming such a hole H in the hole injection layer HIL on the bank layer between a sub-pixel of one color and an adjacent sub-pixel of another color, the lateral leakage current LLC can be prevented, so that the sub-pixel of the other color can be prevented from being accidentally driven to emit light, enabling the display device 100 to be driven at low power.

[0375] Referring to Figure 6C and Figure 6D , it should be noted that the stacked structures of the non-light-transmitting regions (e.g., the remaining regions except the light-transmitting region TA2) and the normal region NA in the second optical region OA2 discussed above may be substantially the same.

[0376] Therefore, the stacked structure of the second light-transmitting region TA2 in the second optical region OA2 will be described in detail below.

[0377] A second electrode layer CE may be provided in the non-light-transmitting regions of the normal region NA and the second optical region OA2, but the second electrode layer CE may not be provided in the second light-transmitting region TA2 of the second optical region OA2.

[0378] For example, the second light-transmitting region TA2 of the second optical region OA2 may correspond to the opening (or opening region) of the second electrode layer CE.

[0379] In one or more aspects, a light-shielding layer LSL including at least one of a first metal layer ML1 and a second metal layer ML2 may be provided in a non-transmissive region of a normal region NA and a second optical region OA2, but the light-shielding layer LSL may not be provided in a second transmissive region TA2 of the second optical region OA2.

[0380] When the transmittance of the second optical region OA2 is substantially the same as the transmittance of the first optical region OA1, the stack structure of the second transmissive region TA2 of the second optical region OA2 may be substantially the same as the stack structure of the first transmissive region TA1 of the first optical region OA1.

[0381] When the transmittance of the second optical region OA2 is different from the transmittance of the first optical region OA1, the stack structure of the second transmissive region TA2 of the second optical region OA2 may be at least partially different from the stack structure of the first transmissive region TA1 of the first optical region OA1.

[0382] For example, when the transmittance of the second optical region OA2 is lower than the transmittance of the first optical region OA1, the second transmissive region TA2 of the second optical region OA2 may not have a transmittance enhancing structure.

[0383] For example, the first planarization layer PLN1 and the passivation layer PAS may not be recessed and / or protruded.

[0384] For example, the width of the second transmissive region TA2 of the second optical region OA2 may be smaller than the width of the first transmissive region TA1 of the first optical region OA1.

[0385] In one or more aspects, a substrate SUB and various types of insulating layers (BUF, GI, ILD1, ILD2, PAS, PLN1, PLN2, BNK, and ENCAP) provided in a non-transmissive region of a normal region NA and a second optical region OA2 may be similarly provided in the second transmissive region TA2 of the second optical region OA2.

[0386] For example, among elements or layers provided in a non-transmissive region of a normal region NA and a second optical region OA2, a material layer having electrical properties other than the insulating layer (e.g., a metal material layer, a semiconductor layer, etc.) may not be provided in the second transmissive region TA2 of the second optical region OA2.

[0387] For example, referring to Figure 6C and Figure 6D , the metal material layers (ML1, ML2, GATE, GM, TM, SD1, and SD2) and the semiconductor layer related to the transistor (ACT) may not be provided in the second transmissive region TA2 of the second optical region OA1.

[0388] In one or more aspects, the first electrode layer AE and the second electrode layer CE included in the light-emitting element ED may not be provided in the second light-transmissive region TA2.

[0389] In one or more aspects, it should be noted that, according to design requirements, the light-emitting layer EL included in the light-emitting element ED may be provided in the second light-transmissive region TA2, or may not be provided in the second light-transmissive region TA2.

[0390] Therefore, since a material layer having electrical properties (such as a metal material layer, a semiconductor layer, etc.) is not provided in the second light-transmissive region TA2 of the second optical region OA2, the transmittance of the second light-transmissive region TA2 of the second optical region OA2 can be increased.

[0391] Therefore, the second optoelectronic device 12 can receive the light passing through the second light-transmissive region TA2 and perform a predetermined function (for example, detecting an approaching object or human body, detecting ambient light, etc.).

[0392] As described above, the laminated structure of the Figures 6C to 6D example has been discussed.

[0393] Hereinafter, it is described whether a protective layer PL exists in Figure 6C and Figure 6D .

[0394] Referring to Figure 6C and Figure 6D , a protective layer PL can be provided in the second light-transmissive region TA2.

[0395] As an example, Figure 6C and Figure 6D show an example in which the protective layer PL is provided in the second light-transmissive region TA2, but the exemplary embodiments of the present disclosure are not limited thereto. For example, this configuration can equally apply to the Figure 6B first light-transmissive region TA1.

[0396] The protective layer PL may include an organic material and be configured to cover at least a part of the light-transmissive regions (TA1 and TA2) using a fine metal mask (FMM).

[0397] The protective layer PL can be used to increase the transmittance of the first light-transmissive region TA1 or the second light-transmissive region TA2, and effectively pattern the second electrode layer CE formed in the corresponding light-emitting region EA.

[0398] For example, after forming the protective layer PL in the second light-transmissive region TA2 using the fine metal mask FMM, the second electrode layer CE can be deposited in the corresponding light-emitting region EA using an opening metal mask OMM. Therefore, the second electrode layer CE can be effectively formed in the light-emitting region EA except for the protective layer PL.

[0399] Thus, referring to Figure 6D , the protective layer PL and the second electrode layer CE may be located in the same layer.

[0400] However, as Figure 6D shown, the exemplary embodiments of the present disclosure are not limited to the example of retaining the protective layer PL in the second light-transmissive region TA2. For example, in order to improve the transmittance of the second light-transmissive region TA2, the protective layer PL may be removed after forming the second electrode layer CE.

[0401] For example, as Figure 6C shown, the protective layer TL may not be retained in the second light-transmissive region TA2.

[0402] Figure 7A , Figure 7B and Figure 7C are Figure 5A example enlarged plan views of the first pixel group PG1, the second pixel group PG2, and the third pixel group PG3 of

[0403] Referring together to Figure 7A and Figure 6A , the light-emitting regions EA of the sub-pixels (red SP, green SP, and blue SP) may be substantially the same as the opening regions of the bank layer BNK, respectively.

[0404] In the present embodiment, at least one hole H of the hole injection layer may be located in at least one of a part between the red sub-pixel Red SP of the bank layer BNK in the first pixel group PG1 and the green sub-pixel Green SP adjacent to the red sub-pixel Red SP, a part between the green sub-pixel Green SP of the bank layer BNK in the second pixel group PG2 and the blue sub-pixel Blue SP adjacent to the green sub-pixel Green SP, and a part between the blue sub-pixel Blue SP of the bank layer BNK in the third pixel group PG3 and the red sub-pixel Red SP adjacent to the blue sub-pixel Blue SP.

[0405] That is, Figure 7A a part shown as the bank layer BNK in

[0406] However, the hole H of the hole injection layer according to the exemplary embodiments of the present disclosure is not necessarily only located in Figure 7A a part shown as the bank layer BNK in

[0407] but may be located in a region outside the opening region of the bank layer BNK. Preferably, the hole H may be located on the corresponding part between each blue sub-pixel Blue SP and each red sub-pixel Red SP adjacent to each blue sub-pixel Blue SP of the bank layer BNK.

[0408] Referring to Figure 7A , each part represented as the bank layer BNK may refer to a region defined by two virtual straight lines that extend and touch two adjacent sub-pixels and the respective inner edges facing each other among the respective edges of the opening regions of the sub-pixels.

[0409] Referring to Figure 7B and Figure 6A , at least one hole H of the hole injection layer may be located on at least one of a line connecting the center point of the red sub-pixel Red SP to the center point of an adjacent blue sub-pixel Blue SP, a line connecting the center point of the red sub-pixel Red SP to the center point of an adjacent green sub-pixel Green SP, and a line connecting the center point of the blue sub-pixel Blue SP to the center point of an adjacent green sub-pixel Green SP.

[0410] Preferably, the hole H of the hole injection layer may be located on a line connecting the center point of each red sub-pixel Red SP to the center point of each blue sub-pixel Blue SP adjacent to each red sub-pixel Red SP.

[0411] Even in this example, the hole H may also be located in a region of the bank layer other than the opening region.

[0412] As described above, a plurality of holes H may be formed, and the plurality of holes H may be arranged to be spaced apart from each other.

[0413] Referring to Figure 7C , the holes H may overlap each other to form a large hole H, and the holes H may be arranged to be spaced apart from each other or arranged in a line.

[0414] The position of the hole H referred to above Figures 7A to 7C is merely an example, and the shape, number, and position of the hole H according to the exemplary embodiments of the present disclosure are not necessarily limited thereto.

[0415] Although the description related to the hole H has been provided based on three pixel groups (i.e., the first pixel group PG1, the second pixel group PG2, and the third pixel group PG3), the specific shape, number, and position of the hole H are not limited to a specific pixel group among the pixel groups. For example, various embodiments may be adopted in which the discussion of the hole H in the first pixel group PG1 also applies to the hole H in the second pixel group PG2.

[0416] Hereinafter, a method of manufacturing the display device 100 will be described.

[0417] Figure 8A , Figure 8B and Figure 8CIt is a flowchart showing an exemplary method of manufacturing a display device 100 according to an aspect of the present disclosure.

[0418] Referring Figure 8A , in one or more exemplary embodiments, the manufacturing method of the display device 100 may include a first electrode layer forming step S100, a hole injection layer forming step S200, a hole forming step S300, a hole transport layer forming step S400, a light emitting layer forming step S500, an electron transport layer forming step S600, and a second electrode layer forming step S700.

[0419] When discussing the manufacturing method of the display device 100 according to an aspect of the present disclosure, it should be noted that, unless otherwise clearly stated, the configurations of the first electrode layer, the hole injection layer, one or more holes, the hole transport layer, the light emitting layer, the electron transport layer, and the second electrode layer are the same as those of the first electrode layer AE, the hole injection layer HIL, one or more holes H, the hole transport layer HTL, the light emitting layer EL, the electron transport layer, and the second electrode layer CE of the display device 100 according to the above exemplary embodiments.

[0420] In the first electrode layer forming step S100, the hole injection layer forming step S200, the hole transport layer forming step S400, the light emitting layer forming step S500, the electron transport layer forming step S600, and the second electrode layer forming step S700, the first electrode layer, the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the second electrode layer are respectively formed using an opening metal mask (OMM) or a fine metal mask (FMM).

[0421] In the hole forming step S300, one or more holes H may be formed in the hole injection layer HIL using a laser or a laser beam.

[0422] Forming one or more holes H may mean that one or more portions of the hole injection layer HIL having one or more holes H are removed.

[0423] One or more holes H formed in the hole forming step S300 may be filled with a hole transport layer material of the hole transport layer HTL in the hole transport layer forming step S400.

[0424] Therefore, when one or more holes H are filled with the hole transport layer material, the hole transport layer HTL may contact the bank layer in one or more holes H.

[0425] Referring Figure 8B , in Figure 8A , before the second electrode layer forming step S700, a protective layer forming step S620 of forming a protective layer on the electron transport layer may further be included.

[0426] For example, a protective layer forming step S620 may be performed between the electron transport layer forming step S600 and the second electrode layer forming step S700, but the exemplary embodiments of the present disclosure are not limited thereto.

[0427] It should be noted that the protective layer in the protective layer forming step S620 may be substantially the same as the protective layer PL described in Figure 6D the above.

[0428] The protective layer PL may include an organic material and be deposited using a fine metal mask (FMM) to cover at least a part of one or more light-transmitting regions (TA1 and / or TA2).

[0429] The protective layer PL may be used to increase the light transmittance of one or more light-transmitting regions (TA1 and / or TA2) and effectively pattern the second electrode layer CE formed in the corresponding light-emitting region in the second electrode layer forming step S700.

[0430] For example, after forming the protective layer in one or more light-transmitting regions (TA1 and / or TA2) using a fine metal mask (FMM), the second electrode layer CE can be effectively formed in the light-emitting region except for the protective layer by depositing the second electrode layer CE in the light-emitting region EA using an opening metal mask (OMM).

[0431] Referring to Figure 8C , in Figure 8B the second electrode layer forming step S700, a protective layer removing step S800 of removing the protective layer formed in the protective layer forming step S620 may further be included.

[0432] Figure 9 FIG. is an exemplary schematic diagram showing the presence of lateral leakage current in the display device 100 according to an aspect of the present disclosure.

[0433] Referring to Figure 9 , <x>The image shows a hole H in which a hole injection layer is not formed between the blue sub-pixel Blue SP and the red sub-pixel Red SP adjacent to the blue sub-pixel Blue SP on the bank layer, <y>The image shows a hole H for forming a hole injection layer between a blue sub-pixel Blue SP and a red sub-pixel Red SP adjacent to the blue sub-pixel Blue SP on a part of the bank layer.

[0434] Refer to Figure 9 , in <x>In the image, when no hole H is formed in the hole injection layer, when the corresponding blue light-emitting element ED is driven by the driving transistor, the lateral leakage current LLC flowing through the hole injection layer can move from the blue light-emitting element to the corresponding red light-emitting element, so that the red light-emitting element can be driven to emit red light.

[0435] On the contrary, when the hole H is formed in the hole injection layer, as <y>As shown in the figure, the lateral leakage current LLC flowing through the hole injection layer cannot move from the blue light-emitting element to the red light-emitting element, so the red light-emitting element cannot be driven, resulting in the red light-emitting element not emitting light.

[0436] Therefore, as <y>As shown in the figure, by forming holes in the hole injection layer, the lateral leakage current LLC can be blocked, and the emission of unexpected colors can be prevented.

[0437] Figure 10 It is an exemplary graph showing the change of the extinction coefficient and refractive index with respect to wavelength in the display device 100 according to an aspect of the present disclosure.

[0438] It should be noted that Figure 9 of <x>Image and <y>Each configuration of the image with respect to the presence or absence of holes in the hole injection layer similarly corresponds to Figure 10 of <x>Curve graph and <y>Curve graph.

[0439] At <x>In the configuration, since holes are not formed in the hole injection layer, short-wavelength light that needs to be detected by one or more optoelectronic devices (11 and / or 12) is absorbed by the hole injection layer, resulting in a problem that the detection performance of one or more optoelectronic devices (11 and / or 12) is reduced.

[0440] On the contrary, as in <y>In the configuration, when holes are formed in the hole injection layer, since the amount of the hole injection layer in the hole region is reduced, the absorption rate of short-wavelength light can be decreased.

[0441] In other words, in <y>In the curve graph, it can be seen that the extinction coefficient k corresponding to the short wavelength (380 nm to 430 nm) decreases from 0.2 to 0.4 (k X ) to less than 0.2 (k Y ).

[0442] Therefore, due to the decrease in the extinction coefficient (k Y ) in the short wavelength, the sensing performance of one or more optoelectronic devices (11 and / or 12) configured to sense the short wavelength can be improved.

[0443] Referring to Figure 10 , it can be seen that even if holes are formed in the hole injection layer, the change in the refractive index n in the short wavelength (380 nm to 430 nm) is very small, so it will not affect the refractive index.

[0444] The above exemplary embodiments will be briefly described below.

[0445] According to an exemplary embodiment of the present disclosure, a display device can be provided, including: a substrate on which a normal area capable of setting a plurality of first pixels and having a first resolution and an optical area capable of setting a plurality of second pixels and having a second resolution lower than the first resolution are defined; a first electrode layer located above the substrate; a bank layer located above the substrate, covering a part of the first electrode layer and including an opening area; a hole injection layer located on the first electrode layer and the bank layer, and including at least one hole located on the bank layer; a hole transport layer located on the hole injection layer; and a light-emitting layer located on the hole transport layer.

[0446] In one or more aspects, at least one hole can be filled with the hole transport layer.

[0447] In one or more aspects, the hole transport layer can be in contact with the bank layer at at least one hole.

[0448] In one or more aspects, at least one hole can be located in an area other than the opening area.

[0449] In one or more aspects, the plurality of first pixels or the plurality of second pixels can include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. At least one hole can be located in at least one of a part of the bank layer between the red sub-pixel in the plurality of red sub-pixels and the green sub-pixel adjacent to the red sub-pixel in the plurality of green sub-pixels, a part of the bank layer between the green sub-pixel in the plurality of green sub-pixels and the blue sub-pixel adjacent to the green sub-pixel in the plurality of blue sub-pixels, and a part of the bank layer between the blue sub-pixel in the plurality of blue sub-pixels and the red sub-pixel adjacent to the blue sub-pixel in the plurality of red sub-pixels.

[0450] In one or more aspects, at least one hole may be located in a portion of the bank layer between the blue sub-pixel and the red sub-pixel.

[0451] In one or more aspects, at least one hole may be located on at least one of the lines connecting the center point of a red sub-pixel among a plurality of red sub-pixels to the center point of a blue sub-pixel adjacent to the red sub-pixel among a plurality of blue sub-pixels, the line connecting the center point of a red sub-pixel among a plurality of red sub-pixels to the center point of a green sub-pixel adjacent to the red sub-pixel among a plurality of green sub-pixels, and the line connecting the center point of a blue sub-pixel among a plurality of blue sub-pixels to the center point of a green sub-pixel adjacent to the blue sub-pixel among a plurality of green sub-pixels.

[0452] In one or more aspects, at least one hole may be located on the line connecting the center point of the blue sub-pixel to the center point of the red sub-pixel.

[0453] In one or more aspects, at least one hole may be located in the normal area or the optical area.

[0454] In one or more aspects, the optical area may include a light-transmitting area and a non-light-transmitting area, and the second electrode layer may be located on the light-emitting layer in the non-light-transmitting area.

[0455] In one or more aspects, the display device may further include a protective layer disposed on the light-emitting layer in the light-transmitting area.

[0456] In one or more aspects, the protective layer and the second electrode layer may be disposed in the same layer.

[0457] In one or more aspects, the light-transmitting area may have a circular, elliptical or polygonal shape.

[0458] In one or more aspects, the hole injection layer may contain a p-type dopant.

[0459] In one or more aspects, at least one hole may be configured to prevent current from flowing in the at least one hole.

[0460] In one or more aspects, at least one hole is located in the inclined portion or the flat portion of the bank layer.

[0461] In one or more aspects, the display device includes a plurality of holes, and the plurality of holes are spaced apart from each other, overlap each other or are arranged in a line.

[0462] According to an exemplary embodiment of the present disclosure, a method of manufacturing a display device may be provided, including: forming a first electrode layer; forming a hole injection layer on the first electrode layer; forming holes in the hole injection layer; forming a hole transport layer on the hole injection layer and filling the holes with the hole transport layer; forming an electron transport layer on the light-emitting layer; and forming a second electrode layer on the electron transport layer.

[0463] In one or more aspects, the method of manufacturing a display device may further include forming a protective layer on the electron transport layer before forming the second electrode layer.

[0464] In one or more aspects, the method of manufacturing a display device may further include removing the protective layer after forming the second electrode layer.

[0465] According to an exemplary embodiment of the present disclosure, a display device may be provided, including a substrate, on which a normal area defining a plurality of first pixels and having a first resolution and an optical area defining a plurality of second pixels and having a second resolution lower than the first resolution are provided, wherein at least one of the normal area and the optical area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting element, the light-emitting element is located above the substrate, and wherein the light-emitting element includes: a first electrode layer; a hole injection layer located on the first electrode layer and including at least one hole; a hole transport layer located on the hole injection layer; a light-emitting layer located on the hole transport layer; and a second electrode layer located on the light-emitting layer.

[0466] The above description is provided to enable a person of ordinary skill in the art to make, use, and practice the technical features of the present disclosure, and is provided as an example in the context of a particular application and its requirements. A person of ordinary skill in the art will readily understand various modifications, additions, and substitutions to the described embodiments, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and the drawings provide examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.< / y> < / y> < / x> < / y> < / x> < / y> < / x> < / y> < / y> < / x> < / y> < / x>

Claims

1. A display device, comprising: A substrate having a general area on which a plurality of first pixels can be arranged and having a first resolution and an optical area on which a plurality of second pixels can be arranged and having a second resolution lower than the first resolution; A first electrode layer, located above the substrate; a bank layer, located above the substrate, covering a portion of the first electrode layer and including an opening area; a hole injection layer located on the first electrode layer and the bank layer and comprising at least one hole located on the bank layer; A hole transport layer, located on the hole injection layer; as well as The light-emitting layer is located on the hole transport layer.

2. The display device according to claim 1, wherein: The at least one hole is filled with a hole transport layer.

3. The display device according to claim 1, wherein: The hole transport layer contacts the bank layer at the at least one hole.

4. The display device according to claim 1, wherein: The at least one hole is located in a region other than the opening region.

5. The display device according to claim 1, wherein: The plurality of first pixels or the plurality of second pixels include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, and Wherein, the at least one hole is located in at least one of a portion of the embankment layer between a red sub-pixel among the multiple red sub-pixels and a green sub-pixel adjacent to the red sub-pixel among the multiple green sub-pixels, a portion of the embankment layer between the green sub-pixel among the multiple green sub-pixels and a blue sub-pixel adjacent to the green sub-pixel among the multiple blue sub-pixels, and a portion of the embankment layer between the blue sub-pixel among the multiple blue sub-pixels and the red sub-pixel adjacent to the blue sub-pixel among the multiple red sub-pixels.

6. The display device according to claim 5, wherein: The at least one hole is located in the portion of the bank layer between the blue sub-pixel and the red sub-pixel.

7. The display device according to claim 5, wherein: The at least one hole is located on at least one of a line connecting a center point of the red sub-pixel and a center point of the green sub-pixel, a line connecting a center point of the green sub-pixel and a center point of the blue sub-pixel, and a line connecting a center point of the blue sub-pixel and a center point of the red sub-pixel.

8. The display device according to claim 7, wherein: The at least one hole is located on the line connecting the center point of the blue sub-pixel and the center point of the red sub-pixel.

9. The display device according to claim 1, wherein: The at least one hole is located in the general area or the optical area.

10. The display device according to claim 1, wherein: The optical region includes a light-transmitting region and a non-light-transmitting region, and the second electrode layer is located on the light-emitting layer in the non-light-transmitting region. The display device according to claim 10 , further comprising a protective layer disposed on the light-emitting layer in the light-transmitting region.

12. The display device according to claim 11, wherein: The protection layer and the second electrode layer are arranged in the same layer.

13. The display device according to claim 1, wherein: The hole injection layer includes a p-type dopant.

14. The display device according to claim 4, wherein: The at least one hole is located in the inclined portion or the flat portion of the bank layer.

15. The display device according to claim 1, wherein: The display device includes a plurality of holes that are spaced apart from each other, overlapped with each other, or arranged in a line.

16. A method for manufacturing a display device, the method comprising: forming a first electrode layer; forming a hole injection layer on the first electrode layer; forming holes in the hole injection layer; forming a hole transport layer on the hole injection layer and filling the hole with the hole transport layer; forming a light-emitting layer on the hole transport layer; forming an electron transport layer on the light-emitting layer; as well as A second electrode layer is formed on the electron transport layer.

17. The method according to claim 16, further comprising: Before forming the second electrode layer, a protective layer is formed on the electron transport layer.

18. The method according to claim 17, further comprising: After forming the second electrode layer, the protection layer is removed.

19. A display device, comprising a substrate, wherein a general area having a first resolution and a plurality of first pixels is disposed on the substrate, and an optical area having a second resolution lower than the first resolution and a plurality of second pixels is disposed on the substrate, in, At least one of the general area and the optical area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a light emitting element, and the light emitting element is located above the substrate. Wherein, the light emitting element comprises: a first electrode layer; a hole injection layer, located on the first electrode layer and comprising at least one hole; A hole transport layer, located on the hole injection layer; a light-emitting layer, located on the hole transport layer; and The second electrode layer is located on the light-emitting layer.

20. The display device according to claim 19, wherein: The display device further includes a bank layer, the bank layer being located between the first electrode layer and the hole injection layer, the bank layer having a portion corresponding to a light emitting region of each sub-pixel forming an opening region, and Wherein, the at least one hole is located between opening areas of adjacent sub-pixels.

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