SOI semiconductor structure and manufacturing method thereof

Abstract

The invention relates to an SOI semiconductor structure and a manufacturing method thereof. The method comprises the following steps: obtaining an SOI wafer; the SOI wafer comprises a bottom semiconductor layer, a buried dielectric layer and a top semiconductor layer which are stacked from bottom to top; removing the top semiconductor layer of the first region of the SOI wafer, and thinning the buried dielectric layer of the first region; and forming a first semiconductor layer on the thinned buried dielectric layer in the first region. The thickness of the buried dielectric layer and the thickness of the top semiconductor layer are designed to be matched with the highest-voltage device in the chip to be manufactured, and in the first area where the low-voltage device is located, the top semiconductor layer is removed, and the buried dielectric layer is thinned to be matched with the thickness of the low-voltage device. And forming a first semiconductor layer of which the thickness is adaptive to that of the low-voltage device in the first region. Therefore, the buried dielectric layer and the semiconductor layer with appropriate thickness can be independently configured for devices with different withstand voltages, and device parameters and integrated circuit performance are optimized.

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