Method of manufacturing an optoelectronic device

Abstract

The present description relates to a method of manufacturing optoelectronic devices, comprising the successive steps of: a) forming an active diode stack (101) by epitaxial growth on a growth substrate; b) transferring the active diode stack onto a first transfer substrate; c) removing the growth substrate; d) forming a plurality of dies (131) by cleaving the first transfer substrate and the active diode stack; and e) transferring the dies onto a second transfer substrate (133), each die comprising a portion of the active diode stack.

Description

Technical Field

[0001] This disclosure generally relates to the field of optoelectronic devices. Specifically, it aims to provide methods for manufacturing optoelectronic devices, each of which includes, for example, a plurality of semiconductor diodes based on gallium nitride (GaN) or indium gallium nitride (InGaN), and electronic circuitry for controlling these diodes. Background Technology

[0002] Self-emissive display devices have been provided, comprising gallium nitride-based light-emitting diode (LED) arrays and electronic control circuitry capable of individually controlling the LEDs to display images. The use of gallium nitride-based LEDs is particularly effective in fabricating microdisplays with high brightness and resolution.

[0003] To form such a device, control circuitry and an LED array can be fabricated separately, and then interconnected. The LED array of this device can be fabricated in particular by a method comprising the steps of: forming an active stack of LEDs on a substrate, defining emitting regions by photolithography, etching the active LED stack, and forming anode and cathode contacts for each emitting region, as well as metal lines connected to pads, enabling coupling of the cathode and anode of the emitting regions to the control circuitry. These methods are specifically described in International Application No. WO2017 / 068029 and French Patent No. FR3079350 (DD18591 / B16845), previously filed and obtained by the applicant.

[0004] Once the LED array is formed, it is then connected to the control circuitry via a so-called wire bonding operation, either by using solder bumps or metal pillars, or by hybrid bonding with the LED array, i.e., by stacking and connecting the two elements together. Examples of hybrid bonding are described in the aforementioned International Application No. WO2017 / 068029 and French Patent No. FR3079350.

[0005] However, a drawback of this method is that during the assembly of these two components, precise alignment of the control circuitry and the LED array is required, ensuring that each LED is correctly positioned on its corresponding metal pad within the control circuitry. This alignment is particularly difficult to achieve as pixel pitch decreases and hinders increases in resolution and / or pixel integration density.

[0006] To overcome this shortcoming, particularly in the applicant's previously filed international application WO2017 / 194845 (DD16946 / B15015), a method for manufacturing an optoelectronic device is also provided, comprising the following sequential steps:

[0007] a) The control circuit is manufactured in the form of an integrated circuit, which includes multiple metal pads on its surface. The metal pads are designed to be connected to LEDs to allow individual control of the current flowing through each LED.

[0008] b) An active stack of LEDs extending continuously across the entire surface of the control circuit is transferred to the surface of the control circuit, including metal pads, to connect the semiconductor layer of the active LED stack to the metal pads of the control circuit; and

[0009] c) Construct an active LED stack to define the different LEDs of the device and insulate them from each other.

[0010] The advantage of this method is that the positions of the different LEDs in the active LED stack are not yet defined during the step of transferring the active LED stack onto the control circuit. Therefore, the transfer step does not exhibit any significant constraints in terms of alignment accuracy. The different LEDs in the active LED stack can then be defined by substrate structuring and depositing insulating and conductive layers on the substrate, providing a much higher alignment accuracy than that achievable during the transfer of one substrate to another.

[0011] In existing methods, active LED stacks are typically formed on sapphire wafers via epitaxial growth. While this enables the formation of high-performance LEDs, the use of sapphire wafers has the disadvantage of resulting in high manufacturing costs. Furthermore, sapphire wafers have a diameter of approximately 100 mm or 150 mm, while methods for forming control circuits are better suited to silicon wafers with larger diameters (e.g., approximately 300 mm). To attempt to address these issues, active stacks of gallium nitride-based LEDs have been formed on silicon substrates, for example, on silicon wafers with a diameter substantially equal to that of the wafer used to form the control circuitry. However, for certain emission wavelengths, particularly green and red, the LEDs formed in this way exhibit lower performance levels than those obtained by using sapphire wafers.

[0012] European Patent Application EP 4016594 describes an alternative method that involves reforming a large-diameter wafer by transferring a chip obtained by cutting a second sapphire wafer (on which an active stack of LEDs has previously been formed) having a diameter smaller than that of the first wafer onto a first silicon wafer typically having a diameter of about 200 mm or 300 mm. However, this method has the disadvantage of including the step of cutting the second wafer, which is particularly complex and expensive to perform, as sapphire is a very hard material and cutting it can cause chipping at the edges of the chip. Furthermore, after transferring the chip onto the first wafer, the method performs a step to remove the fragments from the second wafer produced by the previous cutting step. This removal step, performed by laser ablation, is difficult to control because the first wafer contains electronic circuitry of the type, such as CMOS (Complementary Metal-Oxide-Semiconductor), which is at risk of irreversible damage from exposure to a laser beam.

[0013] Due to the difference in thermal expansion coefficients between sapphire and gallium nitride (GaN), the GaN-based layer epitaxially grown on the second wafer is also subjected to high stress. During epitaxial growth at high temperatures, one or more GaN-based layers of the active LED stack are epitaxially grown on a thick GaN buffer layer, allowing lattice constant matching between the sapphire of the growth substrate and the GaN of the active LED stack. Therefore, the stress is gradually released within the buffer layer, allowing the layers of the active LED stack to be grown under very little or no stress at the epitaxial growth temperatures of these layers. During the cooling of the second wafer, the stress applied in the buffer layer becomes highly compressible. After the highly rigid second wafer is removed, the stress in the GaN layer is transferred to the first wafer. This can cause very large deformations in the first wafer, such as approximately several hundred micrometers, consequently making the processing of the reformed substrate incompatible with standard microelectronic devices.

[0014] Another method is described in the applicant’s previously obtained European patent EP 3780123 (DD19602 / B18565), which involves performing two full-board transfers before cutting to avoid cutting the sapphire, and then performing the chip-to-board transfer by non-aligned bonding of the type described in the aforementioned international application WO2017 / 194845. Summary of the Invention

[0015] There is a need to overcome all or some of the shortcomings of existing optoelectronic device manufacturing methods.

[0016] For this purpose, the embodiments provide a method for manufacturing an optoelectronic device, comprising the following sequential steps:

[0017] a) Forming an active diode stack by epitaxial growth on a growth substrate;

[0018] b) Transfer the active diode stack onto the first transfer substrate;

[0019] c) Remove the growth substrate;

[0020] d) Multiple dies are formed by cutting the first transfer substrate and stacking the active diodes; and

[0021] e) Transfer the die to the second transfer substrate, each die including a portion of an active diode stack.

[0022] According to an embodiment, the growth substrate or transfer substrate is heated, preferably to a temperature of 40°C or higher, more preferably to a temperature of 70°C or higher.

[0023] According to an embodiment, in step b), the growth substrate and the transfer substrate are heated, preferably to a temperature higher than or equal to 40°C.

[0024] According to an embodiment, at step b), the active diode stack is bonded to the first transfer substrate by directly bonding a first bonding layer previously deposited on the surface of the active diode stack opposite to the growth substrate to a second bonding layer previously deposited on the first transfer substrate.

[0025] According to an embodiment, at step b), the surfaces of the first bonding layer and the second bonding layer to be in contact are activated before bonding.

[0026] According to an embodiment, the first bonding layer and the second bonding layer are made of amorphous silicon.

[0027] According to an embodiment, the first bonding layer and the second bonding layer are metal layers, preferably made of titanium.

[0028] According to an embodiment, at step e), the die is bonded to the second transfer substrate by directly bonding a third bonding layer previously deposited on the surface of the active diode stack opposite to the first transfer substrate to a fourth bonding layer previously deposited on the second transfer substrate.

[0029] According to an embodiment, the third and fourth bonding layers are made of silicon oxide.

[0030] According to an embodiment, the method further includes the following steps after step e):

[0031] f) Transfer the components, including the second transfer substrate and the active diode stack, onto the active substrate, which includes integrated control circuitry.

[0032] According to an embodiment, at step f), a portion of the active diode stack and the second transfer substrate are bonded to the active substrate by bonding a first insulating layer previously deposited on the surface of the active diode stack opposite to the second transfer substrate and a first contact element located in the first insulating layer to a second insulating layer previously deposited on the active substrate and a second contact element located in the second insulating layer, respectively.

[0033] According to an embodiment, the method further includes a step g) of etching the die after step e) in order to compensate for misalignment of the die relative to the second transfer substrate.

[0034] According to an embodiment, the method further includes step h) after step g), depositing an insulating layer that fills the laterally extending gaps between the grains, and then removing a portion of the insulating layer that is vertically aligned with the grains.

[0035] According to an embodiment, the growth substrate is made of sapphire.

[0036] According to an embodiment, the active diode stack includes gallium nitride.

[0037] According to an embodiment, the active diode stack is a stack of light-emitting diodes, comprising a first semiconductor layer and a second semiconductor layer of opposite conductivity types in sequence from the growth substrate. Attached Figure Description

[0038] The foregoing features and advantages, as well as others, will be described in detail in the remainder of the disclosure of the specific embodiments given, with reference to the accompanying drawings, which are illustrative and not limiting, in which:

[0039] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L and Figure 1M These are simplified and partial side and cross-sectional views, showing the structure obtained at the end of an example step in an embodiment of the optoelectronic device manufacturing method;

[0040] Figure 2A , Figure 2B , Figure 2C and Figure 2D These are simplified and partial side views and cross-sectional views, showing the... Figures 1A to 1M The structure obtained at the end of the steps in an alternative implementation of the method; and

[0041] Figure 3A , Figure 3B , Figure 3C and Figure 3D These are simplified and partial side and cross-sectional views, respectively, showing the... Figures 1A to 1M The structure obtained at the end of the steps in another alternative implementation of the method. Detailed Implementation

[0042] In the various figures, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0043] For clarity, only those steps and elements useful for understanding the described embodiments have been shown and described in detail. In particular, applications that may benefit from the described optoelectronic device have not been described in detail, and the described embodiments are compatible with all or most applications implementing at least one optoelectronic device and may be adapted within the capabilities of those skilled in the art upon reading this disclosure. Furthermore, the formation of the integrated circuit for controlling the semiconductor diode has not been described in detail, and the described embodiments are compatible with common structures and manufacturing methods of such control circuits. Additionally, the composition and arrangement of the different layers of the active semiconductor diode stack have not been described in detail, and the described embodiments are compatible with typical active semiconductor diode stacks (particularly gallium nitride-based).

[0044] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0045] In the following description, when referring to absolute position qualifiers (such as “front”, “back”, “top”, “bottom”, “left”, “right”, etc.), or relative position qualifiers (such as “top”, “bottom”, “upper”, “lower”, etc.), or orientation qualifiers (such as “horizontal”, “vertical”, etc.), refer to the orientation of the drawing unless otherwise stated.

[0046] Unless otherwise stated, the expressions “approximately,” “about,” “basically,” and “probably” indicate plus or minus 10%, preferably plus or minus 5%.

[0047] In the following description, unless otherwise stated, the qualifiers “insulating” and “conductive” mean electrically insulating and electrically conductive, respectively.

[0048] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L and Figure 1M These are simplified and partial side and cross-sectional views, showing the structure obtained at the end of an example step in an embodiment of the optoelectronic device manufacturing method.

[0049] Figures 1A to 1M More specifically, the fabrication of an optoelectronic display device is shown, which includes an LED array and electronic control circuitry that enables individual control of the LEDs to display an image.

[0050] Figure 1A The upper surface of the growth substrate 103 is shown (on Figure 1A The structure obtained at the end of the step of forming an active LED stack 101 on the orientation of the LED is as follows. The active LED stack 101 is based, for example, on gallium nitride (GaN).

[0051] The active LED stack 101 is formed by epitaxial growth from the upper surface of a growth substrate 103. The growth substrate 103 is, for example, a wafer or a wafer sheet. Preferably, the growth substrate 103 is made of sapphire. Sapphire does indeed have the advantage of allowing the growth of high-quality gallium nitride LED stacks.

[0052] In the example shown, the active LED stack 101 includes, in sequence from the upper surface of the growth substrate 103, an N-type doped gallium nitride layer 105, an emitter layer 107, and a P-type doped gallium nitride layer 109. For example, the emitter layer 107 or active layer includes a stack of multiple emitter layers forming a quantum well, such as layers based on gallium nitride, indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium gallium nitride (AlInGaN), gallium phosphide (GaP), aluminum gallium phosphide (AlGaP), aluminum indium gallium phosphide (AlInGaP), or any combination of one or more of these materials.

[0053] As a variation, the emitter layer 107 can be intrinsic, i.e., an unintentionally doped gallium nitride layer, for example having a doping density of 10... 15 Up to 10 18 at / cm 3 The concentration of residual donor species within the range, for example, about 10 17 at / cm 3 .

[0054] In the example shown, the lower surface of emitter layer 107 contacts the upper surface of layer 105, and the upper surface of emitter layer 107 contacts the lower surface of layer 109. In practice, a stack of one or more buffer layers (not shown), such as an undoped gallium nitride layer, may form an interface between the growth substrate 103 and the gallium nitride layer 105.

[0055] As an example, the thickness of layer 105 is in the range of 0.2 µm to 2 µm, for example, about 1 µm. As an example, the thickness of layer 107 is in the range of 30 nm to 300 nm, for example, about 100 nm. As an example, the thickness of layer 109 is in the range of 5 nm to 300 nm, for example, about 100 nm. For example, the active LED stack 101 extends continuously and across a uniform thickness over the entire upper surface of the growth substrate 103.

[0056] Figure 1A The structure also includes a metal layer 111 on the upper surface of the active LED stack 101. In the example shown, the metal layer 111 is deposited on top of the gallium nitride layer 109 and in contact with its upper surface. The metal layer 111 is deposited, for example, by implementing a vacuum deposition technique, such as by physical vapor deposition (PVD), by vacuum sputtering, by chemical vapor deposition (CVD), or by vacuum evaporation. The metal layer 111 specifically ensures the functionality of the electrical contacts on the gallium nitride layer 109 of the LED stack 101. The metal layer 111 can also ensure the functionality of an optical reflector or mirror and / or the function of a barrier against the diffusion of metal elements.

[0057] As an example, metal layer 111 is formed by stacking multiple different metal layers (not shown in detail in the figures), which include, in order from the upper surface of gallium nitride layer 109:

[0058] - A first metal layer, for example made of a transparent and conductive oxide such as indium tin oxide (ITO), contacts the upper surface of the gallium nitride layer 109 and provides electrical contact on the gallium nitride layer 109;

[0059] - A second metal layer, for example made of titanium nitride (TiN), is in contact with the upper surface of the first metal layer, forming a barrier to the diffusion of metal elements; and

[0060] - A third metal layer, for example made of aluminum, is in contact with the upper surface of the second metal layer and functions as an optical reflector.

[0061] For example, the thickness of the first metal layer can be adjusted so that the distance between the quantum well of the emission layer 107, which is closest to layer 109, and the upper surface of the second metal layer allows for constructive interference of light in the structure. This, in turn, allows for optimal light extraction.

[0062] As an example, the first metal layer has a thickness in the range of 20 nm to 100 nm, for example, approximately 60 nm. As an example, the second metal layer has a thickness in the range of 1 nm to 10 nm, for example, approximately 5 nm. As an example, the third metal layer has a thickness in the range of 100 nm to 200 nm, for example, approximately 100 nm.

[0063] As a variation, the metal layer 111 can be formed by any stack of layers made of transparent and conductive oxides (e.g., ITO) and / or layers based on metals, metal alloys, or metal oxides (e.g., nickel, nickel oxide, nickel aluminum oxide, aluminum, silver, platinum, etc.).

[0064] Figure 1B It shows in Figure 1A The structure is obtained at the end of a subsequent step in which a bonding stack 113 is formed on the upper surface of the metal layer 111 of the structure.

[0065] For example, the bonding stack 113 is selected to allow thermal bonding using surface activated bonding (SAB) or atomic diffusion bonding (ADB) techniques, followed by removal of the material used for bonding without damaging the gallium nitride layer 109. As an example, the subsequent removal of the material used for bonding can be performed by a wet etching process (e.g., by exposure to hydrofluoric acid and / or nitric acid) or by dry etching (e.g., by deep reactive ion etching (DRIE) using, for example, sulfur hexafluoride (SF6)).

[0066] As an example, the bonding stack 113 includes, in sequence from the upper surface of the metal layer 111, an insulating layer 115, an optional silicon nitride (SiN) layer 117, and a bonding layer 119. In the example shown, the lower surface of layer 117 contacts the upper surface of layer 115, and the upper surface of layer 117 contacts the lower surface of layer 119. Layer 115 includes at least one layer made of oxide, nitride, or oxynitride, for example. As an example, layer 115 is made of silicon oxide (SiO2), silicon nitride, or silicon oxynitride (SiON). As a variation, layer 115 may be an etch stop layer, for example, formed of a titanium layer, for example having a thickness of about 10 nm, coated with a titanium nitride layer, for example having a thickness of about 50 nm.

[0067] The bonding layer 119 is made of, for example, amorphous silicon (a-Si).

[0068] As an example, layer 115 has a thickness ranging from 300 nm to 600 nm. For example, layer 117 has a thickness of about 200 nm. For example, layer 119 has a thickness of about 20 nm.

[0069] Figure 1C The structure is shown at the end of a subsequent step in which an active LED stack 101 is transferred and bonded to the upper surface of a temporary transfer substrate 121 or handle, and then the growth substrate 103 is removed.

[0070] Prior to this, a bonding layer 123 is formed, for example, on the upper surface of the temporary transfer substrate 121 (in... Figure 1C The substrate 121 is, for example, a wafer or wafer made of a semiconductor material (e.g., silicon). For example, the substrate 121 has a lateral dimension substantially equal to that of those on which the substrate 103 is grown.

[0071] Bonding layer 123 is made of, for example, the same material as bonding layer 119 (e.g., amorphous silicon). Bonding layer 123 has, for example, a thickness substantially the same as that of bonding layer 119, such as about 20 nm. For example, bonding layer 123 extends continuously over the entire upper surface of substrate 121. Depending on the desired surface condition, bonding layer 123 can be submitted to the planarization operation prior to the transfer step.

[0072] During the transfer step, the assembly including the growth substrate 103, the active LED stack 101, the metal layer 111, and the bonding stack 113 can be flipped and transferred onto the temporary transfer substrate 121 so that the upper surface of the bonding layer 119 (on the...) Figure 1B The active LED stack 101 is placed in the orientation of the temporary transfer substrate 121 to contact the upper surface of the bonding layer 123. In this example, the bonding of the active LED stack 101 to the temporary transfer substrate 121 is achieved by placing the lower surface of the bonding layer 119 (in the orientation of the temporary transfer substrate 123) in contact with the upper surface of the bonding layer 123. Figure 1C The bonding is achieved by directly bonding the material (in the orientation of the bonding layer) to the upper surface of the bonding layer 123. The term "direct bonding" here means that the bonding is spontaneous and there is no fluid layer (e.g., adhesive layer) at the surface. Although this is spontaneous bonding, pressure may be applied during bonding.

[0073] As an example, the bonding is more specifically covalent bonding under ultra-high vacuum through temperature control of substrates 103 and 121. For example, the surfaces to be contacted are pre-activated, for example by bombardment with argon atoms having an energy of approximately 200 eV, reaching approximately 10 15 at / cm 2The dosage. For example, this activation is achieved by implementing the SAB technique mentioned above. As a variation, surface activated bonding (SAB) can be replaced by atomic diffusion bonding (ADB) of amorphous silicon deposited in ultra-high vacuum with a small thickness (e.g., in the range of 1 nm to 10 nm). This layer can advantageously replace the layer previously deposited on the surface.

[0074] Before the two bonding surfaces are placed in contact, at least one of the substrates (of growth substrate 103 and temporary transfer substrate 121) is heated, for example. As an example, one of substrates 103 and 121 is heated to a temperature about 20°C or about 50°C above room temperature, for example, above or equal to 40°C or above or equal to 70°C. In cases where growth substrate 103 has a greater coefficient of thermal expansion than layer 105 and layer 105 has a greater coefficient of thermal expansion than temporary transfer substrate 121, substrates 103 and 121 are advantageously heated to different temperatures, for example, a greater heating temperature for substrate 103 than for substrate 121. Heating growth substrate 103 allows for stress relaxation in layer 105 because it allows for approaching the growth temperature. Once bonding occurs and the structure has cooled to room temperature, the difference in the coefficients of thermal expansion between the materials of substrates 121 and 103 leads to an increase in stress in substrates 103 and 121. At the end of the step of removing the growth substrate 103, layer 105 will be subjected to less stress, resulting in less deformation of the transfer substrate 121 due to the difference in the coefficients of thermal expansion between layer 105 and the temporary transfer substrate 121. The selection of the temperatures taken for substrates 103 and 121 prior to bonding is, for example, subject to a trade-off between two objectives:

[0075] - Maintain structural integrity as it returns to room temperature, because if excessive stress is applied between substrate 121 and substrate 103, the material's fracture point may be reached; and

[0076] - After removing the growth substrate 103, a slightly curved transfer substrate 121 is obtained, for example, less than 100 µm or 120 µm, so that the structure can be processed by standard microelectronic devices, especially dry etching devices of the RIE (reactive ion etching) or ICP (inductively coupled plasma) type.

[0077] As an example, when substrate 103 has a higher coefficient of thermal expansion than layer 105, and layer 105 has a higher coefficient of thermal expansion than substrate 121, growth substrate 103 is heated to a temperature in the range of 95°C to 150°C, and transfer substrate 121 is heated to a temperature of approximately 40°C. As a variation, transfer substrate 121 may not be heated and may, for example, be held at room temperature, such as approximately 20°C. Depending on the materials forming substrates 103 and 121, as a variation, transfer substrate 121 may be heated to a temperature higher than that of growth substrate 103; in this case, growth substrate may or may not be heated. For example, this corresponds to the case where substrate 103 has a lower coefficient of thermal expansion than substrate 121.

[0078] As a variation, the growth substrate 103 and the temporary transfer substrate 121 are, for example, heated to a temperature about 20°C or 25°C higher than room temperature. As an example, substrates 103 and 121 are each heated to a temperature higher than or equal to 40°C or 45°C.

[0079] For example, the removal of the growth substrate 103 is performed by implementing a laser lift-off (LLO) technique, during which a laser beam is projected from its surface opposite the active LED stack 101 through the substrate 103. In the event that the temporary transfer substrate 121 warps due to the transfer and bonding of the active LED stack 101, the laser beam is controlled, for example, to perform a helical scan instead of a raster scan. The laser lift-off step is followed, for example, by removing gallium bumps formed on the upper surface of layer 105 under laser action (e.g., by wet treatment with hydrochloric acid or hot water).

[0080] In the example shown, layer 105 has been, for example, via RIE or ICP on its upper surface side (in... Figure 1C (In the orientation) it is thinned.

[0081] Figure 1D It shows in Figure 1C The structure is obtained at the end of a subsequent step where another bonding stack 125 is formed on the upper surface of the gallium nitride layer 105.

[0082] As an example, the bonding stack 125 includes, in order from the upper surface of the gallium nitride layer 105, an etch stop layer 127, for example, made of silicon nitride, and a bonding layer 129, for example, made of silicon oxide. In the example shown, the lower surface of layer 127 contacts the upper surface of layer 105, and the upper surface of layer 127 contacts the lower surface of layer 129. As an example, the etch stop layer 127 has a thickness of approximately 150 nm. As an example, the bonding layer 129 has a thickness of approximately 600 nm.

[0083] Furthermore, during this step, the upper surface of the bonding layer 129 is planarized, for example, by CMP (chemical and mechanical polishing).

[0084] Figure 1E It shows that Figure 1D The structure is obtained after subsequent steps of cutting the structure into multiple dies 131. More specifically, the components including temporary transfer substrate 121, bonding layer 123, bonding stack 113, metal layer 111, active LED stack 101 and bonding stack 125 are cut into multiple dies 131.

[0085] In the example shown, each die 131 includes portions of a temporary transfer substrate 121, a bonding layer 123, a bonding stack 113, a metal layer 111, an active LED stack 101, and a bonding stack 125. As an example, the die 131 is cut by sawing. For example, the dies 131 have the same dimensions.

[0086] Advantageously, it can provide Figure 1D The initial step of the structure inspection is to detect epitaxial defects. Then, cutting can be performed in such a way as to concentrate defects so that grains with low defect rates can be selected subsequently 131.

[0087] Figure 1F The structure is shown at the end of a subsequent step where the die 131 is transferred and bonded to the upper surface of a temporary transfer substrate 133 or a handle, and then the temporary transfer substrate 121 and bonding layers 119 and 123 are removed.

[0088] Prior to this, a bonding layer 135 is formed, for example, on the upper surface of the temporary transfer substrate 133 (in... Figure 1F The substrate 133 is, for example, a wafer or wafer made of a semiconductor material (e.g., silicon). For example, the substrate 133 has a larger lateral dimension than those of the growth substrate 103.

[0089] The bonding layer 135 is made of, for example, the same material as the bonding layer 129 (e.g., silicon oxide). For example, the bonding layer 135 has a thickness that is substantially equal to or less than that of the bonding layer 129, for example, about 200 nm. The bonding layer 135 extends continuously over, for example, the entire upper surface of the substrate 133.

[0090] During the transfer step, the die 131 can be flipped and transferred onto the temporary substrate 133 so that the lower surface of the bonding layer 129 (on Figure 1F In this example, the bonding of the active LED stack 101 to the temporary transfer substrate 133 is achieved by contacting the upper surface of the bonding layer 129 (in the orientation of the LED stack 101) with the upper surface of the bonding layer 135. Figure 1FThe grain 131 is directly bonded to the upper surface of the bonding layer 135 in the orientation of the grain. The direct bonding between the grain 131 and the temporary transfer substrate 133 is, for example, molecular bonding, thermo-press bonding or eutectic bonding.

[0091] Then, portions of the transfer substrate 121 and bonding layers 119 and 123 included in each grain 131 are removed, for example, by grinding.

[0092] Figure 1G The structure obtained at the end of subsequent steps, including depositing the encapsulation layer 137, depositing the insulating passivation layer 139, and planarizing the structure, is shown.

[0093] In the example shown, the encapsulation layer 137 is deposited on Figure 1F The encapsulation layer 137 is applied to the upper surface of the structure. In this example, layer 137 coats the side surfaces and upper surface of die 131. Layer 137 is then, after deposition, located on top of and in contact with the upper surface of a portion of layer 117 (or layer 115, if layer 117 is omitted), and on top of and in contact with the side surfaces of the bonding stack 125, the active LED stack 101, the metal layer 111, layer 115, and layer 117. Encapsulation layer 137 is designed, for example, to protect the side surfaces of die 131 from penetration by liquids used during subsequent wet etching steps.

[0094] As an example, the encapsulation layer is made of silicon nitride.

[0095] In the example shown, an insulating passivation layer 139 is then deposited over the entire upper surface of the structure. For example, layer 139 is deposited on a thickness greater than the cumulative thickness of the bonding stack 125, the active LED stack 101, the metal layer 111, layer 115, and layer 117. Layer 139 is made of an oxide (e.g., silicon oxide). As an example, layer 139 has a thickness of about a few micrometers, for example, equal to about 3 µm or 4 µm. Layer 139 is then planarized, for example, by CMP, to obtain an assembly with a substantially planar upper surface. This planarization is performed, for example, by stopping on layer 117. Layer 117 is then removed, for example, by etching. As an example, at the end of the planarization step, the upper surface of the insulating layer 115 is flush with the upper surface of the insulating passivation layer 139.

[0096] Figure 1H The structure obtained at the end of the subsequent steps of defining and personalizing multiple basic LEDs in each die 131 is shown.

[0097] In the example shown, trenches 141 are formed in the LED stack 101. In this example, each trench extends vertically from the upper surface of the insulating layer 115, through the metal layer 111, through the gallium nitride layer 109 and the emitter layer 107, and terminates at the thickness of layer 105. As an example, trenches 141 are formed by etching (using the material of layer 115 as a hard mask).

[0098] Figure 1I The structure obtained at the end of the subsequent steps of depositing another insulating passivation layer 143 and forming trenches 145 and vias 147 is shown.

[0099] In the example shown, an insulating passivation layer 143 is deposited over the entire upper surface of the structure. Layer 143 is conformally deposited in the trench 141, for example, by a method of ALD (Atomic Layer Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). Layer 143 is made of, for example, oxides (e.g., aluminum oxide), nitrides (e.g., silicon nitride or aluminum nitride), or a stack of layers made of these materials. Layer 143 is then anisotropically etched, for example, by RIE or ICP-type dry etching, to expose the bottom of the trench 141.

[0100] In the example shown, trench 145 is formed in an extension of previously formed trench 141. Trench 145 has a smaller lateral dimension than those of trench 141, and the sidewalls of each trench 145 are formed by a portion of insulating passivation layer 143. In the example shown, each trench 145 extends vertically from the upper surface of insulating layer 115, through metal layer 111, through gallium nitride layer 109, emitter layer 107, and gallium nitride layer 105, and terminates at the thickness of layer 127 of bonding stack 125. Among other things, trench 145 enables a portion of gallium nitride layer 105 of each basic LED to insulate a portion of layer 105 of other LEDs.

[0101] In the example shown, the via 147 has a depth less than that of the trench 145. The via 147 extends vertically from the upper surface of layer 115 across the entire thickness of layer 115. In the example shown, the bottom of each via 147 is formed by a portion of the upper surface of metal layer 111.

[0102] Figure 1J The structure obtained at the end of the subsequent step of forming conductive regions 149 within trench 145 and via 147 is shown. In the example shown, regions 149 fill trench 145 and via 147.

[0103] As an example, region 149 on the upper surface side of the component is formed by continuous deposition of the following:

[0104] - At least one mirror layer extending to and contacting the top of the side surface and bottom of the groove 145 and the through hole 147;

[0105] - At least one seed layer extending on top of the mirror layer and in contact with the mirror layer; and

[0106] - At least one fill layer.

[0107] As an example, the mirror layer is an aluminum layer or a titanium layer coated with an aluminum layer. As an example, the seed layer is formed by stacking multiple layers, including a titanium layer, a titanium nitride layer, and a copper layer in order from the mirror layer. As an example, the filler layer is made of a metal (e.g., copper) or a metal alloy.

[0108] Region 149 is formed, for example, by an inlay process. The mirror layer is formed, for example, by ion beam deposition (IBD) or physical vapor deposition. The filler layer is formed, for example, by electrochemical deposition.

[0109] A filler layer is deposited, for example, over the entire upper surface of the component, spanning a thickness sufficient to fill the trenches 145 and the vias 147. A step of planarizing the upper surface of the component, for example, by chemical mechanical polishing, is then performed such that region 149 is flush with a portion of the upper surface of layer 115.

[0110] Figure 1K It shows in Figure 1J The structure is obtained at the end of the subsequent steps of forming a stack 151 of insulating layers 153 and 155 on the upper surface of the structure, forming a through conductive via 157 in the stack 151, forming a stack 159 of insulating layers 161 and 163 on the stack 151, and forming a contact element 165 in the stack 159.

[0111] As an example, insulating layers 153 and 155 are made of silicon nitride and silicon oxide, respectively. Conductive vias 157 are made of, for example, a metal (e.g., copper) or a metal alloy. Conductive vias 157 are formed, for example, by implementing an inlay-type process. For example, conductive vias 157 can adjust the proportion of conductive material on the upper surface of the component. In the example shown, each conductive via 157 extends vertically through the entire stack 151 and is located on and in contact with the upper surface of one of the regions 149.

[0112] As an example, insulating layers 161 and 163 are made of silicon nitride and silicon oxide, respectively. Contact elements 165 are formed, for example, by implementing an inlay-type process (e.g., the type described in the applicant's previously obtained French patent number FR3079350 (DD18591 / B16845)). Contact elements 165 are made, for example, of a metal (e.g., copper) or a metal alloy. In the example shown, each contact element 165 extends vertically through the entire stack 159 and is located on top of and in contact with the upper surface of one of the conductive vias 157.

[0113] Figure 1L The structure is shown at the end of the steps of forming insulating layers 173 and 175 on the surface of a substrate 167 including an active region 169, forming a through conductive via 177 in the stack 171, forming insulating layers 181 and 183 on the stack 171, and forming a contact element 185 in the stack 179.

[0114] Substrate 167 is, for example, a wafer or a sheet of wafer made of a semiconductor material (e.g., silicon). The active region 169 of substrate 167 includes, for example, multiple integrated control circuits. The control circuits (for readability, in...) Figure 1L (Not detailed herein) For example, it is formed using CMOS (Complementary Metal-Oxide-Semiconductor) technology. The control circuitry formed in the active region 169 is, for example, of the ASIC (Application-Specific Integrated Circuit) type. As an example, the substrate 167 has a larger lateral dimension than those of the growth substrate 103.

[0115] For example, stacks 171 and 179 are similar to or the same as stacks 151 and 159, respectively. Furthermore, conductive vias 177 and contact elements 185 are similar to or the same as conductive vias 157 and contact elements 165, for example.

[0116] Figure 1M It shows that in the Figure 1K Component transfer and bonding to Figure 1L The structure obtained at the end of subsequent steps of the component assembly. During this step, the components including temporary transfer substrate 133, layer 135, stack 125, stack 101, layer 111, layer 115, and stacks 151 and 159 can be relative to each other. Figure 1K The orientation is reversed so that the surface of the LED stack 101 opposite to the substrate 133 is bonded to the upper surface of the substrate 167. The lower surface of the insulating layer 163 and the lower surface of the contact element 165 (in Figure 1M The active LED stack 101 to the substrate 167 can be bonded to the upper surface of the insulating layer 183 and the upper surface of the contact element 185, respectively, in terms of orientation. In this example, the bonding of the active LED stack 101 to the substrate 167 is achieved by direct bonding of the contact surfaces, for example, more specifically, by mixing metals with oxides. As an example, an annealing operation is then performed (e.g., at a temperature of approximately 400°C and for a duration of approximately 2 hours) to solidify the bonding.

[0117] At the end of the transfer step, the individual LEDs previously defined in the active LED stack 101 are connected to the electronic control circuitry formed in the active region 169 of the substrate 167.

[0118] Once the active LED stack 101 is bonded to the upper surface of the substrate 167, the temporary transfer substrate 133 is removed, for example by grinding and then wet etching (utilizing selective stopping on the material of layer 135).

[0119] For example, a chemical-mechanical polishing step is then performed on the upper surface side of the component to remove layers 135 and 129. As an example, the chemical-mechanical polishing stops at layer 127.

[0120] For example, a passivation layer (not shown) made of silicon nitride is then deposited, for example, on the upper surface side of the component, and microlenses 187 are formed perpendicularly to each basic LED of the optoelectronic display device. As an example, microlenses 187 are made of an insulating material, such as silicon nitride or gallium nitride.

[0121] about Figures 1A to 1M The advantage of the described method is that it does not include the step of cutting the growth substrate 103 into grains or chips. This is particularly advantageous when the growth substrate 103 is made of sapphire, a material that is very difficult to cut.

[0122] about Figures 1A to 1M Another advantage of the described method is that the step of removing the growth substrate 103 is performed before the active LED stack 101 is transferred to the semiconductor substrate 167 (where the control circuitry is integrated both inside and on top of it). This ensures that, in the case of implementing such removal by projecting a laser beam through the substrate 103, for example during a laser stripping step, there is no risk of damaging the control circuitry.

[0123] about Figures 1A to 1M Another advantage of the described method is that it can achieve optimal optical configuration in terms of light extraction, especially due to the presence of LEDs with resonant cavities, the tilting in gallium nitride which facilitates light extraction to the external environment, and the fact that microlenses can be fabricated from gallium nitride.

[0124] Figure 2A , Figure 2B , Figure 2C and Figure 2D These are simplified and partial side views and cross-sectional views, showing the... Figures 1A to 1M The structure obtained at the end of the steps in an alternative implementation of the method. For example, Figures 2A to 2D The variant usually corresponds to the case where the first bond is a metal-to-metal bond.

[0125] Figure 2A It shows in Figure 1A The structure obtained at the end of the step of forming a bonding stack 201 on the upper surface of the metal layer 111 of the structure.

[0126] In the example shown, the bonding stack 201 includes, in order from the upper surface of the metal layer 111, a layer 203 made of a metal nitride (e.g., titanium nitride (TiN)) and a bonding layer 205 made of a metal (e.g., titanium). In the example shown, the lower surface of layer 203 contacts the upper surface of the metal layer 111, and the upper surface of layer 203 contacts the lower surface of layer 205.

[0127] As an example, layer 203 has a thickness of approximately 40 nm. As an example, layer 205 has a thickness of approximately 600 nm.

[0128] Although this is in Figure 2A Not shown in the diagram to avoid drawing overload, but during subsequent steps of removing layer 205, another layer can be inserted between layers 203 and 205 to form a stop layer.

[0129] During subsequent steps, such as those described above... Figures 1C to 1E The steps described:

[0130] -For example, Figure 2A The structure is flipped and then transferred to a temporary transfer substrate 121, in which the bonding layer 123 of the substrate 121 is made of metal (e.g., titanium);

[0131] - Remove the growth substrate 103 and form a bonding stack 125 on the active LED stack 101; and

[0132] -Cut the components to obtain grain 131.

[0133] Figure 2B The structure obtained at the end of subsequent steps, including transferring and bonding the die 131 to the upper surface of the temporary transfer substrate 133, removing a portion of the thickness of the temporary transfer substrate 121, and depositing the encapsulation layer 137, is shown.

[0134] For example, transferring the die 131 to the upper surface of the temporary transfer substrate 133 is related to the above. Figure 1F The same or similar procedures are followed. For example, partial removal of the temporary transfer substrate 121 is performed by grinding. For instance, an encapsulation layer 137 is deposited over the entire upper surface of the structure, as previously described. Figure 1G As stated above.

[0135] Figure 2C The structure obtained at the end of the subsequent steps of removing the entire temporary transfer substrate 133 and removing the bonding layers 123 and 207 is shown.

[0136] Temporary transfer substrate 133 is removed, for example, by grinding. As an example, bonding layers 123 and 207 are removed by etching, for example by wet etching (using a stop on the metal nitride layer 203).

[0137] Figure 2D The structure obtained at the end of the subsequent step of depositing the passivation layer 139 is shown.

[0138] For example, the formation of the passivation layer 139 is related to previous findings. Figure 1G The similarities or identical ones described herein will not be elaborated upon further below.

[0139] Then, for example, from Figure 2D Implemented in components related to previous discussions Figures 1H to 1M The similar or identical subsequent steps described.

[0140] For example, Figures 2A to 2D The variant has the same Figures 1A to 1M The same or similar advantages of the methods.

[0141] Figure 3A , Figure 3B , Figure 3C and Figure 3D These are simplified and partial top and side views, as well as a cross-sectional view, showing the... Figures 1A to 1M The structure obtained at the end of a step in an alternative implementation of the method. For example, Figures 3A to 3D The variation typically corresponds to the case where the grain 131 is transferred onto the temporary transfer substrate 133 by means of a water film.

[0142] Figure 3A The structure obtained at the end of the steps of transferring and bonding the die 131 to the bonding layer 135 coated with the temporary transfer substrate 133 is shown. As an example, based on the above regarding... Figures 1A to 1E The steps of the method yield grain 131.

[0143] The transfer of grain 131 is performed, for example, by implementing a water film bonding technique, as described in, for example, European patent application number EP 3593376 previously filed by the applicant.

[0144] In the example shown, grain 131 has a generally square overall shape in the top view. However, this example is not limiting, and as a variation, grain 131 can have any overall shape, such as rectangular, elliptical, circular, etc.

[0145] At the end of the transfer and bonding steps, the die 131 may be laterally and / or angularly misaligned relative to the desired location. To overcome this problem, the die 131 is etched, for example, to obtain a die 301 aligned with the desired location. To enable this misalignment correction, for example, the die 131 is given a lateral dimension larger than those of the desired die 301 after transfer to the temporary transfer substrate 133.

[0146] Figure 3B The structure obtained after subsequent steps of depositing the encapsulation layer 137 and the insulating passivation layer 139 is shown, for example, as previously described. Figure 1G Discussed.

[0147] Figure 3C The structure is shown after subsequent steps, such as photolithography, followed by vertical etching in accordance with each grain 131 to structure the insulating passivation layer 139.

[0148] In the example shown, layer 139 is removed vertically in accordance with each grain 131 to expose the upper surface of layer 137 located on each grain 131 (in Figure 3C (in the orientation).

[0149] Figure 3D This shows the upper surface side of the temporary transfer substrate 133 (on) Figure 3D (in the orientation) Figure 3C The structure is obtained at the end of the subsequent steps of planarization of the structure.

[0150] In the example shown, at the end of this step, the upper surface of the insulating passivation layer 139 is flush with the upper surface of the grain 131, more specifically, the upper surface of a portion of layer 137 coated on each grain. As an example, the planarization step is performed by chemical-mechanical polishing, for example by stopping on layer 137.

[0151] For example, Figures 3A to 3D The variant has the same Figures 1A to 1M The same or similar advantages of the methods.

[0152] The above about Figures 3A to 3D Another advantage of the described variant is that it can greatly improve the flatness of the component (a key element for subsequent hybrid bonding with substrate 167).

[0153] Compared with previous information Figures 1H to 1M The similar or identical subsequent steps described then, for example, from Figure 1G The components are used.

[0154] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, Figures 2A to 2D Variations and Figures 3A to 3D Variations can be combined.

[0155] Furthermore, the conductivity types of gallium nitride layers 105 (N-type, in the example) and 109 (P-type, in the example) can be reversed.

[0156] Furthermore, while examples of display devices including gallium nitride-based LEDs have been described in detail, the described embodiments can be applied by those skilled in the art to manufacture devices including multiple gallium nitride-based photodiodes (each individually addressable to acquire an image).

[0157] More generally, the described embodiments can be applied to the manufacture of any display device or photosensitive sensor based on semiconductor diodes, including those based on semiconductor materials other than gallium nitride, such as diodes based on other III-V semiconductor materials.

[0158] The embodiments described can also be applied to the manufacture of any electronic device, including multiple semiconductor components based on gallium nitride or other semiconductor materials (such as III-V materials), and integrated circuits suitable for individually controlling these components. As an example, the semiconductor components can be power components, such as transistors, diodes, etc.

[0159] Finally, based on the functional indications given above, the actual implementation of the embodiments and variations is within the capabilities of those skilled in the art. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this disclosure.

Claims

1. A method for manufacturing an optoelectronic device, comprising the following sequential steps: a) An active diode stack (101) is formed by epitaxial growth on a growth substrate (103). b) Transfer the active diode stack onto the first transfer substrate (121); c) Remove the growth substrate; d) By cutting the first transfer substrate and the active diode stack, a plurality of grains (131) are formed. e) Transferring the dies to a second transfer substrate (133), each die comprising a portion of the active diode stack; and f) Transfer the components, including portions of the second transfer substrate (133) and the active diode stack (101), onto an active substrate (167) including integrated control circuitry.

2. The method according to claim 1, wherein, At step b), the growth substrate (103) or the transfer substrate (121) is heated.

3. The method according to claim 2, wherein, The growth substrate (103) or the transfer substrate (121) is heated to a temperature of 40°C or higher.

4. The method according to claim 2, wherein, The growth substrate (103) or the transfer substrate (121) is heated to a temperature of 70°C or higher.

5. The method according to claim 1, wherein, In step b), the growth substrate (103) and the transfer substrate (121) are heated.

6. The method according to claim 5, wherein, The growth substrate (103) and the transfer substrate (121) are heated to a temperature of 40°C or higher.

7. The method according to any one of claims 1 to 6, wherein, At step b), the active diode stack (101) is bonded to the first transfer substrate (121) by directly bonding the first bonding layer (119) previously deposited on the surface of the active diode stack opposite to the growth substrate to the second bonding layer (123) previously deposited on the first transfer substrate.

8. The method according to claim 7, wherein, At step b), the surfaces of the first bonding layer (119) and the second bonding layer (123) to be in contact are activated before bonding.

9. The method according to claim 7, wherein, The first bonding layer (119) and the second bonding layer (123) are made of amorphous silicon.

10. The method according to claim 7, wherein, The first bonding layer (119) and the second bonding layer (123) are metal layers.

11. The method according to claim 10, wherein, The first bonding layer (119) and the second bonding layer (123) are made of titanium.

12. The method according to any one of claims 1 to 6, wherein, At step e), the die (131) is bonded to the second transfer substrate (133) by directly bonding the third bonding layer (129) previously deposited on the surface of the active diode stack (101) opposite to the first transfer substrate (121) to the fourth bonding layer (135) previously deposited on the second transfer substrate.

13. The method according to claim 12, wherein, The third bonding layer (129) and the fourth bonding layer (135) are made of silicon oxide.

14. The method according to claim 1, wherein, At step f), a portion of the active diode stack (101) and the second transfer substrate (133) are bonded to the active substrate (167) by bonding a first insulating layer (163) previously deposited on the surface of the active diode stack opposite to the second transfer substrate and a first contact element (165) located in the first insulating layer to a second insulating layer (183) previously deposited on the active substrate and a second contact element (185) located in the second insulating layer, respectively.

15. The method according to any one of claims 1 to 6, further comprising step g) after step e) etching the grain (131) to compensate for misalignment of the grain relative to the second transfer substrate (133).

16. The method of claim 15, further comprising, after step g), depositing an insulating layer (139) filling the laterally extending gaps between the grains (131), and then removing a portion of the insulating layer perpendicularly aligned with the grains (131) in step h).

17. The method according to any one of claims 1 to 6, wherein, The growth substrate (103) is made of sapphire.

18. The method according to any one of claims 1 to 6, wherein, The active diode stack (101) includes gallium nitride.

19. The method according to any one of claims 1 to 6, wherein, The active diode stack (101) is a light-emitting diode stack that includes a first gallium nitride layer (105) and a second gallium nitride layer (109) of opposite conductivity types in sequence from the growth substrate (103).

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