一种数据通路、芯片及电子设备
By introducing bypass control and dual-port memory into the data path, pipeline stalls caused by RAW relationships between instructions are resolved, improving the processing efficiency of the data path and reducing clock cycle latency.
CN120255961BActive Publication Date: 2026-07-17NEW H3C SEMICON TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEW H3C SEMICON TECH CO LTD
- Filing Date
- 2025-03-04
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing technologies, the RAW relationship between instructions causes pipeline stalls, affecting the efficiency of data path instruction processing.
Method used
The first and second multiplexers are used as bypasses. The source of operands is controlled by the bypass control signal. The output of the calculation unit is directly used as the operand, without reading from the register. Synchronous reading and writing of data is achieved by combining dual-port memory. A conflict detection unit and a data splicing unit are added to handle read and write conflicts and asymmetric access.
Benefits of technology
It reduces pipeline pauses, improves the efficiency of data path instruction processing, saves clock cycles, and solves the latency problem caused by RAW relationships.
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Figure CN120255961B_ABST
Abstract
本申请实施例提供了一种数据通路、芯片及电子设备，涉及芯片技术领域，上述数据通路包括：第一多路复用器和第二多路复用器；在待处理指令指示的第一操作数所在的源寄存器与待处理指令的上一指令指示的目的寄存器相同的情况下，第一旁路控制信号指示第二输入接口或第三输入接口起效；目的寄存器用于存储上一指令对应的数据处理结果；在待处理指令指示的第二操作数所在的源寄存器与上一指令指示的目的寄存器相同的情况下，第二旁路控制信号指示第五输入接口或第六输入接口起效。应用本申请实施例提供的方案能够在指令间存在RAW关系的情况下提高数据通路处理指令的效率。
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